Miniature LED chip and manufacturing method thereof

Abstract

The invention provides a miniature LED chip and a manufacturing method thereof, and the manufacturing method of the miniature LED chip provided by the invention comprises the steps: forming a plurality of sub epitaxial laminations which are arranged at intervals through cutting channels and cutting alignment structures which are arranged corresponding to the sub epitaxial laminations through deep etching of the epitaxial laminations, according to the cutting alignment structure, the channels and the corresponding sub epitaxial laminations are arranged at intervals, the channels are cutting deviation control lines, the cutting alignment precision can be improved when physical separation of an LED chip device is achieved through the cutting channels, and then the cutting yield is improved; besides, a photoresist grid line pattern is formed on the surface of the cutting channel preset area, the substrate is exposed through a dry etching process to form the cutting channel, the grid line density of the photoresist grid line pattern is gradually reduced in the direction from the center of the epitaxial lamination layer to the edge of the epitaxial lamination layer, and no grid line exists in the edge area of the epitaxial lamination layer; the load effect related to the etching depth-to-width ratio is utilized to improve the line width uniformity of the etching cutting channel, and the cutting yield is further improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor device manufacturing, and more specifically, relates to a micro LED chip and a manufacturing method thereof. Background Art

[0002] LED (Light Emitting Diode) is a semiconductor device that converts electrical energy into light energy. Specifically, the LED chip epitaxial stack includes at least an N-type semiconductor layer, an active area, and a P-type semiconductor layer stacked in sequence. Due to its small size, long life, rich colors, and low energy consumption, it is widely used in lighting, display, backlighting, and other fields. At the same time, due to the need for high resolution of LED display screens, the spacing and size of LED chips are getting smaller and smaller, such as Mini-LED and other micro-light-emitting devices.

[0003] Mini-LED and other micro-light-emitting devices are micrometer-sized and are a new generation of LED technology. They inherit the high efficiency, high reliability, high brightness and fast response time of small-pitch LEDs, and the smaller-pitch LEDs have lower power consumption and cost. Currently, Mini-LEDs usually adopt a flip-chip structure, which separates the devices between Mini-LEDs by deeply etching the grooves, and physically separates the devices by laser cutting the grooves.

[0004] However, the inventors have found that Figure 1 As shown in the dotted box, as the size of LED chips decreases, positive photoresist masks are used for deep etching grooves. Since the thickness of the positive photoresist mask is relatively thick and the exposure energy on the upper surface is relatively large, there is serious diffraction and serious changes in the photoresist morphology after high-temperature baking, which leads to obvious edge effects of deep etching grooves. The pattern is severely deformed after etching, and the grooves present arc-shaped irregular lines. In addition, the high-temperature growth stress cannot be released during the epitaxial process, causing the epitaxial wafer to warp, resulting in poor uniformity of the line width of deep etching grooves in different areas. On the other hand, Figure 2 As shown in the figure, in the dry etching process with the presence of a device wall, the existence of the plasma sheath will make the potential lower as it is closer to the sheath, thereby reducing the etching rate at the edge of the epitaxial stack and causing the overall deep etching uniformity of the epitaxial stack to decrease. The above situation will cause the laser cutting groove to cut off when achieving physical separation of the device, and the AOI (Automatic Optical Inspection) visual inspection pattern recognition accuracy after point measurement will be poor and the detection rate will decrease, thereby affecting the yield and reliability of the LED chip. Summary of the invention

[0005] In view of this, the present invention provides a micro light emitting diode epitaxial wafer and a method for manufacturing the same, so as to solve the problem in the prior art that the laser cutting grooves are easily cut off-center when realizing the physical separation of the devices due to the serious deformation of the etched groove pattern after deep etching of the epitaxial wafer, the grooves presenting arc-shaped irregular lines, or the poor uniformity of the line width of the deep etched grooves in different areas, thus affecting the yield and reliability of the LED chip.

[0006] To achieve the above purpose, the technical solution adopted by the present invention is as follows:

[0007] A method for manufacturing a micro LED chip, comprising:

[0008] Providing a substrate, growing an epitaxial stack on the substrate, the epitaxial stack comprising a first-type semiconductor layer, an active region, and a second-type semiconductor layer sequentially stacked along a growth direction;

[0009] Deeply etching the epitaxial stack to form a plurality of sub-epitaxial stacks spaced apart from each other by cutting paths and cutting alignment structures arranged corresponding to the sub-epitaxial stacks, wherein the cutting alignment structures are spaced apart from the corresponding sub-epitaxial stacks by channels, the channels are cutting deviation control lines, the cutting paths and the channels expose the substrate surface, and each sub-epitaxial stack has a first-type mesa exposing a portion of the first-type semiconductor layer and a second-type mesa exposing the second-type semiconductor layer;

[0010] A first electrode and a second electrode are made on each sub-epitaxial stack. The first electrode is deposited on the first type mesas to form contact with the first type semiconductor layer and is insulated from the side walls of the sub-epitaxial stack. The second electrode is deposited on the second type mesas to form contact with the second type semiconductor layer, and the first electrode and the second electrode are arranged far apart.

[0011] Preferably, before the deep etching of the epitaxial stack, the method further comprises: etching the epitaxial stack to synchronously obtain the cutting alignment structure and the channel preset area and the cutting road preset area adjacent thereto; the channel preset area and the cutting road preset area respectively expose the corresponding first-type semiconductor layer;

[0012] Wherein, the cutting alignment structure includes a portion of the epitaxial stack or at least a portion of the first type semiconductor layer.

[0013] Preferably, a photoresist grid line pattern is formed on the surface of the predetermined cutting path area of ​​a partial area of ​​the epitaxial stack, and the predetermined cutting path area of ​​the entire area of ​​the epitaxial stack is etched by a dry etching process to expose the substrate to form the cutting path;

[0014] Wherein, the gate line density of the photoresist gate line pattern gradually decreases from the center of the epitaxial stack toward the edge of the epitaxial stack, and there is no gate line in the edge area of ​​the epitaxial stack.

[0015] Preferably, a photoresist is patterned by exposure, development, and hardening processes using a photomask having grid lines to form the photoresist grid line pattern, specifically comprising the following steps:

[0016] A01, after forming the channel preset area, the cutting road preset area and the cutting alignment structure, spin coating the entire surface with photoresist;

[0017] A02, using a photomask with grid lines to expose the photoresist, wherein the grid lines of the photomask correspond to the preset area of ​​the photoresist grid line pattern, and after exposure diffraction, the photoresist between the preset area of ​​the photoresist grid line pattern and the grid lines of the photomask is exposed, and the photoresist not blocked by the photomask forms an exposure area;

[0018] A03, removing the photoresist in the exposure area through development to form a photoresist grid line protrusion;

[0019] A04. Harden the photoresist grid line protrusions to form a photoresist grid line pattern. The photoresist grid line pattern isolates the surface of the preset area of ​​the cutting path into a plurality of small-pitch grooves.

[0020] Preferably, proximity exposure is adopted, the exposure interval between the photomask and the photoresist is L1, the width of a single grid line of the photomask is L2, and the wavelength of the exposure light source is L3, then, L3≤L2≤2L3;

[0021] Among them, the value range of L1 is 0um-60um, excluding the endpoint value; the value range of L2 is 0.3um-1um, including the endpoint value; the value range of L3 is 300nm-500nm, including the endpoint value.

[0022] Preferably, the photoresist further has a first opening, the first opening corresponds to the preset channel area, after exposure and development, the patterned photoresist still reveals the preset channel area, and the substrate is etched along the exposed preset channel area to form the channel, and the cutting alignment structure also includes an etching surface between the channel and the cutting road;

[0023] Alternatively, the photolithography plate further has a second opening, which corresponds to the channel preset area and the cutting alignment structure. After exposure and development, the patterned photoresist also reveals the channel preset area and the cutting alignment structure. The substrate is etched along the exposed channel preset area to form the channel, and the cutting alignment structure is etched to expose a portion of the first-type semiconductor layer.

[0024] Preferably, each sub-epitaxial stack further includes a transparent conductive layer, an insulating layer, a first pad and a second pad; wherein the transparent conductive layer is disposed on the second-type mesa, and the second electrode is deposited on the surface of the transparent conductive layer or is connected to the second-type semiconductor layer by embedding the transparent conductive layer through a first through hole;

[0025] The insulating layer covers the exposed surfaces of each of the sub-epitaxial stacks, the transparent conductive layer and the channel, and the insulating layer has a second through hole exposing the first electrode and a third through hole exposing the second electrode;

[0026] The first pad is electrically connected to the first electrode through the second through hole, the second pad is electrically connected to the second electrode through the third through hole, and the first pad is spaced apart from the second pad.

[0027] Preferably, the insulating layer comprises an etching isolation layer and an insulating reflective layer which are sequentially stacked in a direction away from the substrate.

[0028] Preferably, forming the second through hole and the third through hole comprises: firstly etching the insulating reflective layer to the surface of the etching isolation layer using a first etching gas, and then continuing to etch the exposed etching isolation layer to the surface of the first electrode and the second electrode using a second etching gas to form the second through hole and the third through hole penetrating the insulating reflective layer;

[0029] The first etching gas includes one or more of CF4 and CHF3; the second etching gas includes one or more of HBr, BCl3 and HF.

[0030] Preferably, the first pad and the second pad both extend in directions away from each other to the surface of the insulating layer in a direction perpendicular to the channel, and the first pad and the second pad are located in a region surrounded by the cutting alignment structure.

[0031] The present invention further provides a micro LED chip, the micro LED chip comprising:

[0032] substrate;

[0033] An epitaxial stack is arranged on the surface of the substrate, wherein the epitaxial stack comprises: a first-type semiconductor layer, an active region and a second-type semiconductor layer sequentially stacked on the substrate from bottom to top;

[0034] The epitaxial stack has a cutting path and a channel exposing the surface of the substrate, and the epitaxial stack forms a plurality of mutually spaced sub-epitaxial stacks and a cutting alignment structure corresponding to the sub-epitaxial stack through the cutting path, wherein the cutting alignment structure is spaced from the corresponding sub-epitaxial stack through the channel, the channel is a cutting deviation control line, and each sub-epitaxial stack has a first type mesa exposing a portion of the first type semiconductor layer and a second type mesa exposing the second type semiconductor layer;

[0035] A first electrode and a second electrode are arranged on each sub-epitaxial stack:

[0036] The first electrode is arranged on the first type mesa to form contact with the first type semiconductor layer and is insulated from the side wall of the sub-epitaxial stack;

[0037] The second electrode is disposed on the second-type mesa to form contact with the second-type semiconductor layer, and the first electrode and the second electrode are disposed far apart.

[0038] Preferably, the cutting alignment structure includes a portion of the epitaxial stack or at least a portion of the first type semiconductor layer.

[0039] Preferably, the sub-epitaxial stack further comprises a transparent conductive layer, an insulating layer, a first pad and a second pad; wherein the transparent conductive layer is disposed on the second-type mesa, and the second electrode is deposited on the surface of the transparent conductive layer or is connected to the second-type semiconductor layer by embedding the transparent conductive layer through a first through hole;

[0040] The insulating layer covers the exposed surfaces of each of the sub-epitaxial stacks, the transparent conductive layer and the channel, and the insulating layer has a second through hole exposing the first electrode and a third through hole exposing the second electrode;

[0041] The first pad is electrically connected to the first electrode through the second through hole, the second pad is electrically connected to the second electrode through the third through hole, and the first pad is spaced apart from the second pad.

[0042] Preferably, the first pad and the second pad both extend in directions away from each other to the surface of the insulating layer in a direction perpendicular to the channel, and the first pad and the second pad are located in a region surrounded by the cutting alignment structure.

[0043] Through the above technical solution, the following effects are achieved:

[0044] The manufacturing method of the micro LED chip provided by the present invention forms a plurality of sub-epitaxial stacks arranged at intervals through cutting paths and a cutting alignment structure arranged corresponding to the sub-epitaxial stacks through deep etching of the epitaxial stacks, wherein the cutting alignment structure is arranged at intervals with the corresponding sub-epitaxial stacks through a trench, and the trench is a cutting deviation control line, which can improve the cutting alignment accuracy when the physical separation of LED chip devices is achieved through the cutting path, thereby improving the cutting yield. In the subsequent AOI process, by identifying whether the trench is complete, it is determined whether the LED chip is cut deviated, thereby improving the AOI detection rate; even if the alignment cutting path is cut deviated during cutting, the LED chip device separation can be achieved through the trench, thereby improving the overall yield and reliability of the LED chip, and avoiding the problem of cutting deviation caused by the cutting path presenting arc-shaped irregular lines or the deep etching groove line width uniformity in different areas.

[0045] Furthermore, a photoresist grid line pattern is formed on the surface of a preset cutting path area in a partial area of ​​the epitaxial stack, and the preset cutting path area in the entire area of ​​the epitaxial stack is etched by a dry etching process to expose the substrate to form a cutting path, wherein the grid line density of the photoresist grid line pattern gradually decreases from the center of the epitaxial stack toward the edge of the epitaxial stack, and there is no grid line in the edge area of ​​the epitaxial stack, and the load effect related to the etching aspect ratio is utilized to gradually increase the etching rate of the cutting path from the center of the epitaxial stack toward the edge of the epitaxial stack, which is neutralized by the dry etching in the presence of the device wall in the existing process, and the etching rate at the edge of the epitaxial stack caused by the presence of the plasma sheath decreases, so as to improve the line width uniformity of the etched cutting path, thereby achieving the uniformity control of the etched cutting paths in different areas of the epitaxial stack, and further improving the cutting yield.

[0046] Furthermore, the first soldering pad and the second soldering pad are arranged to extend in directions away from each other to the surface of the insulating reflective layer in the perpendicular direction of the channel, so as to increase the contact area between the first soldering pad, the second soldering pad and the insulating reflective layer, thereby improving the push-pull force reliability of the LED chip and avoiding the risk of electrode falling off. In addition, the first soldering pad and the second soldering pad are located in the area surrounded by the cutting alignment structure, which can avoid the first soldering pad and the second soldering pad from extending beyond the cutting alignment structure to the cutting path, causing the first soldering pad and the second soldering pad to be cut off when cutting, thereby causing leakage.

[0047] The micro LED chip provided by the present invention is manufactured by using the aforementioned micro LED chip manufacturing method, and can improve the cutting alignment accuracy when realizing the physical separation of LED chip devices through the cutting path, thereby improving the cutting yield. In the subsequent AOI process, by identifying whether the groove is complete, it is determined whether the LED chip is cut off-center, thereby improving the AOI detection rate; even if the alignment cutting path is cut off-center during cutting, the LED chip device separation can be achieved through the groove, thereby improving the overall yield and reliability of the LED chip, and avoiding the problem of cutting off-center due to the cutting path presenting arc-shaped irregular lines or the poor uniformity of the line width of the deep etched grooves in different areas. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0049] Figure 1 This is a FIB (focused ion beam) image of a LED chip after deep etching to form grooves in the prior art;

[0050] Figure 2 It is a schematic diagram of the potential distribution at different positions of an LED chip in a dry etching process with a device wall in the prior art;

[0051] Figure 3 A flow chart of a method for manufacturing a micro LED chip provided by an embodiment of the present invention;

[0052] Figures 4 to 12 for Figure 3 Process cross-sectional diagram corresponding to each step of the manufacturing method shown;

[0053] Fig.13 A schematic diagram of a photolithography plate structure provided by an embodiment of the present invention;

[0054] Fig.14 for Fig.13 A schematic diagram of a sub-photomask and photomask grid line distribution of the photomask shown;

[0055] Fig.15 for Fig.14 Schematic diagram of the cross section along line FF;

[0056] Fig.16 A flow chart of a method for manufacturing a photoresist grid line pattern provided by an embodiment of the present invention;

[0057] Figures 17 to 21 for Fig.16The process cross-sectional diagram corresponding to each step of the manufacturing method is shown.

[0058] Explanation of symbols in the figure:

[0059] A, cutting road; B, trench; C, cutting alignment structure; L1, exposure spacing between photomask and photoresist; L2, width of a single grid line of photomask; L3, wavelength of exposure light source; L4, width of a single grid line of photoresist grid line pattern;

[0060] 1. Substrate; 2. First-type semiconductor layer; 21. First-type mesa; 22. Channel preset area; 23. Cutting road preset area; 3. Active area; 4. Second-type semiconductor layer; 41. Second-type mesa; 5. Photoresist; 51. Photoresist grid line pattern; 52. Photoresist grid line pattern preset area; 53. Exposure area; 54. Photoresist grid line protrusion; 6. Photomask; 61. Photomask grid line; 62. Sub-photomask; 63. First opening; 64. Second opening; 7. Transparent conductive layer; 8. First electrode; 9. Second electrode; 10. Insulating layer; 101. Etching isolation layer; 102. Insulating reflective layer; 100. First pad; 200. Second pad. DETAILED DESCRIPTION

[0061] To make the content of the present invention clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0062] In the following description, many specific details are set forth to facilitate a full understanding of the present application, but the present application may also be implemented in other ways different from those described herein, and those skilled in the art may make similar generalizations without violating the connotation of the present application. Therefore, the present application is not limited to the specific embodiments disclosed below.

[0063] Secondly, the present application is described in detail with reference to the schematic diagram. When describing the embodiments of the present application in detail, for the sake of convenience, the cross-sectional diagrams showing the device structure will not be partially enlarged according to the general scale, and the schematic diagrams are only examples, which should not limit the scope of protection of the present application. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.

[0064] In view of this, the present application provides a method for manufacturing a micro LED chip, such as Figure 3 As shown, the production method includes:

[0065] Step S100, providing a substrate, and growing an epitaxial stack on the substrate, wherein the epitaxial stack includes a first-type semiconductor layer, an active region, and a second-type semiconductor layer sequentially stacked along a growth direction;

[0066] Step S200, deeply etching the epitaxial stack to form a plurality of sub-epitaxial stacks spaced apart from each other by cutting paths and cutting alignment structures arranged corresponding to the sub-epitaxial stacks, wherein the cutting alignment structures are spaced apart from the corresponding sub-epitaxial stacks by channels, the channels are cutting deviation control lines, the cutting paths and the channels expose the substrate surface, and each sub-epitaxial stack has a first-type mesa exposing a portion of the first-type semiconductor layer and a second-type mesa exposing the second-type semiconductor layer;

[0067] Step S300, making a first electrode and a second electrode on each sub-epitaxial stack, the first electrode is deposited on the first type mesa to form contact with the first type semiconductor layer, and is insulated from the side wall of the sub-epitaxial stack; the second electrode is deposited on the second type mesa to form contact with the second type semiconductor layer, and the first electrode and the second electrode are arranged far apart.

[0068] The method for manufacturing a micro LED chip provided by an embodiment of the present invention will be described in detail below with reference to the accompanying drawings corresponding to each step, including:

[0069] Step S100: Figure 4 As shown, a substrate 1 is provided, and an epitaxial stack is grown on the substrate 1, wherein the epitaxial stack includes a first-type semiconductor layer 2, an active region 3, and a second-type semiconductor layer 4 which are sequentially stacked along a growth direction;

[0070] It should be noted that the growth substrate 1 provided in this embodiment can be a substrate made of sapphire or other materials, and the embodiment of the present invention does not make specific restrictions on this. Moreover, this embodiment does not limit the specific doping types of the first-type semiconductor layer 2 and the second-type semiconductor layer 4. The doping types of the first-type semiconductor layer 2 and the second-type semiconductor layer 4 are opposite. The first-type semiconductor layer 2 can be a P-type semiconductor layer or an N-type semiconductor layer, and the materials of the N-type semiconductor layer and the P-type semiconductor layer can be GaN.

[0071] Step S200: Figure 5 or Figure 6 As shown, the epitaxial stack is deeply etched to form a plurality of sub-epitaxial stacks spaced apart from each other by a cutting path A and a cutting alignment structure C arranged corresponding to the sub-epitaxial stack, wherein the cutting alignment structure C is spaced apart from the corresponding sub-epitaxial stack by a channel B, the channel B is a cutting deviation control line, the cutting path A and the channel B expose the surface of the substrate 1, and each sub-epitaxial stack has a first type mesa 21 exposing a portion of the first type semiconductor layer 2 and a second type mesa 41 exposing the second type semiconductor layer 4;

[0072] It should be noted that, in the present embodiment, the cutting alignment structure C and the channel B surround the corresponding sub-epitaxial stack, and the cutting alignment structure C is cut between the cutting path A and the channel B; by deeply etching the epitaxial stack to expose the surface of the substrate 1, a plurality of sub-epitaxial stacks arranged at intervals through the cutting path A are formed, so that the subsequent deposition of the insulating layer can cover each sub-epitaxial stack, thereby avoiding the problem of incomplete coverage, which in turn affects the reliability of the LED chip.

[0073] It should also be noted that Figure 5 or Figure 6 Only one sub-epitaxial stack is shown, which corresponds to one LED chip. It can be understood that there are many sub-epitaxial stacks such as Figure 5 or Figure 6 The sub-epitaxial stack shown.

[0074] In an embodiment of the present application, the provided growth substrate 1 may be a substrate made of sapphire or other materials, and this embodiment of the present invention does not impose any specific limitation on this.

[0075] Optionally, in this embodiment, the angle between the sidewall of the channel B and the substrate 1 is 30°-88°.

[0076] In another embodiment of the present application, Figure 7 As shown, before deeply etching the epitaxial stack, the method further includes: etching the epitaxial stack to synchronously obtain the cutting alignment structure C and the channel preset area 22 and the cutting road preset area 23 adjacent thereto; the channel preset area 22 and the cutting road preset area 23 respectively expose the corresponding first type semiconductor layer 2;

[0077] The cutting alignment structure C includes a portion of the epitaxial stack 2 or at least a portion of the first type semiconductor layer 2 .

[0078] Specifically, at least one first area and at least one second area on the upper surface of the epitaxial stack are etched to form a groove in the first area and a cutting path preset area 23 in the second area. The groove and the cutting path preset area 23 are separated by a cutting alignment structure C, and the portion of the groove adjacent to the cutting alignment structure C is the channel preset area 22.

[0079] Optionally, in this embodiment, the channel preset area 22, the cutting road preset area 23 and the cutting alignment structure C can be formed simultaneously by one photolithography, and the etching can be performed by a dry etching process such as inductively coupled plasma (ICP).

[0080] It should be noted that the etching gas of the ICP etching process is not limited in this embodiment. Optionally, the etching gas of the ICP etching process is Cl 2 , Ar and O 2 Mixed gas, gas ratio is C l 2 :Ar:O 2=5:1:2.

[0081] Based on the above embodiments, in an embodiment of the present application, Figure 8 As shown, a photoresist grid line pattern 51 is formed on the surface of the predetermined cutting path area 23 of a part of the epitaxial stack. Figure 5 or Figure 6 As shown, the predetermined cutting path area 23 of the entire epitaxial stack is etched by a dry etching process to expose the substrate 1 to form a cutting path A;

[0082] The gate line density of the photoresist gate line pattern 51 gradually decreases from the center of the epitaxial stack toward the edge of the epitaxial stack, and there is no gate line in the edge region of the epitaxial stack.

[0083] It should be noted that, in the present embodiment, the load effect related to the etching aspect ratio is utilized so that the etching rate of the cutting path A gradually increases from the center of the epitaxial stack toward the edge of the epitaxial stack; the load effect related to the etching aspect ratio refers to the etching rate of smaller holes or grooves in the etching of high aspect ratio structures, such as deep holes or deep grooves, which is lower than that of larger holes or grooves. This is because it is difficult for the etching gas to enter the deep part, and at the same time it is difficult for the reaction products to escape, resulting in a decrease in the etching rate at the bottom.

[0084] It should also be noted that, in the present embodiment, it is not limited whether the width dimensions of each gate line of the photoresist gate line pattern 51 are consistent. The width dimensions of each gate line of the photoresist gate line pattern 51 may be the same or different, as long as the gate line density of the photoresist gate line pattern 51 gradually decreases from the center of the epitaxial stack toward the edge of the epitaxial stack.

[0085] Optionally, in this embodiment, if Figures 13 to 15 As shown, a photoresist 5 is patterned by a photoresist plate 6 having a grid line through exposure, development, and hardening processes to form a photoresist grid line pattern 51, as shown in FIG. Fig.16 As shown, it specifically includes the following steps:

[0086] A01、 Fig.17 As shown, after forming the channel preset area 22, the cutting road preset area 23 and the cutting alignment structure C, the entire surface photoresist 5 is spin-coated;

[0087] A02, such as Fig.18 As shown, a photoresist 5 is exposed using a photomask 6 having grid lines, wherein the photomask grid lines 61 correspond to the photoresist grid line pattern preset area 52, and after exposure diffraction, the photoresist 5 between the photoresist grid line pattern preset area 52 and the photomask grid lines 61 is exposed, and an exposure area 53 is formed with the photoresist 5 not blocked by the photomask 6;

[0088] A03, removing the photoresist 5 in the exposure area 53 through development to form a photoresist grid line protrusion 54;

[0089] A04、 Fig.19 As shown, the photoresist grid line protrusion 54 is hardened to form a photoresist grid line pattern 51. The photoresist grid line pattern 51 isolates the surface of the cutting path preset area 23 into a plurality of small-pitch grooves.

[0090] It should be noted that, in this embodiment, Fig.14 for Fig.13 A schematic diagram of a sub-photomask and the distribution of photomask grid lines of the photomask shown, wherein the unfilled part is the hollow area and the filled part is the shielding area.

[0091] Optionally, in this embodiment, proximity exposure is adopted, the exposure interval between the photomask and the photoresist is L1, the width of a single grid line of the photomask is L2, and the wavelength of the exposure light source is L3, then, L3≤L2≤2L3;

[0092] Among them, the value range of L1 is 0um-60um, excluding the endpoint value; the value range of L2 is 0.3um-1um, including the endpoint value; the value range of L3 is 300nm-500nm, including the endpoint value.

[0093] Optionally, in this embodiment, the width of a single gate line of the photoresist gate line pattern is L4, and the value range of L4 is 0.3um-1um, including the endpoint value.

[0094] Optionally, in this embodiment, the thickness of the photoresist 5 is greater than 8 um, and the exposure amount corresponding to the exposure is greater than 15 mj / um.

[0095] Optionally, in this embodiment, the development includes but is not limited to one or more of tetramethylammonium hydroxide and KOH, and the development time is 100s-300s, including endpoint values.

[0096] Optionally, in this embodiment, the temperature of the hardened film is greater than 120°C, and preferably, the temperature range of the hardened film is 125°C-150°C.

[0097] In one embodiment of the present application, refer to Fig.13 As shown, with the center point of the photomask 6 as the center, R1, R2, R3 as the radius respectively form a first circle, a second circle and a third circle, and R1<R2<R3, the first circle is the center area of ​​the photomask, the circumference of the first circle and the circumference of the second circle form a ring as the middle area of ​​the photomask, and the circumference of the second circle and the circumference of the third circle form a ring as the edge area of ​​the photomask;

[0098] Among them, the photolithography plate includes multiple sub-photolithography plates 62, the number of photolithography grid lines 61 between each sub-photolithography plate 62 in the central area of ​​the photolithography plate is greater than or equal to 5; the number of photolithography grid lines 61 between each sub-photolithography plate 62 in the middle area of ​​the photolithography plate is less than 5 and greater than or equal to 2; there are no photolithography grid lines 61 between each sub-photolithography plate in the edge area of ​​the photolithography plate.

[0099] It should be noted that, in the present embodiment, the number of grating lines of the photoresist in each area of ​​the photoresist is consistent with the number of grating lines of the corresponding photoresist grating line pattern, that is, the number of grating lines of the photoresist grating line pattern of each cutting lane preset area corresponding to the central area of ​​the photoresist is greater than or equal to 5, the number of grating lines of the photoresist grating line pattern of each cutting lane preset area corresponding to the middle area of ​​the photoresist is less than 5 and greater than or equal to 2, and there are no grating lines in each cutting lane preset area corresponding to the edge area of ​​the photoresist.

[0100] Based on the above embodiments, in an embodiment of the present application, Fig. 20 As shown, the photoresist 6 also has a first opening 63, and the first opening 63 corresponds to the channel preset area 22. After exposure and development, the patterned photoresist 5 still reveals the channel preset area 22. Figure 5 As shown, the substrate 1 is etched along the exposed channel preset area 22 to form a channel B, and the cutting alignment structure C also includes an etching surface between the channel B and the cutting path A;

[0101] or, as Fig.21 As shown, the photoresist 6 also has a second opening 64, and the second opening 64 corresponds to the channel preset area 22 and the cutting alignment structure C. After exposure and development, the patterned photoresist 5 also reveals the channel preset area 22 and the cutting alignment structure C. Figure 6 As shown, the substrate 1 is exposed along the exposed channel preset area 22 to form a channel B, and at the same time, the etching and cutting alignment structure C is exposed to part of the first type semiconductor layer.

[0102] It should be noted that, in this embodiment, the photoresist 5 is patterned through a photomask 6, and the channel preset area 22 is exposed while the photoresist gate line pattern 51 is formed, or the photoresist 5 is patterned through a photomask 6, and the channel preset area 22 and the cutting alignment structure C are exposed while the photoresist gate line pattern 51 is formed, providing a basis for deep etching of the epitaxial stack.

[0103] Optionally, in this embodiment, the remaining photoresist 5 is removed to expose the first type mesas 21 and the second type mesas 41 in each sub-epitaxial stack.

[0104] Step S300: Fig. 9 As shown, in Figure 5In the device structure shown, a first electrode 8 and a second electrode 9 are made on each sub-epitaxial stack. The first electrode 8 is deposited on the first type mesas 21 to form contact with the first type semiconductor layer 2, and is insulated from the side wall of the sub-epitaxial stack; the second electrode 9 is deposited on the second type mesas 41 to form contact with the second type semiconductor layer 4, and the first electrode 8 and the second electrode 9 are arranged far apart.

[0105] or, as Fig.10 As shown, in Figure 6 In the device structure shown, a first electrode 8 and a second electrode 9 are made on each sub-epitaxial stack, and the first electrode 8 is deposited on the first type mesas 21 to form contact with the first type semiconductor layer 2, and is insulated from the side walls of the sub-epitaxial stack; the second electrode 9 is deposited on the second type mesas 41 to form contact with the second type semiconductor layer 4, and the first electrode 8 and the second electrode 9 are arranged far apart.

[0106] Based on the above embodiments, in an embodiment of the present application, Fig.11 As shown, each sub-epitaxial stack further includes: a transparent conductive layer 7, an insulating layer 10, a first pad 100 and a second pad 200; wherein the transparent conductive layer 7 is disposed on the second type mesa 41, and the second electrode 9 is deposited on the surface of the transparent conductive layer 7 or is embedded in the transparent conductive layer 7 through the first through hole to form a connection with the second type semiconductor layer 4;

[0107] The insulating layer 10 covers the exposed surfaces of each sub-epitaxial stack, the transparent conductive layer 7 and the channel B, and the insulating layer 10 has a second through hole exposing the first electrode 8 and a third through hole exposing the second electrode 9;

[0108] The first pad 100 is electrically connected to the first electrode 8 through the second through hole, the second pad 200 is electrically connected to the second electrode 9 through the third through hole, and the first pad 100 and the second pad 200 are spaced apart.

[0109] It should be noted that, in this embodiment, Figure 5 The device structure shown in FIG. 1 is prepared. In other embodiments, the device structure shown in FIG. 1 may be prepared on the device structure shown in FIG. Figure 6 The device structure is shown in the figure and will not be described in detail here.

[0110] Optionally, in this embodiment, the transparent conductive layer 7 may be deposited by a magnetron sputtering process.

[0111] Optionally, in this embodiment, the radio frequency power of the transparent conductive layer 7 ranges from 200W to 400W, including the endpoint values, and the direct current power of the transparent conductive layer 7 ranges from 50W to 100W, including the endpoint values.

[0112] Optionally, in this embodiment, the thickness of the transparent conductive layer 7 ranges from 300A to 2000A, including endpoint values.

[0113] Optionally, in this embodiment, after the transparent conductive layer 7 is formed, the transparent conductive layer 7 is alloyed by RTA process to form a good ohmic contact between the transparent conductive layer 7 and the second-type semiconductor layer 4 .

[0114] Specifically, the RTA process (rapid thermal annealing process) is used. 2 (Oxygen) / N 2 The transparent conductive layer 7 is annealed in a (nitrogen) atmosphere, and the annealing temperature ranges from 500°C to 650°C, including the endpoint values; the oxygen gas flow ranges from 2sccm to 5sccm, including the endpoint values; the nitrogen gas flow ranges from 1LPM to 10LPM, including the endpoint values.

[0115] Optionally, in this embodiment, the insulating layer 10 also covers the exposed surface of the cutting alignment pattern.

[0116] Based on the above embodiments, in one embodiment of the present application, refer to Fig.11 As shown, the insulating layer 10 includes an etching isolation layer 101 and an insulating reflective layer 102 which are sequentially stacked in a direction away from the substrate 1 .

[0117] It should be noted that, in this embodiment, the etching isolation layer 101 is used to protect the metal material of the first electrode 8 and the second electrode 9 from being etched when forming the second through hole and the third through hole.

[0118] Optionally, in this embodiment, the etching isolation layer 101 and the insulating reflective layer 102 are prepared by ion-assisted plating.

[0119] Based on the above embodiments, in one embodiment of the present application, the etching isolation layer 101 can be made of HfO 2 The process conditions for preparing the etching isolation layer 101 of the coating material may include: the gas flow rate of oxygen is 25sccm-50sccm, including the endpoint value; the coating temperature range is 160℃-200℃, including the endpoint value; the thickness range is 100A-500A, including the endpoint value.

[0120] On the basis of the above embodiments, in one embodiment of the present application, forming the second through hole and the third through hole includes: firstly etching the insulating reflective layer 102 to the surface of the etching isolation layer 101 using the first etching gas, and then continuing to etch the exposed etching isolation layer 101 to the surface of the first electrode 8 and the second electrode 9 using the second etching gas, to form the second through hole and the third through hole penetrating the insulating layer 10;

[0121] The first etching gas includes but is not limited to one or more of CF4 and CHF3; the second etching gas includes but is not limited to one or more of HBr, BCl 3, and HF.

[0122] Before preparing the insulating reflective layer 102, 2000W-4000W of ionized high energy Ar + (Argon ion) / O 2 - (Oxygen ions) bombard the etching isolation layer 101 to clean the etching isolation layer 101 and improve the adhesion between the etching isolation layer 101 and the insulating reflective layer 102 .

[0123] On the basis of the above embodiments, in one embodiment of the present application, the insulating reflective layer 102 includes a DBR structure.

[0124] It should be noted that in this embodiment, the DBR structure is a periodic structure in which two materials with different refractive indices are alternately stacked in an ABAB manner, wherein the high refractive index layer can be made of Ti 3 O 5 layer, the low refractive index layer can be made of SiO 2 layer.

[0125] Optionally, in this embodiment, in the preparation of the SiO 2 When the ion source baffle is opened, the following process conditions can be adopted: the ion source baffle is opened intermittently, and the intermittent time range is 2s-5s, including the end value; the gas flow rate of oxygen is 10sccm-40sccm, including the end value; the ion source power range is 400W-600W, including the end value; the process vacuum adopts 1.0E -4 Pa-1.0E -5 Pa, including endpoint values; the coating temperature is 120°C-150°C, including endpoint values.

[0126] And, in the preparation of Ti in DBR structure 3 O 5 When the layer is formed, the following process conditions can be adopted: the ion source baffle is always open, the gas flow rate of oxygen is 40sccm-60sccm, including the end value; the ion source power range is 600W-1000W, including the end value; the process vacuum adopts 2.0E -2 Pa-9.0E -2 Pa, including endpoint values; the coating temperature is 120°C-150°C, including endpoint values.

[0127] Optionally, in this embodiment, each layer of Ti is evaporated 3 O 5 After the layer is formed, each Ti layer is bombarded with oxygen ions. 3 O 5 layer surface, so that Ti 3 O 5 The layer is fully oxidized and reduces Ti 3 O 5The film stress of each Ti layer is determined by bombarding each Ti layer with oxygen ions. 3 O 5 O 2 The gas flow rate is 20-30 sccm, and the ion source power is 200-400 W. The high / low refractive index DBR structure is prepared by controlling the ion energy of the overlapping Ti3O5 layer / SiO2 layer, the vacuum environment, the gas flow rate of oxygen and other parameters.

[0128] It should be noted that, in this embodiment, the number of cycles of the alternately stacked DBR structures is not specifically limited and can be set according to actual needs.

[0129] On the basis of the above embodiments, in one embodiment of the present application, the first electrode 8 and the second electrode 9 both include but are not limited to one or more combinations of Cr, Ni, Al, Ti, Pt, and Au.

[0130] In another embodiment of the present application, refer to Fig.11 As shown, the first electrode 8 and the second electrode 9 both include metal layers stacked in a multi-layer manner along the growth direction, and both use the Ti layer as the end layer and the Pt layer as the etching stop layer, and the second through hole and the third through hole also penetrate the Ti layer to expose the Pt layer; the insulating layer 10 also covers the side walls of the first electrode 8 and the second electrode 9.

[0131] It should be noted that, in the present embodiment, the first electrode 8 and the second electrode 9 both end with the Ti layer, that is, the upper surface and the side wall of the first electrode 8 and the second electrode 9 are both the Ti layer, and the Ti layer has an adhesion effect, which can improve the adhesion between the first electrode 8, the second electrode 9 and the insulating layer 10; the Pt layer has a slower etching rate, so that the LED device obtains a larger process window in the photolithography process, and the Pt layer has stable properties and is not easily oxidized after being exposed, which can improve the stability of the LED device.

[0132] Based on the above embodiments, in an embodiment of the present application, Fig.12 As shown, the first pad 100 and the second pad 200 extend in directions away from each other to the surface of the insulating layer 10 in the vertical direction of the channel B, and the first pad 100 and the second pad 200 are located in the area surrounded by the cutting alignment structure C.

[0133] It should be noted that, in this embodiment, the first pad 100 and the second pad 200 are both insulated from the first channel B by the insulating layer 10 .

[0134] On the basis of the above-mentioned embodiments, in one embodiment of the present application, a plurality of independent LED light-emitting units are formed by a laser cutting process.

[0135] Optionally, in this embodiment, the substrate 1 is thinned by a grinding and thinning process before laser cutting.

[0136] This embodiment provides a micro LED chip, referring to Fig. 9 or Fig.10 As shown, the micro LED chip includes:

[0137] Substrate 1;

[0138] An epitaxial stack is arranged on the surface of the substrate 1, wherein the epitaxial stack comprises: a first-type semiconductor layer 2, an active region 3 and a second-type semiconductor layer 4 which are sequentially stacked on the substrate 1 from bottom to top;

[0139] The epitaxial stack has a cutting path A and a channel B exposing the surface of the substrate 1, and the epitaxial stack forms a plurality of mutually spaced sub-epitaxial stacks and a cutting alignment structure C corresponding to the cutting path A, wherein the cutting alignment structure C is spaced from the corresponding sub-epitaxial stack through the channel B, the channel B is a cutting deviation control line, and each sub-epitaxial stack has a first type mesa 21 exposing a portion of the first type semiconductor layer 2 and a second type mesa 41 exposing the second type semiconductor layer 4;

[0140] A first electrode and a second electrode are arranged on each sub-epitaxial stack:

[0141] The first electrode 8 is disposed on the first type mesa 21 to form contact with the first type semiconductor layer 2 and is insulated from the side wall of the sub-epitaxial stack;

[0142] The second electrode 9 is disposed on the second type mesa 41 to form contact with the second type semiconductor layer 4 , and the first electrode 8 and the second electrode 9 are disposed apart from each other.

[0143] It should be noted that, in this embodiment, the cutting alignment structure C and the trench B surround the corresponding sub-epitaxial stack, and the cutting alignment structure C is spaced between the cutting lane A and the trench B; Fig. 9 or Fig.10 Only one sub-epitaxial stack is shown, which corresponds to one LED chip. It can be understood that there are many sub-epitaxial stacks such as Fig. 9 or Fig.10 The sub-epitaxial stack shown.

[0144] It should also be noted that the growth substrate 1 provided in this embodiment can be a substrate made of sapphire or other materials, and the embodiment of the present invention does not make specific restrictions on this. Moreover, this embodiment does not limit the specific doping types of the first-type semiconductor layer 2 and the second-type semiconductor layer 4. The doping types of the first-type semiconductor layer 2 and the second-type semiconductor layer 4 are opposite. The first-type semiconductor layer 2 can be a P-type semiconductor layer or an N-type semiconductor layer, and the materials of the N-type semiconductor layer and the P-type semiconductor layer can be GaN.

[0145] In an embodiment of the present application, the provided growth substrate 1 may be a substrate made of sapphire or other materials, and this embodiment of the present invention does not impose any specific limitation on this.

[0146] Optionally, in this embodiment, the angle between the sidewall of the channel B and the substrate 1 is 30°-88°.

[0147] On the basis of the above embodiments, in one embodiment of the present application, the cutting alignment structure C includes a portion of the epitaxial stack or at least a portion of the first type semiconductor layer 2 .

[0148] Based on the above embodiments, in one embodiment of the present application, refer to Fig.11 As shown, each sub-epitaxial stack further includes: a transparent conductive layer 7, an insulating layer 10, a first pad 100 and a second pad 200; wherein the transparent conductive layer 7 is disposed on the second type mesa 41, and the second electrode 9 is deposited on the surface of the transparent conductive layer 7 or is embedded in the transparent conductive layer 7 through the first through hole to form a connection with the second type semiconductor layer 4;

[0149] The insulating layer 10 covers the exposed surfaces of each sub-epitaxial stack, the transparent conductive layer 7 and the channel B, and the insulating layer 10 has a second through hole exposing the first electrode 8 and a third through hole exposing the second electrode 9;

[0150] The first pad 100 is electrically connected to the first electrode 8 through the second through hole, the second pad 200 is electrically connected to the second electrode 9 through the third through hole, and the first pad 100 and the second pad 200 are spaced apart.

[0151] Optionally, in this embodiment, the thickness of the transparent conductive layer 7 ranges from 300A to 2000A, including endpoint values.

[0152] Optionally, in this embodiment, the insulating layer 10 also covers the exposed surface of the cutting alignment pattern.

[0153] Based on the above embodiments, in one embodiment of the present application, refer to Fig.11 As shown, the insulating layer 10 includes an etching isolation layer 101 and an insulating reflective layer 102 which are sequentially stacked in a direction away from the substrate 1 .

[0154] It should be noted that, in this embodiment, the etching isolation layer 101 is used to protect the metal material of the first electrode 8 and the second electrode 9 from being etched when forming the second through hole and the third through hole.

[0155] Optionally, in this embodiment, the etching isolation layer 101 may be made of HfO 2 And other coating materials.

[0156] On the basis of the above embodiments, in one embodiment of the present application, the insulating reflective layer 102 includes a DBR structure.

[0157] It should be noted that, in this embodiment, the DBR structure is a periodic structure in which two materials with different refractive indexes are alternately stacked in an ABAB manner, wherein the high refractive index layer can be a Ti3O5 layer, and the low refractive index layer can be a SiO2 layer.

[0158] It should be noted that, in this embodiment, the number of cycles of the alternately stacked DBR structures is not specifically limited and can be set according to actual needs.

[0159] In one embodiment of the present application, the first electrode 8 and the second electrode 9 both include but are not limited to one or more combinations of Cr, Ni, Al, Ti, Pt, and Au.

[0160] In another embodiment of the present application, the first electrode 8 and the second electrode 9 both include metal layers stacked in a multi-layer manner along the growth direction, and both use the Ti layer as the end layer and the Pt layer as the etching stop layer, and the second through hole and the third through hole also penetrate the Ti layer to expose the Pt layer; the insulating reflective layer also covers the side walls of the first electrode and the second electrode.

[0161] It should be noted that, in the present embodiment, the first electrode 8 and the second electrode 9 both end with the Ti layer, that is, the upper surface and the side wall of the first electrode 8 and the second electrode 9 are both the Ti layer, and the Ti layer has an adhesion effect, which can improve the adhesion between the first electrode 8, the second electrode 9 and the insulating layer 10; the Pt layer has a slower etching rate, so that the LED device obtains a larger process window in the photolithography process, and the Pt layer has stable properties and is not easily oxidized after being exposed, which can improve the stability of the LED device.

[0162] Based on the above embodiments, in one embodiment of the present application, refer to Fig.12 As shown, the first pad 100 and the second pad 200 extend in directions away from each other to the surface of the insulating layer 10 in the vertical direction of the channel B, and the first pad 100 and the second pad 200 are located in the area surrounded by the cutting alignment structure C.

[0163] It should be noted that, in this embodiment, the first pad 100 and the second pad 200 are both insulated from the first channel B by the insulating layer 10 .

[0164] In summary, through the above technical solution, the following effects are achieved:

[0165] The manufacturing method of the micro LED chip provided in the present embodiment forms a plurality of sub-epitaxial stacks spaced apart from each other by cutting paths and a cutting alignment structure arranged corresponding thereto by deep etching of the epitaxial stack, wherein the cutting alignment structure is spaced apart from the corresponding sub-epitaxial stack by a channel, and the channel is a cutting deviation control line, which can improve the cutting alignment accuracy when the physical separation of the LED chip device is achieved through the cutting path, thereby improving the cutting yield. In the subsequent AOI process, whether the channel is complete can be identified to determine whether the LED chip is cut deviated, thereby improving the AOI detection rate. Even if the alignment cutting path is cut deviated during cutting, the LED chip device can be separated through the channel, thereby improving the overall yield and reliability of the LED chip, and avoiding the problem of cutting deviation caused by the cutting path presenting arc-shaped irregular lines or the deep etching groove line width uniformity in different areas.

[0166] Furthermore, a photoresist grid line pattern is formed on the surface of a preset cutting path area in a partial area of ​​the epitaxial stack, and the preset cutting path area in the entire area of ​​the epitaxial stack is etched by a dry etching process to expose the substrate to form a cutting path, wherein the grid line density of the photoresist grid line pattern gradually decreases from the center of the epitaxial stack toward the edge of the epitaxial stack, and there is no grid line in the edge area of ​​the epitaxial stack, and the load effect related to the etching aspect ratio is utilized to gradually increase the etching rate of the cutting path from the center of the epitaxial stack toward the edge of the epitaxial stack, which is neutralized by the dry etching in the presence of the device wall in the existing process, and the etching rate at the edge of the epitaxial stack caused by the presence of the plasma sheath decreases, so as to improve the line width uniformity of the etched cutting path, thereby achieving the uniformity control of the etched cutting paths in different areas of the epitaxial stack, and further improving the cutting yield.

[0167] Furthermore, the first soldering pad and the second soldering pad are arranged to extend in directions away from each other to the surface of the insulating reflective layer in the perpendicular direction of the channel, so as to increase the contact area between the first soldering pad, the second soldering pad and the insulating reflective layer, thereby improving the push-pull force reliability of the LED chip and avoiding the risk of electrode falling off. In addition, the first soldering pad and the second soldering pad are located in the area surrounded by the cutting alignment structure, which can avoid the first soldering pad and the second soldering pad from extending beyond the cutting alignment structure to the cutting path, causing the first soldering pad and the second soldering pad to be cut off when cutting, thereby causing leakage.

[0168] The micro LED chip provided by the present invention is manufactured by using the aforementioned micro LED chip manufacturing method, and can improve the cutting alignment accuracy when realizing the physical separation of LED chip devices through the cutting path, thereby improving the cutting yield. In the subsequent AOI process, by identifying whether the groove is complete, it is determined whether the LED chip is cut off-center, thereby improving the AOI detection rate; even if the alignment cutting path is cut off-center during cutting, the LED chip device separation can be achieved through the groove, thereby improving the overall yield and reliability of the LED chip, and avoiding the problem of cutting off-center due to the cutting path presenting arc-shaped irregular lines or the poor uniformity of the line width of the deep etched grooves in different areas.

[0169] Those skilled in the art should understand that, in the disclosure of the present invention, the terms "horizontal", "vertical", "upper", "lower", etc., indicating the orientation or position relationship are based on the orientation or position relationship shown in the drawings, which are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, the above terms should not be understood as limiting the present invention.

[0170] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0171] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for manufacturing a micro LED chip, characterized in that: include: Providing a substrate, growing an epitaxial stack on the substrate, the epitaxial stack comprising a first-type semiconductor layer, an active region, and a second-type semiconductor layer sequentially stacked along a growth direction; Deeply etching the epitaxial stack to form a plurality of sub-epitaxial stacks spaced apart from each other by cutting paths and cutting alignment structures arranged corresponding to the sub-epitaxial stacks, wherein the cutting alignment structures are spaced apart from the corresponding sub-epitaxial stacks by channels, the channels are cutting deviation control lines, the cutting paths and the channels expose the substrate surface, and each sub-epitaxial stack has a first-type mesa exposing a portion of the first-type semiconductor layer and a second-type mesa exposing the second-type semiconductor layer; A first electrode and a second electrode are made on each sub-epitaxial stack. The first electrode is deposited on the first type mesas to form contact with the first type semiconductor layer and is insulated from the side walls of the sub-epitaxial stack. The second electrode is deposited on the second type mesas to form contact with the second type semiconductor layer, and the first electrode and the second electrode are arranged far apart.

2. The method for manufacturing a micro LED chip according to claim 1, wherein: Before the deep etching of the epitaxial stack, the method further includes: etching the epitaxial stack to synchronously obtain the cutting alignment structure and the channel preset area and the cutting road preset area adjacent thereto; the channel preset area and the cutting road preset area respectively expose the corresponding first-type semiconductor layer; Wherein, the cutting alignment structure includes a portion of the epitaxial stack or at least a portion of the first type semiconductor layer.

3. The method for manufacturing a micro LED chip according to claim 2, wherein: Forming a photoresist grid line pattern on the surface of the predetermined cutting path area of ​​a partial area of ​​the epitaxial stack, and etching the predetermined cutting path area of ​​the entire area of ​​the epitaxial stack by a dry etching process to expose the substrate to form the cutting path; Wherein, the gate line density of the photoresist gate line pattern gradually decreases from the center of the epitaxial stack toward the edge of the epitaxial stack, and there is no gate line in the edge area of ​​the epitaxial stack.

4. The method for manufacturing a micro LED chip according to claim 3, wherein: The photoresist is patterned by using a photomask with grid lines through exposure, development, and hardening processes to form the photoresist grid line pattern, which specifically includes the following steps: A01, after forming the channel preset area, the cutting road preset area and the cutting alignment structure, spin coating the entire surface with photoresist; A02, using a photomask with grid lines to expose the photoresist, wherein the grid lines of the photomask correspond to the preset area of ​​the photoresist grid line pattern, and after exposure diffraction, the photoresist between the preset area of ​​the photoresist grid line pattern and the grid lines of the photomask is exposed, and the photoresist not blocked by the photomask forms an exposure area; A03, removing the photoresist in the exposure area through development to form a photoresist grid line protrusion; A04. Harden the photoresist grid line protrusions to form a photoresist grid line pattern. The photoresist grid line pattern isolates the surface of the preset area of ​​the cutting path into a plurality of small-pitch grooves.

5. The method for manufacturing a micro LED chip according to claim 4, wherein: Proximity exposure is adopted, the exposure distance between the photomask and the photoresist is L1, the width of a single grid line of the photomask is L2, and the wavelength of the exposure light source is L3, then, L3≤L2≤2L3; Among them, the value range of L1 is 0um-60um, excluding the endpoint value; the value range of L2 is 0.3um-1um, including the endpoint value; the value range of L3 is 300nm-500nm, including the endpoint value.

6. The method for manufacturing a micro LED chip according to claim 4, wherein: The photoresist plate also has a first opening, the first opening corresponds to the preset channel area, after exposure and development, the patterned photoresist still reveals the preset channel area, and the substrate is etched along the exposed preset channel area to form the channel, and the cutting alignment structure also includes an etching surface between the channel and the cutting road; Alternatively, the photolithography plate further has a second opening, which corresponds to the channel preset area and the cutting alignment structure. After exposure and development, the patterned photoresist also reveals the channel preset area and the cutting alignment structure. The substrate is etched along the exposed channel preset area to form the channel, and the cutting alignment structure is etched to expose a portion of the first-type semiconductor layer.

7. The method for manufacturing a micro LED chip according to claim 1, wherein: Each sub-epitaxial stack further includes a transparent conductive layer, an insulating layer, a first pad and a second pad; wherein the transparent conductive layer is disposed on the second-type mesa, and the second electrode is deposited on the surface of the transparent conductive layer or is connected to the second-type semiconductor layer by embedding the transparent conductive layer through a first through hole; The insulating layer covers the exposed surfaces of each of the sub-epitaxial stacks, the transparent conductive layer and the channel, and the insulating layer has a second through hole exposing the first electrode and a third through hole exposing the second electrode; The first pad is electrically connected to the first electrode through the second through hole, the second pad is electrically connected to the second electrode through the third through hole, and the first pad is spaced apart from the second pad.

8. The method for manufacturing a micro LED chip according to claim 7, wherein: The insulating layer includes an etching isolation layer and an insulating reflective layer which are sequentially stacked in a direction away from the substrate.

9. The method for manufacturing a micro LED chip according to claim 8, wherein: Forming the second through hole and the third through hole includes: firstly etching the insulating reflective layer to the surface of the etching isolation layer using a first etching gas, and then continuing to etch the exposed etching isolation layer to the surface of the first electrode and the second electrode using a second etching gas to form the second through hole and the third through hole penetrating the insulating reflective layer; The first etching gas includes one or more of CF4 and CHF3; the second etching gas includes one or more of HBr, BCl 3 and HF.

10. The method for manufacturing a micro LED chip according to claim 7, wherein: The first pad and the second pad both extend in directions away from each other to the surface of the insulating layer in a direction perpendicular to the channel, and the first pad and the second pad are located in a region surrounded by the cutting alignment structure.

11. A micro LED chip, characterized in that: The micro LED chip comprises: substrate; An epitaxial stack is arranged on the surface of the substrate, wherein the epitaxial stack comprises: a first-type semiconductor layer, an active region and a second-type semiconductor layer sequentially stacked on the substrate from bottom to top; The epitaxial stack has a cutting path and a channel exposing the surface of the substrate, and the epitaxial stack forms a plurality of mutually spaced sub-epitaxial stacks and a cutting alignment structure corresponding to the sub-epitaxial stack through the cutting path, wherein the cutting alignment structure is spaced from the corresponding sub-epitaxial stack through the channel, the channel is a cutting deviation control line, and each sub-epitaxial stack has a first type mesa exposing a portion of the first type semiconductor layer and a second type mesa exposing the second type semiconductor layer; A first electrode and a second electrode are arranged on each sub-epitaxial stack: The first electrode is arranged on the first type mesa to form contact with the first type semiconductor layer and is insulated from the side wall of the sub-epitaxial stack; The second electrode is disposed on the second-type mesa to form contact with the second-type semiconductor layer, and the first electrode and the second electrode are disposed far apart.

12. The micro LED chip according to claim 11, characterized in that: The cutting alignment structure includes a portion of the epitaxial stack or at least a portion of the first type semiconductor layer.

13. The micro LED chip according to claim 11, characterized in that: The sub-epitaxial stack further includes a transparent conductive layer, an insulating layer, a first pad and a second pad; wherein the transparent conductive layer is disposed on the second-type mesa, and the second electrode is deposited on the surface of the transparent conductive layer or is embedded in the transparent conductive layer through a first through hole to form a connection with the second-type semiconductor layer; The insulating layer covers the exposed surfaces of each of the sub-epitaxial stacks, the transparent conductive layer and the channel, and the insulating layer has a second through hole exposing the first electrode and a third through hole exposing the second electrode; The first pad is electrically connected to the first electrode through the second through hole, the second pad is electrically connected to the second electrode through the third through hole, and the first pad is spaced apart from the second pad.

14. The micro LED chip according to claim 13, characterized in that: The first pad and the second pad both extend in directions away from each other to the surface of the insulating layer in a direction perpendicular to the channel, and the first pad and the second pad are located in a region surrounded by the cutting alignment structure.

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