Light emitting diode and manufacturing method of light emitting diode

Abstract

The invention provides a light-emitting diode and a manufacturing method of the light-emitting diode, and belongs to the field of light-emitting devices. The light-emitting diode comprises an epitaxial structure, a protective layer, a first electrode structure and a second electrode structure, the epitaxial structure comprises a step structure, and the step structure comprises a step top surface and a step bottom surface; the protection layer comprises a first protection layer, the first protection layer is located on the step bottom surface of the step structure, and the first protection layer is in electric contact with the step bottom surface; the first electrode structure is in electric contact with the step top surface of the step structure, and the second electrode structure is in electric contact with the first protection layer. The light-emitting diode structure can prevent the patterning process from damaging the epitaxial structure at the bottom surface of the step, thereby ensuring the quality of the light-emitting diode and avoiding voltage rise.

Description

Technical Field

[0001] The present disclosure relates to the field of light-emitting devices, and in particular to a light-emitting diode and a method for manufacturing the light-emitting diode. Background Art

[0002] Light-emitting diodes are semiconductor light-emitting devices that can be used in display, lighting and other display fields.

[0003] The related art provides a light emitting diode, which includes: an epitaxial structure, an electrode and other structures.

[0004] However, the light emitting diode of the above structure needs to be patterned during manufacture, and the epitaxial structure is easily damaged during the patterning process, which in turn causes the problem of increased chip voltage. Summary of the invention

[0005] The embodiments of the present disclosure provide a light emitting diode and a method for manufacturing the light emitting diode, which can avoid damaging the epitaxial structure. The technical solution is as follows:

[0006] In one aspect, a light emitting diode is provided, the light emitting diode comprising:

[0007] An epitaxial structure, a protective layer, a first electrode structure and a second electrode structure;

[0008] The epitaxial structure includes a step structure, which includes a step top surface and a step bottom surface; the protective layer includes a first protective layer, which is located on the step bottom surface of the step structure, and the first protective layer is electrically in contact with the step bottom surface; the first electrode structure is electrically in contact with the step top surface of the step structure, and the second electrode structure is electrically in contact with the first protective layer.

[0009] Optionally, the protective layer further includes a second protective layer, the second protective layer and the first protective layer are arranged at an interval, the second protective layer is located on a step top surface of the step structure, and the first electrode structure is in electrical contact with the second protective layer.

[0010] Optionally, the light emitting diode further comprises: a dielectric layer, a metal reflective layer, and a passivation layer;

[0011] The dielectric layer is located at the top surface and the bottom surface of the step of the step structure, and the dielectric layer has a first through hole and a second through hole, the first through hole is located at the top surface of the step of the step structure, and the second through hole is located at the bottom surface of the step of the step structure; the metal reflective layer is located on the dielectric layer, and the metal reflective layer is electrically in contact with the top surface of the step of the step structure through the first through hole; the second protective layer covers the metal reflective layer, and the first protective layer is electrically in contact with the bottom surface of the step of the step structure through the second through hole; the passivation layer covers the dielectric layer and the protective layer; the first electrode structure is electrically in contact with the second protective layer through the passivation layer, and the second electrode structure is electrically in contact with the first protective layer through the passivation layer.

[0012] Optionally, the first protective layer is circular, and the radius of the first protective layer is 10-15 μm.

[0013] Optionally, a distance between the second protective layer and the first protective layer is 15-20 μm.

[0014] Optionally, the dielectric layer includes a first dielectric sublayer and a second dielectric sublayer stacked in sequence, the first dielectric sublayer is a silicon oxide layer, and the second dielectric sublayer is a DBR layer;

[0015] The second through hole passes through the first dielectric sublayer and the second dielectric sublayer in sequence, and a diameter of the second through hole in the first dielectric sublayer is smaller than a diameter of the second through hole in the second dielectric sublayer. The first protective layer is located in the second through hole in the first dielectric sublayer.

[0016] Optionally, the protective layer includes a Cr / Al / Ti / Al / Ti / Al / Ti / Pt / Ti stack.

[0017] Optionally, the thickness of each layer in the Cr / Al / Ti / Al / Ti / Al / Ti / Pt / Ti stack is:

[0018]

[0019] Optionally, the passivation layer includes a first passivation sublayer and a second passivation sublayer stacked together, the first passivation sublayer is a DBR layer, and the second passivation sublayer is a silicon oxide layer.

[0020] In another aspect, a method for manufacturing a light emitting diode is provided, the method comprising:

[0021] Fabricating epitaxial structures;

[0022] Performing a patterning process on the epitaxial structure to form a step structure, wherein the step structure includes a step top surface and a step bottom surface;

[0023] Manufacturing a protective layer, wherein the protective layer comprises a first protective layer, the first protective layer is located on a bottom surface of the step structure, and the first protective layer is in electrical contact with the bottom surface of the step;

[0024] A first electrode structure and a second electrode structure are manufactured, wherein the first electrode structure is in electrical contact with the top surface of the step structure, and the second electrode structure is in electrical contact with the first protective layer.

[0025] The technical solution provided by the embodiments of the present disclosure has the following beneficial effects:

[0026] The light-emitting diode provided by the embodiment of the present disclosure includes a protective layer arranged on the bottom surface of the step. On the one hand, the protective layer is used to connect the second electrode structure and the bottom surface of the step structure to play an electrical connection role. On the other hand, when the patterning process is performed during the manufacturing process of the light-emitting diode, the bottom surface of the step of the epitaxial structure is protected, and the patterning process can be prevented from damaging the epitaxial structure at the bottom surface of the step, thereby ensuring the quality of the light-emitting diode and avoiding voltage increase. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0028] Figure 1 is a structural schematic diagram of a light emitting diode provided by an embodiment of the present disclosure;

[0029] Figure 2 is a schematic diagram of the structure of a protective layer provided by an embodiment of the present disclosure;

[0030] Figure 3 is a flow chart of a method for manufacturing a light emitting diode provided by an embodiment of the present disclosure;

[0031] Figure 4 This is a flow chart of another method for manufacturing a light emitting diode provided in an embodiment of the present disclosure.

[0032] The reference numerals are as follows:

[0033] 100: substrate; 101: first semiconductor layer; 102: active layer; 103: second semiconductor layer; 104: transparent conductive layer; 105: dielectric layer; 106: metal reflective layer; 107: protective layer; 108: passivation layer; 109: first electrode structure; 110: second electrode structure; 201: step structure; 151: first through hole; 152: second through hole; 171: second protective layer; 172: first protective layer; 1501: first dielectric sublayer; 1502: second dielectric sublayer; 181: first passivation sublayer; 182: second passivation sublayer; 191: first electrode; 192: first electrode pad; 1101: second electrode; 1102: second electrode pad; 183: third through hole; 184: fourth through hole; 185: fifth through hole; 186: sixth through hole. DETAILED DESCRIPTION

[0034] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0035] Figure 1 is a schematic diagram of the structure of a light emitting diode provided by an embodiment of the present disclosure. Figure 1 The light emitting diode includes: an epitaxial structure 10 , a protective layer 107 , a first electrode structure 109 and a second electrode structure 110 .

[0036] The epitaxial structure 10 includes a step structure 201, and the step structure 201 includes a step top surface and a step bottom surface; the protective layer 107 includes a first protective layer 172, and the first protective layer 172 is located at the bottom surface of the step of the step structure 201, and the first protective layer 172 is electrically contacted with the bottom surface of the step; the first electrode structure 109 is electrically contacted with the top surface of the step of the step structure 201, and the second electrode structure 110 is electrically contacted with the first protective layer 172.

[0037] The light-emitting diode provided by the embodiment of the present disclosure includes a protective layer arranged on the bottom surface of the step. On the one hand, the protective layer is used to connect the second electrode structure and the bottom surface of the step structure to play an electrical connection role. On the other hand, when the patterning process is performed during the manufacturing process of the light-emitting diode, the bottom surface of the step of the epitaxial structure is protected, and the patterning process can be prevented from damaging the epitaxial structure at the bottom surface of the step, thereby ensuring the quality of the light-emitting diode and avoiding voltage increase.

[0038] See again Figure 1 The protective layer 107 further includes a second protective layer 171 , which is spaced apart from the first protective layer 172 . The second protective layer 171 is located on the top surface of the step structure 201 , and the first electrode structure 109 is in electrical contact with the second protective layer 171 .

[0039] In this implementation, in addition to the first protection layer, a second protection layer is also provided to protect the epitaxial quality at the step top surface of the step structure.

[0040] See again Figure 1 , the light emitting diode further includes: a dielectric layer 105, a metal reflective layer 106, and a passivation layer 108;

[0041] The dielectric layer 105 is located at the top and bottom surfaces of the step of the step structure 201, and the dielectric layer 105 has a first through hole 151 and a second through hole 152, wherein the first through hole 151 is located at the top surface of the step of the step structure 201, and the second through hole 152 is located at the bottom surface of the step of the step structure 201; the metal reflective layer 106 is located on the dielectric layer 105, and the metal reflective layer 106 is electrically in contact with the top surface of the step of the step structure 201 through the first through hole 151; the second protective layer 171 covers the metal reflective layer 106, and the first protective layer 172 is electrically in contact with the bottom surface of the step of the step structure 201 through the second through hole 152; the passivation layer 108 covers the dielectric layer 105 and the protective layer 107; the first electrode structure 109 passes through the passivation layer 108 to electrically contact the second protective layer 171, and the second electrode structure 110 passes through the passivation layer 108 to electrically contact the first protective layer 172.

[0042] In the related art, the second electrode structure will pass through the passivation layer to connect to the bottom surface of the step structure, so it is necessary to perform a patterned opening on the passivation layer during the manufacturing process, and the passivation layer opening through which the second electrode structure passes corresponds to the second through hole of the dielectric layer. Therefore, the patterned opening process (for example, ICP etching for the passivation layer DBR) will damage the epitaxial structure at the bottom surface of the step. To this end, the protective layer in the embodiment of the present disclosure includes a second protective layer and a first protective layer, wherein the first protective layer is used to connect the second electrode structure and the bottom surface of the step structure, so that when the passivation layer is opened, the patterning process can be avoided from damaging the epitaxial structure at the bottom surface of the step, thereby ensuring the quality of the light-emitting diode and avoiding voltage increase.

[0043] like Figure 1 As shown, in the embodiment of the present disclosure, the first protection layer 172 may be located in the second through hole 172 .

[0044] Figure 2 Schematic diagram of a protective layer provided by an embodiment of the present disclosure. Figure 2 The first protective layer 172 is circular, and the radius of the first protective layer 172 is 10-15 μm.

[0045] In this implementation, a circular first protective layer is used for easy manufacturing, and the above radius can cooperate with the opening of the dielectric layer to protect the epitaxial structure.

[0046] Exemplarily, the radius of the first protection layer 172 is 11 μm.

[0047] In other implementations, the first protective layer may also be in other shapes, and accordingly, the openings in the dielectric layer match the shape of the first protective layer.

[0048] In the embodiment of the present disclosure, the distance between the second protection layer 171 and the first protection layer 172 is 15-20 μm.

[0049] In this implementation, the above spacing design can avoid short circuits on the one hand, and on the other hand make the gap small enough to prevent light from leaking to the passivation layer as much as possible.

[0050] In the disclosed embodiment, the dielectric layer 105 includes a first dielectric sublayer 1501 and a second dielectric sublayer 1502 stacked in sequence, the first dielectric sublayer 1501 is a silicon oxide layer, and the second dielectric sublayer 1502 is a distributed Bragg reflector (DBR) layer.

[0051] Exemplarily, the first dielectric sublayer 1501 is a SiO 2 layer.

[0052] Exemplarily, the DBR layer may be a stacked layer formed of at least one period of a silicon oxide layer (eg, SiO 2 ) and a titanium oxide layer (eg, Ti 3 O 5 , Ti 2 O 3 ).

[0053] In this implementation, the above structure can achieve both the current blocking effect and the reflection effect, thereby ensuring the light extraction efficiency.

[0054] In the embodiment of the present disclosure, the thickness of the second dielectric sublayer may be 0.3-0.4 micrometers. For example, the thickness of the second dielectric sublayer may be 0.35 micrometers.

[0055] like Figure 1 As shown, the second through hole 152 passes through the first dielectric sublayer 1501 and the second dielectric sublayer 1502 in sequence, and the diameter of the second through hole 152 in the first dielectric sublayer 1501 is smaller than the diameter of the second through hole 152 in the second dielectric sublayer 1502, and the first protective layer 172 is located in the second through hole 152 in the first dielectric sublayer 1501.

[0056] Exemplarily, the size of the first protection layer 172 is smaller than that of the second through hole 152 .

[0057] In other implementations, the second dielectric sub-layer 1502 may also include only a DBR layer.

[0058] In other implementations, the dielectric layer may also only include a silicon oxide layer.

[0059] In the embodiment of the present disclosure, the protection layer 107 may include a combination of a Cr layer, an Al layer, a Ti layer, and a Pt layer.

[0060] For example, the protection layer 107 may include a Cr / Al / Ti / Al / Ti / Al / Ti / Pt / Ti stack.

[0061] Using the above structure as a protective layer can, on the one hand, protect the metal reflective layer to ensure that the epitaxy is not damaged when etching the passivation layer; on the other hand, the structural stack can serve as an ohmic contact layer between the epitaxy and the electrode to ensure electrical connection between the electrode and the epitaxy.

[0062] In the embodiment of the present disclosure, the thickness of each layer in the Cr / Al / Ti / Al / Ti / Al / Ti / Pt / Ti stack is:

[0063] In this implementation, the protective layer is composed of layers within the above-mentioned thickness range, which can achieve a protective effect, avoid excessive thickness, and is conducive to making the LED thinner and lighter.

[0064] Exemplarily, the thickness of each layer in the Cr / Al / Ti / Al / Ti / Al / Ti / Pt / Ti stack is:

[0065] In the embodiment of the present disclosure, the passivation layer 108 includes a stacked first passivation sublayer 181 and a second passivation sublayer 182 , the first passivation sublayer 181 is a DBR layer, and the second passivation sublayer 182 is a silicon oxide layer.

[0066] Exemplarily, the second passivation sublayer 182 is a SiO 2 layer.

[0067] Exemplarily, the DBR layer may be a stacked layer formed of at least one period of a silicon oxide layer (eg, SiO 2 ) and a titanium oxide layer (eg, Ti 3 O 5 , Ti 2 O 3 ).

[0068] When using the DBR structure, the passivation layer needs to be etched using inductively coupled plasma (ICP). When the passivation layer is etched using ICP, the epitaxial structure is easily damaged. Using the first protective layer 172 for protection can solve the epitaxial damage problem.

[0069] Of course, the passivation layer may also be other structures that are etched using ICP, and the embodiments of the present disclosure are not limited to this.

[0070] like Figure 1 As shown, the epitaxial structure 10 includes a first semiconductor layer 101 , an active layer 102 and a second semiconductor layer 103 stacked in sequence, the bottom surface of the step structure is located in the first semiconductor layer 101 , and the top surface of the step structure is located in the second semiconductor layer 103 .

[0071] The light emitting diode further comprises a substrate 100 , and a first semiconductor layer 101 , an active layer 102 and a second semiconductor layer 103 are sequentially stacked on the surface of the substrate 100 .

[0072] like Figure 1 As shown, the first electrode structure 109 includes a first electrode 191 and a first electrode pad 192 , and the second electrode structure 110 includes a second electrode 1101 and a second electrode pad 1102 .

[0073] The first passivation sublayer 181 covers the dielectric layer 105 and the protective layer 107 .

[0074] The first electrode 191 is connected to the second protection layer 171 through the third through hole 183 of the first passivation sublayer 181 , and the second electrode 1101 is connected to the first protection layer 172 through the fourth through hole 184 of the first passivation sublayer 181 .

[0075] The second passivation sublayer 182 covers the first passivation sublayer 181 , the first electrode 191 , and the second electrode 1101 .

[0076] The first electrode pad 192 is connected to the first electrode 191 through the fifth through hole 185 of the second passivation sublayer 182 , and the second electrode pad 1102 is connected to the second electrode 1101 through the sixth through hole 186 of the second passivation sublayer 182 .

[0077] It should be noted that, due to the cross-sectional position, the figure only shows the electrode structure connected to the left epitaxial structure, and does not fully show all the electrode structures connected to the right epitaxial structure.

[0078] Optionally, the light emitting diode further includes a transparent conductive layer 104 , which is located between the epitaxial structure 10 and the dielectric layer 105 , and the metal reflective layer 106 is connected to the epitaxial structure 10 through the transparent conductive layer 104 .

[0079] In the embodiment of the present disclosure, the substrate 100 may be any one of a sapphire substrate, a silicon substrate, etc., and the present disclosure does not limit the material of the substrate.

[0080] Exemplarily, the substrate 100 is a sapphire substrate.

[0081] In the embodiment of the present disclosure, the first semiconductor layer 101 may be an N-type semiconductor layer, the active layer 102 may be a multi-quantum well layer, and the second semiconductor layer 103 may be a P-type semiconductor layer.

[0082] Exemplarily, the first semiconductor layer 101 is an N-type GaN layer, the active layer 102 is an InGaN / GaN layer, and the second semiconductor layer 103 is a P-type GaN layer.

[0083] In another example, the first semiconductor layer 101 may be a P-type semiconductor layer, the active layer 102 may be a multi-quantum well layer, and the second semiconductor layer 103 may be an N-type semiconductor layer.

[0084] In the embodiment of the present disclosure, the transparent conductive layer 104 may be an indium tin oxide (ITO) layer.

[0085] In the embodiment of the present disclosure, the metal reflective layer 106 may be an Ag layer, or a stack of Ag, Ni, and TiW.

[0086] In the embodiment of the present disclosure, the first electrode 191 and the second electrode 1101 include a Cr layer, an Al layer, a Ti layer, a Ni layer, a Pt layer, and an Au layer stacked in sequence.

[0087] In the embodiment of the present disclosure, the first electrode pad 192 and the second electrode pad 1102 include a Ti layer, an Al layer, a Ni layer, a Pt layer, an Au layer, and an AuSn layer stacked in sequence.

[0088] In one example, when the second semiconductor layer 103 is an N-type semiconductor layer, the first electrode 191 is an N-electrode, and the first electrode pad 192 is an N-electrode pad; when the first semiconductor layer 101 is a P-type semiconductor layer, the second electrode 1101 is a P-electrode, and the second electrode pad 1102 is a P-electrode pad.

[0089] In another example, when the second semiconductor layer 103 is a P-type semiconductor layer, the first electrode 191 is a P-electrode, and the first electrode pad 192 is a P-electrode pad; when the first semiconductor layer 101 is an N-type semiconductor layer, the second electrode 1101 is an N-electrode, and the second electrode pad 1102 is an N-electrode pad.

[0090] Figure 3 A method for manufacturing a light emitting diode is provided in an embodiment of the present disclosure. Figure 3 The method steps include:

[0091] S11. Fabricating an epitaxial structure.

[0092] The epitaxial structure includes a first semiconductor layer, an active layer and a second semiconductor layer stacked in sequence.

[0093] In the embodiment of the present disclosure, the first semiconductor layer may be an N-type semiconductor layer, the active layer may be a multi-quantum well layer, and the second semiconductor layer may be a P-type semiconductor layer.

[0094] Exemplarily, the first semiconductor layer is an N-type GaN layer, the active layer is an InGaN / GaN layer, and the second semiconductor layer is a P-type GaN layer.

[0095] S12, performing a patterning process on the epitaxial structure to form a step structure.

[0096] Illustratively, a bottom surface of the step of the step structure is located in the first semiconductor layer, and a top surface of the step of the step structure is located in the second semiconductor layer.

[0097] S13, manufacturing a protective layer, wherein the protective layer comprises a first protective layer, the first protective layer is located on a bottom surface of the step of the step structure, and the first protective layer is in electrical contact with the bottom surface of the step.

[0098] S14, manufacturing a first electrode structure and a second electrode structure, wherein the first electrode structure is in electrical contact with a top surface of the step structure, and the second electrode structure is in electrical contact with the first protective layer.

[0099] The light-emitting diode provided by the embodiment of the present disclosure includes a protective layer arranged on the bottom surface of the step. On the one hand, the protective layer is used to connect the second electrode structure and the bottom surface of the step structure to play an electrical connection role. On the other hand, when the patterning process is performed during the manufacturing process of the light-emitting diode, the bottom surface of the step of the epitaxial structure is protected, and the patterning process can be prevented from damaging the epitaxial structure at the bottom surface of the step, thereby ensuring the quality of the light-emitting diode and avoiding voltage increase.

[0100] Figure 4 This is a flow chart of another method for manufacturing a light emitting diode provided in an embodiment of the present disclosure. Figure 4 The method steps include:

[0101] S21. A first semiconductor layer, an active layer, and a second semiconductor layer are sequentially formed on a surface of a substrate, wherein the first semiconductor layer, the active layer, and the second semiconductor layer are in a step structure.

[0102] In the embodiment of the present disclosure, the first semiconductor layer is an N-type GaN layer, the active layer is an InGaN / GaN layer, and the second semiconductor layer is a P-type GaN layer.

[0103] In one example, step S21 includes:

[0104] The first step is to grow the first semiconductor layer.

[0105] Wherein, the first semiconductor layer is an N-type GaN layer.

[0106] For example, a Metal Organic Chemical Vapor Deposition (MOCVD) device is used to grow an N-type GaN layer on the surface of a substrate.

[0107] In the disclosed embodiment, the growth of the semiconductor layer can be achieved by using Veeco K465i or C4 or RB MOCVD equipment or AIXTRON metal organic compound chemical vapor deposition equipment. High purity H2 (hydrogen) or high purity N2 (nitrogen) or a mixture of high purity H2 and high purity N2 is used as a carrier gas, high purity NH3 is used as an N source, trimethyl gallium (TMGa) and triethyl gallium (TEGa) are used as gallium sources, trimethyl indium (TMIn) is used as an indium source, silane (SiH4) is used as an N-type dopant, trimethyl aluminum (TMAl) is used as an aluminum source, and bis(cyclopentadienyl) magnesium (CP2Mg) is used as a P-type dopant.

[0108] The second step is to grow the active layer.

[0109] Among them, the active layer is an InGaN / GaN layer.

[0110] Exemplarily, an InGaN / GaN layer is grown on the surface of the N-type GaN layer using MOCVD equipment.

[0111] The third step is to grow the second semiconductor layer.

[0112] Wherein, the second semiconductor layer is a P-type GaN layer.

[0113] Exemplarily, a P-type GaN layer is grown on the surface of the InGaN / GaN layer using MOCVD equipment.

[0114] In the fourth step, the first semiconductor layer, the active layer and the second semiconductor layer are patterned to form a step structure.

[0115] Exemplarily, the ICP etching technology is used to pattern the first semiconductor layer, the active layer, and the second semiconductor layer stacked in sequence in the epitaxial structure to form a step structure.

[0116] S22, manufacturing a transparent conductive layer, wherein the transparent conductive layer is located on the second semiconductor layer.

[0117] In one example, step S22 includes:

[0118] Wherein, the transparent conductive layer is an ITO layer.

[0119] This step may include: forming an ITO film on the surface of the second semiconductor layer using magnetron sputtering technology; forming a photoresist mask pattern on the ITO film; and performing patterning with an ITO etching solution under the shielding of the photoresist mask pattern to form an ITO layer.

[0120] It should be noted that if a photoresist mask pattern is used in the method provided in the embodiment of the present disclosure, a stripping step is also included after use, which will not be described in detail here.

[0121] S23, manufacturing a dielectric layer on the epitaxial structure, wherein the dielectric layer has a first through hole and a second through hole, wherein the first through hole is located on a top surface of the step of the step structure, and the second through hole is located on a bottom surface of the step of the step structure.

[0122] In the embodiment of the present disclosure, the dielectric layer 105 includes a first dielectric sublayer 1501 and a second dielectric sublayer 1502 stacked in sequence, the first dielectric sublayer 1501 is a silicon oxide layer, and the second dielectric sublayer 1502 is a DBR layer.

[0123] Exemplarily, the first dielectric sublayer is a SiO2 layer.

[0124] Exemplarily, the DBR layer may be a stacked layer formed of at least one period of a silicon oxide layer (eg, SiO 2 ) and a titanium oxide layer (eg, Ti 3 O 5 , Ti 2 O 3 ).

[0125] In this implementation, the above structure can achieve both the current blocking effect and the reflection effect, thereby ensuring the light extraction efficiency.

[0126] In the embodiment of the present disclosure, the thickness of the second dielectric sublayer may be 0.3-0.4 micrometers. For example, the thickness of the second dielectric sublayer may be 0.35 micrometers.

[0127] like Figure 1 As shown, the second through hole 152 passes through the first dielectric sublayer 1501 and the second dielectric sublayer 1502 in sequence, and the diameter of the second through hole 152 in the first dielectric sublayer 1501 is smaller than the diameter of the second through hole 152 in the second dielectric sublayer 1502, and the first protective layer 172 is located in the second through hole 152 in the first dielectric sublayer 1501.

[0128] In other implementations, the second dielectric sub-layer 1502 may also include only a DBR layer.

[0129] In other implementations, the dielectric layer may also only include a silicon oxide layer.

[0130] In one example, step S23 includes:

[0131] A first dielectric sublayer film covering a transparent conductive layer is deposited on the surface of the second semiconductor layer; a second dielectric sublayer film is evaporated on the first dielectric sublayer film; the second dielectric sublayer film is patterned (opened) by ICP etching technology to obtain a second dielectric sublayer; the first dielectric sublayer film is patterned (opened) by wet etching technology to obtain a first dielectric sublayer.

[0132] It is worth noting that different mask patterns are used during ICP etching and wet etching, so that the size of the through hole etched in the first dielectric sub-layer is smaller than the size of the through hole etched in the second dielectric sub-layer.

[0133] Since the first dielectric sub-layer is patterned by wet etching, the buffered oxide etch (BOE) solution used will not damage the semiconductor layer.

[0134] It should be noted that the first dielectric sublayer film is the same as the first dielectric sublayer material, and the second dielectric sublayer film is the same as the second dielectric sublayer material, and the difference is only in the pattern.

[0135] S24, manufacturing a metal reflective layer on the surface of the dielectric layer, wherein the metal reflective layer is connected to the surface of the epitaxial structure through the first through hole.

[0136] Exemplarily, step S24 includes:

[0137] A photoresist mask pattern is formed; under the shielding of the photoresist mask pattern, a metal reflective layer is formed on the surface of the dielectric layer by using magnetron sputtering technology, and the metal reflective layer is connected to the transparent conductive layer through the first through hole.

[0138] In the embodiment of the present disclosure, the metal reflective layer 106 may be an Ag layer, or a stack of Ag, Ni, and TiW.

[0139] S25, manufacturing a protective layer, wherein the protective layer comprises a second protective layer and a first protective layer which are arranged at an interval, wherein the second protective layer covers the metal reflective layer, and the first protective layer is in electrical contact with the step bottom surface of the step structure through the second through hole.

[0140] In the embodiment of the present disclosure, the first protection layer 172 may be located in the second through hole 172 .

[0141] Exemplarily, step S25 includes:

[0142] A photoresist mask pattern is formed, and the photoresist mask pattern corresponds to the area between the second protective layer and the first protective layer; under the shielding of the photoresist mask pattern, an electron beam vacuum evaporation technology is used to form a protective layer on the metal reflective layer.

[0143] See also Figure 2 The first protective layer 172 is circular, and the radius of the first protective layer 172 is 10-15 μm.

[0144] In this implementation, a circular first protective layer is used for easy manufacturing, and the above radius can cooperate with the opening of the dielectric layer to protect the epitaxial structure.

[0145] Exemplarily, the radius of the first protection layer 172 is 11 μm.

[0146] In other implementations, the first protective layer may also be in other shapes, and accordingly, the openings in the dielectric layer match the shape of the first protective layer.

[0147] In the embodiment of the present disclosure, the distance between the second protection layer 171 and the first protection layer 172 is 15-20 μm.

[0148] In this implementation, the above spacing design can avoid short circuits on the one hand, and on the other hand make the gap small enough to prevent light from leaking to the passivation layer as much as possible.

[0149] In the embodiment of the present disclosure, the protection layer 107 may include a combination of a Cr layer, an Al layer, a Ti layer, and a Pt layer.

[0150] For example, the protection layer 107 may include a Cr / Al / Ti / Al / Ti / Al / Ti / Pt / Ti stack.

[0151] The above structure is used as a protective layer. On the one hand, it can protect the metal reflective layer and ensure that the epitaxy will not be damaged when etching the passivation layer. On the other hand, the structural stack can serve as an ohmic contact layer between the epitaxy and the electrode to ensure the electrical connection between the electrode and the epitaxy.

[0152] In the embodiment of the present disclosure, the thickness of each layer in the Cr / Al / Ti / Al / Ti / Al / Ti / Pt / Ti stack is:

[0153] In this implementation, the protective layer is composed of layers within the above-mentioned thickness range, which can achieve a protective effect, avoid excessive thickness, and is conducive to making the LED thinner and lighter.

[0154] Exemplarily, the thickness of each layer in the Cr / Al / Ti / Al / Ti / Al / Ti / Pt / Ti stack is:

[0155] S26 , manufacturing a first passivation sublayer, wherein the first passivation sublayer covers the dielectric layer and the protective layer.

[0156] In one example, the first passivation sublayer is a DBR layer.

[0157] In one example, step S26 includes: depositing a first passivation sublayer film; forming a third through hole and a fourth through hole in the first passivation sublayer film by a patterning technique to obtain a first passivation sublayer.

[0158] The fourth through hole is connected to the second through hole, that is, corresponds to the first protective layer of the protective layer. The third through hole and the fourth through hole are opened by ICP etching. When opening, the first protective layer of the protective layer can prevent ICP etching from damaging the epitaxial structure at the bottom of the step.

[0159] S27, manufacturing a first electrode and a second electrode, wherein the first electrode is connected to the second protective layer through the third through hole of the first passivation sublayer, and the second electrode is connected to the first protective layer through the fourth through hole of the first passivation sublayer.

[0160] In one example, step S27 includes:

[0161] The first electrode and the second electrode are manufactured by electron beam evaporation technology.

[0162] In the embodiment of the present disclosure, the first electrode 191 and the second electrode 1101 include a Cr layer, an Al layer, a Ti layer, a Ni layer, a Pt layer, and an Au layer stacked in sequence.

[0163] S28, manufacturing a second passivation sublayer, wherein the second passivation sublayer covers the first passivation sublayer, the first electrode, and the second electrode.

[0164] In one example, the second passivation sublayer may be a silicon oxide layer.

[0165] In one example, step S28 includes: depositing a second passivation sublayer film; forming a fifth through hole and a sixth through hole in the second passivation sublayer film by a patterning technique to obtain a second passivation sublayer.

[0166] The sixth through hole is connected to the fourth through hole and the second through hole, that is, it corresponds to the first protective layer of the protective layer. The fifth through hole and the sixth through hole are opened by wet etching.

[0167] S29, manufacturing a first electrode pad and a second electrode pad, wherein the first electrode pad is connected to the first electrode through the fifth through hole of the second passivation sublayer, and the second electrode pad is connected to the second electrode through the sixth through hole of the second passivation sublayer.

[0168] In one example, step S29 includes:

[0169] The first electrode pad and the second electrode pad are manufactured by electron beam evaporation technology.

[0170] In the embodiment of the present disclosure, the first electrode pad 192 and the second electrode pad 1102 include a Ti layer, an Al layer, a Ni layer, a Pt layer, an Au layer, and an AuSn layer stacked in sequence.

[0171] Table 1 below is a comparative test data table of the LED structure provided by the embodiment of the present disclosure and the LED structure of the related technology. Under the condition of a point measurement current of 65mA, the difference in photoelectric parameters between the LED provided by the related technical solution (the first protective layer without a protective layer) and the embodiment of the present disclosure is compared. From the test results of the chip, when the voltage of the LED provided by the embodiment of the present disclosure is 0.577V lower than the chip voltage of the original technical solution, the brightness of the two is equivalent. This shows that the LED provided by the embodiment of the present disclosure effectively blocks the damage of the ICP to the first semiconductor layer during the etching of the DBR (passivation layer), thereby avoiding the problem of voltage increase.

[0172] In Table 1, VF1 is voltage, unit is V; LOP is brightness, unit is mW; WLD is wavelength, unit is nm.

[0173] Table 1

[0174]

[0175]

[0176] In the related art, the second electrode structure will pass through the passivation layer to connect to the bottom surface of the step structure, so it is necessary to perform a patterned opening on the passivation layer during the manufacturing process, and the passivation layer opening through which the second electrode structure passes corresponds to the second through hole of the dielectric layer. Therefore, the patterned opening process (for example, ICP etching for the passivation layer DBR) will damage the epitaxial structure at the bottom surface of the step. To this end, the protective layer in the embodiment of the present disclosure includes a second protective layer and a first protective layer, wherein the first protective layer is used to connect the second electrode structure and the bottom surface of the step structure, so that when the passivation layer is opened, the patterning process can be avoided from damaging the epitaxial structure at the bottom surface of the step, thereby ensuring the quality of the light-emitting diode and avoiding voltage increase.

[0177] The above description is only an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A light emitting diode, characterized in that: The light emitting diode comprises: An epitaxial structure (10), a protective layer (107), a first electrode structure (109) and a second electrode structure (110); The epitaxial structure (10) comprises a step structure (201), wherein the step structure (201) comprises a step top surface and a step bottom surface; the protective layer (107) comprises a first protective layer (172), wherein the first protective layer (172) is located at the step bottom surface of the step structure (201), and the first protective layer (172) is in electrical contact with the step bottom surface; the first electrode structure (109) is in electrical contact with the step top surface of the step structure (201), and the second electrode structure (110) is in electrical contact with the first protective layer (172).

2. The light emitting diode according to claim 1, characterized in that: The protective layer (107) further comprises a second protective layer (171), the second protective layer (171) and the first protective layer (172) being arranged at an interval, the second protective layer (171) being located on the top surface of the step of the step structure (201), and the first electrode structure (109) being in electrical contact with the second protective layer (171).

3. The light emitting diode according to claim 2, characterized in that: The light emitting diode further comprises: a dielectric layer (105), a metal reflective layer (106), and a passivation layer (108); The dielectric layer (105) is located on the top surface and the bottom surface of the step of the step structure (201); the dielectric layer (105) has a first through hole (151) and a second through hole (152); the first through hole (151) is located on the top surface of the step of the step structure (201); and the second through hole (152) is located on the bottom surface of the step of the step structure (201); the metal reflective layer (106) is located on the dielectric layer (105); the metal reflective layer (106) is connected to the top surface of the step of the step structure (201) through the first through hole (151). The invention relates to a method for electrically contacting a step structure (201) and a second protective layer (171) for electrically contacting the second protective layer (171); the second protective layer (172) is electrically contacted with the step bottom surface of the step structure (201) through the second through hole (152); the passivation layer (108) is electrically contacted with the dielectric layer (105) and the protective layer (107); the first electrode structure (109) is electrically contacted with the second protective layer (171) through the passivation layer (108); and the second electrode structure (110) is electrically contacted with the first protective layer (172) through the passivation layer (108).

4. The light emitting diode according to claim 2 or 3, characterized in that: The distance between the second protective layer (171) and the first protective layer (172) is 15-20 μm.

5. The light emitting diode according to any one of claims 1 to 4, characterized in that: The first protective layer (172) is circular, and the radius of the first protective layer (172) is 10-15 μm.

6. The light emitting diode according to claim 3, characterized in that: The dielectric layer (105) comprises a first dielectric sublayer (1501) and a second dielectric sublayer (1502) which are stacked in sequence, the first dielectric sublayer (1501) being a silicon oxide layer, and the second dielectric sublayer (1502) being a DBR layer; The second through hole (152) passes through the first dielectric sublayer (1501) and the second dielectric sublayer (1502) in sequence, and the diameter of the second through hole (152) in the first dielectric sublayer (1501) is smaller than the diameter of the second through hole (152) in the second dielectric sublayer (1502), and the first protective layer (172) is located in the second through hole (152) in the first dielectric sublayer (1501).

7. The light emitting diode according to any one of claims 1 to 6, characterized in that: The protective layer (107) includes a Cr / Al / Ti / Al / Ti / Al / Ti / Pt / Ti stack.

8. The light emitting diode according to claim 7, characterized in that: The thickness of each layer in the Cr / Al / Ti / Al / Ti / Al / Ti / Pt / Ti stack is:

9. The light emitting diode according to claim 3, characterized in that: The passivation layer (108) comprises a first passivation sublayer (181) and a second passivation sublayer (182) which are stacked, wherein the first passivation sublayer (181) is a DBR layer, and the second passivation sublayer (182) is a silicon oxide layer.

10. A method for manufacturing a light emitting diode, characterized in that: The method comprises: fabricating epitaxial structures; Performing a patterning process on the epitaxial structure to form a step structure, wherein the step structure includes a step top surface and a step bottom surface; Manufacturing a protective layer, wherein the protective layer comprises a first protective layer, the first protective layer is located on a bottom surface of the step structure, and the first protective layer is in electrical contact with the bottom surface of the step; A first electrode structure and a second electrode structure are manufactured, wherein the first electrode structure is in electrical contact with the top surface of the step structure, and the second electrode structure is in electrical contact with the first protective layer.

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