A control circuit for a five-level full-bridge inverter

Abstract

The application discloses a control circuit of a five-level full-bridge inverter in the technical field of power electronics, and the five-level full-bridge inverter comprises a high-frequency bridge arm and a low-frequency bridge arm, the high-frequency bridge arm comprises four SiC tubes and two Si tubes, and the low-frequency bridge arm comprises two Si tubes; the control circuit comprises a closed-loop control circuit and a driving modulation circuit; the closed-loop control circuit comprises a sampling circuit and a closed-loop controller, the sampling circuit is used for collecting the current and voltage of the output end of the five-level full-bridge inverter; the closed-loop controller obtains the current and voltage of the output end of the five-level full-bridge inverter to generate a modulation signal; the driving modulation circuit obtains the modulation signal generated by the closed-loop controller to generate a driving signal, and sequentially drives the four SiC tubes to take turns to bear the switching loss, so that the switching losses among all the switching tubes are balanced, and the power level and conversion efficiency of the inverter are improved.

Description

Technical Field

[0001] This invention relates to the field of power electronics technology, and in particular to a control circuit for a five-level full-bridge inverter. Background Technology

[0002] With the increasing severity of environmental problems, traditional power generation methods are increasingly unable to meet people's demands for environmental protection. New energy power generation has gained a foothold in the current power generation model, and inverters, as the connection hub between new energy power generation and the power grid, play a crucial role in this process. Furthermore, flexible interconnection of distribution networks can mitigate grid voltage and frequency fluctuations caused by intermittent power output from new energy sources, and single-phase full-bridge inverters are key equipment in flexible distribution network interconnection. Five-level inverters have become a research hotspot due to their advantages such as multiple output levels, low output current harmonics, and excellent output performance.

[0003] Power electronic inverters have always pursued high efficiency, high power density, and high reliability. Inverters based on traditional Si devices are limited by the performance bottlenecks of Si devices themselves, making it difficult to achieve significant improvements in power and efficiency. Compared to inverters using all SiC devices, hybrid inverters combining SiC and Si devices offer a better balance between performance and cost. ANPC circuits, with their simple structure and numerous redundant modes, have become a hot research topic in recent years for the hybrid application of SiC and Si devices. Furthermore, multilevel converters can achieve higher voltage levels and can be used in higher power applications. Applying hybrid SiC and Si ANPC bridge arms to a five-level converter topology can significantly improve the converter's power density and conversion efficiency.

[0004] For example, the paper "A Megawatt-scale Medium-voltage High-efficiency High Power Density 'SiC+Si' Hybrid Three-level ANPC Inverter for Aircraft Hybrid-electric Propulsion Systems" proposes a 4-SiC hybrid ANPC bridge arm modulation strategy to concentrate the converter switching losses on the four SiC devices. However, due to the topology characteristics of the three-level ANPC converter, the loss distribution of the four SiC devices is severely unbalanced, and the performance advantages of all SiC devices cannot be fully utilized.

[0005] For example, the paper "Five-Level Hybrid Active-NPC H-Bridge Converter With Novel Space-Vector-Modulation Scheme" proposes a 2-SiC hybrid ANPC five-level converter topology and modulation strategy, which can concentrate the switching losses on the SiC devices and does not have the problem of loss equalization; however, the high temperature of the two SiC devices limits the further development of the converter power level. Summary of the Invention

[0006] The purpose of this invention is to overcome the shortcomings of the prior art and provide a control circuit for a five-level full-bridge inverter. By applying the 4-SiC ANPC bridge arm to the five-level full-bridge inverter, in the control strategy, the four SiC power transistors take turns bearing the open-circuit loss within one power frequency cycle, which optimizes the loss distribution of SiC devices, fully utilizes the performance advantages of all SiC devices, and improves the efficiency and power rating of the inverter.

[0007] To achieve the above objectives, the present invention is implemented using the following technical solution:

[0008] This invention provides a control circuit for a five-level full-bridge inverter, including a closed-loop control circuit and a drive modulation circuit; the closed-loop control circuit includes a sampling circuit and a closed-loop controller, the sampling circuit is used to acquire the current and voltage at the output terminal of the five-level full-bridge inverter; the closed-loop controller acquires the current and voltage at the output terminal of the five-level full-bridge inverter to generate a modulation signal;

[0009] The driving modulation circuit includes first to seventh comparators, first to fourteenth multipliers, first to sixth OR gates, first to seventh inverters, and first to eighth driving circuits;

[0010] The modulation signal is input to the positive input terminals of the first, third, fourth, and seventh comparators; the negative modulation signal is input to the positive input terminals of the second, fifth, and sixth comparators; and a DC bias signal is input to the negative input terminals of the first and second comparators. The negative input terminal of the third comparator is grounded; the negative input terminals of the fourth and sixth comparators receive carrier signals. The negative input terminals of the fifth and seventh comparators receive carrier signals. ;

[0011] The input terminals of the first to seventh inverters are respectively connected to the output terminals of the first to seventh comparators; the output terminal of the first inverter is respectively connected to the first input terminal of the first multiplier and the second input terminals of the fourth and sixth multipliers; the output terminal of the second inverter is respectively connected to the first input terminal of the second multiplier and the second input terminals of the tenth and twelfth multipliers; the output terminal of the third inverter is respectively connected to the second input terminals of the second, ninth, and eleventh multipliers and the input terminal of the seventh driving circuit; the output terminals of the fourth, fifth, sixth, and seventh inverters are respectively connected to the first input terminals of the fifth, eighth, eleventh, and fourteenth multipliers.

[0012] The output of the first comparator is connected to the second input of the second OR gate and the thirteenth and fourteenth multipliers; the output of the second comparator is connected to the second input of the first OR gate and the seventh and eighth multipliers; the output of the third comparator is connected to the second input of the first, third, and fifth multipliers and the input of the eighth driving circuit; the outputs of the fourth, fifth, sixth, and seventh comparators are respectively connected to the first input of the third, seventh, ninth, and thirteenth multipliers.

[0013] The output of the first multiplier is connected to the first input of the first OR gate; the output of the second multiplier is connected to the first input of the second OR gate; the outputs of the third, fifth, ninth, and eleventh multipliers are respectively connected to the first inputs of the fourth, sixth, tenth, and twelfth multipliers; the outputs of the fourth, sixth, tenth, and twelfth multipliers are respectively connected to the first inputs of the fourth, third, sixth, and fifth OR gates; the outputs of the seventh, eighth, thirteenth, and fourteenth multipliers are respectively connected to the second inputs of the third, fourth, fifth, and sixth OR gates.

[0014] The input terminals of the first to sixth drive circuits are respectively connected to the output terminals of the fifth, sixth, fourth, third, second, and first OR gates, and the output terminals of the first to eighth drive circuits are respectively connected to the drive terminals of the five-level full-bridge inverter.

[0015] Optionally, the five-level full-bridge inverter includes a high-frequency bridge arm and a low-frequency bridge arm; the high-frequency bridge arm includes a switching transistor connected in series between the positive and negative terminals of the DC-side bus. Switching transistor Switching transistor and switching transistors The switching transistor and the switching transistor The common terminal and the switch transistor and the switching transistor A switching transistor is connected in series between the common terminals. and switching transistor The low-frequency bridge arm includes a switching transistor connected in series between the positive and negative terminals of the DC-side bus. and switching transistor The switching transistor and the switching transistor The common terminal and the switch transistor and the switching transistor The common terminals are connected in series between the positive and negative poles of the AC side bus; the output terminals of the first to eighth drive circuits are respectively connected to the switching transistors. The gate.

[0016] Optionally, the switching transistor The switching transistor The switching transistor and the switching transistor It is a SiC tube.

[0017] Optionally, a voltage-dividing capacitor is also connected in series between the positive and negative terminals of the DC side bus. and voltage divider capacitors The voltage divider capacitor and the voltage divider capacitor The common terminal and the switch transistor and the switching transistor The common terminal is connected and used as a neutral point.

[0018] Optionally, a filter inductor is also connected in series between the positive and negative terminals of the AC side bus. and load resistance The load resistor A filter capacitor is connected in parallel. The filter inductor and the filter capacitor This forms an LC filter circuit.

[0019] Optionally, the sampling circuit includes a current sampling circuit and a voltage sampling circuit, wherein the current sampling circuit acquires data from the filter inductor. The voltage sampling circuit collects the current from the load resistance. The voltage is used as the current and voltage at the output of the five-level full-bridge inverter.

[0020] Optionally, when the modulation signal is greater than the DC bias signal Switching transistor Switching transistor and switching transistors Acquired drive signals Normally low, switching transistor and switching transistor Acquired drive signal Constantly high, switching transistor and switching transistor Acquired drive signals High-frequency actions;

[0021] When the modulation signal is greater than zero and less than the DC bias signal Switching transistor Switching transistor and switching transistors Acquired drive signals Normally low, switching transistor and switching transistor Acquired drive signal Constantly high, switching transistor and switching transistor Acquired drive signals High-frequency actions;

[0022] When the modulation signal is greater than the DC bias signal Negative value and less than zero, switching transistor Switching transistor and switching transistors Acquired drive signals Normally low, switching transistor and switching transistor Acquired drive signal Constantly high, switching transistor and switching transistor Acquired drive signals High-frequency actions;

[0023] When the modulation signal is less than the DC bias signal Negative value, switching transistor Switching transistor and switching transistors Acquired drive signals Normally low, switching transistor and switching transistor Acquired drive signal Constantly high, switching transistor and switching transistor Acquired drive signals High-frequency action.

[0024] Compared with the prior art, the beneficial effects achieved by the present invention are as follows:

[0025] The control circuit of the five-level full-bridge inverter provided by this invention is set on a five-level full-bridge inverter containing a high-frequency bridge arm composed of four SiC power transistors. The control circuit generates modulation signals from the current and voltage at the output of the five-level full-bridge inverter, which are then used by a modulation circuit to generate drive signals. These drive signals are then generated by a drive modulation circuit to drive and control the five-level full-bridge inverter. This allows the four SiC power transistors to take turns bearing the open-circuit losses within one power frequency cycle, optimizing the loss distribution of the SiC devices and improving the inverter's efficiency. Simultaneously, by fully utilizing the performance advantages of all SiC power devices, the power rating of the inverter is significantly improved. Attached Figure Description

[0026] Figure 1 This is a structural block diagram of the five-level full-bridge inverter and its control circuit provided in an embodiment of the present invention;

[0027] Figure 2 This is a circuit diagram of a five-level full-bridge inverter provided in an embodiment of the present invention;

[0028] Figure 3 This is a circuit diagram of a five-level full-bridge inverter and its control circuit provided in an embodiment of the present invention;

[0029] Figure 4 This is a modulation waveform diagram of a five-level full-bridge inverter provided in an embodiment of the present invention;

[0030] Figure 5 The positive half-cycle bridge arm output voltage of the five-level full-bridge inverter provided in this embodiment of the invention is... and Switching circuit mode diagram;

[0031] Figure 6 The positive half-cycle bridge arm output voltage of the five-level full-bridge inverter provided in this embodiment of the invention is... and Switching circuit mode diagram. Detailed Implementation

[0032] The present invention will be further described below with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present invention, and should not be used to limit the scope of protection of the present invention.

[0033] Example 1:

[0034] like Figure 1As shown, this embodiment of the invention provides a control circuit for a five-level full-bridge inverter, including a closed-loop control circuit and a drive modulation circuit. The closed-loop control circuit includes a sampling circuit and a closed-loop controller. The sampling circuit is used to collect the current and voltage at the output terminal of the five-level full-bridge inverter. The closed-loop controller obtains the current and voltage at the output terminal of the five-level full-bridge inverter to generate a modulation signal. The drive modulation circuit obtains the modulation signal generated by the closed-loop controller to generate a drive signal. The five-level full-bridge inverter obtains the drive signal generated by the drive modulation circuit for drive control.

[0035] like Figure 2 As shown, the five-level full-bridge inverter provided in this embodiment of the invention includes a high-frequency bridge arm and a low-frequency bridge arm; the high-frequency bridge arm includes a switching transistor connected in series between the positive and negative terminals of the DC side bus. Switching transistor Switching transistor and switching transistors Switching transistor and switching transistor common terminal and switching transistor and switching transistor A switching transistor is connected in series between the common terminals. and switching transistor The low-frequency bridge arm includes a switching transistor connected in series between the positive and negative terminals of the DC-side bus. and switching transistor Switching transistor and switching transistor common terminal and switching transistor and switching transistor The common terminals are connected in series between the positive and negative poles of the AC bus; the output terminals of the first to eighth drive circuits are respectively connected to the switching transistors. The gate of the switch. Switching transistor Switching transistor and switching transistors It is a SiC tube.

[0036] A voltage divider capacitor is also connected in series between the positive and negative terminals of the DC side bus. and voltage divider capacitors Voltage divider capacitor and voltage divider capacitors common terminal and switching transistor and switching transistor The common terminal is connected and serves as the neutral point. A filter inductor is also connected in series between the positive and negative terminals of the AC side bus. and load resistance load resistance A filter capacitor is connected in parallel. Filter inductor and filter capacitor This forms an LC filter circuit.

[0037] like Figure 3 As shown, the sampling circuit includes a current sampling circuit and a voltage sampling circuit. The current sampling circuit acquires data from the filter inductor. current The voltage sampling circuit collects the load resistance. voltage , which serves as the current and voltage at the output of the five-level full-bridge inverter.

[0038] The driving modulation circuit includes first to seventh comparators, first to fourteenth multipliers, first to sixth OR gates, first to seventh inverters, and first to eighth driving circuits; the specific connection relationship is as follows:

[0039] The positive input terminals of the first, third, fourth, and seventh comparators receive the modulation signal. The positive input terminals of the second, fifth, and sixth comparators are input with negative modulation signals. The negative input terminals of the first and second comparators receive DC bias signals. The negative input terminal of the third comparator is grounded; the negative input terminals of the fourth and sixth comparators receive carrier signals. The negative input terminals of the fifth and seventh comparators receive the carrier signal. .

[0040] The inputs of the first through seventh inverters are connected to the outputs of the first through seventh comparators, respectively; the output of the first inverter is connected to the first input of the first multiplier and the second inputs of the fourth and sixth multipliers, respectively; the output of the second inverter is connected to the first input of the second multiplier and the second inputs of the tenth and twelfth multipliers, respectively; the output of the third inverter is connected to the second inputs of the second, ninth, and eleventh multipliers and the input of the seventh driver circuit, respectively; the outputs of the fourth, fifth, sixth, and seventh inverters are connected to the first inputs of the fifth, eighth, eleventh, and fourteenth multipliers, respectively.

[0041] The output of the first comparator is connected to the second input of the second OR gate and the thirteenth and fourteenth multipliers; the output of the second comparator is connected to the second input of the first OR gate and the seventh and eighth multipliers; the output of the third comparator is connected to the second input of the first, third, and fifth multipliers and the input of the eighth driver circuit; the outputs of the fourth, fifth, sixth, and seventh comparators are connected to the first input of the third, seventh, ninth, and thirteenth multipliers, respectively.

[0042] The output of the first multiplier is connected to the first input of the first OR gate; the output of the second multiplier is connected to the first input of the second OR gate; the outputs of the third, fifth, ninth, and eleventh multipliers are connected to the first inputs of the fourth, sixth, tenth, and twelfth multipliers, respectively; the outputs of the fourth, sixth, tenth, and twelfth multipliers are connected to the first inputs of the fourth, third, sixth, and fifth OR gates, respectively; and the outputs of the seventh, eighth, thirteenth, and fourteenth multipliers are connected to the second inputs of the third, fourth, fifth, and sixth OR gates, respectively.

[0043] The input terminals of the first to sixth drive circuits are respectively connected to the output terminals of the fifth, sixth, fourth, third, second, and first OR gates, and the output terminals of the first to eighth drive circuits are respectively connected to the drive terminals of the five-level full-bridge inverter.

[0044] like Figure 4 As shown, the working principle of this embodiment is as follows:

[0045] DC bias signal The value is the carrier signal. peak value, carrier signal and The frequency is 40kHz, and the modulation signal The frequency is 50Hz.

[0046] When the modulating signal Greater than DC bias signal Switching transistor Switching transistor and switching transistors Acquired drive signals Normally low, switching transistor and switching transistor Acquired drive signal Constantly high, switching transistor and switching transistor Acquired drive signals High-frequency action.

[0047] When the modulating signal Greater than zero and less than the DC bias signal Switching transistor Switching transistor and switching transistors Acquired drive signals Normally low, switching transistor and switching transistor Acquired drive signal Constantly high, switching transistor and switching transistor Acquired drive signals High-frequency action.

[0048] When the modulating signal Greater than DC bias signal Negative value and less than zero, switching transistor Switching transistor and switching transistors Acquired drive signals Normally low, switching transistor and switching transistor Acquired drive signal Constantly high, switching transistor and switching transistor Acquired drive signals High-frequency action.

[0049] When the modulating signal Less than DC bias signal Negative value, switching transistor Switching transistor and switching transistors Acquired drive signals Normally low, switching transistor and switching transistor Acquired drive signal Constantly high, switching transistor and switching transistor Acquired drive signals High-frequency action.

[0050] like Figure 5 and Figure 6 As shown, the positive half-cycle mode switching process of the five-level full-bridge inverter in this embodiment is illustrated.

[0051] Figure 5 The bridge arm output voltage is given. exist and The switching process of circuit modes during transitions. Bridge arm output voltage. equal Time (see) Figure 5 (a) in the middle, switching transistor Switching transistor Switching transistor It is in the ON state. First, turn off the switch transistor. Flow through the switching transistor The current in the channel then flows through the switching transistor. The body diode, the circuit mode switches to dead-time freewheeling mode (see Figure 5 (b)); then, turn on the switch transistor. Flow through the switching transistor The current in the body diode is redirected to the switching transistor. The channel, bridge arm output voltage from Switch to (See Figure 5 (c)); then, turn off the switch transistor. Flow through the switching transistor The current in the channel then flows through the switching transistor. The body diode, the circuit mode switches to dead-time freewheeling mode (see Figure 5 (b)); Finally, turn on the switch. Flow through the switching transistor The current in the body diode is redirected to the switching transistor. The channel, bridge arm output voltage Return to 0. At this stage, the switching transistor... It bears the main switching losses.

[0052] Figure 6 The bridge arm output voltage is given. between 0 and The switching process of circuit modes during transitions. Bridge arm output voltage. When equal to 0, the switching transistor Switching transistor Switching transistor In the on state (see) Figure 6 (a)). First, turn off the switch transistor. Flow through the switching transistor The current in the channel then flows through the switching transistor. The body diode, the circuit mode switches to dead-time freewheeling mode (see Figure 6 (b)); then, turn on the switch transistor. Flow through the switching transistor The current in the body diode is redirected to the switching transistor. The channel, bridge arm output voltage Switch from 0 to (See Figure 6 (c)); then, turn off the switch transistor. Flow through the switching transistor The current in the channel then flows through the switching transistor. The body diode, the circuit mode switches to dead-time freewheeling mode (see Figure 6 (b)); Finally, turn on the switch. Flow through the switching transistor The current in the body diode is redirected to the switching transistor. The channel, bridge arm output voltage Return to 0. At this stage, the switching transistor... It bears the main switching losses.

[0053] The switching logic of the modulation scheme proposed in this embodiment of the invention is similar to that in the negative half-cycle and the positive half-cycle, and will not be repeated here.

[0054] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A control circuit for a five-level full-bridge inverter, characterized by The control circuit comprises a closed-loop control circuit and a drive modulation circuit; the closed-loop control circuit comprises a sampling circuit and a closed-loop controller, the sampling circuit is used for collecting the current and voltage of the output end of the five-level full-bridge inverter; the closed-loop controller obtains the current and voltage of the output end of the five-level full-bridge inverter to generate a modulation signal; The drive modulation circuit comprises first to seventh comparators, first to fourteenth multipliers, first to sixth or gates, first to seventh inverters and first to eighth drive circuits; The positive input terminals of the first, third, fourth and seventh comparators input the modulating signal; the positive input terminals of the second, fifth and sixth comparators input the negative modulating signal; the negative input terminals of the first and second comparators input a DC bias signal ; the negative input terminal of the third comparator is grounded; the negative input terminals of the fourth and sixth comparators input a carrier signal ; the negative input terminals of the fifth and seventh comparators input a carrier signal ​ The input ends of the first to seventh inverters are connected to the output ends of the first to seventh comparators respectively; the output end of the first inverter is connected to the first input end of the first multiplier and the second input ends of the fourth and sixth multipliers respectively; the output end of the second inverter is connected to the first input end of the second multiplier and the second input ends of the tenth and twelfth multipliers respectively; the output end of the third inverter is connected to the second input ends of the second, ninth and eleventh multipliers and the input end of the seventh drive circuit respectively; the output ends of the fourth, fifth, sixth and seventh inverters are connected to the first input ends of the fifth, eighth, eleventh and fourteenth multipliers respectively; The output end of the first comparator is connected to the second input ends of the second or gate and the thirteenth and fourteenth multipliers; the output end of the second comparator is connected to the second input ends of the first or gate and the seventh and eighth multipliers; the output end of the third comparator is connected to the second input ends of the first, third and fifth multipliers and the input end of the eighth drive circuit; the output ends of the fourth, fifth, sixth and seventh comparators are connected to the first input ends of the third, seventh, ninth and thirteenth multipliers respectively; The output end of the first multiplier is connected to the first input end of the first or gate; the output end of the second multiplier is connected to the first input end of the second or gate; the output ends of the third, fifth, ninth and eleventh multipliers are connected to the first input ends of the fourth, sixth, tenth and twelfth multipliers respectively; the output ends of the fourth, sixth, tenth and twelfth multipliers are connected to the first input ends of the fourth, third, sixth and fifth or gates respectively; the output ends of the seventh, eighth, thirteenth and fourteenth multipliers are connected to the second input ends of the third, fourth, fifth and sixth or gates respectively; The input ends of the first to sixth drive circuits are connected to the output ends of the fifth, sixth, fourth, third, second and first or gates respectively, and the output ends of the first to eighth drive circuits are connected to the drive ends of the five-level full-bridge inverter; The five-level full-bridge inverter comprises a high-frequency bridge arm and a low-frequency bridge arm , a switch tube , a switch tube , a switch tube , a common end of the switch tube and the switch tube is connected in series with a common end of the switch tube and the switch tube , a switch tube and a switch tube ; the low-frequency bridge arm comprises a switch tube and a switch tube connected in series between the positive and negative poles of the DC side bus; a common end of the switch tube and the switch tube is connected in series with a common end of the switch tube and the switch tube between the positive and negative poles of the AC side bus; and output ends of the first to eighth driving circuits are connected to gates of the switch tubes respectively.

2. The control circuit of a five-level full-bridge inverter according to claim 1, characterized in that, The switch tube The switch tube The switch tube The switch tube is a SiC tube.

3. The control circuit of a five-level full-bridge inverter according to claim 1, characterized in that, The direct current side bus positive and negative poles are also connected in series with a voltage division capacitor and a voltage division capacitor , a common end of the voltage division capacitor and the voltage division capacitor is connected with a common end of the switch tube and the switch tube and serves as a neutral point.

4. The control circuit of a five-level full-bridge inverter according to claim 1, characterized in that, The alternating current side bus positive and negative poles are also connected in series with a filter inductor and a load resistor , the load resistor is connected in parallel with a filter capacitor , the filter inductor and the filter capacitor form an LC filter circuit.

5. The control circuit of a five-level full-bridge inverter according to claim 4, characterized in that, The sampling circuit comprises a current sampling circuit and a voltage sampling circuit, the current sampling circuit collects the current of the filter inductor , and the voltage sampling circuit collects the voltage of the load resistor , as the current and voltage of the five-level full-bridge inverter output end.

6. The control circuit of the five-level full-bridge inverter according to claim 1, wherein, When the modulated signal is greater than the DC bias signal , the switch tube , the switch tube , and the switch tube The obtained driving signal is always low, the switch tube and the switch tube The obtained driving signal is always high, the switch tube and the switch tube The obtained driving signal high frequency operation; When the modulated signal is greater than zero and less than the DC bias signal , the switch tube , the switch tube , and the switch tube The driving signal obtained is always low, the switch tube and the switch tube The driving signal obtained is always high, the switch tube and the switch tube The driving signal obtained is high frequency When the modulated signal is greater than the DC bias signal a negative value and less than zero, the switch tube , the switch tube and the switch tube The obtained driving signal is always low, the switch tube and the switch tube The obtained driving signal is always high, the switch tube and the switch tube The obtained driving signal high frequency operation; When the modulated signal is less than the DC bias signal Negative value, switch tube , switch tube And switch tube The obtained driving signal Low, switch tube And switch tube The obtained driving signal High, switch tube And switch tube The obtained driving signal High frequency operation.

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