Four-quadrature phase error correction system and correction method thereof

Abstract

The present invention provides a four-orthogonal phase error correction system and a correction method thereof, wherein the system includes a phase adjustment module, a phase difference characterization module, a phase difference comparison module and a logic algorithm control module; wherein the phase difference characterization module is used to sequentially characterize the phase difference between each adjacent clock signal to be corrected through four characterization pulses; the phase difference comparison module is used to sequentially compare the pulse widths of two characterization pulses in each pre-selected interval characterization pulse group; the logic algorithm control module is used to correct the corresponding clock signal to be corrected through the phase adjustment module based on the comparison result after the two characterization pulses in each pre-selected interval characterization pulse group are compared. The four-orthogonal phase error correction system and its algorithm provided by the present invention can solve the problem that conventional algorithms have many operation rounds and cannot completely remove residual errors.

Description

Technical Field

[0001] The present invention relates to the field of digital communication technology, and more specifically, to a four-orthogonal phase error correction system and a correction method thereof. Background Art

[0002] Multi-frequency clocks are widely used in modern digital signal systems, such as high-speed interfaces and communication systems. Among them, the most common are half-rate clocks and 1 / 4-rate clocks. For half-rate clocks, you need to pay attention to the duty cycle; for 1 / 4-rate clocks, some systems will use its four orthogonal phases 0°, 90°, 180°, and 270° at the same time. At this time, you need to pay attention to its orthogonal phase error.

[0003] The industry uses error correction methods to correct the phase error of systems with higher phase error requirements. The traditional four-quadrature phase error correction algorithm uses a pulse generator (pulse gen), a logic algorithm, and a digital-time-converter (DTC). Figure 1 The effect diagram of the traditional four-quadrature phase error correction algorithm is shown in FIG. Figure 1 As shown, p0, p1, p2 and p3 are four clock signals to be corrected; the pulse generator is used to generate pulses A, B, C, D, which respectively represent the width of the phase difference between each clock signal (for example, pulse A represents the phase difference between p0 and p1), and the logic algorithm part is used to adjust the phase of the four clock signals to be corrected through a digital control timer.

[0004] Specifically, Figure 1 As shown in the figure, the traditional four-quadrature phase error correction algorithm uses a sequential and continuous cycle to gradually adjust each phase. (Here, the rising edge is used as an example, and some systems use the falling edge; here, the pulse generator uses a positive pulse as an example, and some systems use a negative pulse. Neither affects the function implementation.) The specific process is as follows Figure 2 As shown:

[0005] In the first round of iteration (iteration1), the first comparison is to compare the pulse widths of A and B. If they are not equal, P1 is corrected until the pulse widths of A and B are equal; the second comparison is to compare the pulse widths of B and C. If they are not equal, P2 is corrected until the pulse widths of B and C are equal; the third comparison is to compare the pulse widths of C and D. If they are not equal, P3 is corrected until the pulse widths of C and D are equal.

[0006] In the second round of iteration 2, repeat the operation of the first round; repeat each subsequent round of iteration until the set number of iterations is reached, or the error is corrected to a tolerable range. (It should be noted that here, considering that the system only needs to correct the relative values ​​between the phases, it is not necessary to adjust p0, and only the other three can be corrected. Some systems can also work by continuing from p0 to p1 after the first round of p3. As long as it is a sequential patrol method, it will not affect the conclusion. I will not discuss it here, just take the current example)

[0007] Figure 3 The data processing result of a case where a phase error x is on the p3 clock edge using a conventional algorithm is shown in FIG. Figure 3 As shown in the figure, if p0~p3 are four equally divided 360° phases, and we consider p0 to be position 0, then the ideal position distribution should be at units 1, 2, and 3 (90° is a unit); for the case where an initial phase error x is on the clock edge of p3, the above algorithm can be used to infer that after multiple iterations, the phase error introduced by x will gradually decrease until the phase error is within the tolerable range. Regarding the set number of iterations, that is, Figure 2 The exit condition of the calibration loop implies a question: how many times is enough to correct to a tolerable range? Since the value of the error X can only be roughly estimated in actual situations, designers can only increase the number of redundant iterations to ensure that the residual meets the design requirements, which further worsens the number of iterations.

[0008] From the specific correction process of the conventional algorithm mentioned above, we can see that its main disadvantage is that there is an error residual after each round of correction. The only way to ensure that the error is reduced to a tolerable range is to run the algorithm for multiple rounds and ensure sufficient redundant rounds. Therefore, the conventional algorithm has two problems: 1: multiple rounds of convergence are slow and the error correction efficiency is low; 2: the residual value can only be gradually reduced but not completely removed.

[0009] Based on this, there is an urgent need for an efficient correction method for four orthogonal phase errors that can completely remove the residual value. Summary of the invention

[0010] In view of the above problems, an object of the present invention is to provide a four-orthogonal phase error correction system and correction method thereof to solve the problem that conventional algorithms have many operation rounds and cannot completely remove residual errors.

[0011] The four-orthogonal phase error correction system provided by the present invention is used to correct the phase errors of four clock signals to be corrected whose phases change in sequence; it includes a phase adjustment module, a phase difference characterization module, a phase difference comparison module and a logic algorithm control module; wherein,

[0012] The phase difference characterization module is used to characterize the phase difference between each two adjacent clock signals to be corrected in sequence through four characterization pulses;

[0013] The phase difference comparison module is used to compare the pulse widths of two characterization pulses in each pre-selected alternate characterization pulse group in turn;

[0014] The logic algorithm control module is used for correcting the corresponding clock signal to be corrected through the phase adjustment module based on the comparison result after the comparison of two characterization pulses in each pre-selected alternate characterization pulse group is completed.

[0015] In addition, a preferred solution is that if the four clock signals to be corrected are respectively recorded as p0, p1, p2 and p3, the four characterization pulses are respectively recorded as A, B, C and D; wherein A is used to characterize the phase difference between p0 and p1, B is used to characterize the phase difference between p1 and p2, C is used to characterize the phase difference between p2 and p3, and D is used to characterize the phase difference between p3 and p0; and,

[0016] The pre-selected interval characterization pulse groups are: A and B, C and D, B and C, D and A respectively.

[0017] In addition, a preferred solution is that the phase difference characterization module includes a pulse generator, and the pulse generator is used to generate four characterization pulses.

[0018] In addition, a preferred solution is that the phase difference comparison module includes a comparator, and the comparator is used to compare two characterization pulses in the pre-selected alternate characterization pulse group and generate a comparison result.

[0019] In addition, a preferred solution is that the phase difference comparison module further includes a multiplexer, and the multiplexer is used to select two characterization pulses in each pre-selected alternate characterization pulse group from the pulse generator.

[0020] In addition, a preferred solution is that the phase difference comparison module further includes a low-pass filter, and the low-pass filter is used to perform filtering processing on each characterization pulse selected by the multiplexer.

[0021] In addition, a preferred solution is that the logic algorithm control module is also used to determine each pre-selected interval characterization pulse group in sequence.

[0022] On the other hand, the present invention also provides a method for performing error correction using the aforementioned four-quadrature phase error correction system, the error correction method comprising:

[0023] The pulse widths of the two characterization pulses in each preselected alternate characterization pulse group are compared in turn; and after the two characterization pulses in each preselected alternate characterization pulse group are compared, the corresponding clock signal to be corrected is corrected through the phase adjustment module based on the comparison result.

[0024] In addition, a preferred solution is that the pulse widths of the two characterization pulses in each preselected alternate characterization pulse group are compared in sequence; and after the comparison of the two characterization pulses in each preselected alternate characterization pulse group is completed, the corresponding clock signal to be corrected is corrected by the phase adjustment module based on the comparison result, including:

[0025] Compare the pulse widths of A and B in the first preselected alternate position characterization pulse group, and if they are not equal, correct p1 through the phase adjustment module until the pulse widths of A and B are equal;

[0026] Compare the pulse widths of C and D in the second preselected alternate position characterization pulse group, and if they are not equal, correct p3 through the phase adjustment module until the pulse widths of C and D are equal;

[0027] Compare the pulse widths of B and C in the third preselected alternate position characterization pulse group, and if they are not equal, correct p2 through the phase adjustment module until the pulse widths of B and C are equal;

[0028] The pulse widths of D and A in the fourth preselected alternate position characterization pulse group are compared. If they are not equal, p0 is corrected by the phase adjustment module until the pulse widths of D and A are equal.

[0029] In addition, a preferred solution is that when the linearity of the phase adjustment module reaches a preset value, the pulse widths of the two characterization pulses in each pre-selected alternate characterization pulse group are compared in turn; and after the comparison of the two characterization pulses in each pre-selected alternate characterization pulse group is completed, the corresponding clock signal to be corrected is corrected by the phase adjustment module based on the comparison result, including:

[0030] Compare the pulse widths of A and B in the first preselected alternate position characterization pulse group, and if they are not equal, correct p1 through the phase adjustment module until the pulse widths of A and B are equal;

[0031] Compare the pulse widths of C and D in the second preselected alternate position characterization pulse group, and if they are not equal, correct p3 through the phase adjustment module until the pulse widths of C and D are equal;

[0032] Compare the pulse widths of B and C in the third preselected alternate position characterization pulse group, and if they are not equal, correct p2 through the phase adjustment module until the pulse widths of B and C are equal;

[0033] The synchronization length adjusts p1, p2, and p3 in opposite directions until p1, p2, p3, and p0 are completely orthogonal.

[0034] Compared with the prior art, the four-orthogonal phase error correction system and correction method according to the present invention have the following beneficial effects:

[0035] By designing the control logic in the logic algorithm control module and using a comparison algorithm with a reasonable jump sequence, the phase adjustment module can be quickly and accurately controlled to adjust the phase of the clock signal to be corrected. In addition, by using the method of adjusting the clock signal to be corrected at alternate positions (such as adjusting the two odd-bit clock signals p1 and p3 first, and then adjusting the two even-bit clock signals p2 and p0 with opposite odd and even numbers, and vice versa), only one round of iteration and four comparisons are required to complete the entire error correction process, which can not only improve work efficiency, but also completely eliminate residual errors.

[0036] In order to achieve the above and related purposes, one or more aspects of the present invention include features that will be described in detail later and are particularly pointed out in the claims. The following description and the accompanying drawings describe some exemplary aspects of the present invention in detail. However, these aspects indicate only some of the various ways in which the principles of the present invention can be used. In addition, the present invention is intended to include all of these aspects and their equivalents. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] By referring to the following description in conjunction with the accompanying drawings, and with a more comprehensive understanding of the present invention, other objects and results of the present invention will become more apparent and easy to understand. In the accompanying drawings:

[0038] Figure 1 The effect diagram of the traditional four-quadrature phase error correction algorithm is shown;

[0039] Figure 2 A flow chart showing a conventional four-quadrature phase error correction algorithm is shown;

[0040] Figure 3 The data processing result of a case where a phase error x is on the p3 clock edge using a conventional algorithm is shown;

[0041] Figure 4 The structure diagram of the quadrature phase error correction system provided by the embodiment of the present invention is shown;

[0042] Figure 5 A data processing result display diagram is shown for a case in which an initial phase difference of a phase error generates phase errors of unknown numbers x, y, and z respectively by using the cross-phase error correction method provided by an embodiment of the present invention;

[0043] Figure 6The flowchart of the cross-phase error correction method provided by the embodiment of the present invention is shown.

[0044] The same reference numerals throughout the drawings indicate similar or corresponding features or functions. DETAILED DESCRIPTION

[0045] In the following description, for the purpose of illustration, in order to provide a comprehensive understanding of one or more embodiments, many specific details are set forth. However, it is apparent that these embodiments may also be implemented without these specific details. In other examples, for ease of describing one or more embodiments, known structures and devices are shown in the form of block diagrams.

[0046] Before introducing in detail the four-orthogonal phase error correction system and method provided by the present invention, it should be noted that for the four-orthogonal phase error correction system and method provided by the present invention, the four clock signals to be corrected involved basically tend to four orthogonal phase clock signals, which differ by about 90° in sequence and have corresponding phase errors. The purpose of the present invention is to perform phase error correction on the four clock signals to be corrected whose phases change sequentially.

[0047] The four-orthogonal phase error correction system and method provided by the present invention are described in detail below. Figure 4 The structure of the quadrature phase error correction system provided by the embodiment of the present invention is shown. Figure 5 The data processing result display diagram shows a case in which the initial phase difference of a phase error generates phase errors of certain unknown numbers x, y, and z respectively by using the cross-phase error correction method provided by an embodiment of the present invention. Figure 6 The flowchart of the cross-phase error correction method provided by the embodiment of the present invention is shown.

[0048] Combination Figures 4 to 6 It can be seen that the four-orthogonal phase error correction system provided by the present invention is used to perform phase error correction on the four clock signals to be corrected (approaching four-orthogonal phase clock signals) whose phases change in sequence.

[0049] The four-orthogonal phase error correction system includes a phase adjustment module, a phase difference characterization module, a phase difference comparison module and a logic algorithm control module; wherein the phase difference characterization module is used to sequentially characterize the phase difference between each adjacent clock signal to be corrected through four characterization pulses; the phase difference comparison module is used to sequentially compare the pulse widths of the two characterization pulses in each pre-selected alternate characterization pulse group; the logic algorithm control module is used to correct the corresponding clock signal to be corrected through the phase adjustment module based on the comparison result after the two characterization pulses in each pre-selected alternate characterization pulse group are compared.

[0050] Specifically, Figure 4 As shown, clk0, clk90, clk180 and clk270 on the left are the original input clock signals to be corrected. For the original input clock signals, the phase adjustment module (optional digital control timer) can adjust the original input clock signal clock in order to obtain an optimized clock group that is nearly mutually orthogonal as the clock signal to be corrected.

[0051] Further, if the four clock signals to be corrected can be respectively recorded as p0, p1, p2 and p3, the four characterization pulses can be respectively recorded as A, B, C and D; wherein A is used to characterize the phase difference between p0 and p1, B is used to characterize the phase difference between p1 and p2, C is used to characterize the phase difference between p2 and p3, and D is used to characterize the phase difference between p3 and p0; and, each pre-selected interval characterization pulse group is respectively: A and B, C and D, B and C, D and A.

[0052] In order to enable the phase difference characterization module to characterize the phase difference between each adjacent clock signal to be corrected, the phase difference characterization module may include a pulse generator, which is used to generate four characterization pulses: A, B, C and D, and the width of the phase difference between each adjacent clock signal to be corrected is respectively characterized by its pulse width; for example, ideally, the phase difference between p0 and p1 should be 90°, at which time the duty cycle of pulse A should be 25%, and the level obtained after passing through the low-pass filter should be 0.25 times the power supply voltage VDD.

[0053] Specifically, in order to achieve the size comparison between the two selected phase differences, the phase difference comparison module may include a comparator (CMP), which is used to compare the two characterization pulses in the pre-selected interval characterization pulse group (i.e., two corresponding phase differences) to determine the size of the two phase differences and generate a comparison result.

[0054] In addition, the phase difference comparison module may further include a multiplexer (MUX), wherein the multiplexer is used to select two characterization pulses in each pre-selected alternate characterization pulse group from the pulse generator and send them to the comparator for comparison.

[0055] Of course, the phase difference comparison module may also include a low-pass filter, which is used to filter the characterization pulses selected by the multiplexer to convert them into DC voltages corresponding to the selected characterization pulses for subsequent comparison by a comparator.

[0056] It should be noted that the logic algorithm control module is also used to determine each pre-selected interval characterization pulse group in sequence; that is, the logic algorithm control module has two functions, one is to determine each pre-selected interval characterization pulse group in sequence based on a preset program, so as to control the multiplexer to select the required two characterization pulses in sequence and send them to the comparator; the other is to control the phase adjustment module according to the comparison result sent by the comparator, and correct p1, p3, p2 and p0 in sequence, so as to realize error correction of 4 clock signals with nearly orthogonal phases.

[0057] On the other hand, the present invention also provides a method for performing error correction using the aforementioned four-quadrature phase error correction system, the error correction method comprising:

[0058] The pulse widths of the two characterization pulses in each preselected alternate characterization pulse group are compared in turn; and after the two characterization pulses in each preselected alternate characterization pulse group are compared, the corresponding clock signal to be corrected is corrected through the phase adjustment module based on the comparison result.

[0059] Specifically, the pulse widths of two characterization pulses in each preselected alternate characterization pulse group are compared in sequence; and after the comparison of the two characterization pulses in each preselected alternate characterization pulse group is completed, the corresponding clock signal to be corrected is corrected by the phase adjustment module based on the comparison result, including:

[0060] Compare the pulse widths of A and B in the first preselected alternate position characterization pulse group, and if they are not equal, correct p1 through the phase adjustment module until the pulse widths of A and B are equal;

[0061] Compare the pulse widths of C and D in the second preselected alternate position characterization pulse group, and if they are not equal, correct p3 through the phase adjustment module until the pulse widths of C and D are equal;

[0062] Compare the pulse widths of B and C in the third preselected alternate position characterization pulse group, and if they are not equal, correct p2 through the phase adjustment module until the pulse widths of B and C are equal;

[0063] The pulse widths of D and A in the fourth preselected alternate position characterization pulse group are compared. If they are not equal, p0 is corrected by the phase adjustment module until the pulse widths of D and A are equal.

[0064] Further, Figure 5 The data processing result of the case where the initial phase difference of a phase error produces phase errors of unknown numbers x, y, and z respectively using the cross-phase error correction method provided by an embodiment of the present invention is shown in FIG. Figure 5As shown, similar to the deduction of the existing solution in the background technology, assuming the initial phase difference, the phase errors (relative to the correct position) of the unknown numbers x, y, and z are generated. After one round of iteration (four comparisons) of the four-orthogonal phase error correction method provided by the present invention, the final result is that the values ​​of the four orthogonal phases p0~p3 are y / 2, 1+y / 2, 2+y / 2, and 3+y / 2. The relative phase difference between the two is unit 1, that is, 90°, that is, p1, p2, p3 and p0 are completely orthogonal.

[0065] Furthermore, the details of the results of the four comparisons are shown in the following table:

[0066]

[0067] It should be noted that, under the premise that the linearity of the phase adjustment module (such as DTC) reaches the preset value, if you want to change the final 4 phases from y / 2, 1+y / 2, 2+y / 2, 3+y / 2 to 0, 1, 2, 3, you can omit the fourth comparison step and change it to the step of: "synchronous long reverse adjustment p1, p2, p3".

[0068] Specifically, when the linearity of the phase adjustment module reaches a preset value, the pulse widths of the two characterization pulses in each preselected alternate characterization pulse group are compared in turn; and after the comparison of the two characterization pulses in each preselected alternate characterization pulse group is completed, the corresponding clock signal to be corrected is corrected by the phase adjustment module based on the comparison result, including:

[0069] Compare the pulse widths of A and B in the first preselected alternate position characterization pulse group, and if they are not equal, correct p1 through the phase adjustment module until the pulse widths of A and B are equal;

[0070] Compare the pulse widths of C and D in the second preselected alternate position characterization pulse group, and if they are not equal, correct p3 through the phase adjustment module until the pulse widths of C and D are equal;

[0071] Compare the pulse widths of B and C in the third preselected alternate position characterization pulse group, and if they are not equal, correct p2 through the phase adjustment module until the pulse widths of B and C are equal;

[0072] The synchronization length adjusts p1, p2, and p3 in opposite directions until p1, p2, p3, and p0 are completely orthogonal.

[0073] In addition, it should be noted that the specific configuration schemes of the phase adjustment module, phase difference characterization module, and phase difference comparison module provided by the present invention can be replaced as long as they do not affect the implementation of the entire scheme. For example, the phase adjustment module can be a DTC, a delay module directly controlled by digital, or other methods to achieve the purpose of phase adjustment; taking the forward pulse used by the phase difference characterization module as an example, the reverse pulse generator, or other pulse generation schemes, as long as they can characterize the phase difference between P0~3, will not affect the final result; for example, the position of the multiplexer after the pulse generator and before the low-pass filter (that is, the pulse is selected first and then converted to DC voltage), if it is replaced by the pulse generator first passing through the low-pass filter and then being selected by the multiplexer, it will not affect the overall scheme; and so on. In addition, as long as the order of adjusting the clock signals to be corrected is in accordance with the odd bits first and then the even bits, or the even bits first and then the odd bits (that is, the alternate bits are adjusted), the final orthogonal correction function will not be affected.

[0074] It can be seen from the above specific implementation that the conventional algorithm uses a sequential round scheme, which can converge, but the speed is very slow (requiring more iterations), and the error residual value after each iteration is half of the previous iteration, and the error residual value can never be eliminated in theory. The four-orthogonal phase error correction system and correction method provided by the present invention can complete the orthogonal correction by reasonably setting the comparison order, and theoretically there is no problem of error residual value.

[0075] As above Figures 4 to 6 The four-quadrature phase error correction system and correction method provided by the present invention are described by way of example. However, those skilled in the art should understand that various improvements can be made to the four-quadrature phase error correction system and correction method proposed by the present invention without departing from the content of the present invention. Therefore, the protection scope of the present invention should be determined by the content of the attached claims.

Claims

1. A four-orthogonal phase error correction system, used for correcting the phase errors of four clock signals to be corrected whose phases change in sequence; characterized in that: It includes a phase adjustment module, a phase difference characterization module, a phase difference comparison module and a logic algorithm control module; wherein, The phase difference characterization module is used to characterize the phase difference between each two adjacent clock signals to be corrected in sequence through four characterization pulses; The phase difference comparison module is used to compare the pulse widths of two characterization pulses in each pre-selected alternate characterization pulse group in turn; The logic algorithm control module is used to correct the corresponding clock signal to be corrected through the phase adjustment module based on the comparison result after the two characterization pulses in each pre-selected alternate characterization pulse group are compared; wherein, If the four clock signals to be corrected are respectively recorded as p0, p1, p2 and p3, and the four characterization pulses are respectively recorded as A, B, C and D; then, A is used to characterize the phase difference between p0 and p1, B is used to characterize the phase difference between p1 and p2, C is used to characterize the phase difference between p2 and p3, and D is used to characterize the phase difference between p3 and p0; and the preselected alternate characterization pulse groups are respectively: A and B, C and D, B and C, D and A; and, The phase difference comparison module is used to compare the pulse widths of two characterization pulses in each pre-selected alternate characterization pulse group in turn; and the logic algorithm control module is used to correct the corresponding clock signal to be corrected through the phase adjustment module based on the comparison result after the two characterization pulses in each pre-selected alternate characterization pulse group are compared, including: Compare the pulse widths of A and B in the first preselected alternate position characterization pulse group, and if they are not equal, correct p1 through the phase adjustment module until the pulse widths of A and B are equal; Compare the pulse widths of C and D in the second preselected alternate position characterization pulse group, and if they are not equal, correct p3 through the phase adjustment module until the pulse widths of C and D are equal; Compare the pulse widths of B and C in the third preselected alternate position characterization pulse group, and if they are not equal, correct p2 through the phase adjustment module until the pulse widths of B and C are equal; The pulse widths of D and A in the fourth preselected alternate position characterization pulse group are compared. If they are not equal, p0 is corrected by the phase adjustment module until the pulse widths of D and A are equal.

2. The four-quadrature phase error correction system as claimed in claim 1, characterized in that: The phase difference characterization module comprises a pulse generator, and the pulse generator is used to generate four characterization pulses.

3. The four-quadrature phase error correction system as claimed in claim 2, characterized in that: The phase difference comparison module comprises a comparator, which is used to compare two characterization pulses in the preselected alternate characterization pulse group and generate a comparison result.

4. The four-quadrature phase error correction system as claimed in claim 3, characterized in that: The phase difference comparison module further comprises a multiplexer, and the multiplexer is used for selecting two characterization pulses in each preselected alternate characterization pulse group from the pulse generator.

5. The four-quadrature phase error correction system as claimed in claim 4, characterized in that: The phase difference comparison module further includes a low-pass filter, and the low-pass filter is used to perform filtering processing on each characterization pulse selected by the multiplexer.

6. The four-quadrature phase error correction system according to any one of claims 1 to 5, characterized in that: The logic algorithm control module is also used to determine each pre-selected interval characterization pulse group in sequence.

7. A method for error correction using the four-quadrature phase error correction system according to any one of claims 1 to 6, characterized in that: The correction method comprises: Comparing the pulse widths of two characterizing pulses in each preselected alternate characterizing pulse group in turn; and after the comparison of the two characterizing pulses in each preselected alternate characterizing pulse group is completed, correcting the corresponding clock signal to be corrected through the phase adjustment module based on the comparison result; and, The pulse widths of the two characterization pulses in each preselected alternate characterization pulse group are compared in sequence; and after the comparison of the two characterization pulses in each preselected alternate characterization pulse group is completed, the corresponding clock signal to be corrected is corrected by the phase adjustment module based on the comparison result, including: Compare the pulse widths of A and B in the first preselected alternate position characterization pulse group, and if they are not equal, correct p1 through the phase adjustment module until the pulse widths of A and B are equal; Compare the pulse widths of C and D in the second preselected alternate position characterization pulse group, and if they are not equal, correct p3 through the phase adjustment module until the pulse widths of C and D are equal; Compare the pulse widths of B and C in the third preselected alternate position characterization pulse group, and if they are not equal, correct p2 through the phase adjustment module until the pulse widths of B and C are equal; The pulse widths of D and A in the fourth preselected alternate position characterization pulse group are compared. If they are not equal, p0 is corrected by the phase adjustment module until the pulse widths of D and A are equal.

8. The four-orthogonal phase error correction method according to claim 7, characterized in that: When the linearity of the phase adjustment module reaches a preset value, The pulse widths of the two characterization pulses in each preselected alternate characterization pulse group are compared in sequence; and after the comparison of the two characterization pulses in each preselected alternate characterization pulse group is completed, the corresponding clock signal to be corrected is corrected by the phase adjustment module based on the comparison result, including: Compare the pulse widths of A and B in the first preselected alternate position characterization pulse group, and if they are not equal, correct p1 through the phase adjustment module until the pulse widths of A and B are equal; Compare the pulse widths of C and D in the second preselected alternate position characterization pulse group, and if they are not equal, correct p3 through the phase adjustment module until the pulse widths of C and D are equal; Compare the pulse widths of B and C in the third preselected alternate position characterization pulse group, and if they are not equal, correct p2 through the phase adjustment module until the pulse widths of B and C are equal; The synchronization length adjusts p1, p2, and p3 in opposite directions until p1, p2, p3, and p0 are completely orthogonal.

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