A scanning pulse circuit for a slow-scanning streak camera

Abstract

The present invention provides a scanning pulse circuit of a slow-scanning streak camera, which relates to the technical field of camera pulse circuits, and aims to be better suitable for slow-scanning streak cameras and have better adjustability, including a power supply module, a trigger buffer module, a positive pulse branch and a negative pulse branch; the input end of the first drive circuit and the input end of the second drive circuit are connected to the output end of the trigger buffer module, and the input end of the trigger buffer module contacts the signal; the positive pulse generating circuit outputs a positive pulse, the negative pulse generating circuit outputs a negative pulse, the trigger buffer module is used to output an on-off control signal, and the power supply module is used to power the trigger buffer module, the positive pulse branch and the negative pulse branch. The present invention has a wider waveform adjustment range, a larger voltage amplitude in the linear working area, and a larger slope adjustment range.

Description

Technical Field

[0001] The present invention relates to the technical field of camera pulse circuits, and in particular to a scanning pulse circuit of a slow-scanning streak camera. Background Art

[0002] A streak camera is a high-speed photographic device that can measure the continuous time evolution process in one-dimensional space. When the streak camera performs dynamic scanning, two complementary scanning pulses are used as the working voltage of the deflection electrode.

[0003] The electrons entering the deflection electrode will be radially deflected due to the deflection voltage. Because the front edge of the scanning pulse changes approximately linearly, the offset distance is linearly related to the time. The part of the front edge of the scanning pulse that changes approximately linearly is defined as the linear working area. In applications with strong signals and single-shot working modes, a sufficiently long retrace time is usually required to prevent invalid signals outside the acquisition window from covering valid signals.

[0004] It is necessary to design a pulse scanning circuit with better performance, which can be better suitable for slow-scanning streak cameras and have appropriate nonlinearity and retrace time. Summary of the invention

[0005] The object of the present invention is to provide a scanning pulse circuit of a slow-scanning streak camera, which can be better applicable to the slow-scanning streak camera and has better adjustability.

[0006] The embodiments of the present invention are implemented by the following technical solutions:

[0007] A scanning pulse circuit of a slow-scanning streak camera comprises a power supply module, a trigger buffer module, a positive pulse branch and a negative pulse branch;

[0008] The positive pulse branch includes a first drive circuit, a first gear adjustment circuit and a positive pulse generating circuit connected in sequence; the negative pulse branch includes a second drive circuit, a second gear adjustment circuit and a negative pulse generating circuit connected in sequence;

[0009] The input end of the first driving circuit and the input end of the second driving circuit are connected to the output end of the trigger buffer module, and the input end of the trigger buffer module contacts the signal;

[0010] The positive pulse generating circuit outputs a positive pulse, the negative pulse generating circuit outputs a negative pulse, the trigger buffer module is used to output an on-off control signal, and the power supply module is used to supply power to the trigger buffer module, the positive pulse branch and the negative pulse branch.

[0011] Preferably, if the pulse width of the trigger signal is not less than the threshold time, the trigger buffer module includes a Schmitt trigger, and if the pulse width of the trigger signal is less than the threshold time, the trigger buffer module includes a monostable oscillator.

[0012] Preferably, the first driving circuit comprises a first photoelectrically isolated gate driver, a plurality of resistors and capacitors;

[0013] One end of the first resistor is connected to the output end of the trigger buffer module, the other end of the first resistor is connected to the ANODE end of the first photoelectric isolation gate driver, the CATHODE end and the Vss end of the first photoelectric isolation gate driver are grounded, the VDD end of the first photoelectric isolation gate driver is connected to the positive end +15VP of the 15V DC source and one end of the second resistor, the two Vo ends of the first photoelectric isolation gate driver are commonly connected to one end of the first capacitor, the other end of the first capacitor and the other end of the second resistor are connected to the first gear adjustment circuit, and the Vss end of the first photoelectric isolation gate driver is floating.

[0014] Preferably, the first gear adjustment circuit comprises a first signal relay, a plurality of resistors, a diode and a first NPN transistor; the first signal relay adopts HFD4;

[0015] The first pin of the first signal relay is connected to a 5V DC source and a cathode of a first diode, the eighth pin of the first signal relay is connected to an anode of the first diode and a collector of a first NPN transistor, the emitter of the first NPN transistor is grounded, the base of the first NPN transistor is connected to one end of a fifth resistor and one end of a sixth resistor, and the other end of the sixth resistor is grounded;

[0016] The second pin of the first signal relay is connected to one end of the seventh resistor, the other end of the seventh resistor is connected to one end of the eighth resistor and the seventh pin of the first signal relay, and the other end of the eighth resistor is grounded; the fourth pin of the first signal relay is connected to one end of the ninth resistor, the other end of the ninth resistor is connected to one end of the tenth resistor and the fifth pin of the first signal relay, and the other end of the tenth resistor is grounded; the fourth pin of the first signal relay is connected to the other end of the first capacitor and the other end of the second resistor, and the third pin of the first signal relay is connected to the positive pulse generating circuit;

[0017] The seventh resistor, the eighth resistor, the ninth resistor and the tenth resistor are sliding resistors.

[0018] Preferably, the positive pulse generating circuit comprises a plurality of resistors, a plurality of capacitors and a first NPN high voltage field effect transistor;

[0019] The gate of the first NPN high-voltage field effect transistor is connected to the third pin of the first signal relay and one end of the seventeenth resistor, the other end of the seventeenth resistor is floating, the drain of the first NPN high-voltage field effect transistor is connected to one end of the third capacitor and one end of the eighteenth resistor, the other end of the eighteenth resistor is connected to a 2500V high-voltage DC source, and the other end of the third capacitor is grounded; the source of the first NPN high-voltage field effect transistor is floating and connected to one end of the fourth capacitor and one end of the nineteenth resistor, the other end of the fourth capacitor is connected to one end of the twentieth resistor, the other end of the nineteenth resistor is grounded and connected to one end of the sixth capacitor, the other end of the sixth capacitor is connected to one end of the fifth capacitor, the other end of the fifth capacitor is connected to the other end of the twentieth resistor, one end of the twenty-first resistor, one end of the seventh capacitor and one end of the twenty-second resistor, the other end of the twenty-second resistor is connected to one end of the twenty-third resistor, the other end of the twenty-third resistor is connected to the other end of the seventh capacitor and serves as a positive pulse output end, and the other end of the twenty-first resistor is connected to a first bias module.

[0020] Preferably, the second driving circuit comprises a second photoelectrically isolated gate driver, a plurality of resistors and capacitors;

[0021] One end of the third resistor is connected to the output end of the trigger buffer module, the other end of the third resistor is connected to the ANODE end of the second photoelectric isolation gate driver, the CATHODE end and the Vss end of the second photoelectric isolation gate driver are grounded, the VDD end of the second photoelectric isolation gate driver is connected to the negative end +15VN of the 15V DC source and one end of the fourth resistor, the two Vo ends of the second photoelectric isolation gate driver are commonly connected to one end of the second capacitor, the other end of the second capacitor and the other end of the fourth resistor are connected to the second gear adjustment circuit, and the Vss end of the second photoelectric isolation gate driver is floating.

[0022] Preferably, the second gear adjustment circuit comprises a second signal relay, a plurality of resistors, a diode and a second NPN transistor; the second signal relay adopts HFD4;

[0023] The first pin of the second signal relay is connected to a 5V DC source and a cathode of the second diode, the eighth pin of the second signal relay is connected to an anode of the second diode and a collector of the second NPN transistor, the emitter of the second NPN transistor is grounded, the base of the second NPN transistor is connected to one end of the eleventh resistor and one end of the twelfth resistor, and the other end of the twelfth resistor is grounded;

[0024] The second pin of the second signal relay is connected to one end of a thirteenth resistor, the other end of the thirteenth resistor is connected to one end of a fourteenth resistor and the seventh pin of the second signal relay, and the other end of the fourteenth resistor is grounded;

[0025] The fourth pin of the second signal relay is connected to one end of the ninety-fifth resistor, the other end of the fifteenth resistor is connected to one end of the sixteenth resistor and the fifth pin of the second signal relay, and the other end of the sixteenth resistor is grounded; the fourth pin of the second signal relay is connected to the other end of the second capacitor and the other end of the fourth resistor, and the third pin of the second signal relay is connected to the negative pulse generating circuit;

[0026] The thirteenth resistor, the fourteenth resistor, the fifteenth resistor and the sixteenth resistor are sliding resistors.

[0027] Preferably, the negative pulse generating circuit comprises a plurality of resistors, a plurality of capacitors and a second NPN high voltage field effect transistor;

[0028] The gate of the second NPN high-voltage field effect transistor is connected to the third pin of the second signal relay and one end of the twenty-fourth resistor, the other end of the twenty-fourth resistor is grounded, the source of the second NPN high-voltage field effect transistor is grounded, the drain of the second NPN high-voltage field effect transistor is connected to one end of the eighth capacitor and one end of the twenty-fifth resistor, the other end of the twenty-fifth resistor is connected to a 2500V high-voltage DC source, the other end of the eighth capacitor is connected to one end of the twenty-sixth resistor, one end of the tenth capacitor is grounded, the other end of the tenth capacitor is connected to one end of the ninth capacitor, the other end of the ninth capacitor is connected to the other end of the twenty-sixth resistor, one end of the twenty-seventh resistor, one end of the eleventh capacitor and one end of the twenty-eighth resistor, the other end of the twenty-eighth resistor is connected to one end of the twenty-ninth resistor, the other end of the twenty-ninth resistor is connected to the other end of the eleventh capacitor and serves as a positive pulse output end, and the other end of the twenty-seventh resistor is connected to a second bias module.

[0029] Preferably, the power supply module includes a low-voltage DC power supply module and a high-voltage DC power supply module, the low-voltage DC power supply module is used to power the first drive circuit, the first gear adjustment circuit, the second drive circuit, the second gear adjustment circuit and the trigger buffer module, and the high-voltage DC power supply module is used to power the positive pulse generating circuit and the negative pulse generating circuit.

[0030] The technical solution of the embodiment of the present invention has at least the following advantages and beneficial effects:

[0031] When used, the present invention is equivalent to adjusting the start delay and slope of the linear working area of ​​the scanning pulse by adjusting the conduction speed, static working point and parameters of the forming network of the N-Mosfet, wherein the conduction speed is achieved by adjusting the gate series resistance. Therefore, compared with the traditional circuit, it has a wider waveform adjustment range under the premise of non-deterioration of nonlinearity, and the start delay can be changed to a certain extent by adjusting the static working point;

[0032] Under the design of the two pulse branches of the present invention, a higher voltage can be used for power supply, so that the voltage amplitude in the linear working area is larger and the slope adjustment range is larger;

[0033] The invention has reasonable design and simple structure, and all the electronic components used are easy to purchase and relatively low in price, so it has high cost performance and is easy to promote and implement. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 A schematic diagram of the circuit principle of a scanning pulse circuit of a slow-scanning streak camera provided in Example 1 of the present invention;

[0035] Figure 2 A schematic diagram of the structure of a first driving circuit provided in Embodiment 2 of the present invention;

[0036] Figure 3 A schematic diagram of the structure of a first gear adjustment circuit provided in Embodiment 2 of the present invention;

[0037] Figure 4 A schematic diagram of the structure of a positive pulse generating circuit provided in Embodiment 2 of the present invention;

[0038] Figure 5 A schematic diagram of the structure of a second driving circuit provided in Embodiment 3 of the present invention;

[0039] Figure 6 A schematic diagram of the structure of a second gear adjustment circuit provided in Embodiment 3 of the present invention;

[0040] Figure 7 A schematic diagram of the structure of a negative pulse generating circuit provided in Embodiment 3 of the present invention;

[0041] Figure 8 A schematic diagram of the structure of a low-voltage DC power supply module provided in Example 4 of the present invention;

[0042] Fig. 9 A schematic diagram of the structure of a high-voltage DC power supply module provided in Example 4 of the present invention;

[0043] Icon: R1-first resistor, R2-second resistor, R3-third resistor, R4-fourth resistor, R5-fifth resistor, R6-sixth resistor, R7-seventh resistor, R8-eighth resistor, R9-ninth resistor, R10-tenth resistor, R11-eleventh resistor, R12-twelfth resistor, R13-thirteenth resistor, R14-fourteenth resistor, R15-fifteenth resistor, R16-sixteenth resistor, R17-seventeenth resistor, R18-eighteenth resistor, R19-nineteenth resistor, R20-twentieth resistor, R21-twenty-first resistor, R22-twenty-second resistor, R23-twenty-third resistor, R24-twenty-fourth resistor, R25-twenty-fifth resistor, R26-twenty-sixth resistor, R27-twenty-seventh resistor, R28-twenty-eighth resistor, R29-twenty-ninth resistor, R30-thirtieth resistor, R31-thirty-first resistor, R32-thirty-second resistor, C1-first capacitor, C2-second capacitor, C3-third capacitor, C4-fourth capacitor, C5-fifth capacitor, C6-sixth capacitor, C7-seventh capacitor, C8-eighth capacitor, C9-ninth capacitor, C10-tenth capacitor, C11-eleventh capacitor, C12-twelfth capacitor, C13-thirteenth capacitor, C14-fourteenth capacitor, C15-fifteenth capacitor, C16-sixteenth capacitor, C17-seventeenth capacitor, C18-eighteenth capacitor, C19-nineteenth capacitor, C20-twentieth capacitor, C21-twenty-first capacitor, C22-twenty-second capacitor, C23-twenty-third capacitor, C24-twenty-fourth capacitor, C25-twenty-fifth capacitor , L1-first inductor, D1-first diode, D2-second diode, D3-third diode, D4-fourth diode, D5-fifth diode, D6-sixth diode, D7-seventh diode, D8-eighth diode, Q1-first NPN transistor, Q2-second NPN transistor, Q3-first NPN high-voltage field-effect transistor, Q4-second NPN high-voltage field-effect transistor, U5-first photoelectric isolation gate driver, U6-second photoelectric isolation gate driver, K1-first signal relay, K2-second signal relay, U1-first DC isolation module, U2-second DC isolation module, U3-third DC isolation module, FU1-first fuse. DETAILED DESCRIPTION

[0044] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0045] Example 1

[0046] This embodiment provides a scanning pulse circuit of a slow-scanning streak camera. Figure 1 , including a power supply module, a trigger buffer module, a positive pulse branch and a negative pulse branch;

[0047] The positive pulse branch includes a first drive circuit, a first gear adjustment circuit and a positive pulse generating circuit connected in sequence; the negative pulse branch includes a second drive circuit, a second gear adjustment circuit and a negative pulse generating circuit connected in sequence;

[0048] The input end of the first driving circuit and the input end of the second driving circuit are connected to the output end of the trigger buffer module, and the input end of the trigger buffer module contacts the signal;

[0049] The positive pulse generating circuit outputs a positive pulse, the negative pulse generating circuit outputs a negative pulse, the trigger buffer module is used to output an on-off control signal, and the power supply module is used to supply power to the trigger buffer module, the positive pulse branch and the negative pulse branch.

[0050] As a preferred solution of this embodiment, if the pulse width of the trigger signal is not less than the threshold time, the trigger buffer module includes a Schmitt trigger; if the pulse width of the trigger signal is less than the threshold time, the trigger buffer module includes a monostable oscillator.

[0051] In this embodiment, the power supply module includes a low-voltage DC power supply module and a high-voltage DC power supply module. The low-voltage DC power supply module is used to power the first drive circuit, the first gear adjustment circuit, the second drive circuit, the second gear adjustment circuit and the trigger buffer module, and the high-voltage DC power supply module is used to power the positive pulse generating circuit and the negative pulse generating circuit.

[0052] The streak camera scanning pulse circuit of this embodiment is essentially based on a switch tube. N-MOSFET can be used in the positive pulse branch and the negative pulse branch to control the charging and discharging of the forming network to form the streak camera scanning pulse.

[0053] The trigger signal first forms a standard N-MOSFET on-off control signal through a trigger buffer, and the pulse width of the control signal is related to the on-time of the N-MOSFET, that is, related to the retrace time. If the pulse width of the trigger signal is close to the retrace time, the trigger buffer can be composed of a Schmitt trigger to eliminate burrs, steepen the edge, and restore the voltage amplitude to a standard level such as an LV-TTL level; if the pulse width of the trigger signal is very short compared to the retrace time, the trigger buffer can be composed of a monostable oscillator to generate a fixed long pulse width control signal. That is to say, the threshold time of this embodiment can be preferably set to the on-time of the N-MOSFET in the specific circuit.

[0054] In this embodiment, both scanning pulse generating branches use N-MOSFET. Only positive high voltage power supply is needed, which reduces the complexity of high voltage power supply. Moreover, the withstand voltage of N-MOSFET is much higher than that of P-MOSFET. Under the same linear working area slope, the scanning pulse generated by the present invention can obtain a linear working area with a larger amplitude, which reduces the requirement for the deflection sensitivity of the streak camera.

[0055] The existing technology only adjusts the slope by adjusting the capacitance of the capacitor array. When designing for gears at or above the hundreds of nanosecond level, a larger capacitance is required. In addition, in order to ensure the pulse amplitude, from the perspective of capacitor series voltage division, the energy storage capacitor and isolation capacitor in the discharge circuit need to have a capacitance 5 to 10 times that of the capacitor array, which will inevitably lead to a large capacitor volume. In addition, the gear can only be switched by switching the capacitor array, which will inevitably require a high-voltage-resistant relay or switch. Both of these factors are not conducive to the realization of a compact circuit board.

[0056] In summary, when designing the scheme based on the present embodiment, the pulse waveform is adjusted from three dimensions: the N-MOSFET conduction speed, the static operating point and the forming network parameters. When designing the gear position at the order of 100 ns and above, the conduction speed can be reduced by increasing the series resistance of the N-MOSFET gate, so the requirements for the capacitance of the forming network can be reduced under the premise of ensuring nonlinearity (usually <5%). Therefore, the gear design of 100ns~5μs can be implemented with small-volume ceramic capacitors. The switching gear can be achieved by switching the gear adjustment circuit of the N-MOSFET at the low-voltage control end, and only common relays are needed. Therefore, the design of the present invention can achieve 1~3 gears on a compact structure of a two-layer circuit board within 150mm×150mm.

[0057] In addition, by adjusting the static operating point, the gate-source charging time of the N-MOSFET is reduced, and the starting delay can be adjusted to a certain extent. Combined with the resistance parameters in the shaping network, a lower starting delay time can be obtained. A waveform adjustment parameter is added.

[0058] It should be noted that in the figure, GND is the ground line or 0 line terminal, float is the floating ground terminal, and AGND is the analog ground terminal.

[0059] Based on the effect test results of the technical solution of this embodiment, for the application of slow-scan streak camera, the retrace time can be greater than 1ms, the nonlinearity is less than 5%, and the working area starting point delay is less than 200ns.

[0060] Example 2

[0061] This embodiment is based on the technical solution of Embodiment 1, and mainly further explains the related settings of the positive pulse branch.

[0062] In this embodiment, see Figure 2 , Figure 3 and Figure 4 , the first driving circuit includes a first photoelectric isolation gate driver U5, a plurality of resistors and capacitors; the model of the first photoelectric isolation gate driver U5 is preferably Si8221cc;

[0063] One end of the first resistor R1 is connected to the output end of the trigger buffer module, that is, the input on-off control signal Trig sig, the other end of the first resistor R1 is connected to the ANODE end of the first photoelectric isolation gate driver U5, the CATHODE end and the Vss end of the first photoelectric isolation gate driver U5 are grounded, the VDD end of the first photoelectric isolation gate driver U5 is connected to the positive end +15VP of the 15V DC source and one end of the second resistor R2, the two Vo ends of the first photoelectric isolation gate driver U5 are commonly connected to one end of the first capacitor C1, the other end of the first capacitor C1 and the other end of the second resistor R2 are connected to the first gear adjustment circuit, and the Vss end of the first photoelectric isolation gate driver U5 is floating.

[0064] As a preferred solution, the first gear adjustment circuit includes a first signal relay K1, a plurality of resistors, a diode and a first NPN transistor Q1; the first signal relay K1 adopts HFD4;

[0065] The first pin of the first signal relay K1 is connected to a 5V DC source and a cathode of a first diode D1, the eighth pin of the first signal relay K1 is connected to an anode of the first diode D1 and a collector of a first NPN transistor Q1, the emitter of the first NPN transistor Q1 is grounded, the base of the first NPN transistor Q1 is connected to one end of a fifth resistor R5 and one end of a sixth resistor R6, and the other end of the sixth resistor R6 is grounded;

[0066] The second pin of the first signal relay K1 is connected to one end of the seventh resistor R7, the other end of the seventh resistor R7 is connected to one end of the eighth resistor R8 and the seventh pin of the first signal relay K1, and the other end of the eighth resistor R8 is grounded; the fourth pin of the first signal relay K1 is connected to one end of the ninth resistor R9, the other end of the ninth resistor R9 is connected to one end of the tenth resistor R10 and the fifth pin of the second signal relay K1, and the other end of the tenth resistor R10 is grounded; the fourth pin of the first signal relay K1 is connected to the other end of the first capacitor C1 and the other end of the second resistor R2, and the third pin of the first signal relay K1 is connected to the positive pulse generating circuit;

[0067] The seventh resistor R7, the eighth resistor R8, the ninth resistor R9 and the tenth resistor R10 are sliding resistors.

[0068] Further, the positive pulse generating circuit includes a plurality of resistors, a plurality of capacitors and a first NPN high-voltage field effect transistor Q3;

[0069] The gate of the first NPN high-voltage field effect transistor Q3 is connected to the third pin of the first signal relay K1 and one end of the seventeenth resistor R17, the other end of the seventeenth resistor R17 is floating, the drain of the first NPN high-voltage field effect transistor Q3 is connected to one end of the third capacitor C3 and one end of the eighteenth resistor R18, the other end of the eighteenth resistor R18 is connected to a 2500V high-voltage DC source, and the other end of the third capacitor C3 is grounded; the source of the first NPN high-voltage field effect transistor Q3 is floating and connected to one end of the fourth capacitor C4 and one end of the nineteenth resistor R19, the other end of the fourth capacitor C4 is connected to the twentieth resistor R The first resistor R20 is connected to one end of the 20th resistor R20, the other end of the 21st resistor R21 is connected to one end of the 7th capacitor C7 and one end of the 22nd resistor R22, the other end of the 22nd resistor R22 is connected to one end of the 23rd resistor R23, the other end of the 23rd resistor R23 is connected to the other end of the 7th capacitor C7 and serves as a positive pulse output end, and the other end of the 21st resistor R21 is connected to a first bias module.

[0070] Firstly, the first driving circuit here mainly drives the chip locally to convert the control signal into a driving signal with the same pulse width and amplitude of +15V.

[0071] Next, the first gear adjustment circuit of this embodiment is a resistor network. The resistor network can change the charging speed of the gate-source voltage by adjusting the series resistor Rg of the N-MOSFET gate, thereby adjusting the conduction speed of the N-MOSFET, and finally affecting the leading edge slope of the output pulse to achieve gear adjustment. The static bias voltage of the gate is adjusted by a voltage divider circuit to adjust the output pulse amplitude and starting point delay. This embodiment provides a gear adjustment circuit design with two gears (380V / 700ns, 380V / 2μs). The keying signal SW is input from the fifth resistor R5 to control the on and off of the first NPN transistor Q1. The first NPN transistor Q1 uses a Darlington transistor here. When SW is a +5V signal, the first NPN transistor Q1 is turned on, the first signal relay K1 is switched to pins 2 and 3, and pins 7 and 6 are connected, thereby selecting the resistor network configuration of gear 1. When SW is a 0V signal, the first signal relay K1 is disconnected, and it is switched to pins 3 and 4, and pins 6 and 5 are connected, thereby selecting the resistor network configuration of gear 2. Here, by adjusting the seventh resistor R7, the conduction speed of the first NPN high-voltage field effect transistor Q3 in the subsequent positive pulse generating circuit can be changed; the eighth resistor R8 and the second resistor R2 in the driving circuit form a voltage divider network, thereby adjusting the static operating point of the first NPN high-voltage field effect transistor Q3 and changing the starting delay and amplitude of the pulse. Usually, the static voltage between the gate and the source is set between 0 and 3V.

[0072] The source of the first NPN high-voltage field effect transistor Q3 in the positive pulse generating circuit is not grounded, and as the first NPN high-voltage field effect transistor Q3 is turned on, the potential at its source is constantly increasing. In order to maintain the gate-source voltage between 0 and 20V, the driver chip of the positive pulse branch needs to be powered by a DC isolation module power supply that supports a floating output ground. Because the conduction time of N-MOSFET is generally 10 ns~30 ns, its edge speed is too fast for the slow scanning speed (≥100ns), so a low-pass filter can be set to reduce the slope of the leading edge to form a slope corresponding to the gear. In other aspects, the output impedance can be made close to the impedance of the output line connected to the deflection plate through an impedance matching circuit, and the high-frequency resonance formed by the parasitic inductance of the output line and the capacitance of the deflection plate is accelerated to attenuate.

[0073] Specifically, the positive pulse generation process is as follows: before the first NPN high-voltage field effect tube Q3 is turned on, the third capacitor C3 stores energy. After the first NPN high-voltage field effect tube Q3 is turned on, the third capacitor C3 charges the low-pass filter composed of the nineteenth resistor R19, the fifth capacitor C5, and the sixth capacitor C6 through the fourth capacitor C4 as an isolation capacitor, and then the first NPN high-voltage field effect tube Q3, the third capacitor C3, the fourth capacitor C4, the nineteenth resistor R19, the fifth capacitor C5, and the sixth capacitor C6 form a loop to form a positive pulse front edge that changes from 0 to positive high voltage. The seventh capacitor C7 in the figure is a reserved component for adjusting overshoot, and it can also be not installed according to demand. The twenty-second resistor R22 and the twenty-third resistor R23 play the role of impedance matching and attenuation of high-frequency resonance.

[0074] It is particularly noted that the first bias module provided in this embodiment provides a negative pre-bias voltage, which has the following functions: first, to prevent any electrons from passing through the deflection area before scanning starts; second, to select the linear working area of ​​the pulse front. Its working principle is as follows: as the voltage loaded on the deflection plates on both sides changes from +2Vth to -2Vth, the electron beam will be deflected from one edge of the deflection area to the other edge, and the voltage difference exceeds the range of [-2Vth, +2Vth], which will cause the electron beam to hit the deflection plate and the streak camera to have no signal output. Therefore, when the negative pre-bias voltage is set to -Vbias and the positive pre-bias voltage is set to +Vbias (Vbias ≥ Vth), it can be achieved that no electrons can pass through the deflection area before scanning starts. Therefore, -Vth+Vbias~Vth+Vbias is selected as the linear working area at the front edge of the positive pulse.

[0075] The pre-bias voltage is connected to the shaping network through the fourth capacitor C4 serving as an isolation capacitor and the nineteenth resistor R19. By reasonably setting the pre-bias voltage, a suitable linear working area can be selected.

[0076] In summary, the required scanning pulse can be generated by adjusting the conduction speed and static operating point of the first NPN high-voltage field effect transistor Q3 and performing pulse shaping.

[0077] Example 3

[0078] This embodiment is based on the technical solution of Embodiment 1, and mainly further explains the settings related to the negative pulse branch.

[0079] In this embodiment, see Figure 5 , Figure 6 and Figure 7 , the second driving circuit includes a second photoelectric isolation gate driver U6, a plurality of resistors and capacitors; the model of the second photoelectric isolation gate driver U6 is preferably Si8221cc;

[0080] One end of the third resistor R3 is connected to the output end of the trigger buffer module, the other end of the third resistor R3 is connected to the ANODE end of the second photoelectric isolation gate driver U6, the CATHODE end and the Vss end of the second photoelectric isolation gate driver U6 are grounded, the VDD end of the second photoelectric isolation gate driver U6 is connected to the negative end +15VN of the 15V DC source and one end of the fourth resistor R4, the two Vo ends of the second photoelectric isolation gate driver U6 are commonly connected to one end of the second capacitor C2, the other end of the second capacitor C2 and the other end of the fourth resistor R4 are connected to the second gear adjustment circuit, and the Vss end of the second photoelectric isolation gate driver U6 is floating.

[0081] As a preferred solution, the second gear adjustment circuit includes a second signal relay K2, a plurality of resistors, a diode and a second NPN transistor Q2; the second signal relay K2 adopts HFD4;

[0082] The first pin of the second signal relay K2 is connected to a 5V DC source and a cathode of the second diode D2, the eighth pin of the second signal relay K2 is connected to an anode of the second diode D2 and a collector of the second NPN transistor Q2, the emitter of the second NPN transistor Q2 is grounded, the base of the second NPN transistor Q2 is connected to one end of the eleventh resistor and one end of the twelfth resistor R12, and the other end of the twelfth resistor R12 is grounded;

[0083] The second pin of the second signal relay K2 is connected to one end of the thirteenth resistor R13, the other end of the thirteenth resistor R13 is connected to one end of the fourteenth resistor R14 and the seventh pin of the second signal relay K2, and the other end of the fourteenth resistor R14 is grounded;

[0084] The fourth pin of the second signal relay K2 is connected to one end of the ninety-fifth resistor, the other end of the fifteenth resistor R15 is connected to one end of the sixteenth resistor R16 and the fifth pin of the second signal relay K2, and the other end of the sixteenth resistor R16 is grounded; the fourth pin of the second signal relay K2 is connected to the other end of the second capacitor C2 and the other end of the fourth resistor R4, and the third pin of the second signal relay K2 is connected to the negative pulse generating circuit;

[0085] The thirteenth resistor R13, the fourteenth resistor R14, the fifteenth resistor R15 and the sixteenth resistor R16 are sliding resistors.

[0086] Furthermore, the negative pulse generating circuit includes a plurality of resistors, a plurality of capacitors and a second NPN high voltage field effect transistor Q4;

[0087] The gate of the second NPN high-voltage field effect transistor Q4 is connected to the third pin of the second signal relay K2 and one end of the twenty-fourth resistor R24, the other end of the twenty-fourth resistor R24 ​​is grounded, the source of the second NPN high-voltage field effect transistor Q4 is grounded, the drain of the second NPN high-voltage field effect transistor Q4 is connected to one end of the eighth capacitor C8 and one end of the twenty-fifth resistor R25, the other end of the twenty-fifth resistor R25 is connected to a 2500V high-voltage DC source, the other end of the eighth capacitor C8 is connected to one end of the twenty-sixth resistor R26, one end of the tenth capacitor C10 is grounded, the other end of the tenth capacitor C10 is connected to one end of the ninth capacitor C9, the other end of the ninth capacitor C9 is connected to the other end of the twenty-sixth resistor R26, one end of the twenty-seventh resistor R27, one end of the eleventh capacitor C11 and one end of the twenty-eighth resistor R28, the other end of the twenty-eighth resistor R28 is connected to one end of the twenty-ninth resistor R29, the other end of the twenty-ninth resistor R29 is connected to the other end of the eleventh capacitor C11 and serves as a positive pulse output end, and the other end of the twenty-seventh resistor R27 is connected to the second bias module.

[0088] The working principles of the second driving circuit and the second gear adjustment circuit of this embodiment are respectively the same as the first driving circuit and the first gear adjustment circuit in the positive pulse branch in Example 2. For details, please refer to the description of Example 2.

[0089] In addition, the second bias module of this embodiment provides a positive pre-bias voltage, and the negative pulse leading edge selects Vth-Vbias~-Vth-Vbias as the linear working area.

[0090] The main difference lies in the negative pulse generation in the negative pulse generation circuit. Specifically, the negative pulse generation process is as follows: before the second NPN high-voltage field effect tube Q4 is turned on, the eighth capacitor C8 has two functions: energy storage and isolation. After the second NPN high-voltage field effect tube Q4 is turned on, the eighth capacitor C8, the second NPN high-voltage field effect tube Q4, the ninth capacitor C9, the tenth capacitor C10, and the twenty-sixth resistor R26 form a loop. Since the lower end of the tenth capacitor C10 is clamped to AGND, the upper end of the ninth capacitor C9 forms a negative pulse front edge that changes from 0 to negative high voltage. The eleventh capacitor C11 in the figure is a reserved component for adjusting overshoot, and it can also be not installed according to needs. The twenty-eighth resistor R28 and the twenty-ninth resistor R29 play the role of impedance matching and attenuation of high-frequency resonance.

[0091] Example 4

[0092] This embodiment is based on the technical solution of Embodiment 1, and mainly further explains the relevant settings of the power supply module.

[0093] In this embodiment, the power supply module includes a low-voltage DC power supply module and a high-voltage DC power supply module. The low-voltage DC power supply module is used to power the first drive circuit, the first gear adjustment circuit, the second drive circuit, the second gear adjustment circuit and the trigger buffer module, and the high-voltage DC power supply module is used to power the positive pulse generating circuit and the negative pulse generating circuit.

[0094] As a case study, you can refer to Figure 8-Figure 9 , the low-voltage DC power supply module includes multiple capacitors, multiple resistors, a first fuse FU1, multiple diodes, multiple DC isolation modules and a first inductor L1;

[0095] The anode of the third diode D3 and the anode of the fourth diode D4 are connected to a DC power supply, the cathode of the third diode D3 and the cathode of the fourth diode D4 are connected to the cathode of the fifth diode D5 and one end of the first inductor L1, the anode of the fifth diode D5 is grounded, and the twelfth capacitor C12 and the thirteenth capacitor C13 are respectively connected in parallel with the fifth diode D5;

[0096] The sixteenth capacitor C16 is a polar capacitor, the fourteenth capacitor C14, the fifteenth capacitor C15 and the sixteenth capacitor C16 are connected in parallel, and the positive electrode of the sixteenth capacitor C16 is connected to the other end of the first inductor L1 and one end of the first fuse FU1, and the negative electrode of the sixteenth capacitor C16 is grounded;

[0097] The other end of the first fuse FU1 is connected to the vin end of the first DC isolation module U1, the vin end of the second DC isolation module U2, and the vin end of the third DC isolation module U3, and the gnd end of the first DC isolation module U1, the gnd end and the 0v end of the second DC isolation module U2, and the gnd end and the 0v end of the third DC isolation module U3 are grounded;

[0098] The 0v end of the first DC isolation module U1 is floating, the +vo end is connected to +15VP, one end of the 30th resistor R30, the positive electrode of the 17th capacitor C17 and one end of the 18th capacitor C18, the negative electrode of the 17th capacitor C17 and the other end of the 18th capacitor C18 are floating, and the other end of the 30th resistor R30 is connected to the anode of the sixth diode D6, which is a light emitting diode and has a cathode grounded;

[0099] The +vo terminal of the second DC isolation module U2 is connected to +15VN, one end of the thirty-first resistor R31, the positive electrode of the nineteenth capacitor C19, one end of the twentieth capacitor C20, the negative electrode of the nineteenth capacitor C19 and the other end of the twentieth capacitor C20 are grounded, and the other end of the thirty-first resistor R31 is connected to the anode of the seventh diode D7, the seventh diode D7 is a light emitting diode and the cathode is grounded;

[0100] The +vo terminal of the third DC isolation module U3 is connected to a 5V DC source, one end of the 32nd resistor R32, the positive electrode of the 21st capacitor C21 and one end of the 22nd capacitor C22, the negative electrode of the 21st capacitor C21 and the other end of the 22nd capacitor C22 are grounded, and the other end of the 32nd resistor R32 is connected to the anode of the eighth diode D8, the eighth diode D8 is a light emitting diode and the cathode is grounded;

[0101] The high-voltage DC power supply module includes multiple capacitors, a twenty-third capacitor C23, a twenty-fourth capacitor C24 and a twenty-fifth capacitor C25 are connected in parallel, one end of the parallel circuit is grounded, and the other end is connected to a 2500V high-voltage DC source.

[0102] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A scanning pulse circuit for a slow-scan streak camera, characterized in that: It includes a power supply module, a trigger buffer module, a positive pulse branch and a negative pulse branch; The positive pulse branch includes a first drive circuit, a first gear adjustment circuit and a positive pulse generating circuit connected in sequence; the negative pulse branch includes a second drive circuit, a second gear adjustment circuit and a negative pulse generating circuit connected in sequence; The input end of the first driving circuit and the input end of the second driving circuit are connected to the output end of the trigger buffer module, and the input end of the trigger buffer module contacts the signal; The positive pulse generating circuit outputs a positive pulse, the negative pulse generating circuit outputs a negative pulse, the trigger buffer module is used to output an on-off control signal, and the power supply module is used to supply power to the trigger buffer module, the positive pulse branch and the negative pulse branch; The first gear adjustment circuit includes a first signal relay, a plurality of resistors, a diode and a first NPN transistor; the first signal relay adopts HFD4; The sixth pin of the first signal relay is connected to the first drive circuit; The first pin of the first signal relay is connected to a 5V DC source and a cathode of a first diode, the eighth pin of the first signal relay is connected to an anode of the first diode and a collector of a first NPN transistor, the emitter of the first NPN transistor is grounded, the base of the first NPN transistor is connected to one end of a fifth resistor and one end of a sixth resistor, the other end of the sixth resistor is grounded, and the other end of the fifth resistor is connected to a keying signal SW; The second pin of the first signal relay is connected to one end of the seventh resistor, the other end of the seventh resistor is connected to one end of the eighth resistor and the seventh pin of the first signal relay, and the other end of the eighth resistor is grounded; the fourth pin of the first signal relay is connected to one end of the ninth resistor, the other end of the ninth resistor is connected to one end of the tenth resistor and the fifth pin of the first signal relay, and the other end of the tenth resistor is grounded; the third pin of the first signal relay is connected to the positive pulse generating circuit; The seventh resistor, the eighth resistor, the ninth resistor and the tenth resistor are sliding resistors; The positive pulse generating circuit comprises a plurality of resistors, a plurality of capacitors and a first NPN high voltage field effect transistor; The gate of the first NPN high-voltage field effect transistor is connected to the third pin of the first signal relay and one end of the seventeenth resistor, the other end of the seventeenth resistor is floating, the drain of the first NPN high-voltage field effect transistor is connected to one end of the third capacitor and one end of the eighteenth resistor, the other end of the eighteenth resistor is connected to a 2500V high-voltage DC source, and the other end of the third capacitor is grounded; the source of the first NPN high-voltage field effect transistor is floating and connected to one end of the fourth capacitor and one end of the nineteenth resistor, the other end of the fourth capacitor is connected to one end of the twentieth resistor, the other end of the nineteenth resistor is grounded and connected to one end of the sixth capacitor, the other end of the sixth capacitor is connected to one end of the fifth capacitor, the other end of the fifth capacitor is connected to the other end of the twentieth resistor, one end of the twenty-first resistor, one end of the seventh capacitor and one end of the twenty-second resistor, the other end of the twenty-second resistor is connected to one end of the twenty-third resistor, the other end of the twenty-third resistor is connected to the other end of the seventh capacitor and serves as a positive pulse output end, and the other end of the twenty-first resistor is connected to a first bias module; The second gear adjustment circuit includes a second signal relay, a plurality of resistors, a diode and a second NPN transistor; the second signal relay adopts HFD4; The sixth pin of the second signal relay is connected to the second drive circuit; The first pin of the second signal relay is connected to a 5V DC source and a cathode of the second diode, the eighth pin of the second signal relay is connected to an anode of the second diode and a collector of the second NPN transistor, the emitter of the second NPN transistor is grounded, the base of the second NPN transistor is connected to one end of an eleventh resistor and one end of a twelfth resistor, the other end of the twelfth resistor is grounded, and the other end of the eleventh resistor is connected to a keying signal SW; The second pin of the second signal relay is connected to one end of a thirteenth resistor, the other end of the thirteenth resistor is connected to one end of a fourteenth resistor and the seventh pin of the second signal relay, and the other end of the fourteenth resistor is grounded; The fourth pin of the second signal relay is connected to one end of the fifteenth resistor, the other end of the fifteenth resistor is connected to one end of the sixteenth resistor and the fifth pin of the second signal relay, and the other end of the sixteenth resistor is grounded; the third pin of the second signal relay is connected to the negative pulse generating circuit; The thirteenth resistor, the fourteenth resistor, the fifteenth resistor and the sixteenth resistor are sliding resistors; The negative pulse generating circuit includes a plurality of resistors, a plurality of capacitors and a second NPN high voltage field effect transistor; The gate of the second NPN high-voltage field effect transistor is connected to the third pin of the second signal relay and one end of the twenty-fourth resistor, the other end of the twenty-fourth resistor is grounded, the source of the second NPN high-voltage field effect transistor is grounded, the drain of the second NPN high-voltage field effect transistor is connected to one end of the eighth capacitor and one end of the twenty-fifth resistor, the other end of the twenty-fifth resistor is connected to a 2500V high-voltage DC source, the other end of the eighth capacitor is connected to one end of the twenty-sixth resistor, one end of the tenth capacitor is grounded, the other end of the tenth capacitor is connected to one end of the ninth capacitor, the other end of the ninth capacitor is connected to the other end of the twenty-sixth resistor, one end of the twenty-seventh resistor, one end of the eleventh capacitor and one end of the twenty-eighth resistor, the other end of the twenty-eighth resistor is connected to one end of the twenty-ninth resistor, the other end of the twenty-ninth resistor is connected to the other end of the eleventh capacitor and serves as a positive pulse output end, and the other end of the twenty-seventh resistor is connected to the second bias module.

2. The scanning pulse circuit of a slow-scan streak camera according to claim 1, characterized in that: If the pulse width of the trigger signal is not less than the threshold time, the trigger buffer module includes a Schmitt trigger; if the pulse width of the trigger signal is less than the threshold time, the trigger buffer module includes a monostable oscillator.

3. The scanning pulse circuit of a slow-scan streak camera according to claim 1, characterized in that: The first driving circuit includes a first photoelectrically isolated gate driver, a plurality of resistors and capacitors; One end of the first resistor is connected to the output end of the trigger buffer module, the other end of the first resistor is connected to the ANODE end of the first photoelectric isolation gate driver, the CATHODE end of the first photoelectric isolation gate driver is grounded, the VDD end of the first photoelectric isolation gate driver is connected to the positive end +15VP of the 15V DC source and one end of the second resistor, the two Vo ends of the first photoelectric isolation gate driver are commonly connected to one end of the first capacitor, the other end of the first capacitor and the other end of the second resistor are connected to the sixth pin of the first signal relay in the first gear adjustment circuit, and the Vss end of the first photoelectric isolation gate driver is floating.

4. The scanning pulse circuit of a slow-scan streak camera according to claim 1, characterized in that: The second driving circuit includes a second photoelectrically isolated gate driver, a plurality of resistors and capacitors; One end of the third resistor is connected to the output end of the trigger buffer module, the other end of the third resistor is connected to the ANODE end of the second photoelectric isolation gate driver, the CATHODE end of the second photoelectric isolation gate driver is grounded, the VDD end of the second photoelectric isolation gate driver is connected to the negative end +15VN of the 15V DC source and one end of the fourth resistor, the two Vo ends of the second photoelectric isolation gate driver are commonly connected to one end of the second capacitor, the other end of the second capacitor and the other end of the fourth resistor are connected to the sixth pin of the second signal relay of the second gear adjustment circuit, and the Vss end of the second photoelectric isolation gate driver is floating.

5. The scanning pulse circuit of a slow-scan streak camera according to claim 1, characterized in that: The power supply module includes a low-voltage DC power supply module and a high-voltage DC power supply module. The low-voltage DC power supply module is used to power the first drive circuit, the first gear adjustment circuit, the second drive circuit, the second gear adjustment circuit and the trigger buffer module, and the high-voltage DC power supply module is used to power the positive pulse generating circuit and the negative pulse generating circuit.

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