SiC mosfet driving circuit and control method thereof

Abstract

The application discloses a SiC MOSFET driving circuit and a control method thereof, which comprises an active current source driving circuit, a SiC MOSFET, a load current detection circuit, a drain-source voltage overshoot detection circuit, an analog-digital conversion module and an FPGA module, and the FPGA module is internally provided with an adaptive adjustment algorithm. The load current detection circuit and the drain-source voltage overshoot detection circuit have relatively low real-time requirements, the use of high-speed analog devices is avoided, the hardware design cost is reduced, and the adaptive adjustment algorithm can adjust the SiC MOSFET gate driving parameters in real time according to the output of the load current detection circuit and the drain-source voltage overshoot detection circuit, so that the overshoot and the switching loss are adaptively balanced, and the safe operation of the SiC MOSFET is ensured. The technical problems of high hardware cost of the SiC MOSFET driving circuit with active gate driving and difficulty in balancing the voltage and current overshoot and the switching loss are solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor switching circuit, and particularly relates to a SiC MOSFET driving circuit and a control method thereof. BACKGROUND

[0002] As a substitute for traditional silicon-based devices, silicon carbide metal oxide semiconductor field effect transistor (SiC MOSFET) has the advantages of faster switching speed, lower conduction loss and higher blocking voltage, and is expected to significantly improve the efficiency and power density of electric energy conversion devices. Gate drive directly affects the operating state of the switching device, and good gate drive not only can provide strong guarantee for the safe operation of the switching device, but also can effectively reduce the switching loss and electromagnetic interference generated by the device, and effectively improve the performance of the electric energy conversion device. The typical working principle of gate drive is to charge and discharge the input capacitance of SiC MOSFET by using a voltage source and a gate resistor, so as to realize the conduction and turn-off control of the switching device. Due to the existence of parasitic capacitance and stray inductance, the SiC MOSFET will have obvious current overshoot and current overshoot during the conduction and turn-off process. Once the overshoot current and the overshoot voltage exceed the safe operating area (SOA) of the SiC MOSFET, that is, the current threshold and the voltage threshold, the SiC MOSFET will appear aging, and in severe cases, it will cause irreversible damage to the switching device, and further cause serious threat to the entire circuit system.

[0003] ​Conventional gate driver (CGD) uses fixed gate resistance to drive switching devices, so in order to suppress voltage and current overshoot, CGD can only replace smaller gate resistance with larger resistance. This method will result in longer switching delay, slower switching speed and larger switching loss. In order to better trade off overshoot and loss, active gate driver (AGD) emerges as the times require. Current source drive composed of inductance needs more than 2 control switches and multiple control signals for accurate control of inductive precharge process. Although current mirror composed of current source drive is relatively simple in control process, it needs more control switches and more complex circuit structure. In order to realize accurate closed-loop control in a very short switching stage, switching state detection circuit and feedback circuit need to use high-bandwidth analog devices and analog-to-digital conversion chips, which greatly increases the manufacturing cost of active gate driver. In the application where the DC bus voltage or load current changes greatly over time, such as wind power generation, the voltage and current overshoot of the switching device will be different in each switching period. If the overshoot of the two is far below the threshold of SOA in the case of lower voltage or current, the fixed control parameters of AGD used to suppress voltage or current overshoot will cause unnecessary switching loss. Therefore, for SiC MOSFET drive circuit of active gate driver, how to avoid using high-speed analog devices, reduce hardware cost, and trade off voltage and current overshoot and switching loss is a technical problem that those skilled in the art are eager to solve. SUMMARY

[0004] The application provides a SiC MOSFET drive circuit and a control method thereof, which are used to solve the technical problems of high hardware cost and difficulty in balancing voltage and current overshoot and switching loss of SiC MOSFET drive circuit of active gate driver.

[0005] Therefore, the first aspect of the application provides a SiC MOSFET drive circuit, which comprises an active current source drive circuit, a SiC MOSFET, a load current detection circuit, a drain-source voltage overshoot detection circuit, an analog-to-digital conversion module and an FPGA module.

[0006] The output of the active current source drive circuit is connected with the gate of the SiC MOSFET.

[0007] The load current detection circuit is connected with the SiC MOSFET and is used to detect the drain-source current flowing through the SiC MOSFET and output a voltage signal corresponding to the drain-source current of the SiC MOSFET.

[0008] The drain-source voltage overshoot detection circuit is connected with the SiC MOSFET and is used for detecting the drain-source voltage overshoot of the SiC MOSFET.

[0009] The input end of the analog-digital conversion module is connected with the output end of the load current detection circuit and the output end of the drain-source voltage overshoot detection circuit respectively, and the output end of the analog-digital conversion module is connected with the input end of the FPGA module.

[0010] The FPGA module is internally provided with a PWM unit and a digital controller, the output end of the PWM unit is connected with the PWM signal input end of the active current source driving circuit, the PWM unit is used for generating a PWM signal for controlling the turn-on or turn-off of the active current source driving circuit and generating a reset signal for controlling the reset of the drain-source voltage overshoot detection circuit according to the PWM signal, and the digital controller is internally provided with an adaptive adjustment algorithm, the adaptive adjustment algorithm is used for controlling the gate current size of the SiC MOSFET output by the active current source driving circuit according to the outputs of the load current detection circuit and the drain-source voltage overshoot detection circuit.

[0011] Optionally, the active current source driving circuit comprises a voltage source, a PNP triode, an NPN triode, an adjustable turn-on resistance and an adjustable turn-off resistance.

[0012] The emitter of the PNP triode and the emitter of the NPN triode are connected in parallel, and the collector of the PNP triode and the collector of the NPN triode are connected in parallel.

[0013] The positive pole of the voltage source is connected with the emitter connection end of the PNP triode and the NPN triode, and the negative pole of the voltage source is connected with the Kelvin source of the SiC MOSFET.

[0014] The collector connection end of the PNP triode and the NPN triode is connected with the gate of the SiC MOSFET.

[0015] The base of the PNP triode is connected with one end of the adjustable turn-on resistance, the base of the NPN triode is connected with one end of the adjustable turn-off resistance, the other end of the adjustable turn-on resistance and the other end of the adjustable turn-off resistance are connected and are commonly connected to the Kelvin source of the SiC MOSFET.

[0016] Optionally, the adjustable turn-on resistance comprises a plurality of turn-on resistances with different resistance values connected in parallel, each of the turn-on resistances is connected with a first analog switch in series, and one end of all the turn-on resistances is commonly connected, and one end of all the first analog switches is commonly connected.

[0017] Optionally, the adjustable turn-off resistance comprises a plurality of turn-off resistors with different resistance values connected in parallel, each of the turn-off resistors is connected in series with a second analog switch, and one end of all the turn-off resistors is connected together, and one end of all the second analog switches is connected together.

[0018] Optionally, the adaptive adjustment algorithm is specifically used for:

[0019] comparing the output of the drain-source voltage overshoot detection circuit with a lower overshoot voltage limit, if the output of the drain-source voltage overshoot detection circuit is less than the lower overshoot voltage limit, adjusting the gate current of the SiC MOSFET by reducing the adjustable turn-off resistance, if the output of the drain-source voltage overshoot detection circuit is greater than the lower overshoot voltage limit and less than an upper overshoot voltage limit, not adjusting the adjustable turn-off resistance, and if the output of the drain-source voltage overshoot detection circuit is greater than the upper overshoot voltage limit, adjusting the gate current of the SiC MOSFET by increasing the adjustable turn-off resistance;

[0020] dividing the load current output by the load current detection circuit into a plurality of current intervals, each current interval corresponding to a resistance value, and adjusting the resistance value of the adjustable turn-on resistance to the resistance value corresponding to the current interval into which the load current output by the load current detection circuit falls.

[0021] Optionally, the drain-source voltage overshoot detection circuit comprises an overshoot detection circuit and a subtraction circuit.

[0022] The overshoot detection circuit comprises a diode, a capacitor, a reset switch and a current limiting resistor, the anode of the diode is connected to the drain of the SiC MOSFET, the cathode of the diode is connected to one end of the capacitor, the other end of the capacitor is connected to the source of the SiC MOSFET, one end of the reset switch is connected to the cathode of the diode, the other end of the reset switch is connected to one end of the current limiting resistor, and the other end of the current limiting resistor is connected to a DC bus.

[0023] The subtraction circuit comprises a first resistor, a second resistor, a third resistor, a fourth resistor and an operational amplifier, one end of the first resistor is connected to the cathode of the diode, the other end of the first resistor is connected to the non-inverting input terminal of the operational amplifier, one end of the second resistor is connected to the non-inverting input terminal of the operational amplifier, the other end of the second resistor is grounded, one end of the third resistor is connected to the anode of the diode, the other end of the third resistor is connected to the inverting input terminal of the operational amplifier, one end of the fourth resistor is connected to the inverting input terminal of the operational amplifier, and the other end of the fourth resistor is connected to the output terminal of the operational amplifier.

[0024] Optionally, the load current detection circuit is a Hall current sensor.

[0025] Optionally, the PWM unit generates a reset signal for resetting the drain-source voltage overshoot detection circuit when the PWM signal is converted from low level to high level.

[0026] Optionally, the analog-to-digital conversion module comprises a first ADC chip and a second ADC chip.

[0027] The input end of the first ADC chip is connected with the output end of the drain-source voltage overshoot detection circuit, and the output end of the first ADC chip is connected with the first input end of the digital controller.

[0028] The input end of the second ADC chip is connected with the output end of the load current detection circuit, and the output end of the second ADC chip is connected with the second input end of the digital controller.

[0029] Optionally, when the PNP triode is turned on, the output current of the active current source driving circuit is:

[0030]

[0031] wherein, is the output current of the active current source driving circuit, is the current gain of the PNP triode, is the output voltage of the voltage source, is the voltage drop between the base and the emitter of the PNP triode, is the adjustable on-resistance.

[0032] Optionally, when the NPN triode is turned on, the output current of the active current source driving circuit is:

[0033]

[0034] wherein, is the output current of the active current source driving circuit, is the current gain of the NPN triode, is the output voltage of the voltage source, is the voltage drop between the base and the emitter of the NPN triode, is the adjustable off-resistance.

[0035] The second aspect of the present application provides a control method applied to the SiC MOSFET driving circuit of any one of the first aspect of the present application, comprising:

[0036] The FPGA module generates a PWM signal for controlling the active current source driving circuit to turn on or turn off;

[0037] The FPGA module acquires the output of the load current detection circuit or the output of the drain-source voltage overshoot detection circuit;

[0038] The FPGA module controls the output of the active current source driving circuit to the gate current of the SiC MOSFET according to the load current output by the load current detection circuit or the overshoot voltage output by the drain-source voltage overshoot detection circuit;

[0039] The FPGA module determines whether to generate a reset signal for controlling the reset of the drain-source voltage overshoot detection circuit according to the PWM signal, and if so, generates the reset signal for controlling the reset of the drain-source voltage overshoot detection circuit and sends the reset signal to the drain-source voltage overshoot detection circuit.

[0040] From the above technical solutions, the SiC MOSFET driving circuit provided by the application has the following advantages:

[0041] The SiC MOSFET driving circuit provided by the application includes an active current source driving circuit, a SiC MOSFET, a load current detection circuit, a drain-source voltage overshoot detection circuit, an analog-to-digital conversion module, and an FPGA module, and the FPGA module has a built-in adaptive adjustment algorithm. The load current detection circuit and the drain-source voltage overshoot detection circuit have low real-time requirements, avoiding the use of high-speed analog devices and reducing the hardware design cost. The adaptive adjustment algorithm can adjust the SiC MOSFET gate drive parameters in real time according to the output of the load current detection circuit and the drain-source voltage overshoot detection circuit, thereby adaptively balancing the overshoot and switching loss and ensuring the safe operation of the SiC MOSFET. The technical problems of high hardware cost and difficulty in balancing voltage and current overshoot and switching loss of the active gate drive SiC MOSFET driving circuit are solved.

[0042] At the same time, the SiC MOSFET driving circuit provided by the application uses a current source driving circuit composed of a voltage source and a parallel transistor composed of a PNP transistor and an NPN transistor, which has a simple structure and control mode, produces more constant gate current, and can realize fast turn-on and turn-off of the SiC MOSFET, and better balance between overshoot and switching loss. BRIEF DESCRIPTION OF DRAWINGS

[0043] In order to make the technical scheme of the present application or the prior art clearer, the accompanying drawings needed in the description of the embodiments or the prior art will be briefly introduced. Obviously, the accompanying drawings in the description are only some embodiments of the present application, and for those skilled in the art, other related drawings can be obtained without creative effort.

[0044] Figure 1 A structural schematic diagram of a SiC MOSFET driving circuit provided in an embodiment of the present application;

[0045] Figure 2 A schematic diagram of an active current source driving circuit provided in an embodiment of the present application;

[0046] Figure 3 A schematic diagram of a drain-source voltage overshoot detection circuit provided in an embodiment of the present application;

[0047] Figure 4 A working waveform diagram of a drain-source voltage overshoot detection circuit provided in an embodiment of the present application;

[0048] Figure 5 A voltage and current waveform diagram of a SiC MOSFET under the control of a quasi-closed-loop active gate driving circuit provided in an embodiment of the present application;

[0049] Figure 6 A current waveform diagram of a SiC MOSFET in the turn-on stage under different turn-on resistances provided in an embodiment of the present application;

[0050] Figure 7 A voltage waveform diagram of a SiC MOSFET in the turn-off stage under different turn-off resistances provided in an embodiment of the present application;

[0051] Figure 8 A flowchart of a control method of a SiC MOSFET driving circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0052] In order to make the technical scheme of the present application or the prior art clearer, the accompanying drawings needed in the description of the embodiments or the prior art will be briefly introduced. Obviously, the accompanying drawings in the description are only some embodiments of the present application, and for those skilled in the art, other related drawings can be obtained without creative effort.

[0053] For better understanding, please refer to Figure 1The application provides an embodiment of a SiC MOSFET driving circuit, comprising an active current source driving circuit, a SiC MOSFET, a load current detection circuit, a drain-source voltage overshoot detection circuit, an analog-digital conversion module and an FPGA module.

[0054] The output of the active current source driving circuit is connected with the gate of the SiC MOSFET.

[0055] The load current detection circuit is connected with the SiC MOSFET, and is used for detecting the drain-source current flowing through the SiC MOSFET and outputting a voltage signal corresponding to the drain-source current of the SiC MOSFET.

[0056] The input end of the analog-digital conversion module is connected with the output end of the load current detection circuit and the output end of the drain-source voltage overshoot detection circuit respectively, and the output end of the analog-digital conversion module is connected with the input end of the FPGA module.

[0057] The FPGA module is internally provided with a PWM unit and a digital controller, the output end of the PWM unit is connected with the PWM signal input end of the active current source driving circuit, the PWM unit is used for generating a PWM signal for controlling the turn-on or turn-off of the active current source driving circuit and a reset signal for controlling the reset of the drain-source voltage overshoot detection circuit according to the PWM signal, and the digital controller is internally provided with an adaptive adjustment algorithm, the adaptive adjustment algorithm is used for controlling the size of the gate current of the SiC MOSFET provided by the active current source driving circuit according to the outputs of the load current detection circuit and the drain-source voltage overshoot detection circuit.

[0058] It should be noted that, Figure 1 In the formula, G is the gate of the MOSFET, D is the drain of the MOSFET, S is the source of the MOSFET, is the parasitic capacitance between the gate G and the drain D of the MOSFET, is the parasitic capacitance between the drain D and the source S of the MOSFET, is the parasitic capacitance between the gate G and the source S of the MOSFET, and s is the Kelvin source of the MOSFET, is the parasitic inductance. The output of the active current source driving circuit is connected with the gate G of the SiC MOSFET, and the output of the active current source driving circuit provides the gate current of the SiC MOSFET . The drain-source voltage ( ) overshoot detection circuit detects the overshoot voltage between the drain D and the source S of the switching device MOSFET and outputs to the field programmable gate array (FPGA) module, and the load current ( The detection circuit detects the load current of the SiC MOSFET, that is, the current flowing through the drain source of the SiC MOSFET, converts it into a voltage signal for output. The outputs of the drain-source voltage overshoot detection circuit and the load current detection circuit are first subjected to analog-digital conversion by the analog-digital conversion module before being input into the FPGA module. Specifically, the analog-digital conversion module includes a first ADC chip and a second ADC chip, the input end of the first ADC chip is connected with the output end of the drain-source voltage overshoot detection circuit, the output end of the first ADC chip is connected with the first input end of the digital controller, the input end of the second ADC chip is connected with the output end of the load current detection circuit, and the output end of the second ADC chip is connected with the second input end of the digital controller. The digital controller is internally provided with an adaptive adjustment algorithm for controlling the gate current of the MOSFET, which controls the gate current of the SiC MOSFET output by the active current source driving circuit according to the outputs of the load current detection circuit and the drain-source voltage overshoot detection circuit. The PWM unit inside the FPGA module controls the active current source driving circuit to turn on or turn off by outputting a PWM signal to the active current source driving circuit, and generates a reset signal for controlling the reset of the drain-source voltage overshoot detection circuit according to the PWM signal . The adaptive adjustment algorithm can adjust the gate current in real time according to different working conditions. When the SiC MOSFET operates in the safe operating area (SOA), the gate current can be appropriately increased to reduce the switching loss; when the SiC MOSFET operates at the boundary of the SOA, the gate drive current is reduced to reduce the overshoot and ensure the safe operation of the SiC MOSFET.

[0059] In one embodiment, as shown in Figure 2 , the active current source driving circuit includes a voltage source , a PNP transistor , an NPN transistor , and a base resistor including an adjustable on-resistance and an adjustable off-resistance , the emitter of the PNP transistor and the emitter of the NPN transistor are connected in parallel, the collector of the PNP transistor and the collector of the NPN transistor are connected in parallel, the positive pole of the voltage source is connected with the emitter connection end of the PNP transistor and the NPN transistor , the negative pole of the voltage source is connected with the Kelvin source of the SiC MOSFET, and the base of the PNP transistor and NPN transistor The collector terminal of the PNP transistor is connected to the gate of the SiC MOSFET. The base and adjustable on-resistance One end is connected to the base of the NPN transistor and the adjustable turn-off resistor. One end is connected to an adjustable on-resistance. The other end and the adjustable turn-off resistor The other end is connected and together with the Kelvin source s of the SiC MOSFET. Voltage source It receives the PWM signal output from the FPGA module and outputs a positive level (+15V) or a negative level (-5V) according to the PWM signal. When the voltage source... When the output is positive (+15V), the PNP transistor... When the circuit is turned on, the output current is:

[0060]

[0061] in, The output current of the active current source drive circuit. This represents the current gain of the PNP transistor. The output voltage of the voltage source. This is the voltage drop between the base and emitter of a PNP transistor. It is an adjustable on-resistance.

[0062] Similar to the turn-on process, when the voltage source When the output is negative (-5V), the NPN transistor is turned on, and the output current is:

[0063]

[0064] in, The output current of the active current source drive circuit. This represents the current gain of the NPN transistor. The output voltage of the voltage source. This is the voltage drop between the base and emitter of an NPN transistor. This is an adjustable turn-off resistor. It should be noted that if all parameters remain constant during the switching process, the gate current... The clamped value is constant.

[0065] To achieve active control of the gate current, the adjustable on-resistance Includes several parallel on-resistors of different resistance values ​​( Each on-resistor is connected in series with a first analog switch, and all on-resistors ( One end of all the first analog switches is connected together. ) are connected in common. The first analog switch (S1) is controlled by the analog switch control voltage (V1) output by the FPGA module. When the analog switch control voltage is high, the analog switch is turned on, and the resistance connected in this path is connected in parallel with the base of the transistor. When the signal in this path is low, the analog switch is turned off, and the resistance connected in this path is disconnected from the base of the transistor. ) are controlled by the analog switch control voltage (V1) output by the FPGA module, respectively. When the analog switch control voltage in a certain path is high, the analog switch is turned on, and the resistance connected in this path is connected in parallel with the base of the transistor. When the signal in this path is low, the analog switch is turned off, and the resistance connected in this path is disconnected from the base of the transistor. The adjustable off-resistance (Roff) includes a plurality of off-resistances (Roff1, Roff2, Roff3, Roff4, Roff5, Roff6) connected in parallel, each off-resistance is connected in series with a second analog switch (S2), and one end of all the off-resistances (Roff1, Roff2, Roff3, Roff4, Roff5, Roff6) is connected in common, and one end of all the second analog switches (S2) is connected in common. The second analog switch (S2) is controlled by the analog switch control voltage (V2) output by the FPGA module. When the analog switch control voltage in a certain path is high, the analog switch is turned on, and the resistance connected in this path is connected in parallel with the base of the transistor. When the signal in this path is low, the analog switch is turned off, and the resistance connected in this path is disconnected from the base of the transistor. According to the above two calculation formulas, the current amplitude output by the transistor will change. Therefore, by actively adjusting the adjustable on-resistance (Ron) and the adjustable off-resistance (Roff) through the FPGA module, active control of the gate current (Ig) can be achieved. In one embodiment, to realize quasi-closed loop control, a load current (IL) detection circuit and a drain-source voltage (VDS) overshoot detection circuit are needed to detect the working condition of the SiC MOSFET in real time. The current overshoot peak value generated in the on stage has a direct relationship with the amplitude of the load current, that is, the larger the current flowing through the SiC MOSFET, the larger the corresponding current overshoot. Therefore, the current detection circuit used in the present application detects the load current (IL) after the SiC MOSFET is completely turned on, rather than the high-frequency current in the switching stage. Since only low-frequency load current needs to be detected, a Hall current sensor can complete the detection. The Hall current sensor is connected to the drain (D) of the SiC MOSFET. When the load current (IL) flows through the Hall current sensor, the Hall current sensor generates a voltage signal (VH) from the current signal (IH) detected, and sends the voltage signal (VH) to the FPGA module. In one embodiment, as shown in

[0066] In one embodiment, to realize quasi-closed loop control, a load current (IL) detection circuit and a drain-source voltage (VDS) overshoot detection circuit are needed to detect the working condition of the SiC MOSFET in real time. The current overshoot peak value generated in the on stage has a direct relationship with the amplitude of the load current, that is, the larger the current flowing through the SiC MOSFET, the larger the corresponding current overshoot. Therefore, the current detection circuit used in the present application detects the load current (IL) after the SiC MOSFET is completely turned on, rather than the high-frequency current in the switching stage. Since only low-frequency load current needs to be detected, a Hall current sensor can complete the detection. The Hall current sensor is connected to the drain (D) of the SiC MOSFET. When the load current (IL) flows through the Hall current sensor, the Hall current sensor generates a voltage signal (VH) from the current signal (IH) detected, and sends the voltage signal (VH) to the FPGA module.

[0067] In one embodiment, as shown in Figure 3 ​​​​​​​​​​​​​​​As shown, in this invention, the drain-source voltage overshoot detection circuit includes an overshoot detection circuit and a subtraction circuit. The overshoot detection circuit includes a diode. ,capacitance Reset switch and current limiting resistor ,diode The anode of the diode is connected to the drain D of the SiC MOSFET. Cathode and capacitor One end is connected to the capacitor. The other end is connected to the source (S) of the SiC MOSFET, serving as a reset switch. One end is connected to the diode Cathode connection, reset switch The other end is connected to the current-limiting resistor One end is connected to the current-limiting resistor. The other end is connected to the DC bus. The connection, the subtraction circuit includes a first resistor. Second resistor Third resistor Fourth resistor and operational amplifier First resistor One end is connected to the diode Cathode connection, first resistor The other end is connected to the operational amplifier The non-inverting input terminal is connected, and the second resistor is connected. One end is connected to the operational amplifier The non-inverting input terminal is connected, and the second resistor is connected. The other end is grounded, and the third resistor One end is connected to the diode Anode connection, third resistor The other end is connected to the operational amplifier The inverting input terminal is connected to the fourth resistor. One end is connected to the operational amplifier The inverting input terminal is connected to the fourth resistor. The other end is connected to the operational amplifier Connect the output terminal. Operational amplifier. Output The data is transmitted from the FPGA's analog-to-digital converter to the FPGA's digital controller. To ensure the overshoot detection circuit functions correctly, a reset switch needs to be activated. Turn on, DC bus voltage Through the current-limiting resistor For capacitors Charge until the capacitor... The voltage at both ends reaches the DC bus voltage. Then, reset the switch. Turn off. (For example) Figure 4 As shown, when the PWM signal changes from high to low, the SiC MOSFET is turned off. It rose rapidly and overshooted. When Exceed At that time, diode On capacitor Charging, capacitor Voltage at both ends Rise until the overshoot peak Due to diodes Diode can only conduct in one direction. Will be clamped to Once the overshoot and oscillations have completely disappeared, Will be clamped to It is worth noting that in the subtraction circuit, the first resistor... Second resistor Third resistor and the fourth resistor The resistance values ​​are equal. After the oscillation disappears, and After passing through the subtraction circuit, the output of the subtraction circuit is: The result is then converted into a digital signal and transmitted to the FPGA's digital controller. Finally, as... Figure 4 As shown, when the PWM signal changes from low to high, the PWM unit generates a reset signal to control the reset of the drain-source voltage overshoot detection circuit. Sending the signal to the drain-source voltage overshoot detection circuit to reset the switch. Upon receiving a reset signal Then, reset the switch. Turn on, and put the capacitor Voltage at both ends Reset to Operational amplifier Output for:

[0068]

[0069] The adaptive adjustment algorithm is executed in the FPGA module, and the execution result is output to the adjustable on-resistance. and adjustable turn-off resistor Change the adjustable on-resistance and adjustable turn-off resistor The impedance is adjusted to drive the output current of the current source. This enables active control of the switching behavior of SiC MOSFETs. For example... Figure 5As shown, during the turn-off process, the FPGA module receives the detected overshoot signal. Then, first compare with the lower limit of overshoot voltage. Compare, if it is less than the lower voltage limit (i.e. The adaptive adjustment algorithm will actively reduce the adjustable turn-off resistance. The FPGA module generates a reduced adjustable turn-off resistance. The PWM signal speeds up the turn-off process; if the detected signal is greater than the lower voltage limit but less than the upper voltage limit (i.e., ... The adaptive adjustment algorithm will not generate a PWM signal and will not adjust the adjustable turn-off resistor. If the detected signal is greater than the upper voltage limit (i.e. The adaptive adjustment algorithm will generate an increase in the adjustable turn-off resistance. The PWM signal is adjusted by adding an adjustable turn-off resistor. This reduces overshoot. During the start-up process, the adaptive adjustment algorithm divides the load current into several current intervals ( Each interval has a corresponding resistance value; after the FPGA receives the load current signal, it adjusts the adjustable on-resistance according to the current interval. The resistance value is adjusted to maintain a small overshoot and turn-on loss. To verify the active gate drive's ability to suppress voltage and current overshoot, simulations were performed in LTspice, and the results are as follows. Figure 6 and Figure 7 As shown, with the adjustable on-resistance Increasing the resistance significantly suppresses current overshoot and oscillation, and correspondingly reduces the switching speed; similarly, with the adjustable turn-off resistor... The increase in resistance significantly suppressed voltage overshoot and oscillation.

[0070] The SiC MOSFET driving circuit provided by this invention includes an active current source driving circuit, a SiC MOSFET, a load current detection circuit, a drain-source voltage overshoot detection circuit, and an FPGA module. The FPGA module has a built-in adaptive adjustment algorithm. The load current detection circuit and the drain-source voltage overshoot detection circuit have lower real-time requirements, avoiding the use of high-speed analog devices and reducing hardware design costs. The adaptive adjustment algorithm can generate corresponding PWM control signals based on the outputs of the load current detection circuit and the drain-source voltage overshoot detection circuit, adjusting the SiC MOSFET gate driving parameters in real time to adaptively balance overshoot and switching losses, ensuring the safe operation of the SiC MOSFET. This solves the technical problems of high hardware cost and difficulty in balancing voltage and current overshoot and switching losses in active gate driven SiC MOSFET driving circuits.

[0071] Meanwhile, the SiC MOSFET driving circuit has the advantages that the structure and control mode are relatively simple, the generated gate current is more constant, the SiC MOSFET can be quickly turned on and turned off, and the overshoot and switching loss are better balanced.

[0072] For the convenience of understanding, please refer to Figure 8 An embodiment of the control method applied to the SiC MOSFET driving circuit is provided in the application, which comprises the following steps:

[0073] In step 101, the FPGA module generates a PWM signal for controlling the active current source driving circuit to turn on or turn off.

[0074] It should be noted that the active current source driving circuit is controlled by the PWM signal sent by the FPGA module.

[0075] In step 102, the FPGA module acquires the output of the load current detection circuit or the output of the drain-source voltage overshoot detection circuit.

[0076] It should be noted that when the SiC MOSFET is turned on, the FPGA module acquires the output of the load current detection circuit; and when the SiC MOSFET is turned off, the FPGA module acquires the output of the drain-source voltage overshoot detection circuit.

[0077] In step 103, the FPGA module controls the gate current of the SiC MOSFET according to the load current output by the load current detection circuit or the overshoot voltage output by the drain-source voltage overshoot detection circuit.

[0078] It should be noted that the control process of this step has been described in the SiC MOSFET driving circuit embodiment provided in the application, and will not be repeated here.

[0079] In step 104, the FPGA module determines whether to generate a reset signal for controlling the reset of the drain-source voltage overshoot detection circuit according to the PWM signal; if yes, the reset signal for controlling the reset of the drain-source voltage overshoot detection circuit is generated and sent to the drain-source voltage overshoot detection circuit.

[0080] It should be noted that step 104 can be directly executed after step 101. In this step, when the PWM signal is converted from low level to high level, the reset signal for controlling the reset of the drain-source voltage overshoot detection circuit is generated to control the reset of the drain-source voltage overshoot detection circuit.

[0081] The SiC MOSFET driving circuit control method provided in the embodiment of the present application is applied to the SiC MOSFET driving circuit provided in the present application, and the control principle has been described in the embodiment of the SiC MOSFET driving circuit provided in the present application, which will not be repeated here.

[0082] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacements for some technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A SiC MOSFET driving circuit, characterized in that, It includes an active current source drive circuit, SiC MOSFET, load current detection circuit, drain-source voltage overshoot detection circuit, analog-to-digital converter module, and FPGA module; The output of the active current source drive circuit is connected to the gate of the SiC MOSFET; The load current detection circuit is connected to the SiC MOSFET and is used to detect the drain-source current flowing through the SiC MOSFET and output a voltage signal corresponding to the drain-source current of the SiC MOSFET. The drain-source voltage overshoot detection circuit is connected to the SiC MOSFET and is used to detect the drain-source overshoot voltage of the SiC MOSFET. The input terminal of the analog-to-digital converter module is connected to the output terminals of the load current detection circuit and the drain-source voltage overshoot detection circuit, respectively, and the output terminal of the analog-to-digital converter module is connected to the input terminal of the FPGA module. The FPGA module has a built-in PWM unit and a digital controller. The output of the PWM unit is connected to the PWM signal input of the active current source drive circuit. The PWM unit is used to generate a PWM signal to control the active current source drive circuit to turn on or off and to generate a reset signal to control the reset of the drain-source voltage overshoot detection circuit based on the PWM signal. The digital controller has a built-in adaptive adjustment algorithm. The adaptive adjustment algorithm is used to control the gate current output by the active current source drive circuit to the SiC MOSFET based on the output of the load current detection circuit and the drain-source voltage overshoot detection circuit. The active current source drive circuit includes a voltage source, a PNP transistor, an NPN transistor, an adjustable on-resistance, and an adjustable off-resistance. The emitter of the PNP transistor is connected in parallel with the emitter of the NPN transistor, and the collector of the PNP transistor is connected in parallel with the collector of the NPN transistor. The positive terminal of the voltage source is connected to the emitter terminals of the PNP transistor and the NPN transistor, and the negative terminal of the voltage source is connected to the Kelvin source terminal of the SiC MOSFET. The collector terminals of the PNP transistor and the NPN transistor are connected to the gate of the SiC MOSFET. The base of the PNP transistor is connected to one end of the adjustable on-resistance, the base of the NPN transistor is connected to one end of the adjustable off-resistance, and the other end of the adjustable on-resistance and the other end of the adjustable off-resistance are connected together to the Kelvin source of the SiC MOSFET.

2. The SiC MOSFET driving circuit according to claim 1, characterized in that, The adjustable on-resistance includes several on-resistances of different resistance values ​​connected in parallel. Each on-resistance is connected in series with a first analog switch. One end of all the on-resistances is connected together, and one end of all the first analog switches is connected together.

3. The SiC MOSFET driving circuit according to claim 2, characterized in that, The adjustable shut-off resistor includes several shut-off resistors with different resistance values ​​connected in parallel. Each shut-off resistor is connected in series with a second analog switch. One end of all the shut-off resistors is connected together, and one end of all the second analog switches is connected together.

4. The SiC MOSFET driving circuit according to claim 3, characterized in that, The adaptive adjustment algorithm is specifically used for: The output of the drain-source voltage overshoot detection circuit is compared with the lower limit of the overshoot voltage. If the output of the drain-source voltage overshoot detection circuit is less than the lower limit of the overshoot voltage, the gate current of the SiC MOSFET is adjusted by decreasing the adjustable turn-off resistor. If the output of the drain-source voltage overshoot detection circuit is greater than the lower limit of the overshoot voltage but less than the upper limit of the overshoot voltage, the adjustable turn-off resistor is not adjusted. If the output of the drain-source voltage overshoot detection circuit is greater than the upper limit of the overshoot voltage, the gate current of the SiC MOSFET is adjusted by increasing the adjustable turn-off resistor. The load current output by the load current detection circuit is divided into several current ranges, each current range corresponding to a resistance value. Based on the current range into which the load current output by the load current detection circuit falls, the resistance value of the adjustable on-resistance is adjusted to the resistance value corresponding to the current range into which the load current output by the load current detection circuit falls.

5. The SiC MOSFET driving circuit according to claim 1, characterized in that, The drain-source voltage overshoot detection circuit includes an overshoot detection circuit and a subtraction circuit. The overshoot detection circuit includes a diode, a capacitor, a reset switch, and a current-limiting resistor. The anode of the diode is connected to the drain of the SiC MOSFET, the cathode of the diode is connected to one end of the capacitor, the other end of the capacitor is connected to the source of the SiC MOSFET, one end of the reset switch is connected to the cathode of the diode, the other end of the reset switch is connected to one end of the current-limiting resistor, and the other end of the current-limiting resistor is connected to the DC bus. The subtraction circuit includes a first resistor, a second resistor, a third resistor, a fourth resistor, and an operational amplifier. One end of the first resistor is connected to the cathode of the diode, and the other end of the first resistor is connected to the non-inverting input of the operational amplifier. One end of the second resistor is connected to the non-inverting input of the operational amplifier, and the other end of the second resistor is grounded. One end of the third resistor is connected to the anode of the diode, and the other end of the third resistor is connected to the inverting input of the operational amplifier. One end of the fourth resistor is connected to the inverting input of the operational amplifier, and the other end of the fourth resistor is connected to the output of the operational amplifier.

6. The SiC MOSFET driving circuit according to claim 1, characterized in that, The load current detection circuit is a Hall current sensor.

7. The SiC MOSFET driving circuit according to claim 1, characterized in that, When the PWM signal changes from low level to high level, the PWM unit generates a reset signal to control the reset of the drain-source voltage overshoot detection circuit.

8. The SiC MOSFET driving circuit according to claim 1, characterized in that, The analog-to-digital conversion module includes a first ADC chip and a second ADC chip; The input terminal of the first ADC chip is connected to the output terminal of the drain-source voltage overshoot detection circuit, and the output terminal of the first ADC chip is connected to the first input terminal of the digital controller. The input terminal of the second ADC chip is connected to the output terminal of the load current detection circuit, and the output terminal of the second ADC chip is connected to the second input terminal of the digital controller.

9. A control method for a SiC MOSFET driving circuit according to any one of claims 1-8, characterized in that, include: The FPGA module generates a PWM signal to control the active current source drive circuit to turn on or off. The FPGA module acquires the output of the load current detection circuit or the output of the drain-source voltage overshoot detection circuit. The FPGA module controls the magnitude of the gate current output by the active current source drive circuit to the SiC MOSFET based on the load current output by the load current detection circuit or the overshoot voltage output by the drain-source voltage overshoot detection circuit. The FPGA module determines whether to generate a reset signal to control the reset of the drain-source voltage overshoot detection circuit based on the PWM signal. If so, it generates a reset signal to control the reset of the drain-source voltage overshoot detection circuit and sends the reset signal to the drain-source voltage overshoot detection circuit.

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