LINK-JOINT control circuit based on transmission gate logic
By adopting transmission gate logic and SR-Latch mechanism in the LINK-JOINT circuit, combined with the narrow pulse trigger mode, the high power consumption and self-excitation oscillation problems of traditional circuits are solved, and significant power consumption reduction and area optimization are achieved. It is suitable for Low-power IoT applications.
Patent Information
- Application Number
- CN202411335770.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-24
- Publication Date
- 2024-12-27
AI Technical Summary
The existing LINK-JOINT circuits based on Click unit have limitations in integrated circuit area, power consumption and heat, resulting in high power consumption and high heat, and traditional trigger modes may cause self-exciting oscillations, increasing circuit complexity, Limits its application in complex control paths.
Adopt the LINK-JOINT control circuit based on transmission gate logic, and reduce power consumption through the SR-Latch mechanism and narrow pulse trigger mode, and optimize the control process through the MOS tube-level design and complementary transmission logic circuit, improve logic density and operation efficiency, and reduce Integrated circuit area.
It achieves a power consumption drop of 30% to 80%, reduces the integrated circuit area, avoids self-excitation and improves circuit performance and logic density, and is suitable for IoT scenarios with low power consumption requirements, such as Bluetooth controllers.
Smart Images
Figure CN119210430A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of transmission gate logic circuits, and in particular to a LINK-JOINT control circuit based on transmission gate logic. Background Art
[0002] In the field of modern electronic design, asynchronous circuits are valued for their unique advantages. Such circuits do not rely on global synchronous clock signals and can achieve more flexible timing control. In particular, asynchronous self-clocked circuits can generate local clock signals when needed to drive data paths, thereby reducing the reliance on synchronous clocks in the design, reducing power consumption, and improving system stability.
[0003] As an important branch of asynchronous circuits, the Bundle-data asynchronous self-clocked handshake circuit realizes efficient data exchange by binding the state of the handshake circuit to the data validity of the data path. This circuit usually communicates between units through request and acknowledge signals, but existing solutions, such as the Muller pipeline solution based on the Muller C unit, the mousetrap solution based on the mousetrap unit, and the click solution based on the click unit, have the problem of incompatible handshake signals, which limits their application in complex control paths.
[0004] As a self-clocked asynchronous circuit structure, the LINK-JOINT asynchronous self-clocked circuit can integrate different self-clocked asynchronous controllers and realize complex self-clocked control path design through the connection of two handshake circuits, LINK and JOINT. However, the existing LINK-JOINT circuit implementation based on Click unit has some limitations, especially in terms of integrated circuit area, power consumption and heat. The self-clocked control path occupies a large circuit area, resulting in high power consumption and high heat generation, which not only increases the cost, but also is not conducive to the miniaturization and low-power design of the circuit.
[0005] In addition, the FILL and DRAIN in the traditional edge-triggered LINK-JOINT structure are usually edge-triggered as LINK input terminals, which may cause self-oscillation and uncontrolled problems in many asynchronous handshake circuits based on latch structures. At the same time, since each part of the asynchronous self-clock control path requires several trigger latches, this increases the complexity of the circuit and is not conducive to the design and manufacture of integrated circuits.
[0006] In addition, on the one hand, there are differences in understanding among those skilled in the art; on the other hand, the applicant studied a large number of documents and patents when making the present invention, but due to space limitations, not all details and contents are listed in detail. However, this does not mean that the present invention does not have the characteristics of these prior arts. On the contrary, the present invention already has all the characteristics of the prior art, and the applicant reserves the right to add relevant prior art to the background technology. Summary of the invention
[0007] In view of the shortcomings of the prior art, the present invention provides a LINK-JOINT control circuit based on transmission gate logic to solve at least some of the above technical problems. The LINK-JOINT control circuit based on transmission gate logic proposed in the present invention achieves significant power consumption reduction and technical advantages through innovative structural design. Compared with the traditional edge trigger mode, the SR-Latch mechanism and narrow pulse trigger mode adopted by the LINK part of the present invention effectively avoid the self-oscillation problem and reduce power consumption. Under the SMIC process conditions, the implemented real-time clock peripheral module can achieve a 30% to 80% power consumption reduction, which is extremely important for IoT scenarios with extremely high low power requirements, especially applications such as Bluetooth controllers. In addition, transmission gate logic and complementary pass-transistor logic (CPL) circuits are two efficient logic implementation methods, which use the source and drain of metal oxide semiconductor field effect transistors (MOSFET) as the input of logic signals to reduce the number of MOSFETs in the logic circuit. In particular, the NMOS pull-down network PDN (Pull-Down Network) of the CPL circuit has a higher transistor density and a smaller area in layout implementation, which provides new possibilities for reducing the area of integrated circuits.
[0008] The present invention discloses a LINK-JOINT control circuit based on transmission gate logic, which comprises: a LINK-JOINT structure composed of a LINK unit for saving a working state and a JOINT unit for transferring the state saved by the LINK unit, wherein the LINK unit comprises a state filling input FILL, a state clearing input DRAIN, a full state output FULL and an empty state output EMPTY, and the JOINT unit comprises a full state input FULL, an empty state input EMPTY, a local clock output FIRE, and an inverted local clock output FIREN. The LINK-JOINT structure comprises a plurality of LINK units and a JOINT unit, wherein the LINK units constituting the LINK-JOINT structure can be divided into a first LINK unit as a front-stage LINK unit of a flow controller JOINT unit and a second LINK unit as a rear-stage LINK unit of a control flow, the full state output FULL of the plurality of first LINK units is connected to the full state input FULL of the JOINT unit, and the empty state output EMPTY of the second LINK unit is connected to the empty state input EMPTY of the JOINT unit.
[0009] The LINK-JOINT structure of the present invention realizes efficient storage and transmission of working status through the LINK unit and JOINT unit designed at the MOS tube level. The LINK unit includes a state filling input FILL, a state clearing input DRAIN, a full state output FULL and an empty state output EMPTY, while the JOINT unit includes a full state input FULL, an empty state input EMPTY, a local clock output FIRE and an inverted local clock output FIREN. This design not only optimizes the control process, but also improves the logic density and operation efficiency of the circuit by reasonably configuring the transmission gate and the inverter.
[0010] According to a preferred embodiment, the state clearing inputs DRAIN of the first LINK units and the state filling inputs FILL of the second LINK units can be connected to the same output terminal of the JOINT unit.
[0011] According to a preferred embodiment, the state clear input DRAIN of the plurality of first LINK units is connected to the local clock output FIRE of the JOINT unit, and the state fill input FILL of the second LINK unit is connected to the local clock output FIRE of the JOINT unit.
[0012] In a preferred embodiment, the state clear input DRAIN of the first LINK unit and the state fill input FILL of the second LINK unit are connected to the same output end of the JOINT unit, and by connecting the state clear input DRAIN of the first LINK unit to the local clock output FIRE of the JOINT unit, and connecting the state fill input FILL of the second LINK unit to the local clock output FIRE of the JOINT unit, precise control of the data flow is achieved, thereby further improving the performance of the circuit.
[0013] According to a preferred embodiment, the LINK unit includes a plurality of transmission gates and inverters, and a positive transmission gate and a negative transmission gate can form a pair of transmission gates, wherein the outputs of the pair of transmission gates are connected to the input of an inverter.
[0014] According to a preferred embodiment, the first transmission gate TG1 and the fourth transmission gate TG4 of the LINK unit configuration are negative transmission gates, the second transmission gate TG2 and the third transmission gate TG3 are positive transmission gates, and the outputs of the first transmission gate TG1 and the second transmission gate TG2 as a pair of transmission gates are connected to the input SN1 of the first inverter u1, and the outputs of the third transmission gate TG3 and the fourth transmission gate TG4 as a pair of transmission gates are connected to the input RN1 of the second inverter u2.
[0015] According to a preferred embodiment, the input of the first transmission gate TG1 is connected to the empty state output EMPTY of the LINK unit, and the control input of the first transmission gate TG1 is connected to the state fill input FILL of the LINK unit; the input of the second transmission gate TG2 is grounded, and the control input of the second transmission gate TG2 is connected to the state fill input FILL of the LINK unit; the input of the third transmission gate TG3 is grounded, and the control input of the third transmission gate TG3 is connected to the state clear input DRAIN of the LINK unit; the input of the fourth transmission gate TG4 is connected to the full state output FULL of the LINK unit, and the control input of the fourth transmission gate TG4 is connected to the state clear input DRAIN of the LINK unit.
[0016] According to a preferred embodiment, the JOINT unit includes a pull-down network PDN and several inverters, wherein the input of the third inverter u3 is connected to the set output SN of the pull-down network PDN, and the output of the third inverter u3 is connected to the local clock output FIRE of the JOINT unit; the input of the fourth inverter u4 is connected to the reset output RN of the pull-down network PDN, and the output of the fourth inverter u4 is connected to the inverted local clock output FIREN of the JOINT unit.
[0017] The pull-down network PDN inside the JOINT unit adopts NMOS tube design, and is used in conjunction with a pair of pull-up PMOS tubes, which not only reduces the integrated circuit area, but also improves the transistor density. The set output SN and reset output RN of PDN are connected with inverters u3 and u4 to realize flexible control of the local clock output FIRE and the inverted local clock output FIREN, further optimizing the timing performance of the circuit.
[0018] According to a preferred embodiment, the JOINT unit includes a pair of pull-up PMOS tubes, wherein the drain of the first PMOS tube m5 is connected to the SN terminal of the third inverter u3, the gate of the first PMOS tube m5 is connected to the RN terminal of the fourth inverter u4, and the source of the first PMOS tube m5 is connected to the power supply; the drain of the second PMOS tube m6 is connected to the RN terminal of the fourth inverter u4, the gate of the second PMOS tube m6 is connected to the SN terminal of the third inverter u3, and the source of the second PMOS tube m6 is connected to the power supply.
[0019] According to a preferred embodiment, when the SN end of the pull-down network PDN is in a conducting state, the gate circuit for controlling the second PMOS tube m6 at the RN end releases the charge on the gate of the second PMOS tube m6 at the RN end via the SN end, thereby the second PMOS tube m6 is turned on, so that the output of the RN end is pulled up to the input voltage of the second PMOS tube m6, so that the fourth inverter u4 connected to the RN end inputs the input voltage of the second PMOS tube m6 at the RN end, and then the inverted local clock output FIREN of the fourth inverter u4 is output as 0 at this time.
[0020] According to a preferred embodiment, when the RN end of the pull-down network PDN is in a conducting state, the gate circuit for controlling the first PMOS tube m5 at the SN end releases the charge on the gate of the first PMOS tube m5 at the SN end via the RN end, thereby the first PMOS tube m5 is turned on, so that the output of the SN end is pulled up to the input voltage of the first PMOS tube m5, so that the third inverter u3 connected to the SN end inputs the input voltage of the first PMOS tube m5 at the SN end, and further the local clock output FIRE of the third inverter u3 is output as 0 at this time. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] Figure 1 It is a LINK-JOINT control circuit diagram based on transmission gate logic of a preferred implementation mode provided by the present invention;
[0022] Figure 2 It is a structural schematic diagram of a LINK unit according to a preferred embodiment of the present invention;
[0023] Figure 3It is a structural schematic diagram of a JOINT unit of a preferred embodiment provided by the present invention; DETAILED DESCRIPTION
[0024] The following is a detailed description with reference to the accompanying drawings.
[0025] like Figure 1 As shown, the present invention discloses a LINK-JOINT control circuit based on transmission gate logic, which includes a LINK-JOINT structure composed of a LINK unit and a JOINT unit, wherein the LINK unit can be used to save the working state to play the role of a register of a traditional sequential circuit; the JOINT unit can be used to transfer the state saved by the LINK unit to play the role of a clock generator for the data path. Further, the LINK-JOINT structure can be used as a Bluetooth controller, for example, to form an on-chip handshake network using a combination of the LINK unit and the JOINT unit.
[0026] Preferably, the LINK unit may include a state filling input FILL, a state clearing input DRAIN, a full state output FULL and an empty state output EMPTY.
[0027] Preferably, the state fill input FILL is an input signal for controlling the LINK unit to fill data. When the state fill input FILL is activated (usually a high level), the LINK unit will start to accept new data or information to fill the register or latch it controls. The main function of the state fill input FILL is to control the data writing process. When the state fill input FILL is activated, the LINK unit will store the received data internally until the FILL signal is restored.
[0028] Preferably, the state clear input DRAIN is an input signal for controlling the LINK unit to clear existing data. When the state clear input DRAIN is activated, the LINK unit will start to remove or clear its stored data. The main function of the state clear input DRAIN is to control the reading or clearing process of data. When the state clear input DRAIN is activated, the output data of the register or latch controlled by the LINK unit is marked as invalid by the full state output of the LINK unit (FULL signal is low level) until the empty state is reached or the DRAIN signal is restored.
[0029] Preferably, the full state output FULL is an output signal for indicating whether the storage state of the LINK unit is full. When the data in the register or latch controlled by the LINK unit is updated, the full state output FULL will be activated (usually high level). This signal can be used to notify the system or other units that the current memory output data is valid. It is usually used to prevent data from being read incorrectly.
[0030] Preferably, the empty state output EMPTY is an output signal for indicating whether the storage state of the LINK unit is empty. When the LINK unit does not store any data, the empty state output EMPTY will be activated (usually high level). This signal can be used to notify the system or other units that the current memory is empty and a write operation can be performed. It is usually used to prevent data from being written incorrectly.
[0031] Further preferably, the FILL signal and the DRAIN signal are two inputs of the LINK unit, and are both at a low level when not triggered; the FULL signal and the EMPTY signal are two outputs of the LINK unit, and are at opposite logical levels to each other, wherein, when the FULL signal is at a high level, it indicates that the current LINK unit is in a full state, and when the EMPTY signal is at a high level, it indicates that the current LINK unit is in an empty state.
[0032] Preferably, the JOINT unit may include a full state input FULL, an empty state input EMPTY, a local clock output FIRE, and an inverted local clock output FIREN.
[0033] Preferably, the full state input FULL is an input signal for indicating whether the state of the first LINK unit connected to the JOINT unit is full. When the full state input FULL is activated (usually a high level), it indicates that the output data of the first LINK unit connected to the JOINT unit is valid. This input signal is mainly used to control the inflow of data. When the full state input FULL is activated, the system can take measures to prevent further data from being drained to ensure that data errors are not read.
[0034] Preferably, the empty state input EMPTY is an input signal for indicating whether the state of the second LINK unit connected to the JOINT unit is empty. When the empty state input EMPTY is activated, it indicates that the input data of the second LINK unit connected to the JOINT unit is valid. This input signal is mainly used to control the outflow of data. When the empty state input EMPTY is activated, the system can start related operations to ensure that data will not be written to a non-empty unit, thereby avoiding data write errors.
[0035] Preferably, the local clock output FIRE is the local clock output signal of the JOINT unit, which is usually a narrow pulse signal used to drive internal operations or control the timing of other circuits. The local clock output FIRE plays an important role in the control logic. It can be used for synchronous data processing, state conversion or other timing-related operations. When the local clock output FIRE is activated, it means that the corresponding operation can be performed, such as data reading, writing or state updating.
[0036] Preferably, the inverted local clock output FIREN is an inverted local clock output signal, usually an inverted output of the FIRE signal. When the local clock output FIRE is at a high level, the inverted local clock output FIREN is at a low level, and vice versa. The inverted local clock output FIREN is used to provide a timing control opposite to the FIRE signal, and can be used when an inverted operation is required. For example, in some logic circuits, FIREN can be used as a condition to trigger other circuits to achieve more complex timing control.
[0037] Preferably, the LINK-JOINT structure can be composed of multiple LINK units and one JOINT unit, wherein the LINK units constituting the LINK-JOINT structure can be divided into a first LINK unit and a second LINK unit according to the connection relationship between them and the JOINT unit. Further, LINK units of the same type may have the same input and output connection relationship and be located at the same level of the control flow. Preferably, the first LINK unit can be used as the previous level LINK unit of the control flow, and the second LINK unit can be used as the next level LINK unit of the control flow. Preferably, the first LINK unit may include one or more LINK units, for example, may include j LINK units. Preferably, the second LINK unit may include one LINK unit.
[0038] Preferably, the full state output FULL[1-j] of the first LINK unit is connected to the full state input FULL[1-j] of the JOINT unit, and the state clear input DRAIN[1-j] of the first LINK unit is connected to the local clock output FIRE of the JOINT unit.
[0039] Preferably, the empty state output EMPTY of the second LINK unit is connected to the empty state input EMPTY of the JOINT unit, and the state fill input FILL of the second LINK unit is connected to the local clock output FIRE of the JOINT unit.
[0040] Further preferably, the state clearing input DRAIN[1-j] of the first LINK unit and the state filling input FILL of the second LINK unit can be connected to the same output terminal of the JOINT unit.
[0041] Preferably, the local clock output LC (Local Clock for Control Flow) of the control flow can be connected to the local clock output FIRE of the JOINT unit, and the negative local clock output LCN (Local Clock Negativefor Control Flow) of the control flow can be connected to the negative local clock output FIREN of the JOINT flow control unit.
[0042] Preferably, if Figure 2 As shown, the LINK unit may include a number of transmission gates (TG) and inverters, wherein some transmission gates are positive transmission gates and some transmission gates are negative transmission gates. Preferably, the transmission gate is a switching circuit composed of NMOS and PMOS transistors in parallel. It can be turned on when the control signal is at a high level, allowing the input signal to pass through, and turned off when the control signal is at a low level, not allowing the signal to pass through. The main advantage of the transmission gate is that it can effectively transmit signals in low power consumption and high-speed operation. Preferably, the inverter is a basic logic gate circuit, and its function is to invert the input signal, that is, when the input is at a high level, the output is at a low level; when the input is at a low level, the output is at a high level.
[0043] Preferably, a positive transmission gate and a negative transmission gate can form a pair of transmission gates, wherein the outputs of the pair of transmission gates can be connected to the input of an inverter. Further preferably, Figure 2 As shown, any LINK unit may include four transmission gates and two inverters, wherein the first transmission gate TG1 and the fourth transmission gate TG4 are negative transmission gates, the second transmission gate TG2 and the third transmission gate TG3 are positive transmission gates, and the outputs of the first transmission gate TG1 and the second transmission gate TG2 as a pair of transmission gates can be connected to the input SN1 of the first inverter u1, and the outputs of the third transmission gate TG3 and the fourth transmission gate TG4 as a pair of transmission gates can be connected to the input RN1 of the second inverter u2.
[0044] Preferably, the input of the first transmission gate TG1 is connected to the empty state output EMPTY of the LINK unit, the control input of the first transmission gate TG1 is connected to the state filling input FILL of the LINK unit, and the output of the first transmission gate TG1 is connected to the input SN1 of the first inverter u1.
[0045] Preferably, an input of the second transmission gate TG2 is grounded, a control input of the second transmission gate TG2 is connected to a state filling input FILL of the LINK unit, and an output of the second transmission gate TG2 is connected to an input SN1 of the first inverter u1.
[0046] Preferably, an input of the third transmission gate TG3 is grounded, a control input of the third transmission gate TG3 is connected to a state clear input DRAIN of the LINK unit, and an output of the third transmission gate TG3 is connected to an input RN1 of the second inverter u2.
[0047] Preferably, the input of the fourth transmission gate TG4 is connected to the full state output FULL of the LINK unit, the control input of the fourth transmission gate TG4 is connected to the state clear input DRAIN of the LINK unit, and the output of the fourth transmission gate TG4 is connected to the input RN1 of the second inverter u2.
[0048] Preferably, the inverter u1 connecting the input SN1 to the outputs of the first transmission gate TG1 and the second transmission gate TG2 may have its output connected to the full state output FULL of the LINK unit.
[0049] Preferably, the inverter u2 connecting the input RN1 to the outputs of the third and fourth transmission gates TG3 and TG4 may connect its output to the empty state output EMPTY of the LINK unit.
[0050] Preferably, if Figure 3 As shown, the JOINT unit may include a pull-down network PDN (Pull-Down Network), wherein the pull-down network PDN may be configured as a complementary NMOS pull-down network PDN, and the complementary NMOS pull-down network PDN may be used to implement a logic gate. Further, the logic circuit structure of the complementary NMOS pull-down network PDN is mainly composed of NMOS transistors, which are used to pull the output voltage down to ground (logic 0), and are usually used in combination with a PMOS pull-up network to form a complete CMOS logic gate.
[0051] Preferably, if Figure 3 As shown, the JOINT unit may also include several inverters, wherein the input of the third inverter u3 is connected to the set output SN of the pull-down network PDN, and the output of the third inverter u3 is connected to the local clock output FIRE of the JOINT unit; the input of the fourth inverter u4 is connected to the reset output RN of the pull-down network PDN, and the output of the fourth inverter u4 is connected to the inverted local clock output FIREN of the JOINT unit.
[0052] Preferably, the set output SN (Set Not) refers to the output signal generated by the pull-down network PDN under specific conditions (usually when a path is formed between the ground and SN under the action of the input signal). It is usually used to indicate that the circuit is in a "set" state, that is, the circuit has been activated or enabled. When the set output SN is at a high level, it indicates that the pull-down network has performed a set operation, and a part of the circuit (such as a register or a state machine) is set to a specific state. Since the input of the third inverter u3 is connected to the set output SN, when the set output SN is high, the third inverter u3 generates a corresponding output, thereby affecting the local clock output FIRE of the JOINT unit. This means that the circuit can trigger downstream logic or clock signals under specific conditions to perform data processing or state conversion.
[0053] Preferably, the reset output RN (Reset Not) refers to the output signal generated by the pull-down network under specific conditions, which is used to reset the circuit state to the initial state. Reset is usually when a path is formed between the ground and RN under the action of the input signal, and the reset operation will clear the relevant storage element or circuit state. When the reset output RN is high, it indicates that the circuit has performed a reset operation, clearing or resetting the relevant state. This is usually used to restore the circuit to a known initial state. Since the input of the fourth inverter u4 is connected to the reset output RN, when the reset output RN is high, the fourth inverter u4 generates a corresponding output, thereby affecting the inverted local clock output FIREN of the JOINT unit. This means that the reset operation can affect the clock signal of the circuit, ensuring that other logics are not triggered by mistake in the reset state.
[0054] Preferably, if Figure 3 As shown, the JOINT unit may also include several PMOS tubes, wherein the drain of the first PMOS tube m5 is connected to the SN terminal of the third inverter u3, the gate of the first PMOS tube m5 is connected to the RN terminal of the fourth inverter u4, and the source of the first PMOS tube m5 is connected to the power supply; the drain of the second PMOS tube m6 is connected to the RN terminal of the fourth inverter u4, the gate of the second PMOS tube m6 is connected to the SN terminal of the third inverter u3, and the source of the second PMOS tube m6 is connected to the power supply. Preferably, the PMOS tube is a field effect transistor made of P-type semiconductor material, which is mainly used for switching functions in the circuit. Its main feature is to control the conduction and cutoff of the current, which is achieved by the change of the gate voltage.
[0055] Preferably, the full state input FULL[1~j] of the pull-down network PDN is connected to the full state input FULL[1~j] of the JOINT unit, the empty state input EMPTY of the pull-down network PDN is connected to the empty state input EMPTY of the JOINT unit, the set output SN of the pull-down network PDN is connected to the input of the third inverter u3, and the reset output RN of the pull-down network PDN is connected to the input of the fourth inverter u4.
[0056] Preferably, the LINK-JOINT structure formed by the above connection is set in the circuit, so that the timing circuit control based on the transmission gate logic can be realized by generating a local clock signal to drive the data path. The present invention proposes a new LINK-JOINT structure to achieve a significant reduction in power consumption. For example, the real-time clock peripheral module realized under the SMIC process conditions can achieve a power consumption reduction of more than 30% to 80%, which is undoubtedly of great significance for the IoT scenario used as a Bluetooth controller. In addition, since NMOS is used in the pull-down network PDN, the integrated circuit area can be reduced.
[0057] Preferably, different circuit control schemes may be provided based on different initial states of the LINK unit, wherein the initial state of the LINK unit may be empty or full.
[0058] Preferably, when the LINK unit is initially empty, the following steps may be performed:
[0059] S1.1, when the full state output FULL of the LINK unit is low, the empty state output EMPTY is high, the state filling input FILL and the state clearing input DRAIN of the LINK unit are low, at this time, the first transmission gate TG1 and the fourth transmission gate TG4 are turned on, and the second transmission gate TG2 and the third transmission gate TG3 are turned off;
[0060] S1.2. When the state fill input FILL of the LINK unit changes from a low level to a high level, the first transmission gate TG1 is turned off and the second transmission gate TG2 is turned on, and the input of the first inverter u1 is pulled low, so that the high level generated by the first inverter u1 is output to the full state output FULL of the LINK unit. Since the high level of the full state output FULL is output to the turned-on fourth transmission gate TG4, the input of the second inverter u2 is pulled high, so that the low level generated by it is output to the empty state output EMPTY of the LINK unit. At this time, the LINK unit enters the full state.
[0061] Preferably, when the LINK unit is initially in full state, the following steps may be performed:
[0062] S1.3, when the full state output FULL of the LINK unit is high, the empty state output EMPTY is low, the state filling input FILL and the state clearing input DRAIN of the LINK unit are low, at this time, the first transmission gate TG1 and the fourth transmission gate TG4 are turned on, and the second transmission gate TG2 and the third transmission gate TG3 are turned off;
[0063] S1.4, when the state clear input DRAIN of the LINK unit changes from low level to high level, the fourth transmission gate TG4 is turned off and the third transmission gate TG3 is turned on, and the input of the second inverter u2 is pulled low, so that the high level generated by the second inverter u2 is output to the empty state output EMPTY of the LINK unit. Since the high level of the empty state output EMPTY is output to the turned-on first transmission gate TG1, the input of the first inverter u1 is pulled high, so that the low level generated by it is output to the full state output FULL of the LINK unit. At this time, the LINK unit enters the empty state.
[0064] Preferably, the state transfer of the asynchronous self-clock control path may include the following steps:
[0065] S1.5, the full state input FULL[1~j] of the JOINT unit is at a low level in the initial state, and the empty state input EMPTY is at a high level in the initial state. At this time, the set output SN of the pull-down network PDN is at a high level, the reset output RN is at a low level, and the first PMOS tube m5 is turned on, and the second PMOS tube m6 is turned off, so that the local clock output FIRE of the JOINT unit is at a low level, and the inverted local clock output FIREN is at a high level;
[0066] S1.6, when the level of the full state input FULL[1~j] of the JOINT unit changes and reaches the condition for triggering state transfer, the low level generated by the set output SN of the pull-down network PDN pulls down the input of the third inverter u3 and turns on the second PMOS tube m6, and the high level generated by the reset output RN of the pull-down network PDN pulls up the input of the fourth inverter u4 and turns off the first PMOS tube m5. At this time, the JOINT unit generates a rising edge clock signal at the local clock output FIRE and a falling edge clock signal at the inverted local clock output FIREN;
[0067] S1.7. When the empty state input EMPTY of the JOINT unit becomes a low level, the high level generated by the set output SN of the pull-down network PDN pulls up the input of the third inverter u3 and turns off the second PMOS tube m6. The low level generated by the reset output RN of the pull-down network PDN pulls down the input of the fourth inverter u4 and turns on the first PMOS tube m5. At this time, the local clock output FIRE of the JOINT unit returns to a low level, and the inverted local clock output FIREN returns to a high level.
[0068] Preferably, in step S1.6, after the local clock output FIRE of the JOINT unit generates a rising edge clock signal to reach a high level, the state clearing input DRAIN[1~j] of the first LINK unit and the state filling input FILL of the second LINK unit connected to the local clock output FIRE of the JOINT unit change from a low level to a high level, wherein for the first LINK unit, step S1.4 can be executed to make the first LINK unit enter an empty state; for the second LINK unit, step S1.2 can be executed to make the second LINK unit enter a full state. Further, based on the connection relationship between the first LINK unit and the second LINK unit and the JOINT unit, the empty state input EMPTY of the JOINT unit changes to a low level, so that step S1.7 can be executed.
[0069] Preferably, the step of setting the pull-down network PDN of the JOINT unit includes:
[0070] S1.8. When the SN end of the pull-down network PDN is in the on state, the gate circuit for controlling the second PMOS tube m6 at the RN end releases the charge on the gate of the second PMOS tube m6 at the RN end via the SN end, thereby the second PMOS tube m6 is turned on, so that the output of the RN end is pulled up to the input voltage of the second PMOS tube m6, so that the fourth inverter u4 connected to the RN end inputs the input voltage of the second PMOS tube m6 at the RN end, and then the inverted local clock output FIREN of the fourth inverter u4 is output as 0 at this time.
[0071] Preferably, the resetting step of the pull-down network PDN of the JOINT unit includes:
[0072] S1.9, when the RN end of the pull-down network PDN is in the on state, the gate circuit for controlling the first PMOS tube m5 at the SN end releases the charge on the gate of the first PMOS tube m5 at the SN end via the RN end, thereby the first PMOS tube m5 is turned on, so that the output of the SN end is pulled up to the input voltage of the first PMOS tube m5, so that the third inverter u3 connected to the SN end inputs the input voltage of the first PMOS tube m5 at the SN end, and then the local clock output FIRE of the third inverter u3 is output as 0 at this time.
[0073] Preferably, when the SN end of the pull-down network PDN is in a conducting state, the local clock output FIRE of the third inverter u3 can provide a high level; at this time, the RN end of the pull-down network PDN is in a high impedance state, and the inverted local clock output FIREN of the fourth inverter u4 can provide a low level. Preferably, when the SN end of the pull-down network PDN is in a high impedance state, the local clock output FIRE of the third inverter u3 can provide a low level; at this time, the RN end of the pull-down network PDN is in a conducting state, and the inverted local clock output FIREN of the fourth inverter u4 can provide a high level. This is because the SN end and the RN end are both connected to a PMOS tube for pull-up, so for example, when the RN end is pulled up by the PMOS tube and maintained at a high level, the inverted local clock output FIREN as the output end of the fourth inverter u4 can provide a low level. Further, for the LINK-JOINT structure, the local clock output FIRE of the pull-down network PDN outputs a clock, and the inverted local clock output FIREN outputs an anti-clock.
[0074] It should be noted that the above-mentioned specific embodiments are exemplary, and those skilled in the art can come up with various solutions inspired by the disclosure of the present invention, and these solutions also belong to the disclosure scope of the present invention and fall within the protection scope of the present invention. Those skilled in the art should understand that the present invention specification and its drawings are illustrative and do not constitute a limitation on the claims. The scope of protection of the present invention is defined by the claims and their equivalents. The present invention specification contains multiple inventive concepts, such as "preferably" or "according to a preferred embodiment", which means that the corresponding paragraph discloses an independent concept, and the applicant reserves the right to file a divisional application based on each inventive concept. Throughout the text, the features guided by "preferably" are only an optional method and should not be understood as a must-have setting. Therefore, the applicant reserves the right to abandon or delete the relevant preferred features at any time.
Claims
1. A LINK-JOINT control circuit based on transmission gate logic, characterized in that: It includes: The LINK-JOINT structure consists of a LINK unit for saving the working state and a JOINT unit for transferring the state saved by the LINK unit, where: The LINK unit includes a state fill input FILL, a state clear input DRAIN, a full state output FULL, and an empty state output EMPTY. The JOINT unit includes a full state input FULL, an empty state input EMPTY, a local clock output FIRE, and an inverted local clock output FIREN. The LINK-JOINT structure includes a plurality of LINK units and a JOINT unit, wherein the LINK units constituting the LINK-JOINT structure can be divided into a first LINK unit as a previous stage LINK unit of the control flow and a second LINK unit as a subsequent stage LINK unit of the control flow. The full state outputs FULL of the plurality of first LINK units are connected to the full state input FULL of the JOINT unit, and the empty state outputs EMPTY of the second LINK units are connected to the empty state input EMPTY of the JOINT unit.
2. The circuit according to claim 1, characterized in that The state clear inputs DRAIN of the first LINK units and the state fill inputs FILL of the second LINK units can be connected to the same output terminal of the JOINT unit.
3. The circuit according to claim 1 or 2, characterized in that: The state clear inputs DRAIN of the plurality of first LINK units are connected to the local clock outputs FIRE of the JOINT units, and the state fill inputs FILL of the second LINK units are connected to the local clock outputs FIRE of the JOINT units.
4. The circuit according to any one of claims 1 to 3, characterized in that: The LINK unit includes a plurality of transmission gates and inverters. A positive transmission gate and a negative transmission gate can form a pair of transmission gates, wherein the outputs of the pair of transmission gates can be connected to the input of an inverter.
5. The circuit according to any one of claims 1 to 4, characterized in that: The first transmission gate TG1 and the fourth transmission gate TG4 of the LINK unit configuration are negative transmission gates, the second transmission gate TG2 and the third transmission gate TG3 are positive transmission gates, and the outputs of the first transmission gate TG1 and the second transmission gate TG2 as a pair of transmission gates are connected to the input SN1 of the first inverter u1, and the outputs of the third transmission gate TG3 and the fourth transmission gate TG4 as a pair of transmission gates are connected to the input RN1 of the second inverter u2.
6. The circuit according to any one of claims 1 to 5, characterized in that: The input of the first transmission gate TG1 is connected to the empty state output EMPTY of the LINK unit, and the control input of the first transmission gate TG1 is connected to the state fill input FILL of the LINK unit; the input of the second transmission gate TG2 is grounded, and the control input of the second transmission gate TG2 is connected to the state fill input FILL of the LINK unit; the input of the third transmission gate TG3 is grounded, and the control input of the third transmission gate TG3 is connected to the state clear input DRAIN of the LINK unit; the input of the fourth transmission gate TG4 is connected to the full state output FULL of the LINK unit, and the control input of the fourth transmission gate TG4 is connected to the state clear input DRAIN of the LINK unit.
7. The circuit according to any one of claims 1 to 6, characterized in that: The JOINT unit includes a pull-down network PDN and several inverters, wherein the input of the third inverter u3 is connected to the set output SN of the pull-down network PDN, and the output of the third inverter u3 is connected to the local clock output FIRE of the JOINT unit; the input of the fourth inverter u4 is connected to the reset output RN of the pull-down network PDN, and the output of the fourth inverter u4 is connected to the inverted local clock output FIREN of the JOINT unit.
8. The circuit according to any one of claims 1 to 7, characterized in that: The JOINT unit includes several PMOS tubes, wherein the drain of the first PMOS tube m5 is connected to the SN terminal of the third inverter u3, the gate of the first PMOS tube m5 is connected to the RN terminal of the fourth inverter u4, and the source of the first PMOS tube m5 is connected to the power supply; the drain of the second PMOS tube m6 is connected to the RN terminal of the fourth inverter u4, the gate of the second PMOS tube m6 is connected to the SN terminal of the third inverter u3, and the source of the second PMOS tube m6 is connected to the power supply.
9. The circuit according to any one of claims 1 to 8, characterized in that: When the SN end of the pull-down network PDN is in the on state, the gate circuit of the second PMOS tube m6 for controlling the RN end releases the charge on the gate of the second PMOS tube m6 at the RN end via the SN end, thereby the second PMOS tube m6 is turned on, so that the output of the RN end is pulled up to the input voltage of the second PMOS tube m6, so that the fourth inverter u4 connected to the RN end inputs the input voltage of the second PMOS tube m6 at the RN end, and then the inverted local clock output FIREN of the fourth inverter u4 is output as 0 at this time.
10. The circuit according to any one of claims 1 to 9, characterized in that: When the RN end of the pull-down network PDN is in the on state, the gate circuit for controlling the first PMOS tube m5 at the SN end releases the charge on the gate of the first PMOS tube m5 at the SN end via the RN end, thereby the first PMOS tube m5 is turned on, so that the output of the SN end is pulled up to the input voltage of the first PMOS tube m5, so that the third inverter u3 connected to the SN end inputs the input voltage of the first PMOS tube m5 at the SN end, and then the local clock output FIRE of the third inverter u3 is output as 0 at this time.