Storage unit, storage array, memory, system on chip, and electronic device

Abstract

Provided in the present application are a storage unit, a storage array, a memory, a system on chip, and an electronic device. By means of the present application, calculation is implemented while storing first data, and the utilization rate of the first data can be significantly increased. The storage unit may comprise a storage circuit, a transmission gate circuit, and a logic gate circuit. The storage circuit can be used for storing data, wherein a first control end and a second control end of the storage circuit are electrically connected to a first electrode line, a first input / output end of the storage circuit is electrically connected to a second electrode line, a second input / output end of the storage circuit is electrically connected to a third electrode line, and an output end of the storage circuit is electrically connected to an input end of the transmission gate circuit; a control end of the transmission gate circuit is electrically connected to a fourth electrode line, and an output end of the transmission gate circuit is electrically connected to a first input end of the logic gate circuit; and a second input end of the logic gate circuit is used for receiving second data, and an output end of the logic gate circuit is used as an output end of the storage unit.

Description

Memory cells, memory arrays, memories, system-on-chip chips, and electronic devices Technical Field

[0001] The present application relates to the field of computer technology, and more particularly, to a storage unit, a storage array, a memory, a system-on-chip chip, and an electronic device. Background Art

[0002] With the rapid development of technologies like artificial intelligence and the Internet of Things, the demand for high-computing, energy-efficient chips is becoming increasingly urgent. Chips can utilize a digital in-memory computing architecture. This architecture eliminates the need for extensive digital-to-analog and analog-to-digital conversions and enables full-precision calculations, resulting in higher accuracy.

[0003] Chips using a digital in-memory computing architecture, as provided in related technologies, may include two storage circuits and a logic gate circuit. One storage circuit is used to read data, while the other is used to store data. In other words, the two storage circuits and logic gate circuits enable simultaneous data storage and computing. As can be seen, data reading and writing are implemented using different storage circuits. Only half of the data is available for computing in each cycle, preventing simultaneous computing on both storage circuits and resulting in low data utilization.

[0004] Therefore, there is an urgent need for a technical solution that can store and calculate data simultaneously and has a high data utilization rate.

[0005] Summary of the Invention

[0006] The present application provides a storage unit, a storage array, a memory, a system-on-chip chip, and an electronic device, which can store first data and perform calculations simultaneously, and can greatly improve the utilization rate of the first data.

[0007] In a first aspect, the present application provides a storage unit that may include a storage circuit, a transmission gate circuit, and a logic gate circuit.

[0008] In which, the storage circuit can be used to store first data, the first control end and the second control end of the storage circuit can both be electrically connected to the first electrode line, the first input and output ends of the storage circuit can be electrically connected to the second electrode line, the second input and output ends of the storage circuit can be electrically connected to the third electrode line, the output end of the storage circuit can be electrically connected to the input end of the transmission gate circuit, the control end of the transmission gate circuit can be electrically connected to the fourth electrode line, the output end of the transmission gate circuit can be electrically connected to the first input end of the logic gate circuit, the second input end of the logic gate circuit can be used to receive second data, and the output end of the logic gate circuit serves as the output end of the storage unit.

[0009] The storage unit provided in the present application can store the first data through a storage circuit. The storage circuit can also output the first data to a transmission gate circuit, output the first data to a logic gate circuit through the transmission gate circuit, and implement logical operations on the first data and the second data through the logic gate circuit. Not only can the first data and the second data be stored and logically operated at the same time, but the utilization rate of the first data or the second data can also be greatly improved, thereby achieving high computing power and high energy efficiency of the storage unit.

[0010] In a possible implementation, the storage circuit may include a switch circuit and a storage sub-circuit.

[0011] The first input terminal of the switch circuit can serve as the first control terminal of the storage circuit, and the second input terminal of the switch circuit can serve as the second control terminal of the storage circuit. The first input and output terminals of the switch circuit can serve as the first input and output terminals of the storage circuit, and the second input and output terminals of the switch circuit can serve as the second input and output terminals of the storage circuit. The third input and output terminals of the switch circuit can be electrically connected to the first input and output terminals of the storage sub-circuit, and the fourth input and output terminals of the switch circuit can be electrically connected to the second input and output terminals of the storage sub-circuit. The output terminal of the storage sub-circuit can serve as the output terminal of the storage circuit.

[0012] Furthermore, the switching circuit may include a first switching tube and a second switching tube.

[0013] The control electrode of the first switching transistor can serve as the first input terminal of the switching circuit, and the control electrode of the second switching transistor can serve as the second input terminal of the switching circuit. The control electrodes of the first switching transistor and the second switching transistor (i.e., the first control terminal and the second control terminal of the storage circuit) can each be electrically connected to the first word line (i.e., the first electrode line) for receiving a first control signal. In other words, the first switching transistor and the second switching transistor can each receive the first control signal from the first word line. The first electrode of the first switching transistor (i.e., the first input / output terminal of the storage circuit) can be electrically connected to the first bit line (i.e., the second electrode line) for receiving the first data. In other words, the first switching transistor can receive the first data from the first bit line. The first electrode of the second switching transistor (i.e., the second input / output terminal of the storage circuit) can be electrically connected to the second bit line (i.e., the third electrode line) for receiving the third data. In other words, the second switching transistor can receive the third data from the second bit line. The second electrode of the first switching transistor can serve as the third input / output terminal of the switching circuit, and the second electrode of the second switching transistor can serve as the fourth input / output terminal of the switching circuit.

[0014] The first data and the third data are both 1 or 0, and the first data and the third data are different. That is, the first data can be 1 or 0, and the third data can also be 1 or 0. When the first data is 1, the third data can be 0. Conversely, when the first data is 0, the third data can be 1.

[0015] It is conceivable that the switching circuit can be used: when the first control signal is at a high level, both the first switching tube and the second switching tube can be turned on, and the switching circuit can output the first data to the storage sub-circuit through the first switching tube, and can output the third data to the storage sub-circuit through the second switching tube.

[0016] In another possible implementation, the storage sub-circuit may include a third switch tube, a fourth switch tube, a fifth switch tube, and a sixth switch tube.

[0017] The first electrode of each of the third and fourth switching transistors can be used to receive a first operating voltage (which can be represented by VDD). The second electrode of the third switching transistor and the first electrode of the fifth switching transistor can both be electrically connected to node A, which can serve as the first input / output terminal of the storage sub-circuit. The control electrodes of each of the third and fifth switching transistors can both be electrically connected to node B. The second electrode of the fourth switching transistor and the first electrode of the sixth switching transistor can both be electrically connected to node C, which can be connected to node C, which can also serve as the second input / output terminal of the storage sub-circuit. The control electrodes of each of the fourth and sixth switching transistors can both be electrically connected to node D, and node A can be electrically connected to node D. The second electrodes of the fifth switching transistor T5 and the sixth switching transistor T can both be used to receive a second operating voltage (which can be represented by VSS).

[0018] It can be imagined that the storage sub-circuit can be used for: when the first data is 1 and the third data is 0, the fourth switch tube can be controlled to be turned off and the sixth switch tube can be controlled to be turned on according to the first data, and the third switch tube can be controlled to be turned on and the fifth switch tube can be controlled to be turned off according to the third data, and the first data and the third data can be stored through the third switch tube, the fourth switch tube, the fifth switch tube and the sixth switch tube.

[0019] Alternatively, the storage sub-circuit can be used to: when the first data is 0 and the third data is 1, the fourth switch tube can be controlled to be turned on and the sixth switch tube can be controlled to be turned off according to the first data, and the third switch tube can be controlled to be turned off and the fifth switch tube can be controlled to be turned on according to the third data, and the first data and the third data can be stored through the third switch tube, the fourth switch tube, the fifth switch tube and the sixth switch tube.

[0020] It can be seen that in both cases where the first data is 1 and the third data is 0 or the first data is 0 and the third data is 1, the storage of the first data and the third data can be achieved by turning on or off the third switch tube, the fourth switch tube, the fifth switch tube and the sixth switch tube.

[0021] For example, the first, second, third, fourth, fifth, and sixth switching transistors may each be a metal-oxide-semiconductor field-effect transistor (MOSFET), which may be referred to as a MOS transistor. Of course, the first, second, third, fourth, fifth, and sixth switching transistors may also be other types, which are not limited in this application.

[0022] Furthermore, the first switch tube, the second switch tube, the fifth switch tube, and the sixth switch tube can each be an N-type metal oxide semiconductor field effect transistor (can be referred to as an NMOS tube). The third switch tube and the fourth switch tube can each be a P-type metal oxide semiconductor field effect transistor (can be referred to as a PMOS tube).

[0023] In yet another possible implementation, the transmission gate circuit may include a seventh switching tube and an eighth switching tube.

[0024] Optionally, the control electrodes of the seventh and eighth switching tubes can each serve as the control electrode of a transmission gate circuit. The control electrode of the seventh switching tube can be electrically connected to the second word line (i.e., the fourth electrode line) for receiving a second control signal. That is, the seventh switching tube can receive the second control signal from the second word line. The control electrode of the eighth switching tube can be electrically connected to the third word line (i.e., the fourth electrode line) for receiving a third control signal. That is, the eighth switching tube can receive the third control signal from the third word line. The first electrode of the seventh switching tube is electrically connected to the first electrode of the eighth switching tube and can serve as the input of the transmission gate circuit. The input of the transmission gate circuit can be electrically connected to node A or node C. The second electrode of the seventh switching tube can be electrically connected to the second electrode of the eighth switching tube and can serve as the output of the logic gate circuit.

[0025] The second control signal and the third control signal can both be high or low, and the second control signal and the third control signal are different. That is, the second control signal can be high or low, and the third control signal can also be high or low. When the second control signal is high, the third control signal can be low. Conversely, when the second control signal is low, the third control signal can be high.

[0026] It is conceivable that the transmission gate circuit can be used to control the seventh and eighth switches to be turned off (which can be understood as the transmission gate circuit being closed) based on the second and third control signals, thereby preventing the first and third data from being output to the logic gate circuit. It is conceivable that when the second control signal is high and the third control signal is low, the seventh and eighth switches can be turned off, thereby preventing the first and third data from being output to the logic gate circuit.

[0027] Alternatively, the transmission gate circuit can be configured to control the seventh and eighth switching transistors to be conductive (which can be understood as the transmission gate circuit being open) based on the second and third control signals, thereby outputting the first or third data to the logic gate circuit. It is conceivable that when the second control signal is low and the third control signal is high, the seventh and eighth switching transistors can both be conductive, thereby outputting the first or third data.

[0028] It is understandable that, regardless of whether the seventh and eighth switches are turned on or off, the storage unit can store the first and third data via the storage sub-circuit and perform logical operations on the second data and the first / third data via the logic gate circuit. It is conceivable that, when the seventh and eighth switches are turned off, the first or third data used by the logic gate circuit for performing the logical operation can be the first or third data on the connection line between the transmission gate circuit and the logic gate circuit.

[0029] It is also understood that when both the seventh and eighth switching transistors are turned off, the storage unit and the logic gate circuit operate independently, allowing the first and third data to be stored or outputted via the storage unit, and logical operations to be performed via the logic gate circuit. After the first and third data are stored, both the seventh and eighth switching transistors are turned on, i.e., the transmission gate circuit is opened, completing the refreshing of the first and third data.

[0030] For example, the seventh switch transistor may be a PMOS transistor, and the eighth switch transistor may be an NMOS transistor. Alternatively, the seventh switch transistor may be an NMOS transistor, and the eighth switch transistor may be a PMOS transistor.

[0031] Therefore, it can be understood that the transmission gate circuit can be a CMOS transmission gate, which can include a PMOS transistor and an NMOS transistor connected in parallel. Of course, the transmission gate circuit can also have other structures, which are not limited in this application.

[0032] In an example, the first electrodes of the seventh switch tube and the eighth switch tube can be connected to the node A, and the logic gate circuit can be an AND gate. The AND gate can be used to implement a logic operation and output a logic operation result.

[0033] In another example, the first electrodes of the seventh switch tube and the eighth switch tube can be connected to the node C, and the logic gate circuit can be a NOR gate. The logic operation can be implemented through the NOR gate to output the logic operation result.

[0034] It can be understood that the logic gate circuit can simultaneously realize the storage of the first data and the third data in the storage unit during the process of performing logical operations, that is, realize the update of the first data and the third data, so that all the data stored in the storage unit can meet the refresh requirements of the first data and the third data while performing logical operations, thereby maximizing the time utilization of the first data and the third data in the process of logical operations and the storage space utilization of the storage unit.

[0035] In a second aspect, the present application provides a memory array that may include M first electrode lines (which may be first word lines), M fourth electrode lines (which may be second word lines and third word lines), M input lines, N second electrode lines (which may be first bit lines), N third electrode lines (which may be second bit lines), and M×N memory cells provided by the first aspect and its possible implementations. Memory cells in the same row may share the first electrode line, the fourth electrode line, and the input line. Memory cells in the same column may share the second electrode line and the third electrode line.

[0036] The storage array provided in the present application can receive a first control signal through a first electrode line, receive a second control signal and a third control signal through a fourth electrode line, receive first data through a second electrode line, and receive third data through a third electrode line, and ultimately implement the storage of the first data and the third data through M×N storage cells, and can also implement logical operations on the second data and the first data, or logical operations on the second data and the third data.

[0037] Furthermore, the storage array may further include a summing unit, and some or all of the M×N storage units are connected to the summing unit.

[0038] It is conceivable that there may be one or more summing units. In the case of a single summing unit, all storage units may be connected to the summing unit. In the case of multiple summing units, the M×N storage units may be divided into multiple parts. Each part may include one or more storage units. Each part may be connected to one summing unit.

[0039] Optionally, the summing unit may be configured to sum the logic operation results output by the logic gate circuit in each storage unit.

[0040] Exemplarily, the summing unit may be an addition tree, etc., which is not limited in this application.

[0041] In a third aspect, the present application provides a memory, which may include a control unit, a first decoder, a second decoder, and a storage array provided by the above-mentioned second aspect and its possible implementation methods.

[0042] Optionally, the control unit may be configured to output M channels of second data to each storage unit in the storage array, and output M channels of second control signals and M channels of third control signals to each storage unit based on the computing clock signal. In other words, the output of the M channels of second data, M channels of second control signals, and M channels of third control signals by the control unit must be controlled by the computing clock signal.

[0043] The control unit may also be configured to output a read / write clock signal and first address information of each storage unit to the first decoder, and output a fourth control signal, the read / write clock signal, and second address information of each storage unit to the second decoder. The fourth control signal may be configured to instruct the memory to perform a read operation or a write operation.

[0044] The first decoder can be used to decode the first address information according to the read / write clock signal, and output M first control signals to corresponding storage units according to the obtained first decoding result.

[0045] The second decoder can be used to decode the second address information according to the read / write clock signal and the fourth control signal, and output one channel of first data and one channel of third data to the corresponding storage unit according to the fourth data and the obtained second decoding result.

[0046] In the memory provided by the present application, the control unit can not only output M channels of second data, M channels of second control signals, and M channels of third control signals to the storage unit, but can also output a read / write clock signal, first address information, fourth control signal, and second address information. Furthermore, the first decoder can decode the first address information and output M channels of first control signals, while the second decoder can decode the second address information and output N channels of first data and N channels of third data. Because the storage unit can perform logical operations on the first and third data while storing them, the memory provided by the present application can also perform simultaneous storage and logical operations on the first and third data, thereby achieving high computing power and high energy efficiency of the memory.

[0047] Since the storage and logical operations of the first data and the third data are all completed in the storage unit, the memory provided in the present application can be called a computing in memory (CIM) memory, which can be referred to as a CIM memory for short.

[0048] In a possible implementation, the control unit may include a first controller and a second controller, wherein the second controller, the first decoder, and the second decoder are all connected to the first controller.

[0049] The first controller is used to: output a calculation clock signal and a second control signal to the second controller, obtain the first address information and the second address information, and output a read-write clock signal and the first address information to the first decoder, and output a read-write clock signal, the second address information and a fourth control signal to the second decoder.

[0050] The second controller is configured to divide the second control signal from the first controller into M second control signals and output them one-to-one to the M second word lines in the memory array. The second controller may also be configured to invert the second control signal to obtain a third control signal, and divide the third control signal into M third control signals and output them one-to-one to the M third word lines in the memory array.

[0051] The second controller can also be used to: output M-way second data one-to-one to the logic gate circuit in each storage unit according to the calculation clock signal, or invert the M-way first input data according to the calculation clock signal to obtain M-way second data and output them one-to-one to each logic gate circuit.

[0052] Since the second controller is controlled by the first controller and can output M channels of second data, the first controller can be called a master controller and the second controller can be called an input controller.

[0053] Furthermore, the memory may further include an amplifier, and the amplifier may be connected to the first controller, and the amplifier may also be connected to the second decoder.

[0054] The second decoder can also be used to: select at least one first data from the multiple first data corresponding to the second decoder and output it to the amplifier, and select at least one third data from the multiple third data corresponding to the second decoder and output it to the amplifier based on the read-write clock signal, the fourth control signal and the second decoding result.

[0055] The first controller can also be used to: output a read / write clock signal to the amplifier. It can be seen that the first controller not only outputs a read / write clock signal to the first decoder and the second decoder, but also outputs a read / write clock signal to the amplifier.

[0056] The amplifier can be used to: amplify the difference between the first data and the third data according to the read / write clock signal and output it, that is, obtain the weight data of the memory and output it.

[0057] Exemplarily, the operating modes of the memory may include a read-write mode, a storage calculation mode, a calculation mode, and a hold mode.

[0058] The read / write mode can be used to instruct the memory to perform a read operation or a write operation, i.e., the memory only performs read and write operations. The storage / calculation mode can be used to instruct the memory to perform both storage and calculation operations, i.e., the memory simultaneously performs storage and logical operations. The calculation mode can be used to instruct the memory to perform calculation operations, i.e., the memory only performs calculation operations. The hold mode can be used to instruct the memory to retain the first data and the third data, i.e., the memory does not perform storage operations or calculation operations.

[0059] In one possible implementation, when the memory is in a read-write mode, the memory can be used to: control the second control signal to a high level through the second controller to close each transmission gate circuit in the storage array, write the first data and the third data through each storage cell, and amplify and output the difference between the first data and the third data through the amplifier.

[0060] In another possible implementation, when the memory is in a storage calculation mode, the memory can be used to: control the second control signal to a high level through the second controller to close each transmission gate circuit in the storage array, write the first data and the third data through the storage unit, and amplify and output the difference between the first data and the third data through the amplifier; the memory can also be used to output the logic operation result through each storage unit.

[0061] As can be seen, when the memory is in read-write mode or storage-calculation mode, the second control signal is high, and each transmission gate circuit is closed. In read-write mode, the memory not only stores the first and third data, but also amplifies and outputs the difference between the first and third data. In storage-calculation mode, the memory not only stores the first and third data, amplifies and outputs the difference between the first and third data, but also outputs the result of the logical operation.

[0062] In another possible implementation, when the memory is in a calculation mode, the memory can be used to: control the second control signal to a low level through the second controller, so that each transmission gate circuit in the storage array is opened, and the logic operation result is output through each storage unit.

[0063] In another possible implementation, when the memory is in the hold mode, the memory can be used to: control the second control signal to a low level through the second controller, so that each transmission gate circuit in the storage array is opened, and the first data and the third data are stored through each storage unit.

[0064] As can be seen, when the memory is in calculation mode or hold mode, the second control signal is low, and each transmission gate circuit is open. In calculation mode, the memory is used to output the logical operation result, and in hold mode, the memory is used to store the first and third data.

[0065] In a fourth aspect, the present application provides a circuit layout of a memory cell, which may include a substrate, an N-well region, an active region, a gate layer, and a metal layer. The active region may include a first active region and a second active region.

[0066] Optionally, the substrate and the N-well region may be stacked along a first direction. The first active region may be disposed on the substrate along the first direction, and the second active region may be disposed on the N-well region along the first direction. The gate layer may be disposed on the active region along the first direction, and the metal layer may be disposed on the active region or the gate layer along the first direction.

[0067] The circuit layout provided in the present application can form multiple switching tubes through the substrate, N-well region, active region, gate layer and metal layer, and the storage circuit, transmission gate circuit and logic gate circuit in the storage unit are constituted by multiple switching tubes, thereby not only being able to simultaneously store and perform logical operations on the first data and the second data, but also being able to greatly improve the utilization rate of the first data or the second data, thereby achieving high computing power and high energy efficiency of the storage unit.

[0068] In a possible implementation, the first active region may include a first active sub-region and a second active sub-region, and the second active region may include a third active sub-region and a fourth active sub-region.

[0069] Optionally, the first active sub-region, the third active sub-region, the fourth active sub-region, and the second active sub-region may be arranged in parallel along a second direction. The second direction may be perpendicular to the first direction. It is understood that the first active sub-region, the third active sub-region, the fourth active sub-region, and the second active sub-region may serve as the source or drain of the switch transistor.

[0070] In another possible implementation, the gate layer may include a first gate sublayer, a second gate sublayer, a third gate sublayer, a fourth gate sublayer, a fifth gate sublayer, a sixth gate sublayer, a seventh gate sublayer, and an eighth gate sublayer arranged along a third direction. The third direction may be perpendicular to the first direction, and the third direction may be perpendicular to the second direction. That is, the first direction, the second direction, and the third direction are all perpendicular to each other.

[0071] Optionally, the first gate sublayer, the fourth gate sublayer, the fifth gate sublayer and the eighth gate sublayer are sequentially arranged in parallel along the third direction.

[0072] The first active sub-region, the third active sub-region, and the fourth active sub-region may be stacked and connected to the first gate sub-layer, respectively. The third active sub-region, the fourth active sub-region, and the second active sub-region may be stacked and connected to the fourth gate sub-layer, respectively. The fourth active sub-region and the second active sub-region may be stacked and connected to the fifth gate sub-layer, respectively. The fourth active sub-region and the second active sub-region may be stacked and connected to the eighth gate sub-layer, respectively.

[0073] The second gate sublayer may be located in an extension direction of the first gate sublayer, and the second gate sublayer may be stacked and connected to the second active sub-region. The third gate sublayer may be located in an extension direction of the fourth gate sublayer, and the third gate sublayer may be stacked and connected to the first active sub-region. The sixth gate sublayer and the seventh gate sublayer may both be located in an extension direction of the eighth gate sublayer; wherein the sixth gate sublayer may be stacked and connected to the first active sub-region, and the seventh gate sublayer may be stacked and connected to the third active sub-region.

[0074] In another possible implementation, the metal layer may include a first metal layer and a second metal layer. The first metal layer may be arranged along a third direction, and the second metal layer may be arranged along a second direction. In other words, the arrangement direction of the first metal layer is perpendicular to the arrangement direction of the second metal layer.

[0075] In an example, the first metal layer may include a first metal sub-layer, a second metal sub-layer, a third metal sub-layer, a fourth metal sub-layer, a fifth metal sub-layer, and a sixth metal sub-layer.

[0076] The first metal sublayer, the third metal sublayer and the fifth metal sublayer can be arranged in parallel in sequence along the second direction, the second metal sublayer, the fourth metal sublayer and the sixth metal sublayer can be arranged in parallel in sequence along the second direction, the second metal sublayer can be located in the extension direction of the first metal sublayer, the fourth metal sublayer can be located in the extension direction of the third metal sublayer, and the sixth metal sublayer can be located in the extension direction of the fifth metal sublayer.

[0077] Furthermore, the first metal sublayer and the second metal sublayer can be located between the first gate sublayer and the fourth gate sublayer, the first active sub-region and the third active sub-region can be respectively stacked and connected with the first metal sublayer, and the fourth active sub-region and the second active sub-region can be respectively stacked and connected with the second metal sublayer.

[0078] The third metal sublayer may be located between the fourth gate sublayer and the seventh gate sublayer, and the first active sub-region and the third active sub-region may be stacked and connected to the third metal sublayer, respectively.

[0079] The fourth metal sublayer may be located between the fifth gate sublayer and the eighth gate sublayer, and the second active sub-region and the fourth metal sublayer may be stacked and connected.

[0080] The fifth metal sublayer may be located on a side of the seventh gate sublayer away from the third metal sublayer in the second direction, and the first active sub-region and the third active sub-region may be respectively stacked and connected to the fifth metal sublayer.

[0081] The sixth metal sublayer may be located on a side of the eighth gate sublayer away from the fourth metal sublayer in the second direction, and the fourth active sub-region may be stacked and connected to the sixth metal sublayer.

[0082] In another example, the second metal layer may include a seventh metal sub-layer, an eighth metal sub-layer, a ninth metal sub-layer, and a tenth metal sub-layer;

[0083] The seventh metal sublayer may be stacked with the third active sub-region along the first direction, and the first metal sublayer, the fourth gate sublayer, and the third metal sublayer may be stacked and connected to the seventh metal sublayer, respectively. The eighth gate sublayer and the fifth metal sublayer may be stacked and connected to the eighth metal sublayer, respectively. The ninth metal sublayer may be stacked with the fourth active sub-region along the first direction, and the first gate sublayer and the second metal sublayer may be stacked and connected to the ninth metal sublayer, respectively. The fourth metal sublayer, the eighth gate sublayer, and the sixth metal sublayer may be stacked and connected to the tenth metal sublayer, respectively.

[0084] In one possible implementation, the first active sub-area may be provided with a first through-hole and a second through-hole. The first through-hole may be located on a side of the first gate sub-layer away from the first metal sub-layer in the second direction, and may be used to connect to the first power line. The second through-hole may be located between the third gate sub-layer and the third metal sub-layer, and may be used to connect to the second bit line.

[0085] The second active sub-region may be provided with a third through-hole, a fourth through-hole, and a fifth through-hole. The third through-hole may be located on a side of the second gate sub-layer away from the second metal sub-layer in the second direction, and may be used to connect to the first bit line. The fourth through-hole may be located between the fourth gate sub-layer and the fifth gate sub-layer. The fifth through-hole may be located on a side of the eighth gate sub-layer away from the fourth metal sub-layer in the second direction. Both the fourth through-hole and the fifth through-hole may be used to connect to the first power line.

[0086] The third active sub-region may be provided with a sixth through-hole, and the fourth active sub-region may be provided with a seventh through-hole. The sixth through-hole may be located on a side of the first gate sub-layer away from the first metal sub-layer in the second direction, and the seventh through-hole may be located between the fourth gate sub-layer and the fifth gate sub-layer. Both the sixth through-hole and the seventh through-hole may be used to connect to the second power line.

[0087] The first power line can be used to provide the second operating voltage, and the second power line can be used to provide the first operating voltage.

[0088] In another possible implementation, the second gate sublayer may be provided with an eighth through hole, the third gate sublayer may be provided with a ninth through hole, and the eighth through hole and the ninth through hole may be used to connect to the first word line.

[0089] The fifth gate sublayer may be provided with a tenth through hole, and the tenth through hole may be used to connect an input line, and the input line may be used to provide second data.

[0090] The sixth gate sublayer may be provided with an eleventh through-hole, and the eleventh through-hole may be used to connect the third word line.

[0091] The seventh gate sublayer may be provided with a twelfth through hole, and the twelfth through hole may be used to connect the second word line.

[0092] The fourth metal sub-layer may be provided with a thirteenth through-hole, and the thirteenth through-hole may be used to connect an output line, and the output line may be used to output a logic operation result of the storage unit.

[0093] In a fifth aspect, the present application provides a system on chip (SOC) chip, which may be referred to as an SOC chip. The SOC chip may include a processor and a memory provided by the third aspect and its possible implementations. The memory may be connected to the processor.

[0094] For example, the SOC chip may include one or more CIM memories, which is not limited in this application. The one or more CIM memories may be connected to the processor via a bus.

[0095] Optionally, the SOC chip may further include a static random-access memory (SRAM) and the like, and the SRAM may also be connected to the processor via a bus.

[0096] In a sixth aspect, the present application provides an electronic device that may include an off-chip memory chip and the SOC chip provided by the fifth aspect and its possible implementations. The off-chip memory chip may be connected to a processor in the SOC chip via a bus.

[0097] Exemplarily, the off-chip memory chip may include a non-volatile memory (NVM) and a dynamic random access memory (DRAM), etc., which is not limited in this application.

[0098] Furthermore, the NVM can be connected to the DRAM, and the DRAM can be connected to the processor in the SOC chip through a bus.

[0099] It should be understood that the second to sixth aspects of the present application are consistent with the technical solutions of the first aspect of the present application, and the beneficial effects achieved by each aspect and the corresponding feasible implementation methods are similar, which will not be repeated. BRIEF DESCRIPTION OF THE DRAWINGS

[0100] In order to more clearly illustrate the technical solutions in the present application or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0101] FIG1 is a schematic structural diagram of a storage unit 10 in an embodiment of the present application;

[0102] FIG2 is another schematic structural diagram of the storage unit 10 in an embodiment of the present application;

[0103] FIG3 is another schematic structural diagram of the storage unit 10 in an embodiment of the present application;

[0104] FIG4 is a schematic structural diagram of a circuit layout 20 of a storage unit 10 according to an embodiment of the present application;

[0105] FIG5 is a schematic structural diagram of a storage array 100 according to an embodiment of the present application;

[0106] FIG6 is another schematic structural diagram of the memory array 100 according to an embodiment of the present application;

[0107] FIG7 is a schematic structural diagram of a memory 1100 according to an embodiment of the present application;

[0108] FIG8 is another schematic structural diagram of the memory 1100 in an embodiment of the present application;

[0109] FIG9 is another schematic structural diagram of the memory 1100 in an embodiment of the present application;

[0110] FIG10 is another schematic structural diagram of the memory 1100 in an embodiment of the present application;

[0111] FIG11 is a timing diagram of a memory 1100 in a read / write mode according to an embodiment of the present application;

[0112] FIG12 is a timing diagram of the memory 1100 in the storage calculation mode according to an embodiment of the present application;

[0113] FIG13 is a timing diagram of the memory 1100 in the computing mode according to an embodiment of the present application;

[0114] FIG14 is a timing diagram of the memory 1100 in the hold mode according to an embodiment of the present application;

[0115] FIG15 is a schematic structural diagram of a SOC chip 1000 in an embodiment of the present application;

[0116] FIG16 is a schematic structural diagram of an electronic device 1000 in an embodiment of the present application. DETAILED DESCRIPTION

[0117] The technical solution in this application will be described below with reference to the accompanying drawings.

[0118] To make the objectives, technical solutions, and advantages of this application more clear, the technical solutions of this application will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of this application.

[0119] The terms "first," "second," and the like in the description, embodiments, claims, and drawings of this application are used solely for descriptive purposes and are not to be construed as indicating or implying relative importance or order. Furthermore, the terms "including," "having," and any variations thereof are intended to cover non-exclusive inclusions, such as, for example, inclusion of a series of steps or units. A method, system, product, or apparatus is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0120] It should be understood that in this application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0121] With the rapid development of technologies like artificial intelligence and the Internet of Things (IoT), the demand for high-computing power and high-energy efficiency chips is becoming increasingly urgent. Chips can adopt either the von Neumann architecture or the in-memory computing architecture. In the von Neumann architecture, data, including input data and weights, must be stored in memory before being transferred via a bus to the processor for logical operations. The results of these operations are then transferred back to the memory via the bus. The limited number of read interfaces in the memory limits the number of logical operations per cycle. Furthermore, the data transfer process not only increases chip energy consumption but also limits processor throughput. Compared to the von Neumann architecture, the in-memory computing architecture not only provides storage and read / write capabilities but also supports logical operations such as multiplication and addition within the memory. This reduces frequent interactions between the processor and memory, reduces data transfer volume, and ultimately reduces chip energy consumption. Therefore, chips using the in-memory computing architecture offer both high computing power and high energy efficiency.

[0122] In-memory computing architectures can be categorized as analog and digital. Analog architectures typically require extensive digital-to-analog and analog-to-digital conversions, and computational accuracy is significantly affected by noise, voltage, and temperature. This results in lower computational accuracy, typically below 8 bits. Compared to analog architectures, digital architectures do not require extensive digital-to-analog and analog-to-digital conversions, enabling full-precision computations. Consequently, digital architectures offer higher computational accuracy.

[0123] The chip using a digital in-memory computing architecture provided by the related art may include two storage circuits and a logic gate circuit. One of the storage circuits is used to read data (such as weight data), and the other storage circuit is used to write data (such as weight data). In other words, data can be read, written, and calculated simultaneously through two storage circuits and logic gate circuits. It can be seen that the reading and writing of data are realized through different storage circuits. In each cycle, only half of the data can be used for calculation, and it is impossible to realize logical operations of two storage units at the same time. Therefore, the utilization rate of data is low.

[0124] To overcome the above shortcomings, an embodiment of the present application provides a memory unit, as shown in Figures 1 and 2. In Figures 1 and 2, the memory unit 10 may include a memory circuit 1, a transmission gate circuit 2, and a logic gate circuit 3.

[0125] The storage circuit 1 is used to store first data. The first control terminal (which may be the control electrode (i.e., gate) of the first switch transistor T1) and the second control terminal (which may be the control electrode (i.e., gate) of the second switch transistor T2) of the storage circuit 1 can both be electrically connected to the first word line WL1 (i.e., the first electrode line). The first input / output terminal (which may be the first electrode (which may be the drain) of the first switch transistor T1) of the storage circuit 1 can be electrically connected to the first bit line BL1 (i.e., the second electrode line). The second input / output terminal (which may be the first electrode (which may be the drain) of the second switch transistor T2) of the storage circuit 1 can be electrically connected to the second bit line BL2 (i.e., the third electrode line). The output terminal of the storage circuit 1 (which may be the second electrode (which may be the source) of the third switch transistor T3 and the first electrode (which may be the drain) of the fifth switch transistor T5 as shown in FIG. 1, or the second electrode (which may be the source) of the fourth switch transistor T4 and the first electrode (which may be the drain) of the sixth switch transistor T6 as shown in FIG. 2) can be electrically connected to the input terminal ( The first electrode (which may be the drain) of the seventh switch transistor T7 and the first electrode (which may be the drain) of the eighth switch transistor T8 may be electrically connected. The control end of the transmission gate circuit 2 (which may be the control electrode (i.e., the gate) of the seventh switch transistor T7 and the control electrode (i.e., the gate) of the eighth switch transistor T8) may be electrically connected to the second word line WL2 and the third word line WL3 (i.e., the fourth electrode line). The output end of the transmission gate circuit 2 (which may be the second electrode (which may be the source) of the seventh switch transistor T7 and the second electrode (which may be the source) of the eighth switch transistor T8) may be electrically connected to the first input end of the logic gate circuit 3 (which may be the first input end of the AND gate in FIG. 1 or the first input end of the NOR gate in FIG. 2). The second input end of the logic gate circuit 3 (i.e., the second input end IN of the AND gate in FIG. 1 or the second input end IN of the NOR gate in FIG. 2) may be used to receive the second data. The output end of the logic gate circuit 3 (i.e., the output end OUT of the AND gate in FIG. 1 or the output end OUT of the NOR gate in FIG. 2) may serve as the output end of the storage unit 10.

[0126] Alternatively, the first data may be weight data, etc., and the second data may be input data of the storage unit 10, hereinafter referred to as second input data. The embodiment of the present application is described by taking the first data as weight data as an example, hereinafter referred to as first weight data (which can be represented by W1).

[0127] The storage unit 10 provided in the embodiment of the present application can realize the storage of the first weight data W1 through the storage circuit 1. The storage circuit 1 can also output the first weight data W1 to the transmission gate circuit 2, output the first weight data W1 to the logic gate circuit 3 through the transmission gate circuit 2, and realize the logical operation of the first weight data W1 and the second input data through the logic gate circuit 3. Not only can the first weight data W1 and the second input data be stored and logically operated at the same time, but the utilization rate of the first weight data W1 can also be greatly improved, thereby realizing high computing power and high energy efficiency of the storage unit 120.

[0128] As shown in Figures 1 and 2, the storage circuit 1 may include a switching circuit and a storage sub-circuit. The first input terminal of the switching circuit (which may be the control electrode of the first switching transistor T1) may serve as the first control terminal of the storage circuit 1, and the second input terminal of the switching circuit 1 (which may be the control electrode of the second switching transistor T2) may serve as the second control terminal of the storage circuit 1. The first input / output terminal of the switching circuit (which may be the first electrode of the first switching transistor T1) may serve as the first input / output terminal of the storage circuit 1, and the second input / output terminal of the switching circuit (which may be the first electrode of the second switching transistor T1) may serve as the second input / output terminal of the storage circuit 1. The third input / output terminal of the switching circuit (which may be the second electrode (which may be the source electrode) of the first switching transistor T1) may be electrically connected to the first input / output terminal of the storage sub-circuit (which may be the second electrode of the third switching transistor T3 and the first electrode of the fifth switching transistor T5). The fourth input / output terminal of the switching circuit (which may be the second electrode (which may be the source electrode) of the second switching transistor T2) may be electrically connected to the second input / output terminal of the storage sub-circuit (which may be the second electrode of the fourth switching transistor T4 and the first electrode of the sixth switching transistor T6). The output end of the storage sub-circuit (which can be the second electrode of the third switch tube T3 and the first electrode of the fifth switch tube T5 shown in Figure 1, or the second electrode of the fourth switch tube T4 and the first electrode of the sixth switch tube T6 shown in Figure 2) can serve as the output end of the storage circuit 1.

[0129] 1 and 2 , the switch circuit may include a first switch transistor T1 and a second switch transistor T2 , and the storage sub-circuit may include a third switch transistor T3 , a fourth switch transistor T4 , a fifth switch transistor T5 , and a sixth switch transistor T6 .

[0130] In some embodiments, referring to Figures 1 and 2 , the control electrode of the first switch transistor T1 can serve as the first input terminal of the switching circuit, and the control electrode of the second switch transistor T2 can serve as the second input terminal of the switching circuit. The control electrodes of each of the first switch transistor T1 and the second switch transistor T2 can be electrically connected to the first word line WL1 to receive a first control signal (denoted by CS1). That is, both the first switch transistor T1 and the second switch transistor T2 can receive the first control signal CS1 from the first word line WL1. The first electrode of the first switch transistor T1 can be electrically connected to the first bit line BL1 to receive first weight data W1. That is, the first switch transistor T1 can receive the first weight data W1 from the first bit line BL1. The first electrode of the second switch transistor T2 can be connected to the second bit line BL2 to receive third data (which can be weight data, hereinafter referred to as third weight data, denoted by W3). That is, the second switch transistor T2 can receive third weight data W3 from the second bit line BL2. The second electrode of the first switch transistor T1 can serve as the third input / output terminal of the switching circuit, and the second electrode of the second switch transistor can serve as the fourth input / output terminal of the switching circuit.

[0131] The first weight data W1 and the third weight data W3 are both 1 or 0, and the first weight data W1 and the third weight data W3 are different. That is, the first weight data W1 can be 1 or 0, and the third weight data W3 can also be 1 or 0. When the first weight data W1 is 1, the third weight data W3 can be 0. Conversely, when the first weight data W1 is 0, the third weight data W3 can be 1.

[0132] It can be imagined that the switching circuit can be used: when the first control signal CS1 is at a high level, the first switch tube T1 and the second switch tube T2 can both be turned on, and the switching circuit can transmit the first weight data W1 to the storage sub-circuit through the first switch tube T1, and can transmit the third weight data W3 to the storage sub-circuit through the second switch tube T2.

[0133] For example, the first switch transistor T1 and the second switch transistor T2 can both be N-type metal-oxide-semiconductor field-effect transistors (MOSFETs), which can be referred to as NMOS transistors. Of course, the first switch transistor T1 and the second switch transistor T2 can also be other types, which are not limited in the present embodiment.

[0134] In other embodiments, in the storage sub-circuit, the first electrodes of the third switch T3 and the fourth switch T4 can each be configured to receive a first operating voltage (which can be represented by VDD), the second electrode of the third switch T3 and the first electrode of the fifth switch T5 can both be electrically connected to node A, which can serve as a first input / output terminal of the storage sub-circuit. The control electrode of the third switch T3 and the control electrode of the fifth switch T5 can both be electrically connected to node B, the second electrode of the fourth switch T4 and the first electrode of the sixth switch T6 can both be electrically connected to node C, which can be electrically connected to node C, which can also serve as a second input / output terminal of the storage sub-circuit. The control electrode of the fourth switch T4 and the control electrode of the sixth switch T6 can both be electrically connected to node D, and node A can be electrically connected to node D. The second electrodes of the fifth and sixth switches can both be configured to receive a second operating voltage (which can be represented by VSS).

[0135] It is understood that node A can serve as the output terminal of the storage sub-circuit, as shown in FIG1 , node A is electrically connected to transmission gate circuit 2. Node C can also serve as the output terminal of the storage sub-circuit, as shown in FIG2 , node C is electrically connected to transmission gate circuit 2.

[0136] It can be imagined that the storage sub-circuit can be used for: when the first weight data W1 is 1 and the third weight data W3 is 0, the fourth switch tube T4 can be controlled to be turned off and the sixth switch tube T6 can be controlled to be turned on according to the first weight data W1, and the third switch tube T3 can be controlled to be turned on and the fifth switch tube T5 can be controlled to be turned off according to the third weight data W3, and the first weight data W1 and the third weight data W3 can be stored through the third switch tube T3, the fourth switch tube T4, the fifth switch tube T5 and the sixth switch tube T6.

[0137] Alternatively, the storage subcircuit can be used: when the first weight data W1 is 0 and the third weight data W3 is 1, the fourth switch tube T4 can be controlled to be turned on and the sixth switch tube T6 can be controlled to be turned off according to the first weight data W1, and the third switch tube T3 can be controlled to be turned off and the fifth switch tube T5 can be controlled to be turned on according to the third weight data W3, and the first weight data W1 and the third weight data W3 can be stored through the third switch tube T3, the fourth switch tube T4, the fifth switch tube T5 and the sixth switch tube T6.

[0138] It can be seen that in both cases where the first weight data W1 is 1 and the third weight data W3 is 0 or the first weight data W1 is 0 and the third weight data W3 is 1, the storage of the first weight data W1 and the third weight data W3 can be achieved by turning on or off the third switch tube T3, the fourth switch tube T4, the fifth switch tube T5 and the sixth switch tube T6.

[0139] For example, the third switch transistor T3 and the fourth switch transistor T4 may also be P-type metal-oxide-semiconductor field-effect transistors (MOSFETs), which may be referred to as PMOS transistors. The fifth switch transistor T5 and the sixth switch transistor T6 may also be NMOS transistors. Of course, the third switch transistor T3, the fourth switch transistor T4, the fifth switch transistor T5, and the sixth switch transistor T6 may also be of other types, which are not limited in the present embodiment.

[0140] In a possible implementation, as shown in FIG. 1 and FIG. 2 , the transmission gate circuit 2 may include a seventh switch tube T7 and an eighth switch tube T8 .

[0141] Optionally, the control electrodes of the seventh switch transistor T7 and the eighth switch transistor T8 can each serve as the control electrode of the transmission gate circuit 2. The control electrode of the seventh switch transistor T7 can be electrically connected to the second word line WL2 for receiving a second control signal (denoted by CS2). In other words, the seventh switch transistor T7 can receive the second control signal CS2 from the second word line WL2. The control electrode of the eighth switch transistor T8 can be electrically connected to the third word line WL3 for receiving a third control signal (denoted by CS3). In other words, the eighth switch transistor T8 can receive the third control signal CS3 from the third word line WL3. The first electrode of the seventh switch transistor T7 is electrically connected to the first electrode of the eighth switch transistor T8 and can serve as the input of the transmission gate circuit 2. The first electrode of the seventh switch transistor T7 and the first electrode of the eighth switch transistor T8 can each be electrically connected to node A, as shown in FIG1 . Alternatively, the first electrode of the seventh switch transistor T7 and the first electrode of the eighth switch transistor T8 can each be electrically connected to node C, as shown in FIG2 . The second electrode of the seventh switch transistor T7 and the second electrode of the eighth switch transistor T8 are electrically connected to serve as the output of the transmission gate circuit 2.

[0142] The second control signal CS2 and the third control signal CS3 are both high or low, and the second control signal CS2 and the third control signal CS3 are different. That is, the second control signal CS2 can be high or low, and the third control signal CS3 can also be high or low. When the second control signal CS2 is high, the third control signal CS3 can be low. Conversely, when the second control signal CS2 is low, the third control signal CS3 can be high. As shown in Figures 1 and 2, an inverter can be provided between the second word line WL2 and the third word line WL3 to achieve the difference between the second control signal CS2 and the third control signal CS3.

[0143] It is conceivable that the transmission gate circuit 2 can be used to control the seventh switch tube T7 and the eighth switch tube T8 to be turned off (which can be understood as the transmission gate circuit 2 being closed) according to the second control signal CS2 and the third control signal CS3, thereby preventing the first weight data W1 and the third weight data W3 from being output to the logic gate circuit 3. It is conceivable that when the second control signal CS2 is at a high level and the third control signal CS3 is at a low level, the seventh switch tube T7 and the eighth switch tube T8 can both be turned off, and the seventh switch tube T7 and the eighth switch tube T8 play a role in preventing the first weight data W1 and the third weight data W3 from being output to the logic gate circuit 3.

[0144] Alternatively, the transmission gate circuit 2 can be used to control the seventh switch tube T7 and the eighth switch tube T8 to be turned on (which can be understood as the transmission gate circuit 2 is open) according to the second control signal CS2 and the third control signal CS3, and output the first weight data W1 or the third weight data W3 to the logic gate circuit 3. It can be imagined that when the second control signal CS2 is at a low level and the third control signal CS3 is at a high level, the seventh switch tube T7 and the eighth switch tube T8 can be turned on, and the seventh switch tube T7 and the eighth switch tube T8 play the role of outputting the first weight data W1 or the third weight data W3.

[0145] It is understandable that, regardless of whether the seventh switch T7 and the eighth switch T8 are turned on or off, the storage unit 10 can store the first weight data W1 and the third weight data W3 through the storage sub-circuit, and also perform a logical operation on the second data and the first weight data W1 / the third weight data W3 through the logic gate circuit 3. It is conceivable that, when the seventh switch T7 and the eighth switch T8 are turned off, the first weight data W1 or the third weight data W3 used by the logic gate circuit 3 for the logical operation can be the first weight data W1 or the third weight data W3 on the connection line between the transmission gate circuit 2 and the logic gate circuit 3.

[0146] It can also be understood that when the seventh switch tube T7 and the eighth switch tube T8 are both turned off, the storage circuit 1 and the logic gate circuit 3 operate independently, the first weight data W1 and the third weight data W3 are stored or transmitted through the storage circuit 1, and the logic operation is performed through the logic gate circuit 3. After the first weight data W1 and the third weight data W3 are stored, the seventh switch tube T7 and the eighth switch tube T8 are both turned on, that is, the transmission gate circuit 2 is opened, and the first weight data W1 and the third weight data W3 are refreshed.

[0147] For example, the seventh switch transistor T7 may be a PMOS transistor, and the eighth switch transistor T8 may be an NMOS transistor, as shown in Figures 1 and 2. Alternatively, the seventh switch transistor T7 may be an NMOS transistor, and the eighth switch transistor T8 may be a PMOS transistor.

[0148] Therefore, it can be understood that the transmission gate circuit 2 can be a CMOS transmission gate, which can include a PMOS transistor (i.e., the seventh switch transistor T7) and an NMOS transistor (i.e., the eighth switch transistor T8) connected in parallel. Of course, the transmission gate circuit 2 can also have other structures, which are not limited in the embodiment of the present application.

[0149] In one example, the first electrodes of the seventh switch transistor T7 and the eighth switch transistor T8 can be electrically connected to node A, and the logic gate circuit 3 can be an AND gate, as shown in FIG1 . That is, when node A serves as the output terminal of the storage sub-circuit, the logic gate circuit 3 can be an AND gate, which can implement a logical operation and output the logical operation result.

[0150] In another example, the first electrodes of the seventh switch transistor T7 and the eighth switch transistor T8 can be electrically connected to the node C, and the logic gate circuit 3 can be a NOR gate, as shown in FIG2 . That is, when the node C serves as the output terminal of the storage sub-circuit, the logic gate circuit 3 can be a NOR gate, and a logical operation can be performed through the NOR gate to output the logical operation result.

[0151] It can be understood that since the logic gate circuit 3 in FIG1 can be an AND gate and the logic gate circuit 3 in FIG2 can be a NOR gate, the second input data of the AND gate and the second input data of the NOR gate are different and need to satisfy the following conditions: when the second input data of the AND gate is 1, the second input data of the NOR gate can be 0. Alternatively, when the second input data of the AND gate is 0, the second input data of the NOR gate can be 1. In both FIG1 and FIG2 , IN is used to represent this.

[0152] It can also be understood that, in the process of performing logical operations, the logic gate circuit 3 can simultaneously realize the storage of the first weight data W1 and the third weight data W3 in the storage circuit 1, that is, realize the update of the first weight data W1 and the third weight data W3, thereby satisfying the refresh requirements of the first weight data W1 and the third weight data W3 while performing logical operations for all weight data stored in the storage circuit 1, thereby maximizing the time utilization of the first weight data W1 and the third weight data W3 in the process of logical operations and the storage space utilization of the storage unit 10.

[0153] In one possible implementation, the NOR gate in FIG2 may include a ninth switch transistor T9, a tenth switch transistor T10, an eleventh switch transistor T11, and a twelfth switch transistor T12, as shown in FIG3 . The control electrodes of the ninth switch transistor T9 and the eleventh switch transistor T11 may be electrically connected, serving as the second input terminal IN of the NOR gate for receiving second input data. The control electrodes of the tenth switch transistor T10 and the twelfth switch transistor T12 may be electrically connected, serving as the first input terminal of the NOR gate for receiving first weight data W1 or third weight data W3. The first electrode (which may be the drain) of the ninth switch transistor T9, the first electrode (which may be the drain) of the tenth switch transistor T10, and the second electrode (which may be the source) of the twelfth switch transistor are electrically connected, serving as the output terminal OUT of the NOR gate. The second electrode (which may be the source) of the ninth switch transistor T9 and the second electrode (which may be the source) of the tenth switch transistor T11 may both be configured to receive the second operating voltage VSS. The first electrode (which may be the drain) of the eleventh switch transistor T11 may be configured to receive the first operating voltage VDD. The second electrode (which may be the source electrode) of the eleventh switching transistor T11 may be electrically connected to the first electrode (which may be the drain electrode) of the twelfth switching transistor T12 .

[0154] Optionally, the ninth switch tube T9 and the tenth switch tube T10 may be NMOS tubes, and the eleventh switch tube T11 and the twelfth switch tube T12 may be PMOS tubes.

[0155] The present embodiment also provides a circuit board diagram of a memory cell 10, as shown in FIG4 . The circuit board diagram 20 may include a substrate 11, an N-well region 12, an active region, a gate layer, and a metal layer. The active region may include a first active region (which may include a first active sub-region 131 and a second active sub-region 132) and a second active region (which may include a third active sub-region 133 and a fourth active sub-region 134).

[0156] Alternatively, the substrate 11 and the N-well region 12 may be stacked along a first direction. The first active region may be disposed on the substrate 11 along the first direction, and the second active region may be disposed on the N-well region 12 along the first direction. That is, the first active sub-region 131 and the second active sub-region 132 may be disposed on the substrate 11 along the first direction, and the third active sub-region 133 and the fourth active sub-region 134 may be disposed on the N-well region 12 along the first direction. In other words, a first portion of the active sub-regions may be disposed directly on the substrate 11, and a second portion of the active sub-regions may be disposed on the N-well region 12.

[0157] The gate layer can be disposed on the active area along the Z direction. Since the active area can include a first active area and a second active area, the gate layer can be disposed on the first active area and the second active area along the Z direction. The metal layer can be disposed on the active area or the gate layer along the Z direction. In the embodiments of the present application, the first direction can be described using the Z direction as an example.

[0158] The circuit layout 20 provided in the embodiment of the present application can form multiple switching tubes through the substrate 11, N-well region 12, active region, gate layer and metal layer, and the storage circuit 1, transmission gate circuit 2 and logic gate circuit 3 in the storage unit 10 are constituted by multiple switching tubes, thereby not only being able to simultaneously store and perform logical operations on the first weight data W1 and the second input data, but also being able to greatly improve the utilization rate of the first weight data W1 or the second input data, thereby achieving high computing power and high energy efficiency of the storage unit 10.

[0159] Alternatively, referring to FIG4 , the first active sub-region 131, the third active sub-region 133, the fourth active sub-region 134, and the second active sub-region 132 can be arranged in parallel along a second direction. The second direction can be perpendicular to the Z direction. In the embodiment of the present application, the second direction is taken as the Y direction. It is understood that the first active sub-region 131, the third active sub-region 133, the fourth active sub-region 134, and the second active sub-region 132 can serve as the source or drain of the switch transistor.

[0160] In one possible implementation, the gate layer may include a first gate sublayer 141, a second gate sublayer 142, a third gate sublayer 143, a fourth gate sublayer 144, a fifth gate sublayer 145, a sixth gate sublayer 146, a seventh gate sublayer 147, and an eighth gate sublayer 148 arranged along a third direction. The third direction may be perpendicular to the first direction, and the third direction may be perpendicular to the second direction. That is, the first direction, the second direction, and the third direction are mutually perpendicular. In the embodiment of the present application, the third direction is taken as the X direction as an example.

[0161] Optionally, referring to FIG. 4 , the first gate sublayer 141 , the fourth gate sublayer 144 , the fifth gate sublayer 145 and the eighth gate sublayer 148 are sequentially arranged in parallel along the X direction.

[0162] The first active sub-region 131, the third active sub-region 133, and the fourth active sub-region 134 may be respectively stacked and connected to the first gate sublayer 141 (and may be connected via a through-hole). The third active sub-region 133, the fourth active sub-region 134, and the second active sub-region 132 may be respectively stacked and connected to the fourth gate sublayer 142 (and may be connected via a through-hole). The fourth active sub-region 134 and the second active sub-region 132 may be respectively stacked and connected to the fifth gate sublayer 145 (and may be connected via a through-hole). The fourth active sub-region 134 and the second active sub-region 132 may be respectively stacked and connected to the eighth gate sublayer 148 (and may be connected via a through-hole).

[0163] The second gate sublayer 142 may be located in the extension direction of the first gate sublayer 141, and the second gate sublayer 142 may be stacked and connected to the second active sub-area 132 (may be connected through a through hole). The third gate sublayer 143 may be located in the extension direction of the fourth gate sublayer 144, and the third gate sublayer 143 may be stacked and connected to the first active sub-area 131 (may be connected through a through hole). The sixth gate sublayer 146 and the seventh gate sublayer 147 may both be located in the extension direction of the eighth gate sublayer 148. Among them, the sixth gate sublayer 146 may be stacked and connected to the first active sub-area 131 (may be connected through a through hole), and the seventh gate sublayer 147 may be stacked and connected to the third active sub-area 133 (may be connected through a through hole).

[0164] It is conceivable that the first gate sublayer 141 , the second gate sublayer 142 , the third gate sublayer 143 , the fourth gate sublayer 144 , the fifth gate sublayer 145 , the sixth gate sublayer 146 , the seventh gate sublayer 147 and the eighth gate sublayer 148 can serve as gates of the switching tube.

[0165] In another possible implementation, the metal layer may include a first metal layer and a second metal layer. The first metal layer may be arranged along the X direction, and the second metal layer may be arranged along the Y direction. It can be seen that the first metal layer and the second metal layer are perpendicular.

[0166] In an example, with continued reference to FIG. 4 , the first metal layer may include a first metal sub-layer 151 , a second metal sub-layer 152 , a third metal sub-layer 153 , a fourth metal sub-layer 154 , a fifth metal sub-layer 155 , and a sixth metal sub-layer 156 .

[0167] The first metal sublayer 151, the third metal sublayer 153 and the fifth metal sublayer 155 can be arranged in parallel in sequence along the Y direction, the second metal sublayer 152, the fourth metal sublayer 154 and the sixth metal sublayer 156 can be arranged in parallel in sequence along the Y direction, the second metal sublayer 152 can be located in the extension direction of the first metal sublayer 151, the fourth metal sublayer 154 can be located in the extension direction of the third metal sublayer 153, and the sixth metal sublayer 156 can be located in the extension direction of the fifth metal sublayer 155.

[0168] Furthermore, the first metal sublayer 151 and the second metal sublayer 152 can be located between the first gate sublayer 141 and the fourth gate sublayer 144, the first active sub-region 131 and the third active sub-region 133 can be respectively stacked and connected with the first metal sublayer 151 (can be connected through through holes), and the fourth active sub-region 134 and the second active sub-region 132 can be respectively stacked and connected with the second metal sublayer 152 (can be connected through through holes).

[0169] The third metal sublayer 153 may be located between the fourth gate sublayer 144 and the seventh gate sublayer 147 , and the first active sub-region 131 and the third active sub-region 133 may be stacked and connected to the third metal sublayer 153 (may be connected through a through hole).

[0170] The fourth metal sublayer 154 may be located between the fifth gate sublayer 145 and the eighth gate sublayer 148 , and the second active sub-region 131 and the fourth metal sublayer 154 may be stacked and connected (may be connected through a through hole).

[0171] The fifth metal sublayer 155 may be located on a side of the seventh gate sublayer 147 away from the third metal sublayer 153 in the X direction, and the first active sub-region 131 and the third active sub-region 133 may be respectively stacked and connected to the fifth metal sublayer 155 (may be connected through through holes).

[0172] The sixth metal sublayer 156 may be located on a side of the eighth gate sublayer 148 away from the fourth metal sublayer 154 in the X direction, and the fourth active sub-region 134 may be stacked and connected to the sixth metal sublayer 156 (may be connected through a via).

[0173] In another example, the second metal layer may include a seventh metal sub-layer 157 , an eighth metal sub-layer 158 , a ninth metal sub-layer 159 , and a tenth metal sub-layer 1510 .

[0174] Among them, the seventh metal sublayer 157 can be stacked with the third active sub-region 133 along the Z direction, and the first metal sublayer 151, the fourth gate sublayer 144 and the third metal sublayer 153 can be stacked and connected to the seventh metal sublayer 157 respectively (can be connected through through holes). The eighth gate sublayer 148 and the fifth metal sublayer 155 can be stacked and connected to the eighth metal sublayer 158 respectively (can be connected through through holes). The ninth metal sublayer 159 can be stacked with the fourth active sub-region 134 along the Z direction, and the first gate sublayer 141 and the second metal sublayer 152 can be stacked and connected to the ninth metal sublayer 159 respectively (can be connected through through holes). The fourth metal sublayer 154, the eighth gate sublayer 148 and the sixth metal sublayer 156 can be stacked and connected to the tenth metal sublayer 1510 respectively (can be connected through through holes).

[0175] It can be imagined that the connection between different switching tubes can be achieved through the first metal sublayer 151, the second metal sublayer 152, the third metal sublayer 153, the fourth metal sublayer 154, the fifth metal sublayer 155, the sixth metal sublayer 156, the seventh metal sublayer 157, the eighth metal sublayer 158, the ninth metal sublayer 159 and the tenth metal sublayer 1510, thereby forming a storage unit 10.

[0176] It is also conceivable, referring to Figures 1 to 4 , that the second active sub-region 132 and the second gate sublayer 142 may constitute a switch transistor T1. The first active sub-region 131 and the third gate sublayer 143 may constitute a switch transistor T2. Switch transistors T1 and T2 may constitute the switch circuit of memory circuit 1. The fourth active sub-region 134 and the fourth gate sublayer 144 may constitute a switch transistor T3. The third active sub-region 133 and the first gate sublayer 141 may constitute a switch transistor T4. The second active sub-region 132 and the fourth gate sublayer 144 may constitute a switch transistor T5. The first active sub-region 131 and the first gate sublayer 141 may constitute a switch transistor T6. Thus, switches T3, T4, T5, and T6 may constitute the storage sub-circuit of memory circuit 2. The third active sub-region 133 and the seventh gate sublayer 147 may constitute a switch transistor T7. The first active sub-region 131 and the sixth gate sublayer 146 may constitute a switch transistor T8. Thus, switch transistors T7 and T8 can form transmission gate circuit 2. The second active sub-region 132 and the fifth gate sublayer 145 can form switch transistor T9. The second active sub-region 132 and the eighth gate sublayer 148 can form switch transistor T10. The fourth active sub-region 134 and the fifth gate sublayer 145 can form switch transistor T11. The fourth active sub-region 134 and the eighth gate sublayer 148 can form switch transistor T12. Thus, switch transistors T9, T10, T11, and T12 can form a NOR gate (i.e., logic gate circuit 3 in FIG. 4 ).

[0177] In one possible implementation, the first active sub-area 131 may be provided with a first through-hole 161 and a second through-hole 162. The first through-hole 161 may be located on a side of the first gate sub-layer 141 away from the first metal sub-layer 151 in the X direction and may be used to connect to a first power line. The first power line may be used to provide a second operating voltage VSS. The second through-hole 162 may be located between the third gate sub-layer 143 and the third metal sub-layer 153 and may be used to connect to a second bit line.

[0178] The second active sub-region 132 may be provided with a third through-hole 163, a fourth through-hole 164, and a fifth through-hole 165. The third through-hole 163 may be located on a side of the second gate sub-layer 142 away from the second metal sub-layer 152 in the X direction, and may be used to connect to the first bit line. The fourth through-hole 164 may be located between the fourth gate sub-layer 144 and the fifth gate sub-layer 145. The fifth through-hole 165 may be located on a side of the eighth gate sub-layer 148 away from the fourth metal sub-layer 154 in the X direction. Both the fourth through-hole 164 and the fifth through-hole 165 may be used to connect to the first power line.

[0179] The third active sub-region 133 may be provided with a sixth through-hole 166. The fourth active sub-region 134 may be provided with a seventh through-hole 167. Sixth through-hole 166 may be located on a side of the first gate sub-layer 141 that is farther from the first metal sub-layer 151 in the X-direction. Seventh through-hole 167 may be located between the fourth gate sub-layer 144 and the fifth gate sub-layer 145. Both sixth through-hole 166 and seventh through-hole 167 may be used to connect to a second power supply line. The second power supply line may be used to provide a first operating voltage VDD.

[0180] In another possible implementation, the second gate sublayer 142 may be provided with an eighth through hole 168. The third gate sublayer 143 may be provided with a ninth through hole 169. The eighth through hole 168 and the ninth through hole 169 may be used to connect to the first word line.

[0181] The fifth gate sublayer 145 may be provided with a tenth through hole 1610. The tenth through hole 1610 may be used to connect an input line, and the input line may be used to provide second input data.

[0182] The sixth gate sublayer 146 may be provided with an eleventh through hole 1611 , and the eleventh through hole 1611 may be used to connect to the third word line.

[0183] The seventh gate sublayer 147 may be provided with a twelfth through hole 1612 , and the twelfth through hole 1612 may be used to connect to the second word line.

[0184] The fourth metal sub-layer 154 may be provided with a thirteenth through-hole 1613 . The thirteenth through-hole 1613 may be used to connect to an output line, and the output line may be used to output a logic operation result of the memory cell 10 .

[0185] The present application also provides a memory array, as shown in Figures 5 and 6. Memory array 100 may include M first word lines (i.e., first electrode lines), M second word lines (i.e., fourth electrode lines), M third word lines (i.e., fourth electrode lines), M input lines, N first bit lines (i.e., second electrode lines), N second bit lines (i.e., third electrode lines), and M×N memory cells. In Figure 5, the logic gate circuit in the memory cell may be an AND gate, and in Figure 6, the logic gate circuit in the memory cell may be a NOR gate.

[0186] The M first word lines may include a first word line WL11, a first word line WL12, ..., and a first word line WL1M. The M second word lines may include a second word line WL21, a second word line WL22, ..., and a second word line WL2M. The M third word lines may include a third word line WL31, a third word line WL32, ..., and a third word line WL3M. The M input lines may include an input line IN1, an input line IN2, ..., and an input line INM.

[0187] The N first bit lines may include first bit line BL11, first bit line BL12, ..., first bit line BL1n, ..., first bit line BL1N. The N second bit lines may include second bit line BL21, second bit line BL22, ..., second bit line BL2n, ..., second bit line BL2N.

[0188] As can be seen from Figures 5 and 6, memory cells in the same row can be connected to the same first word line, the same second word line, the same third word line, and the same input line. In other words, memory cells in the same row can share the first word line WL1, the second word line WL2, the third word line WL3, and the input line IN. Similarly, memory cells in the same column can be connected to the same first bit line and the same second bit line. In other words, memory cells in the same column can share the first bit line BL1 and the second bit line BL2.

[0189] The storage array 100 provided in the present application can receive the first control signal CS1 through the first word line, receive the second control signal CS2 through the second word line, and receive the third control signal CS3 through the third word line. It can also receive the first weight data W1 through the first bit line and the third weight data W3 through the second bit line. Finally, the storage of the first weight data W1 and the third weight data W3 is realized through M×N storage cells. It can also realize the logical operation of the second input data and the first weight data W1, or the logical operation of the second input data and the third weight data W3.

[0190] In a possible implementation, as shown in Figures 5 and 6, the memory array 100 may further include a summing unit. Some or all of the M×N memory cells are connected to the summing unit.

[0191] It is conceivable that there may be one or more summing units. In the case where there is one summing unit, all storage units may be connected to the summing unit. In the case where there are multiple summing units (i.e., summing units 21 to summing units 2H in FIG5 ), the M×N storage units may be divided into multiple parts. Each part may include one or more storage units. Each part may be connected to one summing unit. The embodiment of the present application is described by taking multiple summing units as an example.

[0192] Optionally, a summing unit (such as the summing unit 21 ) may be used to sum the logic operation results output by the logic gate circuit 3 in each storage unit, obtain a summing result (which may be represented by ADD), and output the summing result.

[0193] Exemplarily, the summing units 21 to 2H may be adder trees, etc., which is not limited in the embodiment of the present application.

[0194] In one example, the logic gate circuit in the storage unit 10 may be an AND gate, as shown in FIG5 .

[0195] In another example, the logic gate circuit in the storage unit 10 may be a NOR gate, as shown in FIG6 .

[0196] The present invention provides a memory, as shown in Figures 7 and 8. The memory 1100 may include a control unit 200, a first decoder 300 (which may be called a row decoder), a plurality of second decoders (which may be called column decoders), and a memory array 100.

[0197] The multiple second decoders may include second decoders 401, ..., and second decoder 40H. It is conceivable that the number of second decoders is equal to the number of summing units, and that the multiple second decoders correspond one-to-one to the multiple summing units. Of course, the number of second decoders may be determined by the number of storage units. Therefore, there may be only one second decoder, which is not limited in this embodiment of the present application.

[0198] Optionally, the control unit 200 can be used to: output M-way second input data (i.e., input data transmitted on the input line IN1 to the input line INM in Figures 7 and 8) to each memory cell in the memory array 100 according to the calculation clock signal CLKC, and output M-way second control signal CS2 (i.e., control signal transmitted on the second word line WL21 to the second word line WL2M in Figures 7 and 8) and M-way third control signal CS3 (i.e., control signal transmitted on the third word line WL31 to the third word line WL3M in Figures 7 and 8) to each memory cell.

[0199] The control unit 200 may also be configured to: output a read / write clock signal CLKW and first address information IP1 of each memory cell to the first decoder 300, and output a fourth control signal (which may be represented by CS4), the read / write clock signal CLKW, and second address information IP2 of each memory cell to the second decoders 401 to 40H. The first address information IP1 may be used to indicate the row address information of each memory cell, the second address information IP2 may be used to indicate the column address information of each memory cell, and the fourth control signal CS4 may be used to instruct the memory 1100 to perform a read operation or a write operation.

[0200] The first decoder 300 can be used to: decode the first address information IP1 according to the read / write clock signal CLKW, and output M first control signals CS1 (i.e., the control signals transmitted on the first word line WL11 to the first word line WL1M in Figures 7 and 8) to the corresponding storage units according to the obtained first decoding result A1.

[0201] The second decoder 401 can be used to: decode the second address information IP2 according to the read-write clock signal CLKW and the fourth control signal CS4, and output the first weight data W1 (i.e., the weight data transmitted on the first bit line BL11 and the first bit line BL12 in Figures 7 and 8) and the third weight data W3 (i.e., the weight data transmitted on the second bit line BL21 and the second bit line BL22 in Figures 7 and 8) to the corresponding storage unit based on the fourth data (which can be the weight data written to the memory 1100, represented by W4) and the obtained second decoding result A2.

[0202] The second decoder 40H can be used to: decode the second address information IP2 according to the read-write clock signal CLKW and the fourth control signal CS4, and output the first weight data W1 (i.e., the weight data transmitted from the first bit line BL1n to the first bit line BL1N in Figures 7 and 8) and the third weight data W3 (i.e., the weight data transmitted from the second bit line BL2n to the second bit line BL2N in Figures 7 and 8) to the corresponding storage unit according to the fourth weight data W4 and the obtained second decoding result A2.

[0203] It can be understood that the second decoders 401 to 40H can output N channels of first weight data W1 and N channels of third weight data W3 to the memory array 100 .

[0204] In the memory 1100 provided in the embodiment of the present application, the control unit 200 can not only output M-way second input data, M-way second control signal CS2, and M-way third control signal CS3 to the memory array 100, but can also output the read / write clock signal CLKW, the first address information IP1, the fourth control signal CS4, and the second address information IP2. Then, the first decoder 300 decodes the first address information IP1 and outputs the M-way first control signal CS1, and the second decoder 401 to the second decoder 40H decodes the second address information IP2 and outputs the N-way first weight data W1 and N-way third weight data W3. Since the memory array 100 can perform logical operations while storing the first weight data W1 and the third weight data W3, the memory 1100 provided in the embodiment of the present application can also perform simultaneous storage and logical operations on the first weight data W1 and the third weight data W3, thereby achieving high computing power and high energy efficiency of the memory 1100.

[0205] Since the storage and logical operations of the first weight data W1 and the third weight data W3 are all completed in the storage unit, the memory 1100 provided in the embodiment of the present application can be called a computing in memory (CIM) memory, which can be referred to as a CIM memory for short.

[0206] In a possible implementation, the control unit 200 may include a first controller 201 and a second controller 202. The second controller 202, the first decoder 300, and the second decoders 401 to 40H are all connected to the first controller 201.

[0207] The first controller 201 is used to: output the calculation clock signal CLKC and the second control signal CS2 to the second controller 202, obtain the first address information IP1 and the second address information IP2, and output the read-write clock signal CLKW and the first address information IP1 to the first decoder 300, and output the read-write clock signal CLKW, the second address information IP2 and the fourth control signal CS4 to the second decoder 401 to the second decoder 40H.

[0208] The second controller 202 is configured to divide the second control signal CS2 from the first controller 201 into M second control signals CS2 and transmit them one-to-one to the M second word lines (i.e., second word lines WL21 to WL2M) in the memory array 100. The second controller 202 is further configured to invert the second control signal CS2 (via an inverter) to obtain a third control signal CS3, and divide the third control signal CS3 into M third control signals CS3 and transmit them one-to-one to the M third word lines (i.e., third word lines WL31 to WL3M) in the memory array 100.

[0209] The second controller 202 can also be used to: transmit the M channels of second input data (i.e., input data transmitted on input lines IN1 to INM) to the logic gate circuit in each storage unit in a one-to-one correspondence according to the calculation clock signal CLKC, as shown in FIG7. Alternatively, the second controller 202 can be used to invert (implemented by an inverter) the M channels of first input data (i.e., first input data IN1-BD to first input data INM-BD in FIG8) according to the calculation clock signal CLKC, as shown in FIG8, thereby obtaining the M channels of second input data (i.e., input data transmitted on input lines IN1 to INM), which are transmitted to each logic gate circuit in a one-to-one correspondence.

[0210] Since the second controller 202 is controlled by the first controller 201 and the second controller 202 can output M channels of second input data, the first controller 201 can be called a master controller and the second controller 202 can be called an input controller.

[0211] In one example, as shown in FIG9 , the second controller 202 may further output M second control signals CS2 and transmit them to M second word lines. Simultaneously, the second controller 202 may invert the M second control signals CS2 using M inverters to generate M third control signals CS3 and transmit them to M third word lines.

[0212] In another example, as shown in FIG10 , the second controller 202 may further output a second control signal CS2, divide the second control signal CS2 into M second control signals CS2, and transmit the signals to M second word lines. Simultaneously, the second controller 202 may invert the second control signal CS2 via an inverter to generate M third control signals CS3, and transmit the M third control signals CS3 to the M third word lines.

[0213] Furthermore, as shown in Figures 7 to 10, the memory 1100 may also include one or more amplifiers. One or more amplifiers may be connected to the first controller 201, and the amplifiers may also be connected to the second decoder. In the case where the memory includes multiple amplifiers, the multiple amplifiers may be connected to the multiple second decoders in a one-to-one correspondence. The multiple amplifiers may include amplifiers 501 to 50H, with amplifier 501 connected to the second decoder 401, and amplifier 50H connected to the second decoder 40H.

[0214] The second decoder 401 can also be used to: select at least one first weight data W1 from the multiple first weight data W1 corresponding to the second decoder 401 (such as the two first weight data W1 transmitted on the first bit line BL11 and the first bit line BL12) and transmit it to the amplifier 501 according to the read-write clock signal CLKW, the fourth control signal CS4 and the second decoding result A2, and select at least one third weight data W3 from the multiple third weight data W3 corresponding to the second decoder 401 (such as the two third weight data W3 transmitted on the second bit line BL21 and the second bit line BL22) and transmit it to the amplifier 501.

[0215] The second decoder 40H can also be used to: select at least one first weight data W1 from the multiple first weight data W1 corresponding to the second decoder 40H (such as the multiple first weight data W1 transmitted from the first bit line BL1n to the first bit line BL1N) according to the read-write clock signal CLKW, the fourth control signal CS4 and the second decoding result A2, and transmit it to the amplifier 50H, and select at least one third weight data W3 from the multiple third weight data W3 corresponding to the second decoder 40H (such as the multiple third weight data W3 transmitted from the second bit line BL2n to the second bit line BL2N) and transmit it to the amplifier 50H.

[0216] The first controller 201 can also be used to output a read / write clock signal CLKW to the amplifier 501 to the amplifier 50H. It can be seen that the first controller 201 not only outputs the read / write clock signal CLKW to the first decoder 300 and the second decoder 401 to the second decoder 40H, but also outputs the read / write clock signal CLKW to the amplifier 501 to the amplifier 50H.

[0217] Amplifiers 501 to 50H can be used to amplify and output the difference between the first weight data W1 and the third weight data W3 according to the read / write clock signal CLKW, that is, to obtain and output the fifth data (which can be the weight data of the memory 1100 and can be represented by W5).

[0218] The amplifiers 501 to 50H may be sense amplifiers or the like, which is not limited in the embodiment of the present application.

[0219] 7 to 10 , the memory 1100 may further include a plurality of accumulators, which may include accumulators 601 to 60H.

[0220] Optionally, the accumulator (eg, accumulator 601 ) may be configured to accumulate the summation results ADD outputted by the summing unit (eg, summing unit 21 ) in different cycles, obtain an accumulated result, and output the accumulated result.

[0221] In some embodiments, the operating mode of the memory may include a read-write mode, a storage calculation mode, a calculation mode, and a hold mode. Among them, the read-write mode can be used to instruct the memory 1100 to perform a read operation or a write operation, that is, the memory 1100 only reads and writes. The storage calculation mode can be used to instruct the memory 1100 to perform storage operations and calculation operations at the same time, that is, the memory 1100 performs storage and logical operations at the same time. The calculation mode can be used to instruct the memory 1100 to perform calculation operations, that is, the memory 1100 only performs calculation operations. The hold mode can be used to instruct the memory 1100 to maintain the first weight data W1 and the third weight data W3, that is, the memory 1100 does not perform a storage operation or a calculation operation.

[0222] The following is an introduction to the above working modes.

[0223] (1) Read-write mode

[0224] The memory 1100 can be used for: as shown in Figure 11, the second control signal CS2 is controlled to be high level by the second controller 202. It can be understood that the third control signal CS3 can be low level, so that each transmission gate circuit in the storage array 100 is closed, and the first weight data W1 and the third weight data W3 are written through each storage unit, and the difference between the first weight data W1 and the third weight data W3 is amplified through the amplifier 501 to the amplifier 50H and the fourth weight data W4 is output.

[0225] Optionally, the timing diagram of each of the second control signal CS2, the write clock signal CLKW, the fourth control signal CS4, the calculation clock signal CLKC, the first address information IP1, the second address information IP2, the first control signal CS1, the third weight data W3 and the fourth weight data W4 is shown in Figure 11. In Figure 11, the calculation clock signal CLKC can always be at a low level, i and i+1 can represent the number of times the memory 100 performs a write operation, and i+2 and i+3 represent the number of times the memory performs a read operation. It can be understood that when the memory 1100 is in read-write mode, the write clock signal CLKC, the second input data (which can be represented by IN-D, generally referring to the input data transmitted on the input line IN1 to the input line INM) and the summation result ADD can all be low levels, which are not reflected in Figure 11.

[0226] (2) Storage calculation mode

[0227] The memory 1100 can be configured to: as shown in FIG12 , control the second control signal CS2 to a high level via the second controller 202. It is understood that the third control signal CS3 can be a low level, closing each transmission gate circuit in the memory array 100, writing the first weight data W1 and the third weight data W3 through the memory cell, and amplifying the difference between the first weight data W1 and the third weight data W3 via amplifiers 501 to 50H to output the fourth weight data W4. The memory 1100 can also be configured to output a logical operation result through each memory cell.

[0228] Alternatively, a timing diagram of each of the second control signal CS2, the write clock signal CLKW, the fourth control signal CS4, the first address information IP1, the second address information IP2, the first control signal CS1, the third weight data W3, the fourth weight data W4, the calculation clock signal CLKC, the second input data IN-D, and the summation result ADD is shown in FIG12 . In FIG12 , i and i+1 may represent the number of write operations performed by the memory 100, i+2 and i+3 may represent the number of read operations performed by the memory. j and j+1 may represent the number of logical operations performed by the memory 100.

[0229] As can be seen from Figures 11 and 12, when the memory 1100 is in the read-write mode or the storage calculation mode, the second control signal CS2 is high and each transmission gate circuit is closed. In the read-write mode, the memory 1100 not only realizes the storage of the first weight data W1 and the third weight data W3, but also can realize the amplification and output of the difference between the first weight data W1 and the third weight data W3. In the storage calculation mode, the memory 1100 realizes not only the storage of the first weight data W1 and the third weight data W3, but also can realize the amplification and output of the difference between the first weight data W1 and the third weight data W3, but also can realize the output of the logical operation result SUM.

[0230] (3) Calculation model

[0231] The memory 1100 can be used as shown in FIG13 , by controlling the second control signal CS2 to be low through the second controller 202 , so that each transmission gate circuit in the memory array 1100 is opened, and the logic operation result is output through each memory cell.

[0232] Optionally, the timing diagrams of the second control signal CS2, the write clock signal CLKW, the calculation clock signal CLKC, the second input data IN-D, and the summation result ADD are shown in FIG13. In FIG13, the write clock signal CLKW can always be at a low level, and j and j+1 can represent the number of times the memory 100 performs a logical operation. It can be understood that when the memory 1100 is in the calculation mode, the fourth control signal CS4, the first address information IP1, the second address information IP2, the first control signal CS1, the third weight data W3, and the fourth weight data W4 can all be at a low level, which is not shown in FIG13.

[0233] (4) Hold mode

[0234] The memory 1100 can be used as shown in FIG14 . The second controller 202 controls the second control signal CS2 to be low, thereby opening each transmission gate circuit in the memory array 1100. The first weight data W1 or the third weight data W3 from the transmission gate circuit remains unchanged, and the second input data also remains unchanged (because the calculation clock signal CLKC remains unchanged). The first weight data W1 and the third weight data W3 are retained in the memory 1100, and the logic operation is stopped. The first weight data W1 and the third weight data W3 are stored in each storage unit.

[0235] Optionally, the timing diagrams of the second control signal CS2, the write clock signal CLKW, the calculation clock signal CLKC, and the first control signal CS1 are shown in FIG14 . The second control signal CS2, the write clock signal CLKW, the calculation clock signal CLKC, and the first control signal CS1 can be at a low level. It is understood that when the memory 1100 is in the hold mode, the fourth control signal CS4, the first address information IP1, the second address information IP2, the third weight data W3, the fourth weight data W4, the second input data IN-D, and the summation result ADD can all be at a low level, which is not shown in FIG14 .

[0236] As can be seen from Figures 13 and 14, when the memory 1100 is in calculation mode or hold mode, the second control signal CS2 is at a low level, and each transmission gate circuit is open. In calculation mode, the memory 1100 is used to output the logical operation result, and in hold mode, the memory 1100 is used to store the first weight data W1 and the third weight data W3.

[0237] The embodiment of the present application further provides a system on chip (SOC) chip (ie, SOC chip). As shown in FIG15 , the SOC chip 1000 may include a processor 1200 and the aforementioned memory 1100. The memory 1100 may be connected to the processor 1200.

[0238] Exemplarily, the SOC chip 1000 may include one or more memories 1100 (i.e., one or more CIM memories), which is not limited in the present embodiment. The one or more CIM memories may be connected to the processor 1200 via a bus 1400. As shown in FIG15 , in the embodiment of the present application, the SOC chip 1000 may include four CIM memories.

[0239] Optionally, referring to FIG. 15 , the SOC chip 1000 may further include a static random-access memory (SRAM) 1300 , etc. The SRAM 1300 may also be connected to the processor 2000 via a bus 1400 .

[0240] For example, SOC chip 1000 can use neural network algorithms (including convolutional neural networks, vision, text, voice, and other multimodal algorithms) and can be used in artificial intelligence scenarios such as computer vision and natural language processing. SOC chip 1000 can be a neural network accelerator, a digital signal processor, a finite impulse response filter, etc.

[0241] The embodiment of the present application further provides an electronic device, as shown in FIG16 . The electronic device 1000 may include an off-chip memory (OCM) chip 2000 and the aforementioned SOC chip 1000. The off-chip memory chip 2000 may be connected to the processor 1200 in the SOC chip 1000 via a bus 1400.

[0242] For example, referring to FIG. 16 , the off-chip memory chip 2000 may include a non-volatile memory (NVM) 2200 and a dynamic random access memory (DRAM) 2100 , etc., which is not limited in the embodiment of the present application.

[0243] Furthermore, the NVM 2200 may be connected to the DRAM 2100 , and the DRAM 2100 may be connected to the processor 1200 in the SOC chip 1000 via a bus 1400 .

[0244] Optionally, the electronic device 10000 can be a mobile terminal device such as a mobile phone, a computer, a smart car machine, a smart wearable device, or a fixed terminal device such as a cloud computing server, a data center, etc. Of course, the electronic device can also be other devices, which is not limited in the present embodiment.

[0245] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A storage unit, characterized in that: Including storage circuits, transmission gate circuits and logic gate circuits; Wherein, the storage circuit is used to store the first data, the first control end and the second control end of the storage circuit are both electrically connected to the first electrode line, the first input and output ends of the storage circuit are electrically connected to the second electrode line, the second input and output ends of the storage circuit are electrically connected to the third electrode line, the output end of the storage circuit is electrically connected to the input end of the transmission gate circuit, the control end of the transmission gate circuit is electrically connected to the fourth electrode line, the output end of the transmission gate circuit is electrically connected to the first input end of the logic gate circuit, the second input end of the logic gate circuit is used to receive the second data, and the output end of the logic gate circuit serves as the output end of the storage unit.

2. The storage unit according to claim 1, characterized in that The storage circuit includes a switch circuit and a storage sub-circuit; The first input end of the switch circuit serves as the first control end of the storage circuit, and the second input end of the switch circuit serves as the second control end of the storage circuit; the first input and output ends of the switch circuit serve as the first input and output ends of the storage circuit, and the second input and output ends of the switch circuit serve as the second input and output ends of the storage circuit; the third input and output ends of the switch circuit are electrically connected to the first input and output ends of the storage sub-circuit, and the fourth input and output ends of the switch circuit are electrically connected to the second input and output ends of the storage sub-circuit; the output end of the storage sub-circuit serves as the output end of the storage circuit.

3. The storage unit according to claim 2, characterized in that The switch circuit includes a first switch tube and a second switch tube; The control electrode of the first switch tube serves as the first input terminal of the switch circuit, and the control electrode of the second switch tube serves as the second input terminal of the switch circuit. The control electrodes of the first switch tube and the second switch tube are electrically connected to the first word line for receiving the first control signal. The first electrode of the first switch tube is electrically connected to the first bit line for receiving the first data. The first electrode of the second switch tube is electrically connected to the second bit line for receiving third data; the second electrode of the first switch tube serves as the third input and output terminal of the switch circuit, and the second electrode of the second switch tube serves as the fourth input and output terminal of the switch circuit; The first data and the third data are both 1 or 0, and the first data and the third data are different.

4. The storage unit according to claim 2 or 3, characterized in that: The storage sub-circuit includes a third switch tube, a fourth switch tube, a fifth switch tube and a sixth switch tube; The first pole of each of the third switch tube and the fourth switch tube is used to receive a first working voltage; the second pole of the third switch tube and the first pole of the fifth switch tube are both electrically connected to node A, and the node A serves as the first input and output end of the storage sub-circuit; the control poles of each of the third switch tube and the fifth switch tube are both electrically connected to node B, the second pole of the fourth switch tube and the first pole of the sixth switch tube are both electrically connected to node C, the node B is electrically connected to the node C, and the node C serves as the second input and output end of the storage sub-circuit; the control poles of each of the fourth switch tube and the sixth switch tube are both electrically connected to node D, and the node D is electrically connected to the node A; the second poles of the fifth switch tube and the sixth switch tube are used to receive a second working voltage.

5. The storage unit according to any one of claims 1 to 4, characterized in that: The transmission gate circuit includes a seventh switch tube and an eighth switch tube; The control electrodes of the seventh switch tube and the eighth switch tube are respectively used as the control electrodes of the transmission gate circuit; wherein the control electrode of the seventh switch tube is electrically connected to the second word line for receiving the second control signal; the control electrode of the eighth switch tube is electrically connected to the third word line for receiving the third control signal; the first electrode of the seventh switch tube is electrically connected to the first electrode of the eighth switch tube, as the input end of the transmission gate circuit, and the input end of the transmission gate circuit is electrically connected to the node A or the node C; the second electrode of the seventh switch tube is electrically connected to the second electrode of the eighth switch tube, as the output end of the logic gate circuit; The second control signal and the third control signal are both at a high level or a low level, and the second control signal and the third control signal are different.

6. The storage unit according to claim 5, characterized in that The input end of the transmission gate circuit is electrically connected to the node A, and the logic gate circuit is an AND gate.

7. The storage unit according to claim 5, characterized in that The input end of the transmission gate circuit is electrically connected to the node C, and the logic gate circuit is a NOR gate.

8. A storage array, characterized in that: comprising M first electrode lines, M fourth electrode lines, M input lines, N second electrode lines, N third electrode lines and M×N storage units as claimed in any one of claims 1 to 7; The memory cells in the same row share the first electrode line, the fourth electrode line and the input line, and the memory cells in the same column share the second electrode line and the third electrode line.

9. The storage array according to claim 8, characterized in that: The storage array further includes a summing unit; some or all of the M×N storage units are connected to the summing unit; The summing unit is used to sum the logic operation results output by the logic gate circuit in each storage unit.

10. A memory, characterized in that: comprising a control unit, a first decoder, a second decoder and the storage array according to claim 8 or 9; The control unit is used to: output M-way second data to each storage unit in the storage array according to the calculation clock signal, and output M-way second control signals and M-way third control signals to each storage unit; It is also used to output a read / write clock signal and the first address information of each storage unit to the first decoder, and output a fourth control signal, the read / write clock signal and the second address information of each storage unit to the second decoder; wherein the fourth control signal is used to instruct the memory to perform a read operation or a write operation; The first decoder is used to: decode the first address information according to the read / write clock signal, and output M first control signals to corresponding storage units according to the obtained first decoding result; The second decoder is used to decode the second address information according to the read / write clock signal and the fourth control signal, and output a first data and a third data to a corresponding storage unit according to the fourth data and the obtained second decoding result.

11. The memory according to claim 10, characterized in that: The control unit includes a first controller and a second controller; the second controller, the first decoder and the second decoder are all connected to the first controller; The first controller is used to: output the calculation clock signal and the second control signal to the second controller, obtain the first address information and the second address information, and output the read / write clock signal and the first address information to the first decoder, and output the read / write clock signal, the second address information and the fourth control signal to the second decoder; The second controller is used to: divide the second control signal from the first controller into M second control signals and output them one-to-one to the M second word lines in the storage array; and is also used to invert the second control signal to obtain a third control signal, and divide the third control signal into M third control signals and output them one-to-one to the M third word lines in the storage array; It is also used to output the M-way second data one-to-one to the logic gate circuit in each storage unit according to the calculation clock signal, or to invert the M-way fourth data according to the calculation clock signal to obtain the M-way second data and output them one-to-one to each logic gate circuit.

12. The memory according to claim 11, characterized in that: The memory further comprises an amplifier, the amplifier is connected to the first controller, and the amplifier is also connected to the second decoder; The second decoder is further used to: select at least one first data from the multiple first data corresponding to the second decoder and output it to the amplifier according to the read / write clock signal, the fourth control signal and the second decoding result, and select at least one third data from the multiple third data corresponding to the second decoder and output it to the amplifier; The first controller is further used to: output the read / write clock signal to the amplifier; The amplifier is used to amplify and output the difference between the first data and the third data according to the read / write clock signal.

13. The memory according to claim 12, characterized in that: The working modes of the memory include read-write mode, storage calculation mode, calculation mode and holding mode; Wherein, the read / write mode is used to instruct the memory to perform a read operation or a write operation; The storage computing mode is used to instruct the memory to perform storage operations and computing operations simultaneously; The computing mode is used to instruct the memory to perform a computing operation; The retention mode is used to instruct the memory to retain the first data and the third data.

14. The memory according to claim 13, characterized in that: When the memory is in a read-write mode, the memory is used to: control the second control signal to a high level through the second controller to close each transmission gate circuit in the storage array, write the first data and the third data through each storage unit, and amplify and output the difference between the first data and the third data through the amplifier.

15. The memory according to claim 13, characterized in that: When the memory is in a storage calculation mode, the memory is used to: control the second control signal to a high level through the second controller to close each transmission gate circuit in the storage array, write the first data and the third data through the storage unit, and amplify and output the difference between the first data and the third data through the amplifier; the memory is also used to output the logic operation result through each storage unit.

16. The memory according to claim 13, characterized in that: When the memory is in a calculation mode, the memory is used to: control the second control signal to a low level through the second controller, so that each transmission gate circuit in the storage array is opened, and the logic operation result is output through each storage unit.

17. The memory according to claim 13, characterized in that: When the memory is in the holding mode, the memory is used to: The second controller controls the second control signal to be at a low level, so that each transmission gate circuit in the storage array is turned on, and the first data and the third data are stored through each storage unit.

18. A circuit layout of a storage unit, characterized in that: It includes a substrate, an N-well region, an active region, a gate layer and a metal layer; wherein the active region includes a first active region and a second active region; The substrate and the N-well region are stacked along a first direction, the first active region is arranged on the substrate along the first direction, the second active region is arranged on the N-well region along the first direction, the gate layer is arranged on the active region along the first direction, and the metal layer is arranged on the active region or the gate layer along the first direction.

19. The circuit layout of the memory cell according to claim 18, characterized in that: The first active region includes a first active sub-region and a second active sub-region, and the second active region includes a third active sub-region and a fourth active sub-region; The first active sub-region, the third active sub-region, the fourth active sub-region and the second active sub-region are sequentially arranged in parallel along a second direction; wherein the second direction is perpendicular to the first direction.

20. The circuit layout of the memory cell according to claim 19, characterized in that: The gate layer includes a first gate sublayer, a second gate sublayer, a third gate sublayer, a fourth gate sublayer, a fifth gate sublayer, a sixth gate sublayer, a seventh gate sublayer and an eighth gate sublayer arranged along a third direction; wherein the third direction is perpendicular to the first direction, and the third direction is perpendicular to the second direction; The first gate sublayer, the fourth gate sublayer, the fifth gate sublayer and the eighth gate sublayer are sequentially arranged in parallel along the third direction; the first active sub-region, the third active sub-region and the fourth active sub-region are respectively stacked and connected with the first gate sublayer, the third active sub-region, the fourth active sub-region and the second active sub-region are respectively stacked and connected with the fourth gate sublayer, the fourth active sub-region and the second active sub-region are respectively stacked and connected with the fifth gate sublayer, and the fourth active sub-region and the second active sub-region are respectively stacked and connected with the eighth gate sublayer; The second gate sublayer is located in the extension direction of the first gate sublayer, and the second gate sublayer is stacked and connected to the second active sub-region; the third gate sublayer is located in the extension direction of the fourth gate sublayer, and the third gate sublayer is stacked and connected to the first active sub-region; the sixth gate sublayer and the seventh gate sublayer are both located in the extension direction of the eighth gate sublayer, the sixth gate sublayer is stacked and connected to the first active sub-region, and the seventh gate sublayer is stacked and connected to the third active sub-region.

21. The circuit layout of the memory cell according to claim 20, characterized in that: The metal layer includes a first metal layer and a second metal layer; wherein the first metal layer is arranged along the third direction, and the second metal layer is arranged along the second direction.

22. The circuit layout of the memory cell according to claim 21, characterized in that: The first metal layer includes a first metal sublayer, a second metal sublayer, a third metal sublayer, a fourth metal sublayer, a fifth metal sublayer and a sixth metal sublayer; The first metal sublayer, the third metal sublayer and the fifth metal sublayer are sequentially arranged in parallel along the second direction, the second metal sublayer, the fourth metal sublayer and the sixth metal sublayer are sequentially arranged in parallel along the second direction, the second metal sublayer is located in the extension direction of the first metal sublayer, the fourth metal sublayer is located in the extension direction of the third metal sublayer, and the sixth metal sublayer is located in the extension direction of the fifth metal sublayer; The first metal sublayer and the second metal sublayer are both located between the first gate sublayer and the fourth gate sublayer, the first active sub-region and the third active sub-region are respectively stacked and connected to the first metal sublayer, and the fourth active sub-region and the second active sub-region are respectively stacked and connected to the second metal sublayer; The third metal sublayer is located between the fourth gate sublayer and the seventh gate sublayer, and the first active sub-region and the third active sub-region are respectively stacked and connected with the third metal sublayer; The fourth metal sublayer is located between the fifth gate sublayer and the eighth gate sublayer, and the second active sub-region is stacked and connected to the fourth metal sublayer; The fifth metal sublayer is located at a side of the seventh gate sublayer away from the third metal sublayer in the second direction, and the first active sub-region and the third active sub-region are respectively stacked and connected with the fifth metal sublayer; The sixth metal sublayer is located at a side of the eighth gate sublayer away from the fourth metal sublayer in the second direction, and the fourth active sub-region is stacked and connected to the sixth metal sublayer.

23. The circuit layout of the memory cell according to claim 22, characterized in that: The second metal layer includes a seventh metal sublayer, an eighth metal sublayer, a ninth metal sublayer and a tenth metal sublayer; The seventh metal sublayer is stacked with the third active sub-region along the first direction, the first metal sublayer, the fourth gate sublayer and the third metal sublayer are stacked with and connected to the seventh metal sublayer respectively; the eighth gate sublayer and the fifth metal sublayer are stacked with and connected to the eighth metal sublayer respectively; the ninth metal sublayer is stacked with the fourth gate sublayer along the first direction The active sub-areas are stacked, the first gate sub-layer and the second metal sub-layer are stacked and connected to the ninth metal sub-layer respectively; the fourth metal sub-layer, the eighth gate sub-layer and the sixth metal sub-layer are stacked and connected to the tenth metal sub-layer respectively.

24. The circuit layout of the memory cell according to claim 22 or 23, characterized in that: The first active sub-region is provided with a first through hole and a second through hole; wherein the first through hole is located on a side of the first gate sub-layer away from the first metal sub-layer in the second direction, and is used to connect a first power line; the second through hole is located between the third gate sub-layer and the third metal sub-layer, and is used to connect a second bit line; The second active sub-region is provided with a third through hole, a fourth through hole and a fifth through hole; wherein the third through hole is located on a side of the second gate sublayer away from the second metal sublayer in the second direction, and is used to connect the first bit line; the fourth through hole is located between the fourth gate sublayer and the fifth gate sublayer, and the fifth through hole is located on a side of the eighth gate sublayer away from the fourth metal sublayer in the second direction, and both the fourth through hole and the fifth through hole are used to connect the first power line; The third active sub-region is provided with a sixth through hole, and the fourth active sub-region is provided with a seventh through hole; wherein the sixth through hole is located on a side of the first gate sub-layer away from the first metal sub-layer in the second direction, and the seventh through hole is located between the fourth gate sub-layer and the fifth gate sub-layer, and the sixth through hole and the seventh through hole are both used to connect a second power line; The first power line is used to provide a second operating voltage, and the second power line is used to provide a first operating voltage.

25. The circuit layout of the memory cell according to any one of claims 22 to 24, characterized in that: The second gate sublayer is provided with an eighth through hole, the third gate sublayer is provided with a ninth through hole, and the eighth through hole and the ninth through hole are used to connect the first word line; The fifth gate sublayer is provided with a tenth through hole, the tenth through hole is used to connect an input line, and the input line is used to provide second data; The sixth gate sublayer is provided with an eleventh through hole, and the eleventh through hole is used to connect the third word line; The seventh gate sublayer is provided with a twelfth through hole, and the twelfth through hole is used to connect the second word line; The fourth metal sub-layer is provided with a thirteenth through hole, and the thirteenth through hole is used to connect an output line, and the output line is used to output the logic operation result of the storage unit.

26. A system-on-chip chip, characterized in that: The method comprises a processor and a memory as claimed in any one of claims 10 to 17; the memory is connected to the processor.

27. An electronic device, characterized in that: It comprises an off-chip memory chip and the system-on-chip chip as claimed in claim 26; the off-chip memory chip is connected to the system-on-chip chip.

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