Analog quantity sampling source end data error correction and prevention system and method

Abstract

The invention discloses an analog quantity sampling source end data error correction and prevention system and method. The system comprises an ADC chip, an ADC digital interface module and an error data detection and recovery module. The ADC chip is used for converting an acquired analog signal into a digital signal and inputting the digital signal into the ADC digital interface module; the ADC digital interface module is used for repeatedly sending two groups of complete digital sampling signals which are read from a digital interface of an ADC chip and have the same content but different sequences to the error data detection and recovery module through two independent interface data output channels, wherein each digital sampling signal with different sequences is read from the digital interface of the ADC chip; and the error data detection and recovery module performs error detection and / or recovery processing on the digital sampling signals uploaded by the two interface data output channels respectively, and transmits the recovered correct digital sampling signals to the corresponding application function modules. According to the invention, real-time error detection and error correction of ADC sampling data can be realized, and a fault-tolerant effect on accidental data damage when an ADC chip operates in a complex electromagnetic environment is achieved.

Description

Technical Field

[0001] The present invention belongs to the technical field of electric power equipment, and more specifically, relates to a system and method for correcting and preventing errors in analog quantity sampling source data. Background Art

[0002] As we all know, electronic computers process information from the physical world in binary digital form, while physical world information such as temperature, pressure, vibration, and current are all analog quantities and cannot be directly processed by electronic computers, but must be converted into digital signals; analog signals are converted into digital signals through analog / digital converters (ADCs), and then processed by electronic computer software to achieve advanced application functions such as perception, measurement, and control of the physical world. Therefore, ADC chips are widely used in the real world; after the ADC chip completes the data conversion, the sampling signal is generally read from the ADC's digital interface by interface chips such as the CPU, DSP, MCU, and FPGA; many application scenarios require the availability of sampling data, such as in power relay protection equipment, sampling data is directly used to remove power equipment faults to prevent large-scale power outages in the power system; if errors occur in the sampling data during the output process of the ADC chip, serious consequences will result.

[0003] In actual applications, the system composed of ADC chip and interface chip operates in a complex electromagnetic environment such as high temperature, humidity, or electrostatic interference. Some data output by the ADC chip may be damaged by the environment at a certain moment in the transmission process. This accidental error is not easily perceived by computer software and may cause errors in software calculations or logical processing results. To perceive this error, the following methods are currently used: (1) For fixed ADC input, anomaly detection is performed based on preset threshold comparison; (2) For variable ADC input, anomaly detection is performed based on a specific algorithm by obtaining sampling data at multiple different sampling times.

[0004] The paper "Research and Application of Real-time Detection Technology for Data Acquisition Reliability of Secondary Protection Devices in Autonomous and Controllable New Generation Smart Substations", Wang Xiaoli, Zhang Gaijie, Zhao Weiyi, 2020 Issue 11, "Electric Power Automation", the method of detecting whether the ADC output data is abnormal is: connect a fixed voltage to the eighth channel of the ADC, set the sampling threshold of the eighth channel output, compare the eighth channel sampling data output by the ADC with the threshold, and determine whether the eighth channel sampling is abnormal. This paper is based on the premise of presetting the ADC input as a fixed value, and can only be implemented in a static manner. It cannot adapt to dynamically changing ADC inputs and is not universal.

[0005] CN202010885073.9 discloses a method for detecting abnormalities in sampled data, including setting up two identical sampling circuits to sample the same data source, each circuit containing an ADC chip, first calculating the absolute error value between the current first sampled data and the current second sampled data, and when the absolute error value is greater than a preset threshold, then calculating the relative error value between the current first sampled data and the current second sampled data, and comparing it with the floating threshold of the first sampled data to determine whether the current sampled data is abnormal. This patent requires two sampling systems to identify erroneous data, and cannot recover erroneous data.

[0006] CN201611216036.9 discloses a method for preventing errors in single-point sampling of abnormal large numbers in a smart substation protection device, including judging whether the sampled data is greater than a preset threshold value. If it is greater than the threshold value, the current sampled value is compared with the sampled data of the two adjacent sampling cycles based on a specific formula to judge whether the current sampled data is abnormal. This patent cannot recover the erroneous data. Therefore, a source data detection and error correction method is urgently needed to realize the detection and recovery of erroneous data at the sampling source. Summary of the invention

[0007] In order to solve the deficiencies in the prior art, the present invention provides an analog quantity sampling source-end error correction and error prevention system, which provides an ADC chip supporting dual-channel output, an ADC digital interface module, and an error data detection and recovery module; the ADC chip transmits data with the same content but different sequences through dual channels, the ADC digital interface module performs data reordering after receiving the data, the error data detection and recovery module performs error detection on the reordered data, and completes data recovery according to the detection results.

[0008] In order to achieve the above-mentioned object of the invention, the present invention specifically adopts the following technical solutions.

[0009] An analog quantity sampling source end data error correction and error prevention system, comprising an ADC chip, an ADC digital interface module and an error data detection and recovery module;

[0010] The ADC chip is connected to the ADC digital interface module through a data output channel, and is used to convert the collected analog signal into a digital signal and input it into the ADC digital interface module;

[0011] The ADC digital interface module is connected to the ADC chip and the error data detection and recovery module, and reads two groups of digital sampling signals with the same content but different order from the ADC data output channel of the ADC chip, and repeatedly sends each digital sampling signal with different order to the error data detection and recovery module through two independent interface data output channels;

[0012] The error data detection and recovery module performs error detection and / or recovery processing on the digital sampling signals uploaded by the two interface data output channels respectively, and transmits the recovered correct digital sampling signals to the corresponding application function module.

[0013] The digital interface of the ADC chip defines two ADC data output channels, including a first ADC data output channel and a second ADC data output channel. Each ADC data output channel independently outputs digital signals with the same content but different sequences to the ADC digital interface module.

[0014] The error data detection and recovery module includes a data detection unit and a data recovery unit.

[0015] The data detection unit is used to detect whether the data output by the first ADC data output channel is the same as the data output by the second ADC data output channel.

[0016] The data recovery unit is used to recover erroneous data, output correct data and issue an error alarm.

[0017] The ADC digital interface module and the error data detection and recovery module can be implemented by FPGA, CPU / MCU / DSP software.

[0018] The system can also be expanded to connect more than one ADC digital interface module in parallel before an error data detection and recovery module, and each ADC digital interface module is connected to the corresponding ADC chip through two ADC data output channels.

[0019] At the same time, the present invention also provides an analog quantity sampling source end data error correction and error prevention method, the method comprising the following steps:

[0020] Step 1: Set the number of sampled data of the ADC chip to N, where N is an even number, and the order of data output by the first ADC data output channel is D 1 , D 2 , D 3 ,……,D N The data output sequence of the second ADC data output channel is D (N / 2) , D (N / 2+1) ,……,D N , D 1 , D 2 ,……,D (N / 2-1) ;

[0021] Step 2: The first ADC data output channel and the second ADC data output channel of the ADC chip output data simultaneously;

[0022] Step 3: In each sampling cycle, the ADC digital interface module reads two sampling data from the first ADC data output channel of the ADC chip, which are defined as 1A and 1B in the order of reading time; and reads two sampling data from the second ADC data output channel of the ADC chip, which are defined as 2A and 2B in the order of reading time;

[0023] Step 4: The ADC digital interface module sends the data received from the first ADC data output channel and the second ADC data output channel to the error data detection and recovery module;

[0024] Step 5: After receiving the data sent by the ADC digital interface module, the error data detection and recovery module performs error detection and recovery processing on the data.

[0025] The present invention further includes the following preferred embodiments:

[0026] In step 3, in each sampling period, the ADC digital interface module reads the data output by the ADC data output channel, which can be continuous reading or intermittent reading.

[0027] In step 5, after receiving the data sent by the ADC digital interface module, the error data detection and recovery module performs error detection and recovery processing on the data, including:

[0028] Step 5.1: The error data detection and recovery module first compares whether 1A and 2A are the same. If they are not the same, it extracts the different data D from 1A. 1a1 , D 1a2 ,……,D 1aM , and extract the corresponding data D in 2A 2a1 , D 2a2、 D 2a3、 ..., go to step 5.2, if the same, go to step 5.5;

[0029] Step 5.2: Error data detection and recovery module compares D one by one 1a1 , D 1a2 ,……,D 1aM Check whether the data in the time series corresponding to 1B and 2B are the same. If yes, go to step 5.5; if no, go to step 5.3;

[0030] Step 5.3: Error data detection and recovery module compares D one by one 2a1 , D 2a2 , D 2a3 , ...are the data in the time series corresponding to 1B and 2B the same? If yes, go to step 5.4; otherwise, go to step 5.6;

[0031] Step 5.4: Error data detection and recovery module uses 2A D1a1 , D 1a2 ,……,D 1aM Replace the data of 1A detected in step 5.2 to achieve data recovery, and then jump to step 5.2;

[0032] Step 5.5: The error data detection and recovery module outputs the correct data to the application function module;

[0033] Step 5.6: The error data detection and recovery module outputs a data error alarm to the application function module.

[0034] A terminal comprises a processor and a storage medium; the storage medium is used to store instructions; the processor is used to operate according to the instructions to execute the steps of any one of the methods.

[0035] A computer-readable storage medium stores a computer program, which implements the steps of any one of the methods when executed by a processor.

[0036] The beneficial effect of the present invention lies in that, compared with the prior art, the present invention aims at the problem of occasional individual data corruption during transmission of ADC chip output data in actual applications, and proposes an analog quantity sampling source end data error correction and error prevention system and implementation method. For the detection of abnormal data, it is only necessary to obtain data of one sampling cycle, and after the abnormal data is determined, the abnormal data in the case of an equivalent set of sampling data errors within one sampling cycle can be restored. The data recovery time can be completed within the sampling cycle, the data error detection and recovery efficiency is high, and the implementation method is simple and easy, thereby improving the abnormal data judgment efficiency and ADC data availability. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 This is a diagram of an analog quantity sampling source data error correction and error prevention system in an embodiment of the present invention;

[0038] Figure 2 This is a schematic diagram of the ADC chip sampling data output in an embodiment of the present invention;

[0039] Figure 3 This is a schematic diagram of error correction and error prevention principle of sampling data in an embodiment of the present invention;

[0040] Figure 4 1A is a flow chart of error correction and error prevention of sampling data in an embodiment of the present invention;

[0041] Figure 5 2A sampling data error correction and error prevention flow chart in an embodiment of the present invention;

[0042] Figure 6 It is a diagram of an application example of the data error correction and prevention system at the analog sampling source end in an embodiment of the present invention. DETAILED DESCRIPTION

[0043] In order to make the purpose, technical scheme and advantages of the present invention clearer, the technical scheme of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. The embodiments described in this application are only embodiments of a part of the present invention, rather than all embodiments. Based on the spirit of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work belong to the protection scope of the present invention.

[0044] The present invention provides an analog quantity sampling source data error correction and error prevention system, such as Figure 1 The figure shows a data error correction and error prevention system diagram of an analog quantity sampling source end in an embodiment of the present invention, wherein the system includes an ADC chip, an ADC digital interface module, and an error data detection and recovery module;

[0045] The ADC chip is connected to the ADC digital interface module through a data output channel, and is used to convert the collected analog signal into a digital signal and input it into the ADC digital interface module;

[0046] The ADC digital interface module is connected to the ADC chip and the error data detection and recovery module, and reads two groups of complete digital sampling signals with the same content but different order from the ADC data output channel of the ADC chip, and repeatedly sends each digital sampling signal with different order to the error data detection and recovery module through two independent interface data output channels;

[0047] The error data detection and recovery module performs error detection and / or recovery processing on the digital sampling signals uploaded by the two interface data output channels respectively, and transmits the recovered correct digital sampling signals to the corresponding application function module.

[0048] In one embodiment of the present invention, the digital interface of the ADC chip defines two ADC data output channels, including a first data output channel and a second data output channel, and each data output channel independently outputs digital signals with the same content but different sequences to the ADC digital interface module.

[0049] In one embodiment of the present invention, the error data detection and recovery module includes a data detection unit and a data recovery unit.

[0050] In this embodiment, the data detection unit is used to sequentially adjust the second data output by the second data output channel according to a set sequence rule, and detect whether the first data output by the first data output channel is the same as the adjusted second data.

[0051] In this embodiment, the data recovery unit is used to recover erroneous data, output correct data, and issue an error alarm.

[0052] In one embodiment of the present invention, the ADC digital interface module and the error data detection and recovery module can be implemented by FPGA, CPU / MCU / DSP software.

[0053] In a preferred but non-limiting embodiment of the present invention, Figure 6 As shown, the system can also be expanded to connect more than one ADC digital interface module in parallel before an error data detection and recovery module, and each ADC digital interface module is connected to the corresponding ADC chip through two data output channels.

[0054] In an embodiment of the present invention, the ADC data output channel includes a first ADC data output channel and a second ADC data output channel, and the second ADC data output channel and the first ADC data output channel satisfy a set data output sequence rule.

[0055] In one embodiment of the present invention, setting the order rule includes: setting the data output order of the first ADC data output channel to D 1 , D 2 , D 3 ,……,D N , where N is an even number, indicating the number of sampled data of the ADC chip; the data output order of the second ADC data output channel is D (N / 2) , D (N / 2+1) ,……,D N , D 1 , D 2 ,……,D (N / 2-1) .

[0056] In this embodiment, if Figure 2 The figure shows a schematic diagram of the sampling data output principle of the ADC chip in an embodiment of the present invention. In the embodiment, the number of sampling data of the ADC chip is 8, and the data output order of the first data output channel is D1, D2, D3, D4, D5, D6, D7, D8, and the data output order of the second data output channel is D5, D6, D7, D8, D1, D2, D3, D4.

[0057] The ADC digital interface module is connected to the ADC chip and the error data detection and recovery module, and is used to read digital signals from the data output channel of the ADC chip;

[0058] The error data detection and recovery module is connected to the ADC digital interface module, and is used to receive the output data of the ADC digital interface module, determine whether the received data is correct, and recover the error data.

[0059] In one embodiment of the present invention, the error data detection and recovery module includes a data detection unit and a data recovery unit.

[0060] The data detection unit is used to detect whether the data output by the first ADC data output channel is the same as the data output by the second ADC data output channel according to a set sequence rule; the data recovery unit is used to recover erroneous data, output correct data and issue an error alarm.

[0061] At the same time, the present invention also implements a method for error correction and error prevention of analog quantity sampling source data, the method comprising the following steps:

[0062] Step 1: Set the number of sampled data of the ADC chip to N, where N is an even number, and the order of data output by the first ADC data output channel is D 1 , D 2 , D 3 ,……,D N The data output sequence of the second ADC data output channel is D (N / 2) , D (N / 2+1) ,……,D N , D 1 , D 2 ,……,D (N / 2-1) ;

[0063] Step 2: The first ADC data output channel and the second ADC data output channel of the ADC chip output data simultaneously;

[0064] Step 3: In each sampling cycle, the ADC digital interface module reads two sampling data from the first ADC data output channel of the ADC chip, which are defined as 1A and 1B in the order of reading time; and reads two sampling data from the second ADC data output channel of the ADC chip, which are defined as 2A and 2B in the order of reading time;

[0065] Step 4: The ADC digital interface module sends the data received from the first ADC data output channel and the second ADC data output channel to the error data detection and recovery module;

[0066] Step 5: After receiving the data sent by the ADC digital interface module, the error data detection and recovery module performs error detection and recovery processing on the data.

[0067] In one embodiment of the present invention, in step 5, the error data detection and recovery module performs error detection and recovery processing on the dual-channel data after receiving the dual-channel data sent by the ADC digital interface module. The error data detection and recovery module completes data recovery without delay when a data failure occurs at the same time during the dual-channel transmission process, or when a single data failure occurs during the transmission process of any ADC data output channel. Figure 4 As shown, the specific steps are:

[0068] Step 5.1: The error data detection and recovery module first compares whether 1A and 2A are the same. If they are not the same, it extracts the different data D from 1A. 1a1 , D 1a2 ,……,D 1aM , and extract the corresponding data D in 2A 2a1 , D 2a2、 D 2a3、 ..., go to step 5.2, if the same, go to step 5.5;

[0069] Step 5.2: Error data detection and recovery module compares D one by one 1a1 , D 1a2 ,……,D 1aM Check whether the data in the time series corresponding to 1B and 2B are the same. If yes, go to step 5.5; if no, go to step 5.3;

[0070] Step 5.3: Error data detection and recovery module compares D one by one 2a1 , D 2a2 , D 2a3 , ...are the data in the time series corresponding to 1B and 2B the same? If yes, go to step 5.4; otherwise, go to step 5.6;

[0071] Step 5.4: Error data detection and recovery module uses 2A D 1a1 , D 1a2 ,……,D 1aM Replace the data of 1A detected in step 5.2 to achieve data recovery, and then jump to step 5.2;

[0072] Step 5.5: The error data detection and recovery module outputs the correct data to the application function module;

[0073] Step 5.6: The error data detection and recovery module outputs a data error alarm to the application function module.

[0074] In a preferred but non-limiting embodiment of the present invention, Figure 6 The error data detection and recovery module completes data recovery without delay when a data failure occurs at the same time in the dual-channel transmission process, or a single data failure occurs in the transmission process of any ADC data output channel. It also includes using the data of the first ADC data output channel to recover the error data of the second ADC data output channel when the data of the two data output channels are inconsistent.

[0075] In this embodiment, the ADC digital interface module reads two sampling data from the first ADC data output channel of the ADC chip, which are defined as 1A and 1B in the order of reading time; reads two sampling data from the second ADC data output channel of the ADC chip, which are defined as 2A and 2B in the order of reading time; it is assumed that the data D3, D5, D6 of 1A and the data D1, D2, D7 of 2A are disturbed and fail.

[0076] like Figure 3 , Figure 4 As shown, in this embodiment, the error data detection and recovery module includes the following steps:

[0077] Step 7.1: Compare 1A and 2A, extract different data D1, D2, D3, D5, D6, D7;

[0078] Step 7.2: Compare D1 of 1A with D1 of 1B and 2B. D1 of 1A is the same as D1 of 1B and 2B, so no processing is done.

[0079] Step 7.3: Compare D2 of 1A with D2 of 1B and 2B. D2 of 1A is the same as D2 of 1B and 2B, so no action is taken.

[0080] Step 7.4: Compare D3 of 1A with D3 of 1B and 2B, and then compare D3 of 2A with D3 of 1B and 2B, and replace D3 of 1A with D3 of 2A to restore the data;

[0081] Step 7.5: Compare D5 of 1A with D5 of 1B and 2B, and then compare D5 of 2A with D5 of 1B and 2B, and replace D5 of 1A with D5 of 2A to restore the data;

[0082] Step 7.6: Compare D6 of 1A with D6 of 1B and 2B, and then compare D6 of 2A with D6 of 1B and 2B, and replace D6 of 1A with D6 of 2A to restore the data;

[0083] Step 7.7: Compare D7 of 1A with D7 of 1B and 2B. D7 of 1A is the same as D7 of 1B and 2B, so no action is taken.

[0084] Step 8: Output the original correct data of 1A and the correct data after recovery.

[0085] Figure 5 This is the processing flow of the erroneous data appearing in 2A. In this embodiment, the erroneous data detection and recovery module includes the following steps:

[0086] Step 8.1: Compare 1A and 2A, extract different data D1, D2, D3, D5, D6, D7;

[0087] Step 8.2: Compare D1 of 2A with D1 of 1B and 2B, then compare D1 of 1A with D1 of 1B and 2B, and replace D1 of 2A with D1 of 1A to restore the data;

[0088] Step 8.3: Compare D2 of 2A with D2 of 1B and 2B, then compare D2 of 1A with D2 of 1B and 2B, and replace D2 of 2A with D2 of 1A to restore the data;

[0089] Step 8.4: Compare D3 of 2A with D3 of 1B and 2B. D3 of 2A is the same as D3 of 1B and 2B, so no action is taken.

[0090] Step 8.5: Compare D5 of 2A with D5 of 1B and 2B. D5 of 2A is the same as D5 of 1B and 2B, so no action is taken.

[0091] Step 8.6: Compare D6 of 2A with D6 of 1B and 2B. D6 of 2A is the same as D6 of 1B and 2B, so no action is taken.

[0092] Step 8.7: Compare D7 of 2A with D7 of 1B and 2B, then compare D7 of 1A with D7 of 1B and 2B, and replace D7 of 2A with D7 of 1A to restore the data;

[0093] Step 8.8: Output the original correct data of 2A and the correct data after recovery.

[0094] The present disclosure may be a system, a method and / or a computer program product. The computer program product may include a computer-readable storage medium carrying computer-readable program instructions for causing a processor to implement various aspects of the present disclosure.

[0095] A computer-readable storage medium may be a tangible device that can hold and store instructions used by an instruction execution device. A computer-readable storage medium may be, for example, but not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. More specific examples of computer-readable storage media (a non-exhaustive list) include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disk read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device, such as a punch card or a raised structure in a groove on which instructions are stored, and any suitable combination of the foregoing. As used herein, a computer-readable storage medium is not to be interpreted as a transient signal per se, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., a light pulse through a fiber optic cable), or an electrical signal transmitted through a wire.

[0096] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network can include copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in the computer-readable storage medium in each computing / processing device.

[0097] The computer program instructions for performing the operation of the present disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages, such as Smalltalk, C++, etc., and conventional procedural programming languages, such as "C" language or similar programming languages. Computer-readable program instructions may be executed completely on a user's computer, partially on a user's computer, as an independent software package, partially on a user's computer, partially on a remote computer, or completely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., using an Internet service provider to connect via the Internet). In some embodiments, an electronic circuit, such as a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), may be customized by utilizing the state information of the computer-readable program instructions, and the electronic circuit may execute the computer-readable program instructions, thereby realizing various aspects of the present disclosure.

[0098] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, ordinary technicians in the relevant field should understand that the specific implementation methods of the present invention can still be modified or replaced by equivalents, and any modifications or equivalent replacements that do not depart from the spirit and scope of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. An analog quantity sampling source data error correction and error prevention system, comprising an ADC chip, an ADC digital interface module and an error data detection and recovery module, characterized in that: The ADC chip is connected to the ADC digital interface module through a data output channel, and is used to convert the collected analog signal into a digital signal and input it into the ADC digital interface module; The ADC digital interface module is connected to the error data detection and recovery module, and reads two groups of digital sampling signals with the same content but different order from the ADC data output channel of the ADC chip, and repeatedly sends each digital sampling signal with different order to the error data detection and recovery module through two independent interface data output channels; The error data detection and recovery module performs error detection and / or recovery processing on the digital sampling signals uploaded by the two interface data output channels respectively, and transmits the recovered correct digital sampling signals to the corresponding application function module.

2. The analog quantity sampling source data error correction and error prevention system according to claim 1, characterized in that: The digital interface of the ADC chip defines two ADC data output channels, including a first ADC data output channel and a second ADC data output channel. Each ADC data output channel independently outputs digital signals with the same content but different sequences to the ADC digital interface module.

3. The analog quantity sampling source data error correction and error prevention system according to claim 1 or 2, characterized in that: The error data detection and recovery module includes a data detection unit and a data recovery unit.

4. The analog quantity sampling source data error correction and error prevention system according to claim 3 is characterized in that: The data detection unit is used to detect whether the data output by the first ADC data output channel is the same as the data output by the second ADC data output channel.

5. The analog quantity sampling source data error correction and error prevention system according to claim 3 is characterized in that: The data recovery unit is used to recover erroneous data, output correct data and issue an error alarm.

6. The analog quantity sampling source data error correction and error prevention system according to claim 1, characterized in that: The ADC digital interface module and the error data detection and recovery module can be implemented by FPGA, CPU / MCU / DSP software.

7. The analog quantity sampling source data error correction and error prevention system according to claim 1, characterized in that: The system can also be expanded to connect more than one ADC digital interface module in parallel before an error data detection and recovery module, and each ADC digital interface module is connected to the corresponding ADC chip through two ADC data output channels.

8. A method for correcting and preventing errors in analog quantity sampling source data using the system according to any one of claims 1 to 7, characterized in that: The method comprises the following steps: Step 1: Set the number of sampled data of the ADC chip to N, where N is an even number, and the order of data output by the first ADC data output channel is D1, D2, D3, ..., D N The data output sequence of the second ADC data output channel is D (N / 2) , D (N / 2+1) ,……,D N , D1, D2, ..., D (N / 2-1) ; Step 2: The first ADC data output channel and the second ADC data output channel of the ADC chip output data simultaneously; Step 3: In each sampling cycle, the ADC digital interface module reads two sampling data from the first ADC data output channel of the ADC chip, which are defined as 1A and 1B in the order of reading time; and reads two sampling data from the second ADC data output channel of the ADC chip, which are defined as 2A and 2B in the order of reading time; Step 4: The ADC digital interface module sends the data received from the first ADC data output channel and the second ADC data output channel to the error data detection and recovery module; Step 5: After receiving the data sent by the ADC digital interface module, the error data detection and recovery module performs error detection and recovery processing on the data.

9. The method for error correction and error prevention of analog quantity sampling source data according to claim 8, characterized in that: In step 3, in each sampling period, the ADC digital interface module reads the data output by the ADC data output channel, which can be continuous reading or intermittent reading.

10. The method for error correction and error prevention of analog quantity sampling source data according to claim 8, characterized in that: In step 5, after receiving the data sent by the ADC digital interface module, the error data detection and recovery module performs error detection and recovery processing on the data, including: Step 5.1: The error data detection and recovery module first compares whether 1A and 2A are the same. If they are not the same, it extracts the different data D from 1A. 1a1 , D 1a2 ,……,D 1aM , and extract the corresponding data D in 2A 2a1 , D 2a2、 D 2a3、 ..., go to step 5.2, if the same, go to step 5.5; Step 5.2: Error data detection and recovery module compares D one by one 1a1 , D 1a2 ,……,D 1aM Check whether the data in the time series corresponding to 1B and 2B are the same. If yes, go to step 5.5; if no, go to step 5.3; Step 5.3: Error data detection and recovery module compares D one by one 2a1 , D 2a2 , D 2a3 , ...are the data in the time series corresponding to 1B and 2B the same? If yes, go to step 5.4; otherwise, go to step 5.6; Step 5.4: Error data detection and recovery module uses 2A D 1a1 , D 1a2 ,……,D 1aM Replace the data of 1A detected in step 5.2 to achieve data recovery, and then jump to step 5.2; Step 5.5: The error data detection and recovery module outputs the correct data to the application function module; Step 5.6: The error data detection and recovery module outputs a data error alarm to the application function module.

11. A terminal comprising a processor and a storage medium; characterized in that: The storage medium is used to store instructions; The processor is configured to operate according to the instructions to execute the steps of the method according to any one of claims 8 to 10.

12. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the steps of the method according to any one of claims 8 to 10 are implemented.

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