Sampling hold circuit with amplifier auxiliary type output buffer

Abstract

The invention discloses a sampling and holding circuit with an amplifier-assisted output buffer, and the circuit comprises a sampling circuit which is used for carrying out the sampling and holding processing of an analog input voltage signal, and generating holding signals with different common-mode voltages; the amplifier-assisted output buffer comprises a pull-up and pull-down symmetrical source follower and an amplifier, the grid electrode of the source follower is connected with the output end of the sampling circuit, and the source electrode of the source follower serves as the output end of the sampling hold circuit and is used for outputting hold signals; the input end of the amplifier is connected with the output end of the sampling circuit and the drain electrode of the source follower, and the output end of the amplifier is connected with the drain electrode of the source follower. According to the invention, the structure is simple, the robustness is high, the indexes of high bandwidth and high linearity are excellent, the power consumption is low, the area is small, the DC working point is adjustable, and the like.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a sampling and holding circuit with an amplifier-assisted output buffer. Background Art

[0002] In modern radio applications and next-generation mobile communication systems, low-power, high-sampling-rate (GS / s or more) and medium-to-high-resolution (10-bit or more) analog-to-digital converters (ADCs) are required. Generally speaking, the sampling rate of Flash ADC can easily reach more than 1GS / s, but because the number of comparators in the circuit will increase exponentially with the increase of resolution, it is difficult for its resolution to reach more than 8 bits while maintaining low power consumption; SAR ADC can easily achieve a resolution of more than 8 bits and lower power consumption, but due to the characteristics of its successive approximation algorithm, it is difficult for a single-channel ADC to achieve a high sampling rate while maintaining high resolution; pipeline ADC is similar to SAR ADC, but its pipeline characteristics make it easier to achieve a higher sampling rate in a single channel, but the additional residual amplifier and comparator will also sacrifice power consumption.

[0003] In order to achieve higher speeds, time-interleaved ADCs have gradually become the mainstream structure of high-speed and high-precision ADCs. By interleaving N sub-channel ADCs, an ADC with N times the sampling rate can be obtained at the same resolution, greatly improving the performance indicators of the ADC. However, the load of the multiple channel input nodes interleaved together by the time-interleaved ADC also increases by N times, so the bandwidth of the input end has become one of the main bottlenecks limiting the speed development of the time-interleaved ADC. In order to solve this problem, the input signal is usually sampled and held in the front-end input network, and then the held signal is driven by the signal buffer to drive the sub-ADC, which puts higher requirements on the linearity and bandwidth of the signal buffer.

[0004] Currently, the mainstream design of the signal buffer at the front end of the ADC is mostly an AC-coupled multi-level cascode with a pull-up and pull-down symmetrical source follower. This structure has excellent bandwidth characteristics, but the multi-level cascode used to achieve higher linearity also adds additional voltage margin, and requires different DC voltage bias to ensure proper working conditions. Summary of the invention

[0005] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a sample-and-hold circuit with an amplifier-assisted output buffer to solve the above-mentioned problems.

[0006] According to the present invention, a sample-and-hold circuit with an amplifier-assisted output buffer is provided, comprising:

[0007] A sampling circuit, used for performing sampling and holding processing on an analog input voltage signal to generate holding signals with different common mode voltages;

[0008] An amplifier-assisted output buffer, the amplifier-assisted output buffer includes a pull-up and pull-down symmetrical source follower and an amplifier, wherein the gate of the source follower is connected to the output end of the sampling circuit, and the source of the source follower serves as the output end of the sampling and holding circuit for outputting a holding signal, the input end of the amplifier is connected to the output end of the sampling circuit and the drain of the source follower, and the output end of the amplifier is connected to the drain of the source follower.

[0009] In one embodiment, the sampling circuit generates holding signals with different common mode voltages in a split form and is connected to the bias node of the amplifier for DC biasing. The sampling circuit includes a first sampling switch S 1 The sampling circuit N and the sampling circuit P constitute a differential form, and the first sampling switch S 1 The first end is connected to the analog input voltage signal, and the second end is connected to the sampling circuit N and the sampling circuit P.

[0010] In one embodiment, the sampling circuit N and the sampling circuit P adopt bottom plate sampling or top plate sampling.

[0011] In one embodiment, the sampling circuit N and the sampling circuit P have the same structure and each includes a respective sampling capacitor C s , the second sampling switch S 2N / S 2P and the third sampling switch S 3N / S 3P , sampling capacitor C s The bottom plate and the first sampling switch S 1 The second end of the second switch S 2N / S 2P The second end of the sampling capacitor C s The top plate and the third sampling switch S 3N / S 3P The second end of the second sampling switch S is connected to the gate of the source follower. 2N / S 2P The first end is connected to maintain the common mode voltage V CM1 , the third sampling switch S 3N / S 3P The first end of each sampled common mode voltage V CMN / V CMP .

[0012] In one embodiment, the first sampling switch S 1 The first clock signal φ 1 Control; Second sampling switch S 2N / S 2P The second clock signal φ 2 Control; the third sampling switch S 3N / S 3P The third clock signal φ 1i control.

[0013] In one embodiment, the third clock signal φ 1i With the first clock signal φ 1 The third clock signal φ 1i The falling edge and rising edge of the first clock signal φ 1 Before the falling edge and rising edge of the second clock signal φ 2 With the first clock signal φ 1 Inverted, and the second clock signal φ 2 The falling edge of the first clock signal φ 1 Before the rising edge of the second clock signal φ 2 The rising edge of the first clock signal φ 1 After the falling edge of .

[0014] In one embodiment, the source follower includes a first N-type field effect transistor MN1 and a first P-type field effect transistor MP1; wherein the gates of MN1 and MP1 are respectively connected to the output ends of the sampling circuit N and the sampling circuit P, the drains are respectively connected to the output ends of the amplifier, the sources are connected to each other as the output of the sampling and holding circuit, and the substrate ends and sources of MN1 and MP1 are short-circuited.

[0015] In one embodiment, the amplifier is a multi-stage current multiplexing amplifier, including a first-stage amplifier OPAN / OPAP and a second P-type field effect transistor MP2 / a second N-type field effect transistor MN2 constituting a second-stage amplifier; wherein the inverting input terminal of OPAN is connected to the output terminal of the sampling circuit N, the non-inverting input terminal is connected to the drain of MN1 and the drain of MP2, the output terminal is connected to the gate of MP2, and the source of MP2 is connected to VDD; the non-inverting input terminal of OPAP is connected to the output terminal of the sampling circuit P, the inverting input terminal is connected to the drain of MP1 and the drain of MN2, the output terminal is connected to the gate of MN2, and the source of MN2 is Vss.

[0016] In one embodiment, the OPAN and OPAP use a five-transistor OTA, a common-source amplifier, or a common-source common-gate amplifier.

[0017] In one embodiment, OPAN / OPAP respectively includes four field effect transistors M1-M4 / M5-M8 and respective Miller compensation capacitors Cc and zero adjustment resistors RZ; wherein, the source terminals of M1, M2, M5, and M6 are connected together as the input terminal of the amplifier, the gate of M1 is connected to the drain of MP2, the drain is connected to the drain of M3, the gate of M2 is connected to the output terminal of the sampling circuit N, the drain is connected to the drain of M4, the sources of M3 and M4 are connected to VDD and the gates are interconnected, the drain of M3 is connected to the source, the drain of M4 is connected to MP2, and the gate of M3 is connected to the output terminal of the sampling circuit N. The gate of M5 is connected to the drain of MN2, the drain is connected to the drain of M7, the gate of M6 is connected to the output end of the sampling circuit P, the drain is connected to the drain of M8, the sources of M7 and M8 are connected to VSS and the gates are interconnected, the drain of M7 is connected to the source, and the drain of M8 is connected to the gate of MN2; the zero adjustment resistor RZ and the Miller compensation capacitor Cc of OPAN are connected in series between the drain of M4 and the drain of MP2, and the zero adjustment resistor RZ and the Miller compensation capacitor Cc of OPAP are connected in series between the drain of M8 and the drain of MN2.

[0018] As described above, the present invention feeds forward the output holding signal of the sampling circuit to the drain of the pull-up and pull-down symmetrical source follower through a current multiplexing amplifier, thereby improving its linearity and reducing power consumption while maintaining the high bandwidth advantage of the pull-up and pull-down symmetrical structure of the source follower. In addition, due to the symmetrical structure, the circuit can be designed with short channel field effect transistors, thereby reducing the circuit area. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 is a system block diagram of a sample-and-hold circuit with an amplifier-assisted output buffer according to an embodiment of the present invention;

[0020] Figure 2 is a schematic structural diagram of a sample-and-hold circuit with an amplifier-assisted output buffer according to an embodiment of the present invention;

[0021] Figure 3 yes Figure 2 A circuit diagram of a sampling circuit N and a sampling circuit P of a sample-and-hold circuit in FIG.

[0022] Figure 4 yes Figure 3 The trigger timing diagram of the clock signal of the sampling and holding circuit in FIG.

[0023] Figure 5 yes Figure 2 The circuit diagram of the output buffer with amplifier auxiliary type in ;

[0024] Figure 6 This is the FFT simulation result of the traditional four-channel 800M 16-bit ADC under the condition of input clock mismatch;

[0025] Figure 7 It is a diagram of FFT simulation results of a four-channel 800M 16-bit ADC using the sampling and holding circuit with amplifier-assisted output buffer of the present invention under the condition of input clock mismatch. DETAILED DESCRIPTION

[0026] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0027] It should be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present invention, and thus the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0028] The present invention provides a sample-and-hold circuit with an amplifier-assisted output buffer, which is used to sample an input analog voltage signal and hold it through the output buffer to improve the linearity of a multi-channel ADC in the case of sampling clock mismatch. The present invention will be described in detail below in conjunction with a specific embodiment.

[0029] See also Figure 1 and 2 ,in, Figure 1 A system block diagram of a sample-and-hold circuit with an amplifier-assisted output buffer provided by the present invention is shown; Figure 2 FIG. 2 shows a schematic diagram of the structure of a sample-and-hold circuit with an amplifier-assisted output buffer according to the present invention. Figure 1 and 2As shown, the sampling and holding circuit with amplifier-assisted output buffer includes: a sampling circuit 1 and an amplifier-assisted output buffer 2. The input end of the sampling circuit 1 is connected to the input signal, and is used to perform sampling and holding processing on the input analog signal to generate holding signals with different common-mode voltages, that is, to obtain the analog voltage signal that needs to be quantized. The sampling circuit 1 may include two sampling circuits, namely, an inverting sampling circuit N and a positive sampling circuit P. The sampling circuit generates holding signals with different common-mode voltages in a split form and is connected to the bias node of the amplifier for DC biasing. The input end of the amplifier-assisted output buffer 2 is connected to the output end of the sampling circuit 1, and is used to detect the analog voltage signal that needs to be quantized. The output end of the output buffer is connected to a subsequent quantization circuit (not shown) and outputs a holding signal so that the subsequent quantization circuit performs quantization.

[0030] The amplifier-assisted output buffer 2 may include an inverting amplifier OPAN, a positive amplifier OPAP, two N-type field effect transistors MN1, MN2, and two P-type field effect transistors MP1, MP2. Among them, the inverting amplifier OPAN and the positive amplifier OPAP are first-stage amplifiers, and the P-type field effect transistor MP2 and the N-type field effect transistor MN2 are second-stage amplifiers. The inverting amplifiers OPAN and MP2 constitute a second-stage inverting amplifier mOPAP; the positive amplifiers OPAP and MN2 constitute a second-stage positive amplifier mOPAP. MN1 and MP1 constitute a pull-up and pull-down symmetrical source follower. The input end of the source follower (i.e., the gate of MN1 and MP1) is connected to the output end of the sampling circuit, and the output end of the source follower (i.e., the source of MN1 and MP1) is used to connect to the subsequent quantization circuit to pass the analog voltage signal to be quantized to the subsequent quantization circuit. The inverting input terminal of the amplifier is connected to the input terminal of the source follower, and the non-inverting input terminal is connected to the output terminal and is also connected to the drain terminal of the source follower, so as to detect the analog signal at the input terminal and maintain it at the output terminal.

[0031] See also Figure 3 , which is a schematic diagram of the structure of the sampling circuit N and the sampling circuit P of the present invention. Figure 3 As shown, the sampling circuit includes a first sampling switch S 1 The sampling circuit N and the sampling circuit P constitute a differential form, and the first sampling switch S 1 The first end of is connected to the analog input voltage signal, and the second end is connected to the sampling circuit N and the sampling circuit P. The sampling circuit N and the sampling circuit P can adopt bottom plate sampling, top plate sampling or other composite sampling structures. Specifically, the sampling circuit N and the sampling circuit P have the same structure, and each includes a respective sampling capacitor C s , the second sampling switch S 2N / S 2P and the third sampling switch S3N / S 3P , sampling capacitor C s The bottom plate and the first sampling switch S 1 The second end of the second switch S 2N / S 2P The second end of the sampling capacitor C s The top plate and the third sampling switch S 3N / S 3P The second end of the second sampling switch S is connected to the gate of the source follower. 2N / S 2P The first end is connected to maintain the common mode voltage V CM1 , the third sampling switch S 3N / S 3P The first end of each sampled common mode voltage V CMN / V CMP The first sampling switch S 1 , the second sampling switch S 2N / S 2P and the third sampling switch S 3N / S 3P The first, second and third clock signals φ 1 ,φ 2 and φ 1i control.

[0032] The sampling circuit is divided into sampling state and holding state. In the sampling state, φ 1 =1,φ 2 =0,φ 1i =1, that is, the first sampling switch S 1 and the third sampling switch S 3N / S 3P Close, the second sampling switch S 2N / S 2P Disconnected, at this time, the sampling capacitors C of the sampling circuit N and the sampling circuit P s The bottom plate of the sampling circuit N is connected to the input signal Vip to sample the input signal. At the same time, the sampling capacitor C s The top plate connects the DC level V CMN , the sampling capacitor C of the sampling circuit P s The top plate connects the DC level V CMP , then the charge Q stored on the sampling capacitors of sampling circuits N and P is N and Q P As shown in formula (1) and formula (2).

[0033] Q N =C S ·(V ip -V CMN ) (1)

[0034] Q P =C S ·(V ip -V CMP ) (2)

[0035] In the hold state, φ 1 =0,φ 2 =1,φ 1i =0, that is, the first sampling switch S 1 and the third sampling switch S 3N / S 3P Disconnect, the second sampling switch S 2N / S 2P Closed, the sampling capacitor C of the sampling circuit N and the sampling circuit P s The bottom plate connects the DC level V CM1 , the top plate is disconnected from the DC level, and connected to and drives the amplifier auxiliary output buffer 2. Due to the sampling capacitor C s The charge on the MOSFET does not change, so the positive and negative output signals (i.e., the hold signal) V in the hold state can be obtained through charge conservation. op <n>< / n> and V op，如式(3)和式(4)所示。

[0036] Vop＜N＞＝VCM1-Vip+VCMN (3)

[0037] Vop＜P＞＝VCM1-Vip+VCMP (4)

[0038] 因此可以通过调节VCMN、VCMP和VCM1来得到合适的保持信号Vop <n>< / n>和Vop，从而对放大器辅助型输出缓冲器进行合理的偏置。

[0039] 请参阅图4，示出了本发明中的采样电路的时钟信号的触发时序图。如图4所示，为了保证良好的线性度，时钟信号应满足以下要求：

[0040] (1)在第一采样开关S1导通(即，φ1＝1)前，第三采样开关S3N / S3P已经导通(即，φ1i＝1)且第二采样开关S2N / S2P已经断开(φ2＝0)；

[0041] (2)在第一采样开关S1断开(即，φ1＝0)前，第三采样开关S3N / S3P已经断开(即，φ1i＝0)且第二采样开关S2N / S2P尚未导通(φ2＝0)；

[0042] (3)在CLK_AD变成低电平(即，CLK_AD＝0)前，第三采样开关S3N / S3P尚未导通(即，φ1i＝0)且第二采样开关S2N / S2P尚未断开(即，φ2＝1)；

[0043] 也就是说，第三时钟信号φ1i与第一时钟信号φ1同相位且第三时钟信号φ1i的下降沿和上升沿分别在第一时钟信号φ1的下降沿和上升沿之前；第二时钟信号φ2与第一时钟信号φ1反相，且第二时钟信号φ2的下降沿在第一时钟信号φ1的上升沿之前且第二时钟信号φ2的上升沿在第一时钟信号φ1的下降沿之后；并且CLK_AD的上升沿在第一时钟信号φ1的第一个上升沿之后，下降沿在第二时钟信号φ2的第二个下降沿之前。其中，CLK_AD为ADC采样时钟信号，第二时钟信号φ2的上升沿与CLK_AD的下降沿之间的时间为ADC实际有效的采样时间τs。

[0044] OPAN / OPAP可以采用五管OTA、共源极放大器、共源共栅放大器或其他复合型多级放大器结构以提高增益进而提高输出信号的线性度。具体地，如图2和5所示，放大器OPAN / OPAP分别包括四个场效应晶体管M1～M4 / M5～M8及各自的米勒补偿电容Cc和调零电阻RZ；其中，M1、M2和M5、M6的源端连接在一起作为放大器的输入端，M1的栅极与MP2的漏极连接，漏极与M3的漏极连接，M2的栅极与采样电路N的输出端连接，漏极与M4的漏极连接，M3和M4的源极接VDD且栅极互连，M3的漏极与源极连接，M4的漏极与MP2的栅极连接，M5的栅极与MN2的漏极连接，漏极与M7的漏极连接，M6的栅极与采样电路P的输出端连接，漏极与M8的漏极连接，M7和M8的源极接VSS且栅极互连，M7的漏极与源极连接，M8的漏极与MN2的栅极连接；OPAN的调零电阻RZ和米勒补偿电容Cc串联连接在M4的漏极和MP2的漏极之间，OPAP的调零电阻RZ和米勒补偿电容Cc串联连接在M8的漏极和MN2的漏极之间。

[0045] N型场效应晶体管MN1和P型场效应晶体管MP1构成了上下拉对称结构的源极跟随器，且N型场效应晶体管MN1和P型场效应晶体管MP1的衬底和源极短接在一起作为采样保持电路的输出端Vop；同时N型场效应晶体管MN1和P型场效应晶体管MP1的栅极分别受到前级采样电路N和采样电路P的输出信号驱动。另外，场效应晶体管M1～4和MP2、M5～8和MN2分别构成了二级放大器，并且场效应晶体管M1、M2、M5、M6的源极和衬底连接在一起，形成电流复用的结构，减小放大器的电路功耗和所需偏置电压的数量。其次，两个二级放大器连接成单位增益缓冲器的形式，反相输入端分别连接N型场效应晶体管MN1和P型场效应晶体管MP1的栅极，将前级采样电路的输出信号通过闭环放大器分别前馈到N型场效应晶体管MN1和P型场效应晶体管MP1的漏极，在不影响输出带宽的前提下极大程度上提高了输出缓冲器的线性度。

[0046] 图6示出了传统四通道800M 16bitADC在输入时钟失配的情况下的FFT仿真结果图。如图6所示，在不具有本发明的带放大器辅助型输出缓冲器的采样保持电路的情况下，可实现：SNDR＝64.47dB，SFDR＝69.38dB，ENOB＝10.41bit。

[0047] 图7示出了采用本发明所述带放大器辅助型输出缓冲器的采样保持电路的四通道800M16bitADC在输入时钟失配的情况下的FFT仿真结果图。请参阅图7，在带有本发明所述带放大器辅助型输出缓冲器的采样保持电路的情况下，可实现：SNDR＝71.48dB，SFDR＝85.29dB，ENOB＝11.58bit，对比图6有明显的优化效果。

[0048] 其中，所述SNDR为信号-失真噪声比，SFDR表示无杂散动态范围，ENOB为ADC电路结构的有效位数。

[0049] 综上，本发明的优点是：

[0050] (1)采用上下拉对称型源极跟随器，具有较高的能效比，可以同时具备高带宽和低功耗的优秀性能指标。

[0051] (2)采用闭环放大器来钳制上下拉对称型源极跟随器的漏极电压，充分减小沟道调制效应对源极跟随器的影响，提高了线性度。

[0052] (3)采用电流复用形式的放大器，降低了功耗需求，另外也不需要额外的直流偏置电压。

[0053] (4)整体电路呈现对称型设计，因此电路内场效应晶体管均可采用最小尺寸，减小了电路的面积开销，节约成本。

[0054] 上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims

1. A sample-and-hold circuit with an amplifier-assisted output buffer, characterized in that: include: A sampling circuit, used for performing sampling and holding processing on an analog input voltage signal to generate holding signals with different common mode voltages; An amplifier-assisted output buffer, the amplifier-assisted output buffer includes a pull-up and pull-down symmetrical source follower and an amplifier, wherein the gate of the source follower is connected to the output end of the sampling circuit, and the source of the source follower serves as the output end of the sampling and holding circuit for outputting a holding signal, the input end of the amplifier is connected to the output end of the sampling circuit and the drain of the source follower, and the output end of the amplifier is connected to the drain of the source follower.

2. The sample-and-hold circuit with an amplifier-assisted output buffer according to claim 1, characterized in that: The sampling circuit generates holding signals with different common mode voltages in a split form and is connected to the bias node of the amplifier for DC bias. The sampling circuit includes a first sampling switch S1 and a sampling circuit N and a sampling circuit P in a differential form. The first end of the first sampling switch S1 is connected to the analog input voltage signal, and the second end is connected to the sampling circuit N and the sampling circuit P.

3. The sample-and-hold circuit with an amplifier-assisted output buffer according to claim 2, characterized in that: The sampling circuit N and the sampling circuit P adopt bottom plate sampling or top plate sampling.

4. The sample-and-hold circuit with an amplifier-assisted output buffer according to claim 2, wherein: The sampling circuit N and the sampling circuit P have the same structure and each includes a respective sampling capacitor C s , the second sampling switch S 2N / S 2P and the third sampling switch S 3N / S 3P , sampling capacitor C s The bottom plate is connected to the second end of the first sampling switch S1 and the second sampling switch S 2N / S 2P The second end of the sampling capacitor C s The top plate and the third sampling switch S 3N / S 3P The second end of the second sampling switch S is connected to the gate of the source follower. 2N / S 2P The first end is connected to maintain the common mode voltage V CM1 , the third sampling switch S 3N / S 3P The first end of each sampled common mode voltage V CMN / V CMP .

5. The sample-and-hold circuit with amplifier-assisted output buffer according to claim 3, characterized in that: The first sampling switch S1 is controlled by the first clock signal φ1; the second sampling switch S 2N / S 2P The third sampling switch S is controlled by the second clock signal φ2; 3N / S 3P The third clock signal φ 1i control.

6. The sample-and-hold circuit with an amplifier-assisted output buffer according to claim 4, characterized in that: The third clock signal φ 1i The third clock signal φ is in phase with the first clock signal φ1 and 1i The falling edge and rising edge of the second clock signal φ2 are respectively before the falling edge and rising edge of the first clock signal φ1; the second clock signal φ2 is inverted with the first clock signal φ1, and the falling edge of the second clock signal φ2 is before the rising edge of the first clock signal φ1 and the rising edge of the second clock signal φ2 is after the falling edge of the first clock signal φ1.

7. The sample-and-hold circuit with an amplifier-assisted output buffer according to claim 2, wherein: The source follower includes a first N-type field effect transistor MN1 and a first P-type field effect transistor MP1; wherein the gates of MN1 and MP1 are respectively connected to the output ends of the sampling circuit N and the sampling circuit P, the drains are respectively connected to the output ends of the amplifier, the sources are connected to each other as the output of the sampling and holding circuit, and the substrate ends and sources of MN1 and MP1 are short-circuited.

8. The sample-and-hold circuit with amplifier-assisted output buffer according to claim 6, characterized in that: The amplifier is a multi-stage current multiplexing amplifier, including a first-stage amplifier OPAN / OPAP and a second P-type field effect transistor MP2 and a second N-type field effect transistor MN2 constituting a second-stage amplifier; wherein the inverting input terminal of OPAN is connected to the output terminal of the sampling circuit N, the non-inverting input terminal is connected to the drain of MN1 and the drain of MP2, the output terminal is connected to the gate of MP2, and the source of MP2 is connected to V DD The non-inverting input terminal of OPAP is connected to the output terminal of the sampling circuit P, the inverting input terminal is connected to the drain of MP1 and the drain of MN2, the output terminal is connected to the gate of MN2, and the source of MN2 is connected to Vss.

9. The sample-and-hold circuit with an amplifier-assisted output buffer according to claim 8, characterized in that: OPAN and OPAP use five-transistor OTA, common-source amplifier or common-source common-gate amplifier.

10. The sample-and-hold circuit with amplifier-assisted output buffer according to claim 8, characterized in that: OPAN / OPAP includes four field effect transistors M1~M4 / M5~M8 and their respective Miller compensation capacitors C c and zero adjustment resistor R Z ; Among them, the source terminals of M1, M2, M5 and M6 are connected together as the input terminal of the amplifier, the gate of M1 is connected to the drain of MP2, the drain is connected to the drain of M3, the gate of M2 is connected to the output terminal of the sampling circuit N, the drain is connected to the drain of M4, and the sources of M3 and M4 are connected to V DD The gates are interconnected, the drain of M3 is connected to the source, the drain of M4 is connected to the gate of MP2, the gate of M5 is connected to the drain of MN2, the drain is connected to the drain of M7, the gate of M6 is connected to the output end of the sampling circuit P, the drain is connected to the drain of M8, and the sources of M7 and M8 are connected to V SS The gates are interconnected, the drain of M7 is connected to the source, and the drain of M8 is connected to the gate of MN2; the Miller compensation capacitor C of OPAN c and zero adjustment resistor R Z Connected in series between the drain of M4 and the drain of MP2, the Miller compensation capacitor C of OPAP c and zero adjustment resistor R Z Connected in series between the drain of M8 and the drain of MN2.

Images