Data packet processing method and device, computer equipment and storage medium

Abstract

The invention relates to the technical field of network communication. The invention relates to a data packet processing method and device, computer equipment and a storage medium. Comprising the following steps: acquiring an internal bus transmission control signal, acquiring a QoS scheduling signal from the internal bus transmission control signal, receiving a data packet through an Ethernet interface, processing the data packet to obtain a to-be-processed data packet, transmitting the to-be-processed data packet to a switching engine, determining a forwarding path of the to-be-processed data packet by the switching engine according to the QoS scheduling signal, and transmitting the to-be-processed data packet to the switching engine. And when the to-be-processed data packet is transmitted through the serial port, the exchange engine forwards the to-be-processed data packet to the serial port controller, obtains a serial port communication protocol, converts the to-be-processed data packet into a serial signal through the serial port communication protocol, and sends the serial signal to an external serial port device. The method and the device have the effects of realizing efficient and flexible processing and forwarding of the data packets and meeting different transmission requirements.

Description

Technical Field

[0001] The present invention relates to the technical field of network communications, and in particular to a data packet processing method, device, computer equipment and storage medium. Background Art

[0002] With the rapid development of network communication technology, the importance of packet processing technology in modern communication systems is increasing. Network communication has become a key tool for connecting the world, and efficient processing and forwarding of data packets is the basis for ensuring network performance and user experience. With the widespread application of various communication devices, the flexibility of packet processing and multi-interface compatibility are particularly important.

[0003] In practical applications, traditional packet processing systems use a variety of transmission interfaces, such as serial interfaces (RS-232, RS-485, etc.) and Ethernet interfaces. Although these interfaces perform well in their respective fields, the lack of a unified management and scheduling mechanism when multiple interfaces coexist makes cross-interface forwarding of packets complicated and inefficient. For example, when a packet needs to be forwarded from an Ethernet interface to a serial port, traditional processing systems often need to adopt complex protocol conversion and scheduling strategies, resulting in lengthy processing and low reliability.

[0004] Existing packet processing solutions usually involve the following common methods: the first is a solution based on dedicated hardware, which completes the tasks of receiving, processing and forwarding packets through customized hardware modules; the second is a software-based solution, which implements the management and scheduling of packets through software programs; the third is a hybrid solution, which combines the advantages of hardware and software to improve the overall processing efficiency. However, these solutions still have the following problems when processing communications between multiple interfaces: the priority setting of packets is not flexible enough and cannot be dynamically adjusted between different priorities; the forwarding path of packets lacks an intelligent decision-making mechanism and cannot be flexibly adjusted according to real-time network conditions; the protocol conversion and transmission quality detection of packets between different interfaces are not efficient enough, which can easily lead to data loss or transmission delay.

[0005] Specifically, when traditional packet processing systems process multi-interface transmissions, they often need to manually define the priority of each packet and perform complex protocol conversion and packet reorganization. This approach not only increases the complexity of the system, but may also lead to a decrease in packet processing efficiency and transmission delays. In addition, due to the lack of an intelligent scheduling mechanism, traditional solutions cannot flexibly adjust the forwarding path of data packets according to real-time network conditions. These problems make it difficult for existing packet processing technologies to meet the diverse and complex transmission requirements in practical applications.

[0006] Therefore, how to establish an efficient, flexible and unified data packet processing system that supports efficient communication between multiple interfaces and realizes intelligent scheduling and management of data packets is a technical problem that needs to be solved urgently in the current network communication field. Summary of the invention

[0007] In order to achieve efficient and flexible processing and forwarding of data packets and meet different transmission requirements, the present application provides a data packet processing method, apparatus, computer equipment and storage medium.

[0008] The above-mentioned invention objective of the present application is achieved through the following technical solutions: A data packet processing method, the data packet processing method comprising: Acquire an internal bus transmission control signal, and acquire a QoS scheduling signal from the internal bus transmission control signal; receiving a data packet through an Ethernet interface, processing the data packet to obtain a data packet to be processed, and transmitting the data packet to be processed to a switching engine; The switching engine determines the forwarding path of the data packet to be processed according to the QoS scheduling signal, and when the data packet to be processed is transmitted through the serial port, the switching engine forwards the data packet to be processed to the serial port controller; A serial port communication protocol is obtained, the data packet to be processed is converted into a serial signal through the serial port communication protocol, and the serial signal is sent to an external serial port device.

[0009] By adopting the above technical solution, by integrating the key functions such as the switching engine, serial port controller, and QoS scheduling into a SoC chip, and utilizing advanced semiconductor process technology, high integration and performance optimization are achieved. In this way, complex data processing and forwarding functions can be implemented on a single chip, reducing hardware costs and power consumption. The Ethernet interface is responsible for receiving data packets from external network devices, and performing preliminary parsing and processing to obtain data packets to be processed. This preprocessing can speed up the processing of data packets, reduce the burden on the switching engine, and improve the overall data processing efficiency. The switching engine determines the forwarding path of the data packet based on the QoS scheduling signal, and can dynamically adjust the processing order and forwarding path of the data packet according to the preset priority and flow control strategy. This flexibility enables the system to make intelligent adjustments based on real-time network conditions and service quality requirements, and optimize the efficiency and stability of data transmission. The data packet is converted into a serial signal through the serial communication protocol and sent to the external serial port device, supporting multiple serial port standards (such as RS-232 or RS-485, etc.). This support for multiple transmission methods enables the system to adapt to different types of external devices and communication environments, improving the flexibility and versatility of the system. The internal bus serves as a communication bridge between modules, and the transmission control signal is used to coordinate the sending and receiving of data. This mechanism ensures the coordination between various functional modules and ensures that data packets can be processed and transmitted according to the expected process and priority.

[0010] In a preferred example, the present application may be further configured as follows: the step of obtaining the internal bus transmission control signal and obtaining the QoS scheduling signal from the internal bus transmission control signal specifically further includes: By defining the format and transmission rules of the control signal, the format and transmission rules of the control signal include the structure, priority mark and status information of the data packet; According to the format and transmission rules of the control signal, an inter-module communication mechanism is formulated to obtain the internal bus transmission control signal; The QoS scheduling signal is obtained from the internal bus transmission control signal, and the transmission path and priority of the data packet are determined according to the QoS scheduling signal.

[0011] By adopting the above technical solutions, a unified control signal format and transmission rules are defined, including the structure, priority tag and status information of the data packet. This ensures that the communication and collaboration between different modules are more efficient and consistent, and reduces errors and delays caused by inconsistent communication protocols. By formulating an inter-module communication mechanism based on the defined control signal format and transmission rules, it is ensured that each module can accurately understand and process the control signals from other modules. This standardized communication mechanism simplifies the system design and maintenance process and improves the stability and reliability of the system. By integrating unified control signal definitions, standardized communication mechanisms and dynamic QoS scheduling, the system can achieve efficient and flexible data packet processing and forwarding. Whether it is high-priority real-time data or low-priority large data transmission, the system can process it in the expected manner to ensure the timeliness and reliability of the data.

[0012] In a preferred example, the present application may be further configured as follows: receiving a data packet through an Ethernet interface, processing the data packet to obtain a data packet to be processed, and transmitting the data packet to be processed to a switching engine, specifically including: The Ethernet interface is responsible for physical layer processing, converting the electrical signal into a data packet format and performing preliminary analysis to obtain the data packet to be processed, wherein the data packet to be processed includes information such as a source address, a destination address, and a data length; The data packet to be processed is transmitted to the switching engine.

[0013] By adopting the above technical solution, the switching engine can decide how to process the data packet based on the specific transmission requirements and business rules by preliminarily parsing the data packet information. Different data packets may require different priority processing, different forwarding paths or different QoS scheduling strategies. This flexibility and pertinence can effectively meet diverse transmission requirements. After the processed data packet is transmitted to the switching engine, the further processing and forwarding of the data packet can rely on the internal bus transmission control signal. These signals may include the priority tag of the data packet, the target path information and other status information. Through this information, the data packet can be more finely scheduled and managed, further improving the efficiency of data packet processing and the overall performance of the system.

[0014] In a preferred example, the present application can be further configured as follows: the switching engine determines the forwarding path of the data packet to be processed according to the QoS scheduling signal, and when the data packet to be processed is transmitted through the serial port, the switching engine forwards the data packet to be processed to the serial port controller, specifically including: Parsing the QoS scheduling signal to obtain priority information and target path information; Classifying the data packets into different priority levels according to the priority information, and determining to transmit the data packets to be processed to an output port or a target device according to the target address of the data packets to be processed and the target path information in the QoS scheduling signal; When the data packet to be processed is transmitted through the serial port, the switching engine forwards the data packet to be processed to the serial port controller.

[0015] By adopting the above technical solution, by parsing the QoS scheduling signal to obtain priority information, the data packets to be processed can be divided into different priority levels. This hierarchical processing allows the switching engine to give priority to important data, ensure the timely transmission of key data, and improve the overall efficiency and service quality of the network. Using the target path information in the QoS scheduling signal, the switching engine can accurately determine which output port or target device to transmit the data packet to be processed. This precise path decision can be dynamically adjusted according to factors such as network topology and device status to ensure that the data packet can reach the destination quickly and accurately. When the data packet to be processed needs to be transmitted through the serial port, the switching engine can effectively forward the data packet to the serial port controller. By transmitting the control signal through the internal bus, the sending and receiving of the data packet can be coordinated to avoid data packet loss or overlap, thereby ensuring the stability and reliability of the serial port transmission.

[0016] In a preferred example, the present application may be further configured as follows: when the data packet to be processed is transmitted through the serial port, the switching engine forwards the data packet to be processed to the serial port controller, and further includes: Temporarily storing the data packets to be processed; When the data packet to be processed is transmitted through the serial port, the data packet to be processed is transferred from the cache to a data buffer of the serial port controller, and the data buffer of the serial port controller is used to store the data packet to be processed to be sent; When the data buffer of the serial port controller is full, the switching engine suspends sending the data packets to be processed.

[0017] By adopting the above technical solution, the switching engine can ensure that the data packets will not be lost during the processing process by temporarily storing the data packets to be processed. This temporary storage mechanism can handle concurrent data packet streams, prevent data loss or processing confusion, and thus ensure the integrity and reliability of the data. When the data packets to be processed need to be transmitted through the serial port, the switching engine transfers the data packets from the internal cache to the data buffer of the serial port controller. This management method ensures that the data packets are transmitted in a first-in-first-out order, avoids data packet overlap or loss, and ensures the stability and reliability of serial port transmission. When the data buffer of the serial port controller reaches a full state, the switching engine suspends sending the data packets to be processed. This mechanism can effectively avoid the loss or transmission errors of data packets, and ensure the integrity and reliable transmission process of the data.

[0018] In a preferred example, the present application may be further configured as follows: the obtaining of the serial communication protocol, converting the to-be-processed data packet into a serial signal through the serial communication protocol, and sending the serial signal to an external serial port device specifically includes: The data packet to be processed is encapsulated according to the specification of the serial port communication protocol, a serial port device sending completion signal is obtained, a transmission quality detection is performed on the serial port device sending completion signal, and after passing the detection, it is sent to the external serial port device through the serial port interface.

[0019] By adopting the above technical solution, the data packet is encapsulated according to the serial communication protocol specification to ensure the compatibility and correctness of the data with the external serial port device, thereby effectively transmitting data. By sending a completion signal, it is confirmed that the data packet has been completely transmitted to the external serial port device, which enhances the reliability and integrity of data transmission. The transmission quality detection of the sending completion signal ensures that the transmission quality of the data packet meets the requirements, further improving the stability of the system and the credibility of data transmission.

[0020] In a preferred example, the present application can be further configured as follows: the data packet processing method further includes: Monitor the status of the switch to obtain remote management and monitoring of the switch's operating status and configuration information; According to the remote management and monitoring of the operating status and configuration information of the switch, the abnormal state of the switch is identified, the abnormal state of the switch is adjusted, and a configuration command is sent to modify the configuration of the switch.

[0021] By adopting the above technical solution, the operating status and configuration information of the switch can be obtained in real time through remote management and monitoring. This information includes port usage, data flow, error rate, etc., which helps to detect potential problems and anomalies in a timely manner. Based on the monitored information, the abnormal state of the switch can be identified, such as port congestion, link failure, etc. Timely adjustment of abnormal status can effectively reduce data packet loss and delay, and improve network reliability and stability. By sending configuration commands to modify the configuration of the switch, the forwarding strategy and priority setting of the data packet can be adjusted according to real-time needs. This ensures that the data packet is efficiently processed and forwarded according to different transmission requirements and network conditions, improving network performance.

[0022] The second object of the invention is achieved by the following technical solutions: A data packet processing device, the data packet processing device comprising: A signal acquisition module, used to acquire an internal bus transmission control signal, and acquire a QoS scheduling signal from the internal bus transmission control signal; The data packet processing module is used to receive data packets through the Ethernet interface, process the data packets to obtain data packets to be processed, and transmit the data packets to be processed to the switching engine; A switching engine module, used for the switching engine to determine the forwarding path of the data packet to be processed according to the QoS scheduling signal, and when the data packet to be processed is transmitted through the serial port, the switching engine forwards the data packet to be processed to the serial port controller; The serial port communication module is used to obtain a serial port communication protocol, convert the data packet to be processed into a serial signal through the serial port communication protocol, and send the serial signal to an external serial port device.

[0023] By adopting the above technical solution, by integrating the key functions such as the switching engine, serial port controller, and QoS scheduling into a SoC chip, and utilizing advanced semiconductor process technology, high integration and performance optimization are achieved. In this way, complex data processing and forwarding functions can be implemented on a single chip, reducing hardware costs and power consumption. The Ethernet interface is responsible for receiving data packets from external network devices, and performing preliminary parsing and processing to obtain data packets to be processed. This preprocessing can speed up the processing of data packets, reduce the burden on the switching engine, and improve the overall data processing efficiency. The switching engine determines the forwarding path of the data packet based on the QoS scheduling signal, and can dynamically adjust the processing order and forwarding path of the data packet according to the preset priority and flow control strategy. This flexibility enables the system to make intelligent adjustments based on real-time network conditions and service quality requirements, and optimize the efficiency and stability of data transmission. The data packet is converted into a serial signal through the serial communication protocol and sent to the external serial port device, supporting multiple serial port standards (such as RS-232 or RS-485, etc.). This support for multiple transmission methods enables the system to adapt to different types of external devices and communication environments, improving the flexibility and versatility of the system. The internal bus serves as a communication bridge between modules, and the transmission control signal is used to coordinate the sending and receiving of data. This mechanism ensures the coordination between various functional modules and ensures that data packets can be processed and transmitted according to the expected process and priority.

[0024] The third objective of the present application is achieved through the following technical solutions: A computer device comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the above-mentioned data packet processing method when executing the computer program.

[0025] The fourth objective of the present application is achieved through the following technical solutions: A computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the above-mentioned data packet processing method are implemented.

[0026] In summary, the present application includes at least one of the following beneficial technical effects: 1. By integrating the key functions such as the switching engine, serial port controller, and QoS scheduling into a SoC chip, advanced semiconductor process technology is used to achieve high integration and performance optimization. In this way, complex data processing and forwarding functions can be implemented on a single chip, reducing hardware costs and power consumption. The Ethernet interface is responsible for receiving data packets from external network devices, and performing preliminary parsing and processing to obtain data packets to be processed. This preprocessing can speed up the processing of data packets, reduce the burden on the switching engine, and improve the overall data processing efficiency. The switching engine determines the forwarding path of the data packet based on the QoS scheduling signal, and can dynamically adjust the processing order and forwarding path of the data packet according to the preset priority and flow control strategy. This flexibility enables the system to make intelligent adjustments based on real-time network conditions and service quality requirements, and optimize the efficiency and stability of data transmission. The data packet is converted into a serial signal through the serial communication protocol and sent to the external serial port device, supporting multiple serial port standards (such as RS-232 or RS-485, etc.). This support for multiple transmission methods enables the system to adapt to different types of external devices and communication environments, improving the flexibility and versatility of the system. The internal bus serves as a communication bridge between modules, and the transmission control signal is used to coordinate the sending and receiving of data. This mechanism ensures the coordination between various functional modules and ensures that data packets can be processed and transmitted according to the expected process and priority.

[0027] 2. By parsing the QoS scheduling signal to obtain priority information, the data packets to be processed can be divided into different priority levels. This hierarchical processing allows the switching engine to give priority to important data, ensure the timely transmission of critical data, and improve the overall efficiency and service quality of the network. Using the target path information in the QoS scheduling signal, the switching engine can accurately determine which output port or target device to transmit the data packet to be processed. This precise path decision can be dynamically adjusted based on factors such as network topology and device status to ensure that the data packet can reach its destination quickly and accurately. When the data packet to be processed needs to be transmitted through the serial port, the switching engine can effectively forward the data packet to the serial port controller. By transmitting control signals through the internal bus, the sending and receiving of data packets can be coordinated to avoid data packet loss or overlap, thereby ensuring the stability and reliability of serial port transmission; 3. Through remote management and monitoring, the operating status and configuration information of the switch can be obtained in real time. This information includes port usage, data flow, error rate, etc., which helps to detect potential problems and anomalies in a timely manner. Based on the monitored information, the abnormal state of the switch can be identified, such as port congestion, link failure, etc. Timely adjustment of abnormal status can effectively reduce packet loss and delay, and improve network reliability and stability. By sending configuration commands to modify the configuration of the switch, the forwarding strategy and priority setting of the data packet can be adjusted according to real-time needs. This ensures that the data packet is efficiently processed and forwarded according to different transmission requirements and network conditions, improving network performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a flow chart of a data packet processing method in one embodiment of the present application; Figure 2 This is a flowchart of the implementation of step S10 of the data packet processing method in one embodiment of the present application; Figure 3 This is a flowchart of the implementation of step S20 of the data packet processing method in one embodiment of the present application; Figure 4 This is a flowchart of the implementation of step S30 of the data packet processing method in one embodiment of the present application; Figure 5 This is a flowchart of the implementation of step S33 of the data packet processing method in one embodiment of the present application; Figure 6 This is a flowchart of the implementation of step S40 of the data packet processing method in one embodiment of the present application; Figure 7 This is a flowchart of the data packet processing method after step S40 in an embodiment of the present application; Figure 8 is a principle block diagram of a data packet processing method in one embodiment of the present application; Fig. 9 It is a schematic diagram of a device in an embodiment of the present application. DETAILED DESCRIPTION

[0029] The present application is further described in detail below in conjunction with the accompanying drawings.

[0030] In one embodiment, if Figure 1 As shown, the present application discloses a data packet processing method, which specifically includes the following steps: S10: Acquire an internal bus transmission control signal, and acquire a QoS scheduling signal from the internal bus transmission control signal.

[0031] In this embodiment, the internal bus transmission control signal refers to a signal used when transmitting data and control information through the internal bus. The QoS scheduling signal refers to a group of control signals used to manage and optimize the quality of data packet transmission in network communication and data processing systems.

[0032] Specifically, each module (such as the switching engine, serial port controller, etc.) generates corresponding control signals when it needs to send or receive data. These signals are transmitted through the internal bus. Among them, the control signal includes information such as the source address, the destination address, the data type, the priority, and the bandwidth requirement. When the switching engine receives a data packet, it generates a corresponding QoS scheduling signal according to the predefined QoS policy. The QoS scheduling signal contains information such as priority, bandwidth requirement, and delay sensitivity, which is used to guide subsequent data processing and transmission. The generated control signal and QoS scheduling signal need to be encoded according to the internal bus protocol for transmission on the bus. The encoded control signal is transmitted to the target module, such as the serial port controller, through the internal bus.

[0033] Furthermore, an architecture is adopted to integrate the switching engine, serial port controller, cache management, QoS scheduling, data buffer, and various interfaces and logic circuits into one chip.

[0034] S20: receiving a data packet through the Ethernet interface, processing the data packet to obtain a data packet to be processed, and transmitting the data packet to be processed to the switching engine.

[0035] Specifically, the PHY chip receives the electrical signal from the Ethernet cable through the RJ45 port. The PHY chip converts the received analog electrical signal into a digital signal. The MAC layer receives the digital signal from the PHY chip and reassembles it into a complete Ethernet frame. The MAC layer performs frame detection and error checking (such as CRC checking) to ensure the integrity and correctness of the data frame. If an error frame is detected, the frame is discarded and the error information is recorded. The MAC layer parses the Ethernet frame and extracts the header information such as the destination MAC address, source MAC address and Ethernet type. The type of data frame is identified according to the Ethernet type field, such as IPv4, IPv6 and ARP. Valid data packets are extracted from the parsed Ethernet frame, including IP packets and transport layer data. The data packets are classified, such as IP data packets, ARP data packets, etc. According to the priority information of the data packet (such as determining its priority. The extracted data packets are temporarily stored in the receiving buffer for storing the data packets to be processed. The data packets to be processed are transmitted from the receiving buffer to the switching engine through the internal bus.

[0036] It should be understood that the PHY chip is used to convert the analog electrical signals received from the Ethernet cable into digital signals, and convert the sent digital signals into analog electrical signals for transmission through the cable. The MAC layer is used to ensure the effective transmission of data frames on the local network, manage the order of sending and receiving data frames, and handle conflict detection and avoidance. The receive buffer is used to provide a buffer space to cope with sudden changes in network traffic, ensure the continuity and stability of data processing, and avoid data packet loss.

[0037] S30: The switching engine determines a forwarding path for the data packet to be processed according to the QoS scheduling signal. When the data packet to be processed is transmitted through the serial port, the switching engine forwards the data packet to be processed to the serial port controller.

[0038] Specifically, by receiving a QoS scheduling signal, the information includes priority, bandwidth allocation, and delay requirements. Parse the priority information in the QoS scheduling signal to determine the priority of the data packet to be processed. Parse the bandwidth and delay requirements to ensure that these requirements are followed during the forwarding of the data packet to be processed. The switching engine parses the destination address (such as IP address or MAC address) of the data packet to be processed to determine the forwarding path. Search for a matching forwarding table entry in the forwarding table of the switching engine according to the destination address. Obtain the forwarding path information of the data packet to be processed from the forwarding table entry, including the destination port and interface type (such as Ethernet port or serial port). Determine the processing order and forwarding priority of the data packet to be processed based on the parsed QoS priority information. Ensure that there is sufficient bandwidth available on the forwarding path based on the bandwidth requirements. Select a low-latency forwarding path and interface based on the delay requirements. The data packet to be processed needs to be transmitted through the serial port, and the switching engine forwards the data packet to be processed to the serial port controller. The switching engine transmits the data packet to be processed and related control information (such as the destination serial port, priority, etc.) to the serial port controller through the internal bus.

[0039] Furthermore, if the forwarding path of the data packet to be processed points to the Ethernet port, the switching engine forwards the data packet to the corresponding Ethernet interface through the internal bus.

[0040] S40: Acquire a serial port communication protocol, convert the data packet to be processed into a serial signal through the serial port communication protocol, and send the serial signal to an external serial port device.

[0041] In this embodiment, the serial communication protocol refers to RS-232, RS-485, UART, etc.

[0042] Specifically, the data packets received through the Ethernet interface are first processed and preliminarily parsed at the physical layer by the Ethernet interface logic circuit, and then transmitted to the switching engine. The switching engine determines the forwarding path and priority of the data packet based on the preset forwarding table and QoS scheduling signal. When the data packet needs to be transmitted through the serial port, the switching engine forwards it to the serial port controller. The serial port controller encapsulates the data packet into a data frame according to the serial port communication protocol (such as RS-232, RS-485 or UART), stores it in the transmit buffer, and converts it into a serial signal bit by bit, and sends it to the external serial port device through the TX pin.

[0043] In one embodiment, if Figure 2 As shown, in step S10, the internal bus transmission control signal is obtained, and the QoS scheduling signal is obtained from the internal bus transmission control signal, which specifically includes: S11: By defining the format and transmission rules of the control signal, the format and transmission rules of the control signal include the structure, priority mark and status information of the data packet.

[0044] Specifically, by defining the structure of the data packet, including the start bit, data bit, check bit and stop bit, the integrity of the data frame during transmission is ensured. Secondly, the priority tag field identifies the processing priority of the data packet, and the status information field transmits the current status of the data packet, such as the sending status or receiving status. The transmission of control signals relies on the correct start and stop bits, effectively transmitting the data bits, and using the check bits to detect and correct transmission errors.

[0045] S12: According to the format and transmission rules of the control signal, formulate the inter-module communication mechanism to obtain the internal bus transmission control signal.

[0046] Specifically, establish the structure of the data packet, including the start bit, data bit, check bit, and stop bit, to ensure the accuracy and integrity of data transmission. Secondly, develop a detailed communication protocol to clarify the role of each module in communication and the required control signals, such as priority tags and status information, so as to manage and adjust the data transmission process in real time. Select the appropriate hardware interface and internal bus, such as UART, SPI, or I2C.

[0047] S13: Obtain a QoS scheduling signal from the internal bus transmission control signal, and determine the transmission path and priority of the data packet according to the QoS scheduling signal.

[0048] Specifically, the priority field indicates the priority of the data packet (e.g., high, medium, low). The path field indicates the transmission path of the data packet (e.g., through the Ethernet interface or the serial port interface). The status field indicates the current processing status of the data packet (e.g., received, being processed, sent). The internal bus transmits control signals, which may be transmitted in the form of data frames and contain necessary QoS information. The switching engine generates control signals containing QoS information according to predetermined rules. The control signal is encapsulated into a data frame and sent through the internal bus. The QoS scheduling signal is extracted. Receive data frames: Receive data frames containing QoS information through the internal bus. Parse the data frame and extract the priority field and the path field. Update the processing status of the data packet according to the parsed status field. Determine the processing order of the data packets according to the priority level. High-priority data packets are processed first, and low-priority data packets are processed second. Read the path field to determine the transmission path of the data packet. Determine whether the data packet is forwarded through the Ethernet interface or transmitted through the serial port interface according to the value of the path field. According to the path field, forward the data packet to the corresponding interface module (such as the Ethernet interface or the serial port interface).

[0049] In one embodiment, if Figure 3 As shown, in step S20, a data packet is received through the Ethernet interface, the data packet is processed to obtain a data packet to be processed, and the data packet to be processed is transmitted to the switching engine, which specifically includes: S21: The Ethernet interface is responsible for physical layer processing, converting electrical signals into data packet formats and performing preliminary analysis to obtain data packets to be processed. The data packets to be processed include information such as source address, destination address, and data length.

[0050] Specifically, the PHY chip receives and converts electrical signals into digital signals. Synchronizes and recovers data and clock signals for decoding. The MAC layer receives digital signals and assembles them into Ethernet frames. Parses the Ethernet frame header information and extracts the source address, destination address, and type / length fields. Verifies the integrity of the frame through the frame check sequence. Extracts the source address, destination address, and data length information in the Ethernet frame.

[0051] S22: Transmit the data packet to be processed to the switching engine.

[0052] Specifically, in the process of processing data packets, the Ethernet interface is first responsible for converting the electrical signal of the physical layer into the data packet format, and performing preliminary parsing to extract key information including the source address, destination address and data length. The received data packets are then transmitted to the switching engine.

[0053] In one embodiment, if Figure 4As shown, in step S30, the switching engine determines the forwarding path of the data packet to be processed according to the QoS scheduling signal. When the data packet to be processed is transmitted through the serial port, the switching engine forwards the data packet to be processed to the serial port controller, which specifically includes: S31: Analyze the QoS scheduling signal to obtain priority information and target path information.

[0054] In this embodiment, the priority information refers to the quality of service type, priority tag, flow control information and processing order. The target path information refers to the destination address, forwarding table information, path selection and relay nodes.

[0055] Specifically, the QoS scheduling signal is parsed to obtain the priority information and the target path information.

[0056] S32: Classify the data packets into different priority levels according to the priority information, and decide to transmit the data packets to be processed to the output port or the target device according to the target address of the data packets to be processed and the target path information in the QoS scheduling signal.

[0057] Specifically, according to the priority information in the QoS scheduling signal, a corresponding priority tag is assigned to each received data packet. Including a numerical value or a flag bit, which is used to distinguish the processing priority of the data packet. The received data packet is subjected to target address resolution to determine to which output port or target device the data packet should be transmitted. By looking up the forwarding table or routing table, the next hop or final destination is determined. Using the target path information in the QoS scheduling signal, combined with the result of the target address resolution, it is decided to transmit the data packet to be processed to the output port or target device. Including direct output to the physical port or transmission to the next hop device through the internal bus. According to the path decision, the transmission process of the data packet is controlled.

[0058] S33: When the data packet to be processed is transmitted through the serial port, the switching engine forwards the data packet to be processed to the serial port controller.

[0059] Specifically, the data packet to be processed is taken out of its cache or processing queue. The data packet to be processed is transferred to the data buffer of the serial port controller. This includes copying the content of the data packet to the buffer of the serial port controller, which is achieved through memory copy or DMA operation. The serial port controller is configured to comply with the required serial communication protocol, such as setting parameters such as baud rate, data bit, stop bit, and necessary flow control settings. The serial port controller converts the data packet into a serial signal according to the configured protocol and sends it to the external serial port device through the serial port interface.

[0060] In one embodiment, if Figure 5As shown, in step S33, that is, when the data packet to be processed is transmitted through the serial port, the switching engine forwards the data packet to be processed to the serial port controller, and further includes: S331: Temporarily store the data packets to be processed.

[0061] Specifically, a fixed-size buffer or a dynamically resized data structure is allocated in memory according to the application scenario and system resource limitations.

[0062] S332: When the data packet to be processed is transmitted through the serial port, the data packet to be processed is transferred from the cache to a data buffer of the serial port controller, and the data buffer of the serial port controller is used to store the data packet to be processed to be sent.

[0063] Specifically, when the switching engine decides to transmit a data packet through the serial port, the data packet to be processed is taken out of the cache. The data packet to be processed is copied or moved to the data buffer of the serial port controller. This is achieved through memory copy operations or direct memory access (DMA) to ensure that the content of the data packet is accurately transmitted to the serial port controller. The serial port controller is configured to comply with the required serial port communication protocol and parameters. At the same time, the serial port controller converts the data packet into a serial signal according to the configured protocol and sends it to the external serial port device through the serial port interface.

[0064] S333: When the data buffer of the serial port controller is full, the switching engine suspends sending data packets to be processed.

[0065] Specifically, during the status monitoring process, the free space of the serial port controller data buffer is checked. When it is detected that the serial port controller data buffer is in a full state, the switching engine suspends the sending of subsequent data packets to be processed.

[0066] Furthermore, the state of the data packet is detected by a threshold of free space, and the threshold of free space refers to the minimum amount of unused space reserved in the buffer.

[0067] In one embodiment, if Figure 6 As shown, in step S40, the serial port communication protocol is obtained, the data packet to be processed is converted into a serial signal through the serial port communication protocol, and the serial signal is sent to the external serial port device, which specifically includes: S41: encapsulate the data packet to be processed according to the specification of the serial port communication protocol, obtain the serial port device sending completion signal, perform transmission quality detection on the serial port device sending completion signal, and send it to the external serial port device through the serial port interface after passing the detection.

[0068] Specifically, according to the specification of the serial communication protocol, the data packet to be processed is encapsulated. The data packet header, data field and check part are constructed according to the requirements of the protocol. After the encapsulation is completed, a serial device sending completion signal is generated. Before the sending completion signal is transmitted to the external serial port device, the transmission quality is detected. This includes ensuring the correctness and integrity of the signal and checking whether the communication link is stable. The encapsulated data packet and the sending completion signal are sent to the external serial port device through the serial port interface.

[0069] In one embodiment, if Figure 7 As shown, after step S40, the data packet processing method further includes: S50: Monitor the status of the switch to obtain the operating status and configuration information of the remotely managed and monitored switch.

[0070] In this embodiment, remote management and monitoring of the operating status and configuration information of the switch refers to real-time monitoring of the operating status, configuration management, fault diagnosis and alarm, and remote access control through a network connection.

[0071] Specifically, by configuring a protocol that supports remote access (such as SSH, Telnet, or HTTPS), ensure that the switch is connected to the network and can be accessed through a remote connection tool. The administrator logs in to the switch through the remote connection tool to view and monitor its real-time operating status (such as CPU utilization, interface status, and traffic) and configuration information (such as VLAN settings and routing tables).

[0072] S60: According to the remote management and monitoring of the operation status and configuration information of the switch, an abnormal state of the switch is identified, the abnormal state of the switch is adjusted, and a configuration command is sent to modify the configuration of the switch.

[0073] Specifically, the operating status data of the switch is collected in real time, such as CPU utilization, memory usage, interface status, and traffic conditions. Signal status thresholds are established to identify abnormal conditions, such as high CPU load, abnormal port disconnection, or abnormal traffic. When the monitoring system detects an abnormal state, the alarm mechanism is triggered to notify the administrator. The information is sent to the administrator via email, SMS, or the notification function of the management platform. The administrator connects to the switch management interface through a secure remote access protocol (such as SSH, HTTPS). After the administrator logs in to the switch, he or she views the monitoring data and alarm information and analyzes the causes of the abnormality. Based on the analysis results, it is decided to adjust the configuration of the switch. Modify the port configuration, adjust the VLAN settings, configure the security policy or routing table, etc. At the same time, on the management interface, the administrator enters the corresponding configuration command and makes adjustments through the configuration interface.

[0074] It can be understood that the signal status threshold is used to identify abnormal conditions, such as high CPU load, abnormal port disconnection or abnormal traffic.

[0075] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0076] In one embodiment, a data packet processing device is provided, and the data packet processing device corresponds one-to-one to the data packet processing method in the above embodiment. Figure 8 As shown, the data packet processing device includes a signal acquisition module, a data packet processing module, a switching engine module and a serial port communication module. The detailed description of each functional module is as follows: A signal acquisition module, used to acquire an internal bus transmission control signal, and acquire a QoS scheduling signal from the internal bus transmission control signal; The data packet processing module is used to receive data packets through the Ethernet interface, process the data packets, obtain data packets to be processed, and transmit the data packets to be processed to the switching engine; The switching engine module is used for the switching engine to determine the forwarding path of the data packet to be processed according to the QoS scheduling signal. When the data packet to be processed is transmitted through the serial port, the switching engine forwards the data packet to be processed to the serial port controller; The serial port communication module is used to obtain the serial port communication protocol, convert the data packet to be processed into a serial signal through the serial port communication protocol, and send the serial signal to an external serial port device.

[0077] Optionally, the signal acquisition module includes: A rule-making submodule, used for defining the format and transmission rules of the control signal, wherein the format and transmission rules of the control signal include the structure, priority mark and status information of the data packet; The bus control submodule is used to formulate the inter-module communication mechanism according to the format and transmission rules of the control signal and obtain the internal bus transmission control signal; The QoS scheduling submodule is used to obtain the QoS scheduling signal from the internal bus transmission control signal and determine the transmission path and priority of the data packet according to the QoS scheduling signal.

[0078] Optionally, the data packet processing module includes: The signal conversion submodule, the Ethernet interface is responsible for physical layer processing, converting the electrical signal into a data packet format and performing preliminary analysis to obtain the data packet to be processed. The data packet to be processed includes information such as the source address, destination address, and data length; The transmission submodule is used to transmit the data packets to be processed to the switching engine.

[0079] Optionally, the switching engine module includes: The parsing submodule is used to parse the QoS scheduling signal to obtain priority information and target path information; A transmission submodule, used for classifying data packets into different priority levels according to the priority information, and determining to transmit the data packets to be processed to an output port or a target device according to the target address of the data packets to be processed and the target path information in the QoS scheduling signal; The serial port submodule is used for the switching engine to forward the data packets to be processed to the serial port controller when the data packets to be processed are transmitted through the serial port.

[0080] Optional, serial port submodules include: A storage unit, used for temporarily storing data packets to be processed; A sending unit, used for transferring the data packets to be processed from the cache to the data buffer of the serial port controller when the data packets to be processed are transmitted through the serial port, and the data buffer of the serial port controller is used for storing the data packets to be processed to be sent; The sending pause unit is used for causing the switching engine to pause sending data packets to be processed when the data buffer of the serial port controller is full.

[0081] Optionally, the serial communication module includes: The serial port sending submodule is used to encapsulate the data packets to be processed according to the specifications of the serial port communication protocol, obtain the serial port device sending completion signal, perform transmission quality detection on the serial port device sending completion signal, and send it to the external serial port device through the serial port interface after passing the detection.

[0082] Optionally, the serial communication module also includes: The monitoring module is used to monitor the status of the switch, obtain the operating status and configuration information of the remote management and monitoring switch; The command module is used to remotely manage and monitor the operating status and configuration information of the switch, identify the abnormal status of the switch, adjust the abnormal status of the switch, and send configuration commands to modify the configuration of the switch.

[0083] For the specific definition of the data packet processing device, please refer to the definition of the data packet processing method above, which will not be repeated here. Each module in the above-mentioned data packet processing device can be implemented in whole or in part by software, hardware and a combination thereof. The above-mentioned modules can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory of the computer device in the form of software, so that the processor can call and execute the operations corresponding to the above modules.

[0084] In one embodiment, a computer device is provided. The computer device may be a server, and its internal structure diagram may be as follows: Fig. 9 As shown. The computer device includes a processor, a memory, a network interface and a database connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used for data packet processing database. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a data packet processing method is implemented.

[0085] In one embodiment, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the following steps when executing the computer program: Obtaining an internal bus transmission control signal, and obtaining a QoS scheduling signal from the internal bus transmission control signal; receiving data packets through an Ethernet interface, processing the data packets to obtain data packets to be processed, and transmitting the data packets to be processed to a switching engine; The switching engine determines the forwarding path of the data packet to be processed according to the QoS scheduling signal. When the data packet to be processed is transmitted through the serial port, the switching engine forwards the data packet to be processed to the serial port controller; Obtain the serial port communication protocol, convert the data packet to be processed into a serial signal through the serial port communication protocol, and send the serial signal to the external serial port device.

[0086] In one embodiment, a computer readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the following steps are implemented: Obtaining an internal bus transmission control signal, and obtaining a QoS scheduling signal from the internal bus transmission control signal; receiving data packets through an Ethernet interface, processing the data packets to obtain data packets to be processed, and transmitting the data packets to be processed to a switching engine; The switching engine determines the forwarding path of the data packet to be processed according to the QoS scheduling signal. When the data packet to be processed is transmitted through the serial port, the switching engine forwards the data packet to be processed to the serial port controller; Obtain the serial port communication protocol, convert the data packet to be processed into a serial signal through the serial port communication protocol, and send the serial signal to the external serial port device.

[0087] Those of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be implemented by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application may include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0088] Those skilled in the art can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example. In actual applications, the above-mentioned functions can be distributed and completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.

[0089] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A data packet processing method, characterized in that: The data packet processing method comprises: Acquire an internal bus transmission control signal, and acquire a QoS scheduling signal from the internal bus transmission control signal; receiving a data packet through an Ethernet interface, processing the data packet to obtain a data packet to be processed, and transmitting the data packet to be processed to a switching engine; The switching engine obtains a forwarding path of the data packet to be processed according to the QoS scheduling signal, and when the data packet to be processed is transmitted through the serial port, the switching engine forwards the data packet to be processed to the serial port controller; A serial port communication protocol is obtained, the data packet to be processed is converted into a serial signal through the serial port communication protocol, and the serial signal is sent to an external serial port device.

2. The data packet processing method according to claim 1, characterized in that: The obtaining of the internal bus transmission control signal and obtaining the QoS scheduling signal from the internal bus transmission control signal specifically includes: By defining the format and transmission rules of the control signal, the format and transmission rules of the control signal include the structure, priority mark and status information of the data packet; Generate an inter-module communication mechanism according to the format and transmission rule of the control signal, and obtain the internal bus transmission control signal according to the communication mechanism; The QoS scheduling signal is obtained from the internal bus transmission control signal, and the transmission path and priority of the data packet are determined according to the QoS scheduling signal.

3. The data packet processing method according to claim 1, characterized in that: The receiving of a data packet through an Ethernet interface, processing the data packet to obtain a data packet to be processed, and transmitting the data packet to be processed to a switching engine specifically includes: The Ethernet interface is responsible for physical layer processing, converting the electrical signal into a data packet format and performing preliminary analysis to obtain the data packet to be processed, wherein the data packet to be processed includes a source address, a destination address and data length information; The data packet to be processed is transmitted to the switching engine.

4. The data packet processing method according to claim 1, characterized in that: The switching engine determines the forwarding path of the data packet to be processed according to the QoS scheduling signal, and when the data packet to be processed is transmitted through the serial port, the switching engine forwards the data packet to be processed to the serial port controller, specifically including: Parsing the QoS scheduling signal to obtain priority information and target path information; Classifying the data packets into different priority levels according to the priority information, and determining to transmit the data packets to be processed to an output port or a target device according to the target address of the data packets to be processed and the target path information in the QoS scheduling signal; When the data packet to be processed is transmitted through the serial port, the switching engine forwards the data packet to be processed to the serial port controller.

5. The data packet processing method according to claim 4, characterized in that: When the data packet to be processed is transmitted through the serial port, the switching engine forwards the data packet to be processed to the serial port controller, further comprising: Temporarily storing the data packets to be processed; When the data packet to be processed is transmitted through the serial port, the data packet to be processed is transferred from the cache to a data buffer of the serial port controller, and the data buffer of the serial port controller is used to store the data packet to be processed to be sent; When the data buffer of the serial port controller is full, the switching engine suspends sending the data packets to be processed.

6. The data packet processing method according to claim 1, characterized in that: The obtaining of the serial communication protocol, converting the to-be-processed data packet into a serial signal through the serial communication protocol, and sending the serial signal to an external serial port device specifically includes: The data packet to be processed is encapsulated according to the specification of the serial port communication protocol, a serial port device sending completion signal is obtained, a transmission quality detection is performed on the serial port device sending completion signal, and after obtaining the detection qualified signal, it is sent to the external serial port device through the serial port interface.

7. The data packet processing method according to claim 1, characterized in that: The data packet processing method further includes: Monitor the status of the switch to obtain remote management and monitoring of the switch's operating status and configuration information; According to the remote management and monitoring of the operating status and configuration information of the switch, the abnormal state of the switch is identified, the abnormal state of the switch is adjusted, and a configuration command is sent to modify the configuration of the switch.

8. A data packet processing device, characterized in that: The data packet processing device comprises: A signal acquisition module, used to acquire an internal bus transmission control signal, and acquire a QoS scheduling signal from the internal bus transmission control signal; The data packet processing module is used to receive data packets through the Ethernet interface, process the data packets to obtain data packets to be processed, and transmit the data packets to be processed to the switching engine; A switching engine module, used for the switching engine to determine the forwarding path of the data packet to be processed according to the QoS scheduling signal, and when the data packet to be processed is transmitted through the serial port, the switching engine forwards the data packet to be processed to the serial port controller; The serial port communication module is used to obtain a serial port communication protocol, convert the data packet to be processed into a serial signal through the serial port communication protocol, and send the serial signal to an external serial port device.

9. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the data packet processing method according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the steps of the data packet processing method according to any one of claims 1 to 7 are implemented.

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