System and method for verifying agent receiving module with SPC in chip

Abstract

The invention relates to a system and a method for verifying a current receiving module with an SPC in a chip, and the system comprises the steps: constructing a new verification system composed of an SPC controller, a current transmitting assembly, a to-be-tested design and two buf1 assemblies, and controlling a signal path between the SPC controller and a microcontroller, and a signal path between the current transmitting assembly and the microcontroller through the two buf1 assemblies, thereby achieving the verification of the current receiving module with the SPC in the chip. In the EDA verification stage, the current receiving module with the SPC function can be verified, so that the verification of the current receiving module with the SPC function does not need to be realized at a hardware level. Meanwhile, the verification technology can be well compatible with other existing whole chip verification platforms and a traditional tent receiving module verification platform, has good flexibility and reusability, and can greatly improve the verification efficiency.

Description

Technical Field

[0001] The invention belongs to the technical field of chip verification, and relates to a sent receiving module verification system and method with SPC in a chip. Background Art

[0002] The SENT (single edge nibble transmission) protocol is a single-wire data transmission protocol. The interface of this protocol is widely used in sensors in automobiles, and the SPC (short pwm code) function is an enhanced version of the SENT protocol of the SAE 2716 standard. The traditional SENT protocol is simplex communication, which only supports sensors sending data to microcontrollers (MCUs). The addition of the SPC function enables the microcontroller to send signals to the sensors, allowing the two to achieve half-duplex communication. The SENT receiving module in the microcontroller has only one data line for the data connection with the external sensor, which is a pad (i.e., the input / output part) of the chip.

[0003] The verification of the sent receiving module with SPC function requires simulating the sensor input stimulus, and also capturing the pulses generated by the sent receiving module to control the stimulus input. The verification of the SPC function can be verified using real sensors, but this verification method with the help of hardware reduces the flexibility of verification and requires the use of FPGA chips to build microcontroller chips, which undoubtedly increases the complexity of verification. Therefore, it is necessary to develop a low-cost and flexible verification method for the sent receiving module with SPC function. Summary of the invention

[0004] In view of the problems existing in the above-mentioned traditional technologies, the present invention proposes a sent receiving module verification system with SPC in a chip and a sent receiving module verification method with SPC in a chip, which can realize the verification of the sent receiving module with SPC function in a low-cost and flexible manner.

[0005] In order to achieve the above objectives, the embodiments of the present invention adopt the following technical solutions:

[0006] On the one hand, a sent receiving module verification system with SPC in a chip is provided, comprising an SPC controller, a sent sending component, a design to be tested and two buf1 components, wherein the SPC controller and the sent sending component are components instantiated after the test case base class configuration based on the UVM verification platform, and the design to be tested is a sent receiving module with SPC function to be verified in a microcontroller;

[0007] The SPC controller is connected to the sent sending component, and the SPC controller is connected to the pad of the microcontroller through a buf1 component. A buf1 component is used to connect or disconnect the SPC function trigger signal transmitted from the microcontroller to the SPC controller under the control of the SPC function trigger enable signal; the sent sending component is connected to the pad of the microcontroller through another buf1 component. Another buf1 component is used to connect or disconnect the sent input signal transmitted from the sent sending component to the microcontroller under the control of the sent input enable signal.

[0008] On the other hand, a sent receiving module verification method with SPC in a chip is also provided, which is applied to a sent receiving module verification system with SPC in a chip, wherein the sent receiving module verification system comprises an SPC controller, a sent sending component, a design to be tested and two buf1 components, wherein the SPC controller and the sent sending component are components instantiated after the test case base class configuration based on the UVM verification platform, and the design to be tested is a sent receiving module with SPC function to be verified in a microcontroller;

[0009] The SPC controller is connected to the sent sending component, and the SPC controller is connected to the pad of the microcontroller through a buf1 component. The buf1 component is used to connect or disconnect the SPC function trigger signal transmitted from the microcontroller to the SPC controller under the control of the SPC function trigger enable signal; the sent sending component is connected to the pad of the microcontroller through another buf1 component. The other buf1 component is used to connect or disconnect the sent input signal transmitted from the sent sending component to the microcontroller under the control of the sent input enable signal;

[0010] The verification method of the sent receiving module with SPC in the above chip includes the following steps:

[0011] Generate an SPC function trigger signal through the microcontroller;

[0012] Switch the SPC function trigger enable signal to valid and the sent input enable signal to invalid, open the path of one buf1 component and close the path of another buf1 component;

[0013] After receiving the correct SPC function trigger signal, the SPC controller switches the sent input enable signal to valid and switches the SPC function trigger enable signal to invalid;

[0014] The sent sending component starts sending stimulus data of the sent protocol to the pad of the microcontroller;

[0015] After the sent component finishes sending the stimulus data, the SPC function trigger enable signal is switched to valid again and the sent input enable signal is switched to invalid;

[0016] Configure the microcontroller to read the data from the sent receiving module and generate the next SPC function trigger signal after comparison.

[0017] In one embodiment, when verifying the sent receiving module with the SPC function turned off, the SPC function trigger enable signal is configured to be always invalid, and the sent input enable signal is configured to be always valid.

[0018] In one embodiment, the SPC function trigger enable signal is valid at a high level, and the sent input enable signal is valid at a high level.

[0019] One of the above technical solutions has the following advantages and beneficial effects:

[0020] The sent receiving module verification system and method with SPC in the above chip constructs a new verification system consisting of an SPC controller, a sent sending component, a design to be tested and two buf1 components, and uses the two buf1 components to respectively control the signal path between the SPC controller and the microcontroller, and the signal path between the sent sending component and the microcontroller, thereby achieving half-duplex communication with the sent sending component on a pad of a microcontroller through different enable control signals, thereby realizing the verification of the sent receiving module with SPC function in a low-cost and flexible manner.

[0021] Compared with traditional technologies, the above solution can verify the sent receiving module with SPC function in the EDA verification stage, so that the verification of the sent receiving module with SPC function does not need to be implemented at the hardware level. At the same time, this verification technology can be well compatible with other existing whole chip verification platforms and traditional sent receiving module verification platforms, has good flexibility and reusability, and can greatly improve verification efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0023] Figure 1 It is a structural block diagram of a sent receiving module verification system with SPC in a chip in one embodiment;

[0024] Figure 2 A flowchart of a verification implementation example of a sent receiving module verification system with SPC in a chip in an embodiment;

[0025] Figure 3 The figure is a flowchart of a method for verifying a sent receiving module with SPC in a chip in one embodiment. DETAILED DESCRIPTION

[0026] In order to make the purpose, technical scheme and advantages of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and Examples. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by those skilled in the art of the present invention. The terms used in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0027] It should be noted that the reference to "embodiment" in this article means that the specific features, structures or characteristics described in conjunction with the embodiment may be included in at least one embodiment of the present invention. The presentation of this phrase at various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It will be appreciated by those skilled in the art that the embodiments described herein may be combined with other embodiments. The term "and / or" used in the specification of the present invention and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes these combinations.

[0028] The following will describe the implementation of the present invention in detail with reference to the accompanying drawings in the embodiment diagram of the present invention.

[0029] In one embodiment, Figure 1As shown, a sent receiving module verification system with SPC in a chip is provided, including an SPC controller, a sent sending component, a design to be tested and two buf1 components. The SPC controller and the sent sending component are components instantiated after the configuration of the test case base class (i.e., sent_base_test) based on the UVM verification platform. The design to be tested is a sent receiving module with SPC function to be verified in a microcontroller. The SPC controller and the sent sending component are connected, and the SPC controller is connected to the pad of the microcontroller through a buf1 component, and a buf1 component is used to connect or disconnect the SPC function trigger signal transmitted from the microcontroller to the SPC controller under the control of the SPC function trigger enable signal. The sent sending component is connected to the pad of the microcontroller through another buf1 component, and the other buf1 component is used to connect or disconnect the sent input signal transmitted from the sent sending component to the microcontroller under the control of the sent input enable signal.

[0030] It can be understood that a sent receiving module verification system with SPC in the chip can be built during the EDA (electronic design automation) verification stage to verify the sent receiving module with SPC function. At the same time, the new system can also be compatible with the traditional sent receiving module verification platform.

[0031] A buf1 component is added between the microcontroller and the sent (data) sending component. The function of the buf1 component is: when the sent input enable signal sent_in_en is controlled to be valid (such as high level 1, in some embodiments, the signal can also be valid when the low level 0 is used), the two ends of the buf1 component are connected, that is, the sent input signal sent_in_0 and the sent input signal sent_in_1 are connected. If the sent input enable signal sent_in_en is controlled to be invalid (such as low level 0, in some embodiments, the signal can also be valid when the high level 1 is used), the sent input signal sent_in_1 and the sent input signal sent_in_0 are disconnected, that is, the pad of the microcontroller and the SPC function trigger signal spc_trig_0 cannot be affected. Among them, the buf1 component refers to bufif1 (i.e., a three-state logic gate) represented in Verilog (a hardware description language used to describe digital circuits and systems). bufif1 is a standard unit of the Verilog language, and the logical relationship between its input i, output o and enable en is: when enable en=1, output o=input i, that is, the input and output are connected; when enable en=0, output o is high impedance, that is, the input and output are disconnected.

[0032] Similarly, another buf1 component is added between the microcontroller and the SPC controller. When the SPC function trigger enable signal spc_trig_en is controlled to be valid (such as high level 1, in some embodiments, the signal is valid when the low level 0 is adopted), the value of the SPC function trigger signal spc_trig_1 is equal to the value of the SPC function trigger signal spc_trig_0, that is, the value on the pad of the microcontroller. If the SPC function trigger enable signal spc_trig_en is controlled to be invalid (such as low level 0, in some embodiments, the signal is valid when the high level 1 is adopted), the SPC function trigger signal spc_trig_0 and the SPC function trigger signal spc_trig_1 are disconnected, that is, the value on the pad of the microcontroller and the value of the sent input signal sent_in_1 cannot affect the SPC function trigger signal spc_trig_1.

[0033] By using two buf1 components and different control signals, half-duplex communication is achieved between the microcontroller and the sent component on a pad of the microcontroller. Figure 2 As shown, when the microcontroller inputs an SPC function trigger signal spc_trig, that is, notifies the sensor (here equivalent to the sent sending component, that is, sent_in_driver), the SPC controller in the verification system controls the SPC function trigger enable signal spc_trig_en to 0, closes the path of the SPC function trigger signal spc_trig; controls the sent input enable signal sent_in_en to 1, and opens the path of the sent input signal sent_in. Then let the sent sending component (sent_in_driver) send the stimulus data of the sent protocol to the pad of the microcontroller. After the stimulus data is sent, the SPC controller opens the path of the SPC function trigger signal spc_trig again and closes the path of the sent input signal sent_in. At the same time, after reading the data of the sent receiving module, let the microcontroller send another sent trigger input signal sent_trig_in, let it generate the next SPC function trigger signal spc_trig, and prepare for the next stimulus data transmission, and so on and so forth, until the last stimulus data transmission is completed and the verification is completed, the cycle ends, and the verification ends.

[0034] The sent receiving module verification system with SPC in the above chip constructs a new verification system consisting of an SPC controller, a sent sending component, a design to be tested and two buf1 components. The two buf1 components are used to control the signal path between the SPC controller and the microcontroller, and the signal path between the sent sending component and the microcontroller respectively, so as to achieve half-duplex communication with the sent sending component on a pad of a microcontroller through different enable control signals, thereby realizing the verification of the sent receiving module with SPC function in a low-cost and flexible manner.

[0035] Compared with traditional technologies, the above solution can verify the sent receiving module with SPC function in the EDA verification stage, so that the verification of the sent receiving module with SPC function does not need to be implemented at the hardware level. At the same time, this verification technology can be well compatible with other existing whole chip verification platforms and traditional sent receiving module verification platforms, has good flexibility and reusability, and can greatly improve verification efficiency.

[0036] It can be understood that the designs of the SPC controller and the sent sending components in the sent receiving module verification system with SPC in the above-mentioned chip all follow the existing UVM verification methodology, according to the verification needs of the sent receiving module with SPC function (for example, based on the inherent functions of the entity's SPC controller and the sending circuit of the sent protocol data), the test case base class based on the UVM verification platform (base_test can be recorded as sent_base_test when applied to the verification of the sent receiving module) performs component configuration and instantiation of the corresponding functions and completes the connection between the components, connectivity testing and other basic operations to ensure that the data flow between the components is normal during the verification process.

[0037] In one embodiment, when verifying the sent receiving module with the SPC function turned off, the SPC function trigger enable signal is configured to be always invalid, and the sent input enable signal is configured to be always valid.

[0038] It can be understood that when it is necessary to verify the sent function with the SPC function turned off, it is only necessary to skip the SPC controller waiting for the command to trigger trig, and at the same time control the SPC function trigger enable signal spc_trig_en to always be 0, and control the input enable signal sent_in_en to always be 1, so as to achieve compatibility with the traditional sent receiving module verification platform without the SPC function.

[0039] In one embodiment, the SPC function trigger enable signal is valid at a high level, and the sent input enable signal is valid at a high level.

[0040] It can be understood that in this embodiment, when the SPC function trigger enable signal spc_trig_en is configured to be high level 1, it is effective, and the corresponding buf1 component connects the signals at both ends of its input and output under the control of this signal; accordingly, when the sent input enable signal sent_in_en is configured to be high level 1, it is effective, and the corresponding other buf1 component connects the signals at both ends of its input and output under the control of this signal. Since this configuration is more commonly used, the levels of the aforementioned signals can be configured in the system by default configuration, thereby enabling control more conveniently and quickly.

[0041] Each component in the sent receiving module verification system with SPC in the above chip can be fully or partially implemented by software, hardware and their combination. The above components can be embedded in or independent of a device with data processing function in hardware form, or can be stored in the memory of the above device in software form, so that the processor can call and execute the operations corresponding to the above modules. The above device can be but not limited to various types of chip verification computers available in the art.

[0042] In one embodiment, a sent receiving module verification method with SPC in a chip is provided, which is applied to a sent receiving module verification system with SPC in a chip, and the sent receiving module verification system includes an SPC controller, a sent sending component, a design to be tested, and two buf1 components. The SPC controller and the sent sending component are components instantiated after the test case base class configuration based on the UVM verification platform. The design to be tested is a sent receiving module with SPC function to be verified in a microcontroller. The SPC controller and the sent sending component are connected, and the SPC controller is connected to the pad of the microcontroller through a buf1 component. A buf1 component is used to connect or disconnect the SPC function trigger signal transmitted from the microcontroller to the SPC controller under the control of the SPC function trigger enable signal. The sent sending component is connected to the pad of the microcontroller through another buf1 component, and the other buf1 component is used to connect or disconnect the sent input signal transmitted from the sent sending component to the microcontroller under the control of the sent input enable signal.

[0043] like Figure 3 As shown, the sent receiving module verification method with SPC in the above chip may include the following processing steps S10 to S20:

[0044] S10, generating an SPC function trigger signal through the microcontroller;

[0045] S12, switching the SPC function trigger enable signal to valid and switching the sent input enable signal to invalid, opening a path of a buf1 component and closing a path of another buf1 component;

[0046] S14, after receiving the correct SPC function trigger signal, the SPC controller switches the sent input enable signal to valid and switches the SPC function trigger enable signal to invalid;

[0047] S16, the sent component starts sending the stimulus data of the sent protocol to the pad of the microcontroller;

[0048] S18, after the sent sending component finishes sending the stimulus data, the SPC function trigger enable signal is switched to valid again and the sent input enable signal is switched to invalid;

[0049] S20, configure the microcontroller to read the data of the sent receiving module and generate the next SPC function trigger signal after comparison.

[0050] The verification method of the sent receiving module with SPC in the above chip constructs a new verification system consisting of an SPC controller, a sent sending component, a design to be tested and two buf1 components, and uses the two buf1 components to respectively control the signal path between the SPC controller and the microcontroller, and the signal path between the sent sending component and the microcontroller, so as to achieve half-duplex communication with the sent sending component on a pad of a microcontroller through different enable control signals, thereby realizing the verification of the sent receiving module with SPC function in a low-cost and flexible manner.

[0051] Compared with traditional technologies, the above solution can verify the sent receiving module with SPC function in the EDA verification stage, so that the verification of the sent receiving module with SPC function does not need to be implemented at the hardware level. At the same time, this verification technology can be well compatible with other existing whole chip verification platforms and traditional sent receiving module verification platforms, has good flexibility and reusability, and can greatly improve verification efficiency.

[0052] In one embodiment, when verifying the sent receiving module with the SPC function turned off, the SPC function trigger enable signal is configured to be always invalid, and the sent input enable signal is configured to be always valid.

[0053] In one embodiment, the SPC function trigger enable signal is valid at a high level, and the sent input enable signal is valid at a high level.

[0054] For the specific limitations of the verification method of the sent receiving module with SPC in the chip, please refer to the corresponding limitations of the verification system of the sent receiving module with SPC in the chip above, which will not be repeated here.

[0055] It should be understood that although Figure 2 and Figure 3 The steps in the method are shown in sequence as indicated by the arrows, but the steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of the steps, and the steps can be executed in other orders. Figure 2 and Figure 3 At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequentially, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0056] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided by the present invention can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus dynamic random access memory (RambusDRAM, referred to as RDRAM) and interface dynamic random access memory (DRDRAM).

[0057] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0058] The above embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of protection of the invention. It should be pointed out that, for those of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present invention, which all belong to the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be subject to the attached claims.

Claims

1. A sent receiving module verification system with SPC in a chip, characterized in that: It includes an SPC controller, a sent sending component, a design to be tested and two buf1 components, wherein the SPC controller and the sent sending component are components instantiated after the test case base class configuration based on the UVM verification platform, and the design to be tested is a sent receiving module with an SPC function to be verified in a microcontroller; The SPC controller is connected to the sent sending component, and the SPC controller is connected to the pad of the microcontroller through a buf1 component, and one buf1 component is used to connect or disconnect the SPC function trigger signal transmitted from the microcontroller to the SPC controller under the control of the SPC function trigger enable signal; the sent sending component is connected to the pad of the microcontroller through another buf1 component, and the other buf1 component is used to connect or disconnect the sent input signal transmitted from the sent sending component to the microcontroller under the control of the sent input enable signal.

2. The sent receiving module verification system with SPC in a chip according to claim 1, characterized in that: When verifying the sent receiving module with the SPC function turned off, the SPC function trigger enable signal is configured to be always invalid, and the sent input enable signal is configured to be always valid.

3. The sent receiving module verification system with SPC in a chip according to claim 1 or 2, characterized in that: The SPC function trigger enable signal is valid at a high level, and the sent input enable signal is valid at a high level.

4. A sent receiving module verification method with SPC in a chip, characterized in that: The invention is applied to a sent receiving module verification system with SPC in a chip, the sent receiving module verification system comprises an SPC controller, a sent sending component, a design to be tested and two buf1 components, the SPC controller and the sent sending component are components instantiated after the test case base class configuration based on the UVM verification platform, and the design to be tested is a sent receiving module with SPC function to be verified in a microcontroller; The SPC controller is connected to the sent sending component, the SPC controller is connected to the pad of the microcontroller through one of the buf1 components, and one of the buf1 components is used to connect or disconnect the SPC function trigger signal transmitted from the microcontroller to the SPC controller under the control of the SPC function trigger enable signal; the sent sending component is connected to the pad of the microcontroller through another of the buf1 components, and another of the buf1 components is used to connect or disconnect the sent input signal transmitted from the sent sending component to the microcontroller under the control of the sent input enable signal; The sent receiving module verification method with SPC in the chip comprises the steps of: Generate an SPC function trigger signal by the microcontroller; Switching the SPC function trigger enable signal to valid and switching the sent input enable signal to invalid, opening a path of the buf1 component and closing a path of another buf1 component; After receiving the correct SPC function trigger signal, the SPC controller switches the sent input enable signal to valid and switches the SPC function trigger enable signal to invalid; The sent sending component starts sending the stimulus data of the sent protocol to the pad of the microcontroller; After the sent sending component finishes sending the stimulus data, the SPC function trigger enable signal is switched to valid again and the sent input enable signal is switched to invalid; The microcontroller is configured to read the data of the sent receiving module and generate the next SPC function trigger signal after comparison.

5. The sent receiving module verification method with SPC in a chip according to claim 4, characterized in that: When verifying the sent receiving module with the SPC function turned off, the SPC function trigger enable signal is configured to be always invalid, and the sent input enable signal is configured to be always valid.

6. The sent receiving module verification method with SPC in a chip according to claim 4 or 5, characterized in that: The SPC function trigger enable signal is valid at a high level, and the sent input enable signal is valid at a high level.

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