A printed circuit board configured with impedance circuit and a manufacturing method thereof

Abstract

The present invention relates to a method for manufacturing a printed circuit board configured with an impedance circuit, comprising: arranging a dielectric layer between inner-layer boards so that both sides of each inner-layer board are in contact with the dielectric layer, and bonding the inner-layer boards to the copper foil on the outer side of the inner-layer boards. Arranging a plurality of large copper surfaces that are not connected to each other on the inner-layer board circuits closest to the copper foil respectively to form capacitors with the copper foils respectively for measuring a plurality of capacitance values. Selecting positions on the copper foil, and arranging a plurality of holes penetrating the copper foil and the dielectric layer at the selected positions to leak out the area where the large copper surface is located, so as to measure the capacitance between the copper foil and the large copper surface by probing the holes. Using the copper foil of the characteristic impedance circuit reference layer and the copper foil used for making the impedance circuit after lamination, measuring a plurality of capacitance values ​​between the copper foils, so as to infer the thickness of the dielectric layer between the copper foils based on the plurality of capacitance values. Correcting the width and thickness of the impedance circuit on the copper foil surface according to the inferred thickness of the dielectric layer, so as to obtain a printed circuit board configured with an impedance circuit.

Description

Technical Field

[0001] The invention relates to the technical field of impedance circuit design, and in particular to a method for manufacturing a printed circuit board configured with an impedance circuit. Background Art

[0002] At present, for traditional printed circuit boards, the impedance control of the outer layer or the sub-outer layer of HDI is mainly based on the originally designed line width and line thickness, and then the appropriate prepreg is selected to press out the required dielectric layer thickness. However, during the lamination process of the printed circuit board, the dielectric layer thickness is more easily affected by factors such as the volume, weight, glue content of the glass fiber cloth used in the prepreg, and the error of the hot pressing process parameters, resulting in a certain range of thickness changes, that is, the thickness of the same dielectric layer is uneven.

[0003] In the traditional manufacturing process of printed circuit boards, suitable prepregs are often selected based on the thickness of the inner layer circuit and the residual copper rate, and then the required dielectric layer thickness is pressed. Then the thickness and width of the outer or sub-outer layer circuit are designed according to the pressed dielectric layer thickness, in order to complete the outer or sub-outer layer impedance circuit, and its impedance value can also be controlled within the design range. However, although this method can adjust the thickness of the dielectric layer that affects the impedance value by replacing prepregs of different specifications in the test or mass production stage to meet the impedance specifications. However, since the measurement of the dielectric layer thickness requires the use of slices, it is tantamount to destroying the printed circuit board, and it is difficult to measure the dielectric layer thickness in large quantities before making the outer or sub-outer layer impedance circuit, so the line impedance value can only be measured after the outer or sub-outer layer impedance circuit is completed. In the next mass production, the semi-cured sheet specifications are changed or the thickness and width of the outer or sub-outer layer circuit are adjusted according to the measured line impedance value.

[0004] In summary, it is difficult for the traditional printed circuit board manufacturing method to estimate the thickness of the dielectric layer that has an important influence on the impedance value of the outer or sub-outer impedance line before the outer or sub-outer impedance line electroplating process, and then to produce the printed circuit board, and thus it is difficult to make the impedance line thickness and impedance line width reach the design of the pre-corrected impedance line. Summary of the invention

[0005] Based on this, it is necessary to provide a method for manufacturing a printed circuit board with configured impedance lines, which can estimate the thickness of the dielectric layer that has an important influence on the impedance value of the outer or sub-outer impedance line before the electroplating process of the outer or sub-outer impedance line is carried out, and then carry out the production of the printed circuit board.

[0006] The present invention provides a method for manufacturing a printed circuit board configured with an impedance circuit, wherein the printed circuit board comprises a plurality of inner layer boards on which circuits have been formed, and the method comprises:

[0007] A dielectric layer is arranged between the inner layer boards so that both sides of each inner layer board are in contact with the dielectric layer, and the dielectric layer is obtained by laminating a semi-cured sheet and is used to bond the inner layer board to the first copper foil and the second copper foil on the outer side of the inner layer board;

[0008] Arranging a plurality of large copper surfaces which are not connected to each other on the inner layer circuits which are closest to the first copper foil and the second copper foil respectively, so as to form capacitors with the first copper foil and the second copper foil respectively, for measuring a plurality of capacitance values;

[0009] A first position is selected on the first copper foil or the second copper foil, and a plurality of holes are set at the first position, penetrating the first copper foil or the second copper foil and the dielectric layer, so as to expose the area where the large copper surface is located, so as to measure the capacitance between the first copper foil or the second copper foil and the large copper surface by probing the holes;

[0010] Using the first copper foil of the characteristic impedance line reference layer and the second copper foil for making the impedance line after lamination, multiple capacitance values ​​between the first copper foil and the second copper foil are measured, so as to infer the thickness of the dielectric layer between the first copper foil and the second copper foil based on the multiple capacitance values;

[0011] According to the estimated thickness of the dielectric layer, the width and thickness of the impedance line on the first copper foil and the second copper foil are corrected to obtain the printed circuit board configured with the impedance line.

[0012] In one embodiment, the inner layer board includes an intermediate inner layer board and an outermost inner layer board, the intermediate inner layer board has a plurality of inner layer boards, the outermost inner layer board is divided into a first outermost inner layer board and a second outermost inner layer board, and the first outermost inner layer board is adjacent to the first copper foil, and the second outermost inner layer board is adjacent to the second copper foil;

[0013] The dielectric layer is arranged between the inner layer boards so that both sides of each inner layer board are in contact with the dielectric layer, and the dielectric layer is obtained by laminating the semi-cured sheet and is used to bond the inner layer board to the first copper foil and the second copper foil on the outer side of the inner layer board, including:

[0014] The dielectric layer with a first thickness is arranged between two adjacent intermediate inner layer boards, so as to bond the two adjacent intermediate inner layer boards through the dielectric layer.

[0015] In one embodiment, a dielectric layer is arranged between the inner layer boards so that both sides of each inner layer board are in contact with the dielectric layer, the dielectric layer is obtained by laminating a semi-cured sheet and is used to bond the inner layer board to the first copper foil and the second copper foil on the outer side of the inner layer board, and further comprises:

[0016] Disposing the dielectric layer of the second thickness between the first outermost inner layer board and the first copper foil, so as to bond the first outermost inner layer board and the first copper foil through the dielectric layer;

[0017] The dielectric layer with a third thickness is arranged between the second outermost inner layer board and the second copper foil, so as to bond the second outermost inner layer board and the second copper foil through the dielectric layer.

[0018] In one embodiment, a plurality of large copper surfaces which are not connected to each other are arranged on the inner layer circuits which are closest to the first copper foil and the second copper foil respectively, so as to form capacitors with the first copper foil and the second copper foil respectively, for measuring a plurality of capacitance values, including:

[0019] One or more large copper surfaces which are not connected to each other are respectively arranged on the circuits of the first outermost inner layer board and the second outermost inner layer board;

[0020] Capacitances are formed between the large copper surface and the first copper foil and the second copper foil respectively, so as to measure one or more capacitance values ​​corresponding to one or more large copper surfaces and the first copper foil or the second copper foil.

[0021] In one embodiment, the first position is selected on the first copper foil or the second copper foil, and a plurality of holes are set at the first position that penetrate the first copper foil or the second copper foil and the dielectric layer to leak out the area where the large copper surface is located, so as to measure the capacitance between the first copper foil or the second copper foil and the large copper surface by probing the holes, including:

[0022] Probe the area where the large copper surface is located and the first copper foil or the second copper foil through the hole to measure the capacitance of one or more capacitors isolated by the dielectric layer between the outermost inner layer board and the first copper foil or the second copper foil;

[0023] Based on the capacitance of the one or more capacitors and in combination with the area of ​​each large copper surface, the average thickness of the dielectric layer between the outermost inner layer board and the first copper foil or the second copper foil is calculated.

[0024] In one embodiment, the method further comprises: selecting a first position on the first copper foil or the second copper foil, and providing a plurality of holes penetrating the first copper foil or the second copper foil and the dielectric layer at the first position to expose the area where the large copper surface is located, so as to measure the capacitance between the first copper foil or the second copper foil and the large copper surface by probing the holes;

[0025] When the large copper surface is located on the circuit of the first outermost inner layer board, the second copper foil is used as the characteristic impedance circuit reference layer, a plurality of second positions are selected on the first copper foil, and a plurality of first holes penetrating the first copper foil and the dielectric layer are opened at the plurality of second positions;

[0026] By probing the first holes at multiple second positions, multiple capacitances between the first copper foil and the large copper surface are measured to infer multiple corresponding dielectric layer thicknesses and determine whether the dielectric layer thickness is uniform.

[0027] In one embodiment, the method further comprises: selecting a first position on the first copper foil or the second copper foil, and providing a plurality of holes penetrating the first copper foil or the second copper foil and the dielectric layer at the first position to expose the area where the large copper surface is located, so as to measure the capacitance between the first copper foil or the second copper foil and the large copper surface by probing the holes;

[0028] When the large copper surface is located on the circuit of the second outermost inner layer board, the first copper foil is used as the characteristic impedance circuit reference layer, a plurality of third positions are selected on the second copper foil, and a plurality of second holes penetrating the second copper foil and the dielectric layer are opened at the plurality of third positions;

[0029] By probing the second holes at a plurality of third positions, a plurality of capacitances between the second copper foil and the large copper surface are measured to infer a plurality of corresponding dielectric layer thicknesses and determine whether the dielectric layer thickness is uniform.

[0030] In one embodiment, the method further comprises:

[0031] One or more of the large copper surfaces that are not connected to each other are arranged on the circuit of any of the intermediate inner layers, and a plurality of holes penetrating the first copper foil or the second copper foil, the dielectric layer and the inner layer are opened on the first copper foil or the second copper foil to expose the area where the large copper surface is located on the intermediate inner layer;

[0032] The capacity of one or more capacitors between the large copper surface on the middle layer inner board and the first copper foil or the second copper foil is measured by probing the hole.

[0033] In one embodiment, the method of measuring a plurality of capacitance values ​​between the first copper foil and the second copper foil using the first copper foil of the characteristic impedance line reference layer and the second copper foil for making an impedance line after being pressed together, so as to infer the thickness of the dielectric layer between the first copper foil and the second copper foil based on the plurality of capacitance values, comprises:

[0034] Based on the capacitance of one or more capacitors isolated by the dielectric layer between the outermost inner layer board and the first copper foil or the second copper foil, the thickness of multiple dielectric layers between the first copper foil or the second copper foil and the large copper surface on the outermost inner layer board circuit is estimated;

[0035] The average thickness of the dielectric layer is calculated according to the thicknesses of the plurality of dielectric layers, where the average thickness of the dielectric layer is the sum of the thicknesses of the plurality of dielectric layers divided by the average value of the number of the large copper surfaces.

[0036] In one embodiment, the method of measuring a plurality of capacitance values ​​between the first copper foil and the second copper foil using the first copper foil of the characteristic impedance line reference layer and the second copper foil for making an impedance line after lamination, so as to infer the thickness of the dielectric layer between the first copper foil and the second copper foil based on the plurality of capacitance values, further comprises:

[0037] Based on the capacitance of one or more capacitors between the large copper surface on the middle layer inner layer board and the first copper foil or the second copper foil, the thickness of multiple dielectric layers between the large copper surface on any of the middle layer inner layer board circuits and the first copper foil or the second copper foil is estimated;

[0038] The average thickness of the same dielectric layer is calculated according to the thickness of multiple dielectric layers between the large copper surface and the first copper foil or the second copper foil on the same intermediate layer inner layer circuit.

[0039] The above-mentioned method for manufacturing a printed circuit board configured with an impedance circuit is to set a dielectric layer between the inner layers so that both sides of each inner layer are in contact with the dielectric layer, and the dielectric layer is obtained by laminating a semi-cured sheet, and is used to bond the inner layer to the first copper foil and the second copper foil on the outer side of the inner layer. Then, a plurality of large copper surfaces that are not connected to each other are set on the inner layer circuits closest to the first copper foil and the second copper foil, respectively, to form capacitors with the first copper foil and the second copper foil, respectively, for measuring multiple capacitance values. Subsequently, a suitable position is selected on the first copper foil or the second copper foil, and a plurality of holes penetrating the first copper foil or the second copper foil and the dielectric layer are set at the position to leak out the area where the large copper surface is located, and the capacitance between the first copper foil or the second copper foil and the large copper surface is measured by probing the holes. Then, the first copper foil of the characteristic impedance circuit reference layer and the second copper foil used to make the impedance circuit after lamination are used to measure the multiple capacitance values ​​between the first copper foil and the second copper foil, so as to infer the thickness of the dielectric layer between the first copper foil and the second copper foil based on the multiple capacitance values. Finally, according to the estimated thickness of the dielectric layer, the width and thickness of the impedance line on the first copper foil and the second copper foil are corrected to obtain the printed circuit board configured with the impedance line. This method can estimate the thickness of the dielectric layer that has an important influence on the impedance value of the outer layer or the sub-outer layer impedance line through the large copper surface and the holes on the copper foil before the outer layer or the sub-outer layer impedance line electroplating process is carried out, and then the printed circuit board is carried out, so that the impedance line thickness and the impedance line width can reach the design of the pre-corrected impedance line. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0041] Figure 1 A schematic flow chart of a method for manufacturing a printed circuit board configured with an impedance circuit provided by the present invention;

[0042] Figure 2 A schematic diagram of the structure of a printed circuit board of a method for manufacturing a printed circuit board configured with an impedance circuit in a specific embodiment provided by the present invention.

[0043] In the figure: 100, copper foil; 200, dielectric layer; 300, inner layer board; 400, large copper surface. DETAILED DESCRIPTION

[0044] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0045] Combine the following Figure 1 to Figure 2 A method for manufacturing a printed circuit board with configured impedance circuits according to the present invention is described.

[0046] like Figure 1 As shown, in one embodiment, a method for manufacturing a printed circuit board configured with an impedance circuit includes the following steps:

[0047] Step S110, a dielectric layer is arranged between the inner layer boards so that both sides of each inner layer board are in contact with the dielectric layer, the dielectric layer is obtained by laminating the semi-cured sheet, and is used to bond the inner layer board to the first copper foil and the second copper foil on the outer side of the inner layer board.

[0048] In some embodiments, the present invention provides a method for manufacturing a printed circuit board configured with an impedance circuit, wherein the inner layer board includes an intermediate inner layer board and an outermost inner layer board, the intermediate inner layer board has multiple inner layer boards, the outermost inner layer board is divided into a first outermost inner layer board and a second outermost inner layer board, and the first outermost inner layer board is adjacent to the first copper foil, and the second outermost inner layer board is adjacent to the second copper foil.

[0049] A dielectric layer is arranged between the inner layer boards so that both sides of each inner layer board are in contact with the dielectric layer. The dielectric layer is obtained by laminating a semi-cured sheet and is used to bond the inner layer board to the first copper foil and the second copper foil on the outer side of the inner layer board. Specifically, the following steps are included:

[0050] Step S111: a dielectric layer having a first thickness is disposed between two adjacent intermediate inner layer boards, so as to bond the two adjacent intermediate inner layer boards through the dielectric layer.

[0051] In some embodiments, the present invention provides a method for manufacturing a printed circuit board configured with an impedance circuit, wherein a dielectric layer is arranged between the inner layer boards so that both sides of each inner layer board are in contact with the dielectric layer, and the dielectric layer is obtained by laminating a semi-cured sheet and is used to bond the inner layer board to the first copper foil and the second copper foil on the outer side of the inner layer board, and specifically further comprises the following steps:

[0052] Step S112, disposing a dielectric layer of a second thickness between the first outermost inner layer board and the first copper foil, so as to bond the first outermost inner layer board and the first copper foil through the dielectric layer.

[0053] Step S113, disposing a dielectric layer of a third thickness between the second outermost inner layer board and the second copper foil, so as to bond the second outermost inner layer board and the second copper foil through the dielectric layer.

[0054] Step S120, a plurality of large copper surfaces which are not connected to each other are respectively arranged on the inner layer circuits which are closest to the first copper foil and the second copper foil, so as to form capacitors with the first copper foil and the second copper foil respectively, for measuring a plurality of capacitance values.

[0055] In some embodiments, the present invention provides a method for manufacturing a printed circuit board configured with an impedance circuit, wherein a plurality of large copper surfaces that are not connected to each other are respectively arranged on the inner layer circuits closest to the first copper foil and the second copper foil to form capacitors with the first copper foil and the second copper foil respectively, for measuring a plurality of capacitance values, specifically comprising the following steps:

[0056] Step S121, respectively setting one or more large copper surfaces which are not connected to each other on the circuits of the first outermost inner layer board and the second outermost inner layer board.

[0057] Step S122 , forming capacitances between the large copper surface and the first copper foil and the second copper foil respectively, so as to measure one or more capacitance values ​​corresponding to one or more large copper surfaces and the first copper foil or the second copper foil.

[0058] Step S130, selecting a first position on the first copper foil or the second copper foil, and setting a plurality of holes penetrating the first copper foil or the second copper foil and the dielectric layer at the first position to expose the area where the large copper surface is located, so as to measure the capacitance between the first copper foil or the second copper foil and the large copper surface by probing the holes.

[0059] In some embodiments, the present invention provides a method for manufacturing a printed circuit board configured with an impedance circuit, wherein a first position is selected on a first copper foil or a second copper foil, and a plurality of holes penetrating the first copper foil or the second copper foil and a dielectric layer are arranged at the first position to expose an area where a large copper surface is located, so as to measure the capacitance between the first copper foil or the second copper foil and the large copper surface by probing the holes, specifically comprising the following steps:

[0060] Step S131, probing the area where the large copper surface is located and the first copper foil or the second copper foil through the hole, and measuring the capacitance of one or more capacitors isolated by the dielectric layer between the outermost inner layer board and the first copper foil or the second copper foil.

[0061] Step S132, based on the capacitance of one or more capacitors and in combination with the area size of each large copper surface, the average thickness of the dielectric layer between the outermost inner layer board and the first copper foil or the second copper foil is calculated.

[0062] In some embodiments, the present invention provides a method for manufacturing a printed circuit board configured with an impedance circuit, wherein a first position is selected on a first copper foil or a second copper foil, and a plurality of holes penetrating the first copper foil or the second copper foil and a dielectric layer are arranged at the first position to expose the area where the large copper surface is located, so as to measure the capacitance between the first copper foil or the second copper foil and the large copper surface by probing the holes, and the method further includes the following steps:

[0063] Step S133, when the large copper surface is located on the circuit of the first outermost inner layer board, the second copper foil is used as the characteristic impedance circuit reference layer, multiple second positions are selected on the first copper foil, and multiple first holes penetrating the first copper foil and the dielectric layer are opened at the multiple second positions.

[0064] Step S134 , measuring multiple capacitances between the first copper foil and the large copper surface by probing the first holes at multiple second positions, so as to infer multiple corresponding dielectric layer thicknesses and determine whether the dielectric layer thickness is uniform.

[0065] In some embodiments, the present invention provides a method for manufacturing a printed circuit board configured with an impedance circuit, wherein a first position is selected on a first copper foil or a second copper foil, and a plurality of holes penetrating the first copper foil or the second copper foil and a dielectric layer are arranged at the first position to expose the area where the large copper surface is located, so as to measure the capacitance between the first copper foil or the second copper foil and the large copper surface by probing the holes, and the method further includes the following steps:

[0066] Step S135, when the large copper surface is located on the circuit of the second outermost inner layer board, the first copper foil is used as the characteristic impedance circuit reference layer, multiple third positions are selected on the second copper foil, and multiple second holes penetrating the second copper foil and the dielectric layer are opened at the multiple third positions.

[0067] Step S136 , measuring multiple capacitances between the second copper foil and the large copper surface by probing the second holes at multiple third positions, so as to infer multiple corresponding dielectric layer thicknesses and determine whether the dielectric layer thickness is uniform.

[0068] In some embodiments, the present invention provides a method for manufacturing a printed circuit board configured with an impedance circuit, further comprising the following steps:

[0069] Step S210, setting one or more unconnected large copper surfaces on the circuit of any intermediate layer inner layer board, and opening a plurality of holes penetrating the first copper foil or the second copper foil and the dielectric layer and the inner layer board on the first copper foil or the second copper foil to expose the area where the large copper surface is located on the intermediate layer inner layer board.

[0070] Step S220 , measuring the capacitance of one or more capacitors between the large copper surface on the middle layer inner board and the first copper foil or the second copper foil through the probing hole.

[0071] Step S140, using the first copper foil of the characteristic impedance line reference layer and the second copper foil for making the impedance line after lamination, measure multiple capacitance values ​​between the first copper foil and the second copper foil, so as to infer the thickness of the dielectric layer between the first copper foil and the second copper foil based on the multiple capacitance values.

[0072] In some embodiments, the present invention provides a method for manufacturing a printed circuit board configured with an impedance circuit, using a first copper foil of a characteristic impedance circuit reference layer and a second copper foil for manufacturing an impedance circuit after lamination, measuring multiple capacitance values ​​between the first copper foil and the second copper foil, so as to infer the thickness of the dielectric layer between the first copper foil and the second copper foil based on the multiple capacitance values, specifically comprising the following steps:

[0073] Step S141, based on the capacitance of one or more capacitors isolated by dielectric layers between the outermost inner layer board and the first copper foil or the second copper foil, infer the thickness of multiple dielectric layers between the first copper foil or the second copper foil and the large copper surface on the outermost inner layer board circuit.

[0074] Step S142, calculating an average thickness of the dielectric layer according to the thicknesses of the plurality of dielectric layers, where the average thickness of the dielectric layer is the sum of the thicknesses of the plurality of dielectric layers divided by the average value of the number of large copper surfaces.

[0075] In some embodiments, the present invention provides a method for manufacturing a printed circuit board configured with an impedance circuit, using a first copper foil of a characteristic impedance circuit reference layer and a second copper foil for manufacturing an impedance circuit after lamination, measuring multiple capacitance values ​​between the first copper foil and the second copper foil, so as to infer the thickness of the dielectric layer between the first copper foil and the second copper foil based on the multiple capacitance values, and specifically further comprising the following steps:

[0076] Step S143, based on the capacitance of one or more capacitors between the large copper surface on the intermediate inner layer board and the first copper foil or the second copper foil, infer the thickness of multiple dielectric layers between the large copper surface and the first copper foil or the second copper foil on any intermediate inner layer board circuit.

[0077] Step S144, calculating the average thickness of the same dielectric layer according to the thickness of multiple dielectric layers between the large copper surface and the first copper foil or the second copper foil on the same intermediate layer inner layer circuit.

[0078] Step S150, according to the estimated thickness of the dielectric layer, the width and thickness of the impedance line on the first copper foil and the second copper foil are corrected to obtain a printed circuit board configured with the impedance line.

[0079] The above-mentioned method for manufacturing a printed circuit board configured with an impedance circuit is to set a dielectric layer between the inner layers so that both sides of each inner layer are in contact with the dielectric layer, and the dielectric layer is obtained by laminating a semi-cured sheet, and is used to bond the inner layer to the first copper foil and the second copper foil on the outer side of the inner layer. Then, a plurality of large copper surfaces that are not connected to each other are set on the inner layer circuits closest to the first copper foil and the second copper foil, respectively, to form capacitors with the first copper foil and the second copper foil, respectively, for measuring multiple capacitance values. Subsequently, a suitable position is selected on the first copper foil or the second copper foil, and a plurality of holes penetrating the first copper foil or the second copper foil and the dielectric layer are set at the position to leak out the area where the large copper surface is located, and the capacitance between the first copper foil or the second copper foil and the large copper surface is measured by probing the holes. Then, the first copper foil of the characteristic impedance circuit reference layer and the second copper foil used to make the impedance circuit after lamination are used to measure the multiple capacitance values ​​between the first copper foil and the second copper foil, so as to infer the thickness of the dielectric layer between the first copper foil and the second copper foil based on the multiple capacitance values. Finally, according to the estimated thickness of the dielectric layer, the width and thickness of the impedance line on the first copper foil and the second copper foil are corrected to obtain the printed circuit board configured with the impedance line. This method can estimate the thickness of the dielectric layer that has an important influence on the impedance value of the outer layer or the sub-outer layer impedance line through the large copper surface and the holes on the copper foil before the outer layer or the sub-outer layer impedance line electroplating process is carried out, and then the printed circuit board is carried out, so that the impedance line thickness and the impedance line width can reach the design of the pre-corrected impedance line.

[0080] In a specific embodiment, the present invention provides a method for manufacturing a printed circuit board configured with an impedance circuit, combined with Figure 2 As shown, the printed circuit board may include one or more inner-layer boards 300 with formed circuits, dielectric layers 200 between the inner-layer boards 300 and on the outer side of the inner-layer boards 300, and outermost copper foils 100. The dielectric layer 200 is formed by laminating a prepreg, and is used to bond the inner-layer board 300 and its outer copper foil 100, and to form a dielectric layer 200 with a controlled thickness between the inner-layer circuits adjacent to the outer copper foil 100 and the outer copper foil 100. One or more large copper surfaces 400 that are not connected to each other are arranged on the circuits of the inner-layer board 300 adjacent to the outer copper foil 100 through the dielectric layer 200, so as to form a capacitor with the outer copper foil 100, so as to measure one or more capacitance values.

[0081] In this embodiment, one or more holes are formed at appropriate positions on the outer copper foil 100 to penetrate the outer copper foil 100 and the dielectric layer 200, exposing one or more large copper surfaces 400 on the inner layer board 300. By probing each large copper surface 400 and the outer copper foil 100 on the inner layer board 300, the capacitance of one or more capacitors formed by the one or more large copper surfaces 400 on the inner layer board 300 and the outer copper foil 100 isolated by the dielectric layer 200 can be measured, and then the measured capacitance value and the area of ​​each large copper surface 400 on the inner layer board 300 are used to infer the average thickness of the dielectric layer 200 in the area.

[0082] In this embodiment, the capacitance value of the capacitor formed by each unconnected large copper surface 400 of the inner layer board 300 and the outer copper foil 100 is measured. The average thickness of the dielectric layer 200 between the impedance line and the reference large copper surface 400 is calculated by using this capacitance value, and then the impedance line is corrected to obtain the thickness and width, and then the impedance line is manufactured according to the original printed circuit board manufacturing process.

[0083] It should be noted that, for a high density interconnect circuit board (HDIPCB) having blind holes and which may need to undergo multiple lamination processes, when one of its circuit layers has been arranged with one or more large copper surfaces 400, or one or more large copper surfaces 400 may be added, the one or more large copper surfaces 400 and the outer copper foil 100 may be made to form one or more capacitors in the same manner as the above-mentioned through-hole multilayer board, and the capacitance value may be measured and the average thickness of the dielectric layer 200 in the corresponding area may be inferred.

[0084] In this embodiment, after the thickness of the dielectric layer 200 inside the copper foil 100 is calculated or inferred, the width and thickness of the impedance line on the copper foil 100 can be appropriately corrected according to the impedance calculation formula. Only one type of thickness correction of the impedance line can be selected, and the width design of the impedance line can be based on the partition imaging size limit of the image transfer device, and the uneven thickness of the dielectric layer 200 corresponding to the measured capacitance value of each zone, and one or more line width designs can be used.

[0085] In this embodiment, for some lines, it is required to control the characteristic impedance value of the line, and the thickness of the dielectric layer 200 between the outer layer or the sub-outer layer line and the corresponding adjacent large copper surface 400 is regarded as a flat plate capacitor. The outer copper foil 100 and the dielectric layer 200 are penetrated at an appropriate position of the outer layer to expose the inner layer 300, and the capacitance is measured according to the flat plate capacitor formula: C=ε×ε0×S / d (where C is capacitance, unit F, ε is dielectric constant, ε0 is vacuum dielectric constant 8.86 10 -12F / m, S is the area in square meters, D is the distance in meters) to estimate the thickness of the dielectric layer 200, and then design the matching line copper thickness and line width based on the characteristic impedance formula.

[0086] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0087] The above-mentioned embodiments only express several implementation methods of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the patent of the present invention. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A method for manufacturing a printed circuit board configured with an impedance circuit, characterized in that: The printed circuit board includes a plurality of inner layer boards on which circuits have been formed, and the method includes: A dielectric layer is arranged between the inner layer boards so that both sides of each inner layer board are in contact with the dielectric layer, and the dielectric layer is obtained by laminating a semi-cured sheet and is used to bond the inner layer board to the first copper foil and the second copper foil on the outer side of the inner layer board; Arranging a plurality of large copper surfaces which are not connected to each other on the inner layer circuits which are closest to the first copper foil and the second copper foil respectively, so as to form capacitors with the first copper foil and the second copper foil respectively, for measuring a plurality of capacitance values; A first position is selected on the first copper foil or the second copper foil, and a plurality of holes are set at the first position, penetrating the first copper foil or the second copper foil and the dielectric layer, so as to expose the area where the large copper surface is located, so as to measure the capacitance between the first copper foil or the second copper foil and the large copper surface by probing the holes; Using the first copper foil of the characteristic impedance line reference layer and the second copper foil for making the impedance line after lamination, multiple capacitance values ​​between the first copper foil and the second copper foil are measured, so as to infer the thickness of the dielectric layer between the first copper foil and the second copper foil based on the multiple capacitance values; According to the estimated thickness of the dielectric layer, the width and thickness of the impedance line on the first copper foil and the second copper foil are corrected to obtain the printed circuit board configured with the impedance line.

2. The method for manufacturing a printed circuit board configured with an impedance circuit according to claim 1, characterized in that: The inner layer board includes a middle inner layer board and an outermost inner layer board, the middle inner layer board has a plurality of inner layer boards, the outermost inner layer board is divided into a first outermost inner layer board and a second outermost inner layer board, and the first outermost inner layer board is adjacent to the first copper foil, and the second outermost inner layer board is adjacent to the second copper foil; The dielectric layer is arranged between the inner layer boards so that both sides of each inner layer board are in contact with the dielectric layer, and the dielectric layer is obtained by laminating the semi-cured sheet and is used to bond the inner layer board to the first copper foil and the second copper foil on the outer side of the inner layer board, including: The dielectric layer with a first thickness is arranged between two adjacent intermediate inner layer boards, so as to bond the two adjacent intermediate inner layer boards through the dielectric layer.

3. The method for manufacturing a printed circuit board configured with an impedance circuit according to claim 2, characterized in that: The dielectric layer is arranged between the inner layer boards so that both sides of each inner layer board are in contact with the dielectric layer, the dielectric layer is obtained by laminating the semi-cured sheet, and is used to bond the inner layer board to the first copper foil and the second copper foil on the outer side of the inner layer board, and also includes: Disposing the dielectric layer of the second thickness between the first outermost inner layer board and the first copper foil, so as to bond the first outermost inner layer board and the first copper foil through the dielectric layer; The dielectric layer with a third thickness is arranged between the second outermost inner layer board and the second copper foil, so as to bond the second outermost inner layer board and the second copper foil through the dielectric layer.

4. The method for manufacturing a printed circuit board configured with an impedance circuit according to claim 3, characterized in that: The method of arranging a plurality of large copper surfaces which are not connected to each other on the inner layer circuits which are closest to the first copper foil and the second copper foil respectively, so as to form capacitors with the first copper foil and the second copper foil respectively, for measuring a plurality of capacitance values, comprises: One or more large copper surfaces which are not connected to each other are respectively arranged on the circuits of the first outermost inner layer board and the second outermost inner layer board; Capacitances are formed between the large copper surface and the first copper foil and the second copper foil respectively, so as to measure one or more capacitance values ​​corresponding to one or more large copper surfaces and the first copper foil or the second copper foil.

5. The method for manufacturing a printed circuit board configured with an impedance circuit according to claim 4, characterized in that: The method comprises: selecting a first position on the first copper foil or the second copper foil, and setting a plurality of holes penetrating the first copper foil or the second copper foil and the dielectric layer at the first position to expose the area where the large copper surface is located, so as to measure the capacitance between the first copper foil or the second copper foil and the large copper surface by probing the holes, comprising: Probe the area where the large copper surface is located and the first copper foil or the second copper foil through the hole to measure the capacitance of one or more capacitors isolated by the dielectric layer between the outermost inner layer board and the first copper foil or the second copper foil; Based on the capacitance of the one or more capacitors and in combination with the area of ​​each large copper surface, the average thickness of the dielectric layer between the outermost inner layer board and the first copper foil or the second copper foil is calculated.

6. The method for manufacturing a printed circuit board configured with an impedance circuit according to claim 5, characterized in that: The method further comprises: selecting a first position on the first copper foil or the second copper foil, and providing a plurality of holes penetrating the first copper foil or the second copper foil and the dielectric layer at the first position to expose the area where the large copper surface is located, so as to measure the capacitance between the first copper foil or the second copper foil and the large copper surface by probing the holes; When the large copper surface is located on the circuit of the first outermost inner layer board, the second copper foil is used as the characteristic impedance circuit reference layer, a plurality of second positions are selected on the first copper foil, and a plurality of first holes penetrating the first copper foil and the dielectric layer are opened at the plurality of second positions; By probing the first holes at multiple second positions, multiple capacitances between the first copper foil and the large copper surface are measured to infer multiple corresponding dielectric layer thicknesses and determine whether the dielectric layer thickness is uniform.

7. The method for manufacturing a printed circuit board configured with an impedance circuit according to claim 5, characterized in that: The method further comprises: selecting a first position on the first copper foil or the second copper foil, and providing a plurality of holes penetrating the first copper foil or the second copper foil and the dielectric layer at the first position to expose the area where the large copper surface is located, so as to measure the capacitance between the first copper foil or the second copper foil and the large copper surface by probing the holes; When the large copper surface is located on the circuit of the second outermost inner layer board, the first copper foil is used as the characteristic impedance circuit reference layer, a plurality of third positions are selected on the second copper foil, and a plurality of second holes penetrating the second copper foil and the dielectric layer are opened at the plurality of third positions; By probing the second holes at a plurality of third positions, a plurality of capacitances between the second copper foil and the large copper surface are measured to infer a plurality of corresponding dielectric layer thicknesses and determine whether the dielectric layer thickness is uniform.

8. The method for manufacturing a printed circuit board configured with an impedance circuit according to claim 5, characterized in that: The method further comprises: One or more of the large copper surfaces that are not connected to each other are arranged on the circuit of any of the intermediate inner layers, and a plurality of holes penetrating the first copper foil or the second copper foil, the dielectric layer and the inner layer are opened on the first copper foil or the second copper foil to expose the area where the large copper surface is located on the intermediate inner layer; The capacity of one or more capacitors between the large copper surface on the middle layer inner board and the first copper foil or the second copper foil is measured by probing the hole.

9. The method for manufacturing a printed circuit board configured with an impedance circuit according to claim 8, characterized in that: The method of measuring a plurality of capacitance values ​​between the first copper foil and the second copper foil using the first copper foil of the characteristic impedance line reference layer and the second copper foil for making an impedance line after being pressed together, so as to infer the thickness of the dielectric layer between the first copper foil and the second copper foil based on the plurality of capacitance values, comprises: Based on the capacitance of one or more capacitors isolated by the dielectric layer between the outermost inner layer board and the first copper foil or the second copper foil, the thickness of multiple dielectric layers between the first copper foil or the second copper foil and the large copper surface on the outermost inner layer board circuit is estimated; The average thickness of the dielectric layer is calculated according to the thicknesses of the plurality of dielectric layers, where the average thickness of the dielectric layer is the sum of the thicknesses of the plurality of dielectric layers divided by the average value of the number of the large copper surfaces.

10. The method for manufacturing a printed circuit board configured with an impedance circuit according to claim 9, characterized in that: The method further comprises: measuring a plurality of capacitance values ​​between the first copper foil and the second copper foil using the first copper foil of the characteristic impedance line reference layer and the second copper foil for making an impedance line after being pressed together, so as to infer the thickness of the dielectric layer between the first copper foil and the second copper foil based on the plurality of capacitance values; Based on the capacitance of one or more capacitors between the large copper surface on the middle layer inner layer board and the first copper foil or the second copper foil, the thickness of multiple dielectric layers between the large copper surface on any of the middle layer inner layer board circuits and the first copper foil or the second copper foil is estimated; The average thickness of the same dielectric layer is calculated according to the thickness of multiple dielectric layers between the large copper surface and the first copper foil or the second copper foil on the same intermediate layer inner layer circuit.

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