SONOS memory device and preparation method thereof

Abstract

The invention provides an SONOS memory device and a preparation method thereof, and the method comprises the steps: providing a substrate, and forming a charge storage layer, a polysilicon gate material layer and a hard mask layer on the substrate; forming two discrete oxide layers in the hard mask layer by a self-alignment etching process; removing the polysilicon gate material layer exposed by the two oxide layers through self-alignment etching to form two discrete polysilicon gates; forming a side wall, and isolating the side wall to fill a gap between the two polycrystalline silicon grids; the side walls cover the side walls, far away from one sides of the isolation side walls, of the two polycrystalline silicon grids; and source-drain heavily doped ion implantation is carried out on the substrate at one side, far away from the isolation side wall, of each side wall. The storage density is increased, a source end shared between the two storage tubes and side walls close to the sides of the source end are omitted, the two storage tubes are directly isolated by the isolation side wall, and the area of the storage unit can be effectively reduced. The two storage tubes are formed by using a self-alignment process, the consistency is high, and the uniformity of the storage unit is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit manufacturing, and in particular relates to a SONOS memory device and a preparation method thereof. Background Art

[0002] With the development of technology, the analysis of big data has an increasing demand for data storage and processing, and therefore the demand for non-volatile memory has also increased. As an indispensable storage device in computers, non-volatile memory plays an important storage function for the processed information. Among non-volatile memories, SONOS memory has the advantages of small unit size, good storage retention, low operating voltage, and compatibility with complementary metal oxide semiconductor (CMOS) manufacturing process, and is widely used in electronic products.

[0003] like Figure 1 As shown, there is a two-tube two-bit SONOS memory, in which one storage unit is composed of two storage tubes (storage tube 1 and storage tube 2). In this two-tube two-bit SONOS memory, the two storage tubes share a source terminal S, and the source terminal S does not need to be connected with a contact hole (CT). At a smaller process node, the sidewalls (Spacer) of the two storage tubes close to the source terminal S and the source terminal S that does not need to be connected with a contact hole occupy a larger area. Summary of the invention

[0004] The object of the present invention is to provide a SONOS memory device and a method for preparing the same, which can increase the storage density and store two bits of data in each memory cell. The source end shared by two memory tubes and the manufacturing process of heavily doping the source end are omitted, and the side walls of the two memory tubes close to the source end are omitted. The two memory tubes are directly isolated by the isolation side wall and the gap between the two memory tubes is filled, which can effectively reduce the area of ​​the memory cell. The two memory tubes are formed by a self-alignment process, and the consistency is higher than that of the existing process, which is conducive to improving the uniformity of the memory cell and facilitating the control of the interference of the operation.

[0005] The present invention provides a method for preparing a SONOS memory device, comprising:

[0006] Providing a substrate, and sequentially forming a charge storage layer, a polysilicon gate material layer and a hard mask layer on the surface of the substrate;

[0007] Etching the hard mask layer to form an opening to define a total channel length of two storage tubes;

[0008] forming two separate oxide layers in the opening using a self-aligned etching process;

[0009] Etching to remove the hard mask layer; self-aligning etching to remove the polysilicon gate material layer exposed by the two oxide layers to form two separate polysilicon gates; and removing the oxide layer;

[0010] Forming a sidewall, the sidewall comprising an isolation sidewall and a side sidewall; the isolation sidewall fills the gap between the two polysilicon gates; the side sidewall covers the sidewalls of the two polysilicon gates away from the isolation sidewall;

[0011] Source and drain heavy doping ions are implanted into the substrate at a side of each of the side sidewalls away from the isolation sidewall to form a first heavily doped region and a second heavily doped region.

[0012] Further, forming the two oxide layers by a self-aligned etching process specifically includes:

[0013] Growing an oxide material layer, the oxide material layer covers the surface of the hard mask layer and the surface of the polysilicon gate material layer exposed by the opening, and the oxide material layer forms a recess in the middle area of ​​the opening;

[0014] The oxide material layer is self-alignedly etched to remove the oxide material layer above the upper surface of the hard mask layer and the oxide material layer below the recess to expose the polysilicon gate material layer of a preset width. The oxide material layer after the self-aligned etching is defined as the oxide layer.

[0015] Furthermore, after removing the oxide layer and before forming the sidewall, the preparation method further includes:

[0016] Light doping is performed into the substrate to form a first lightly doped region and a second lightly doped region; the first lightly doped region is located in the substrate below the gap between the two polysilicon gates; the second lightly doped region is located in a storage well in the substrate on one side of each of the two polysilicon gates away from the gap.

[0017] Furthermore, after providing the substrate and before forming the charge storage layer, the preparation method further includes:

[0018] Forming a pad oxide layer on the surface of the substrate, and performing ion implantation on the substrate to form a storage well;

[0019] The pad oxide layer formed on the entire surface of the substrate is removed by an etching process.

[0020] Furthermore, forming the sidewall specifically includes:

[0021] Growing a spacer material layer, wherein the spacer material layer fills the gap between the two polysilicon gates, and the spacer material layer also covers the upper surfaces and side surfaces of the two polysilicon gates and the surface of the charge storage layer;

[0022] The sidewall material layer is etched in a self-aligned manner, and the remaining sidewall material layer is defined as the sidewall.

[0023] The present invention further provides a SONOS storage device, the SONOS storage device comprising a plurality of storage units, the storage units comprising:

[0024] A substrate, on which a first storage tube and a second storage tube are formed; the first storage tube comprises a charge storage layer 1 and a polysilicon gate 1 from bottom to top on the substrate; the second storage tube comprises a charge storage layer 2 and a polysilicon gate 2 from bottom to top on the substrate;

[0025] Sidewalls, the sidewalls include isolation sidewalls and side sidewalls; the side sidewalls include sidewall 1 and sidewall 2; the isolation sidewalls fill the gap between the polysilicon gate 1 and the polysilicon gate 2; the sidewall 1 covers the sidewall of the polysilicon gate 1 away from the isolation sidewall; the sidewall 2 covers the sidewall of the polysilicon gate 2 away from the isolation sidewall;

[0026] A first heavily doped region and a second heavily doped region, wherein the first heavily doped region is located in the substrate on a side of the sidewall 1 away from the isolation sidewall, and the second heavily doped region is located in the substrate on a side of the sidewall 2 away from the isolation sidewall.

[0027] Furthermore, the storage unit also includes:

[0028] A first lightly doped region, wherein the first lightly doped region is located in the substrate below the gap between the first polysilicon gate and the second polysilicon gate;

[0029] A second lightly doped region, wherein the second lightly doped region is located in a storage well in the substrate on one side of the polysilicon gate 1 and the polysilicon gate 2 respectively away from the isolation sidewall.

[0030] Furthermore, the first heavily doped region serves as the source region of the first storage tube, and the first lightly doped region serves as the drain region of the first storage tube; moreover, the first lightly doped region also serves as the source region of the second storage tube, and the second heavily doped region serves as the drain region of the second storage tube.

[0031] Furthermore, one of the storage units is composed of two storage tubes, namely the first storage tube and the second storage tube; wherein when one storage tube is read, the other storage tube is forced to be turned on or off to act as a selection tube.

[0032] Furthermore, the storage unit further includes: an interlayer dielectric layer, the interlayer dielectric layer covers the substrate, the sidewalls, the polysilicon gate 1 and the polysilicon gate 2; a plurality of contact holes are formed in the interlayer dielectric layer, the contact holes are filled with metal to lead out the electrical signals corresponding to each electrode;

[0033] The first contact hole penetrates the interlayer dielectric layer to expose the first heavily doped region; in the first storage tube, the second contact hole penetrates the interlayer dielectric layer to expose the polysilicon gate 1; in the second storage tube, the third contact hole penetrates the interlayer dielectric layer to expose the polysilicon gate 2; and the fourth contact hole penetrates the interlayer dielectric layer to expose the second heavily doped region.

[0034] Compared with the prior art, the present invention has the following beneficial effects:

[0035] The present invention provides a SONOS memory device and a preparation method thereof. The preparation method comprises: providing a substrate, sequentially forming a charge storage layer, a polysilicon gate material layer and a hard mask layer on the surface of the substrate; etching the hard mask layer to form an opening to define the total channel length of two storage tubes; forming two discrete oxide layers in the opening by a self-aligned etching process; etching and removing the hard mask layer; self-aligned etching and removing the polysilicon gate material layers exposed by the two oxide layers to form two discrete polysilicon gates; and removing the oxide layer; forming side walls, the side walls comprising an isolation side wall and a side side wall; the isolation side wall fills the gap between the two polysilicon gates; the side side wall covers the side walls of the two polysilicon gates on the side away from the isolation side wall; and performing source and drain heavy doping ion implantation into the substrate on the side of the side side wall away from the isolation side wall to form a first heavily doped region and a second heavily doped region.

[0036] The present invention provides a novel two-tube two-bit SONOS memory device and a preparation method thereof, which can increase the storage density, and each storage unit can store two bits of data. The source end shared by the two storage tubes and the manufacturing process of the heavily doped source end are omitted, and the side walls of the two storage tubes close to the source end are omitted. The isolation side walls are directly used to isolate the two storage tubes and fill the gap between the two storage tubes, which can effectively reduce the area of ​​the storage unit. The two storage tubes are formed using a self-alignment process, and the consistency is higher than that of the existing process, which is conducive to improving the uniformity of the storage unit and facilitating the control of the interference of the operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 A schematic diagram of a SONOS storage device.

[0038] Figure 2 The present invention is a schematic flow chart of a method for preparing a SONOS memory device according to an embodiment of the present invention.

[0039] Figure 3 It is a schematic diagram of a method for preparing a SONOS memory device according to an embodiment of the present invention after a pad oxide layer is formed.

[0040] Figure 4 It is a schematic diagram after forming a charge storage layer, a polysilicon gate material layer and a hard mask layer in the method for preparing a SONOS memory device according to an embodiment of the present invention.

[0041] Figure 5 It is a schematic diagram of a method for manufacturing a SONOS memory device according to an embodiment of the present invention after an opening is formed in a hard mask layer.

[0042] Figure 6 It is a schematic diagram of the method for preparing a SONOS memory device according to an embodiment of the present invention after an oxide material layer is formed.

[0043] Figure 7 It is a schematic diagram of the method for preparing a SONOS memory device according to an embodiment of the present invention after an oxide layer is formed.

[0044] Figure 8 It is a schematic diagram of the method for preparing a SONOS memory device according to an embodiment of the present invention after removing the hard mask layer.

[0045] Fig. 9 It is a schematic diagram of forming two separate polysilicon gates in the method for preparing a SONOS memory device according to an embodiment of the present invention.

[0046] Fig.10 It is a schematic diagram of a SONOS memory device after light doping implantation in a method for preparing the SONOS memory device according to an embodiment of the present invention.

[0047] Fig.11 It is a schematic diagram of a method for preparing a SONOS memory device according to an embodiment of the present invention after a spacer material layer is formed.

[0048] Fig.12 It is a schematic diagram of a method for manufacturing a SONOS memory device according to an embodiment of the present invention after forming a sidewall spacer.

[0049] Fig.13 It is a schematic diagram of the source and drain after heavy doping in the method for preparing a SONOS memory device according to an embodiment of the present invention.

[0050] Fig.14 It is a schematic diagram of a method for manufacturing a SONOS memory device according to an embodiment of the present invention after forming a contact hole.

[0051] The reference numerals are as follows:

[0052] 01-substrate; 02-storage well; 03-pad oxide layer; 04-charge storage layer; 41-charge storage layer one; 42-charge storage layer two; 05-polysilicon gate material layer; 05'-polysilicon gate; 51-polysilicon gate one; 52-polysilicon gate two; 06-hard mask layer; 07-oxide material layer; 07'-oxide layer; 08-sidewall material layer; 08'-sidewall; 80-isolation sidewall; 81-sidewall one; 82-sidewall two; a-first lightly doped region; LDD-second lightly doped region; P1-first heavily doped region; P2-second heavily doped region; 10-first contact hole; 11-second contact hole; 12-third contact hole; 13-fourth contact hole. DETAILED DESCRIPTION

[0053] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the drawings are in a very simplified form and use an inaccurate scale, which is only used to facilitate and clearly assist in explaining the purpose of the embodiments of the present invention. In the drawings, for clarity, the sizes of layers, regions, and components and their relative sizes may be exaggerated. The same reference numerals throughout represent the same elements.

[0054] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present application necessarily has the first element, component, region, layer or part.

[0055] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0056] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present application. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0057] The embodiment of the present invention provides a method for preparing a SONOS memory device, such as Figure 2 As shown, including:

[0058] Step S1, providing a substrate, and sequentially forming a charge storage layer, a polysilicon gate material layer and a hard mask layer on the surface of the substrate;

[0059] Step S2, etching the hard mask layer to form an opening to define the total channel length of the two storage tubes;

[0060] Step S3, forming two separate oxide layers in the opening by using a self-aligned etching process;

[0061] Step S4, etching and removing the hard mask layer; self-aligning etching and removing the polysilicon gate material layer exposed by the two oxide layers to form two separate polysilicon gates; and removing the oxide layer;

[0062] Step S5, forming a sidewall, wherein the sidewall includes an isolation sidewall and a side sidewall; the isolation sidewall fills the gap between the two polysilicon gates; the side sidewall covers the sidewalls of the two polysilicon gates away from the isolation sidewall;

[0063] Step S6, performing source and drain heavy doping ion implantation into the substrate on a side of each of the side sidewalls away from the isolation sidewall to form a first heavily doped region and a second heavily doped region.

[0064] The following will introduce the SONOS memory device and the manufacturing method thereof provided in the embodiments of the present invention in detail in combination with the accompanying drawings. It should be noted that, in order to simplify the difficulty of drawing, the following embodiments and the accompanying drawings of the present invention are introduced by taking a memory cell forming a SONOS memory device as an example, and the actual situation may include a plurality of memory cells provided in the embodiments of the present invention in which the memory area includes two memory cells, but is not limited thereto.

[0065] The method for manufacturing any memory cell in a SONOS memory device will be described in detail below by combining the structural schematic diagram corresponding to each manufacturing step of the method for manufacturing any memory cell in a SONOS memory device provided in an embodiment of the present invention.

[0066] See also Figure 3 , Figure 3 Schematic diagram of the structure after providing a substrate 01 and forming a liner oxide layer 03 and a storage well 02 in the storage area in an embodiment of the present invention. Figure 3 As shown, the above step S01 is performed to provide a substrate 01, which provides a platform for various components included in a storage unit of a SONOS storage device to be formed subsequently. The substrate 01 can be any suitable substrate material known in the art, for example, it can be at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), carbon silicon (SiC), carbon germanium silicon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP) or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), or it can also be a double-sided polished silicon wafer, or a ceramic substrate such as alumina, a quartz or glass substrate, etc. Exemplarily, in this embodiment, the substrate 01 is, for example, a silicon wafer, and it is a doped silicon wafer, and its doping type can be determined according to the type of storage tube actually formed. In this embodiment, it is exemplarily set to a P-type doped substrate.

[0067] Next, an etching process, such as a dry etching process or a wet etching process, is used to form a plurality of grooves in the substrate 01, and a deposition process, such as a chemical vapor deposition process, a physical vapor deposition process, and an atomic layer deposition process, is used to fill each groove with an insulating material, such as silicon dioxide, to form a plurality of device isolation structures, such as a shallow trench isolation structure (STI), for isolating and defining active areas.

[0068] Afterwards, a deposition process, such as at least one of a chemical vapor deposition process, a physical vapor deposition process, and an atomic layer deposition process, is used to form a pad oxide layer 03 on the entire surface of the substrate 01, and ions are implanted into the substrate 01 region of the storage area to form a storage well 02 in the region. Whether to form an N-well or a P-well can be determined according to the type of storage tubes in the SONOS storage device. In the embodiment of the present invention, a P-well is exemplarily formed in the region to prepare for the subsequent formation of an N-channel storage tube in the region.

[0069] Then, if Figure 3 and Figure 4 As shown, the liner oxide layer 03 formed on the entire surface of the substrate 01 can be removed by an etching process, and a charge storage layer 04, a polysilicon gate material layer 05 and a hard mask layer 06 stacked in sequence are formed on the exposed surface of the substrate 01 by a deposition process, wherein the charge storage layer 04 can be a multi-layer film structure, such as an ONO stacking structure, but is not limited thereto; the hard mask layer 06 is, for example, a silicon nitride layer. The thickness of the charge storage layer 04 is, for example, 80 angstroms to 150 angstroms, the thickness of the polysilicon gate material layer 05 is, for example, 800 angstroms to 2000 angstroms, and the thickness of the hard mask layer 06 is, for example, 800 angstroms to 2000 angstroms.

[0070] Then, if Figure 5 As shown, the hard mask layer 06 is etched to form an opening to define the total channel length of the two storage tubes, and the hard mask layer 06 is etched using a photomask to expose the polysilicon gate material layer 05 .

[0071] Then, if Figure 6 As shown, an oxide material layer 07 is grown, and the oxide material layer 07 covers the surface of the hard mask layer 06 and the surface of the polysilicon gate material layer 05 exposed by the opening, and the oxide material layer 07 forms a recess in the middle area of ​​the opening. The thickness of the oxide material layer 07 defines the channel length of the SONOS tube. The thickness of the oxide material layer 07 is, for example, 50 angstroms to 100 angstroms.

[0072] Then, if Figure 7 As shown, the oxide material layer 07 is self-aligned etched to remove the oxide material layer 07 above the upper surface of the hard mask layer 06 and the oxide material layer 07 below the recess to expose the polysilicon gate material layer 05 of a preset width. The oxide material layer 07 after self-aligned etching is defined as an oxide layer 07'.

[0073] Then, if Figure 8 As shown, the hard mask layer 06 is removed by etching to expose the polysilicon gate material layer 05 .

[0074] Then, if Fig. 9 As shown, the polysilicon gate material layer 05 is self-aligned and etched, and the polysilicon gate material layer 05 not covered by the oxide layer 07' is etched away by a dry etching process or a wet etching process to expose the charge storage layer 04. The remaining polysilicon gate material layer 05 is etched to form two separate polysilicon gates 05'. The two storage tubes are formed using a self-aligned process, and the consistency is higher than that of the existing process, which is conducive to improving the uniformity of the storage unit and facilitating the control of operation interference.

[0075] Then, if Fig.10 As shown, the oxide layer 07' is removed; a light doping injection is performed into the substrate 01, specifically, a light doping injection is performed between the two storage tubes to form a first lightly doped region a in the substrate 01; at the same time, a light doping injection is performed into the storage well 02 outside the two polysilicon gates 05' (each on a side away from the first lightly doped region a) to form a second lightly doped region LDD.

[0076] Then, if Fig.11 As shown, a spacer material layer 08 is grown, and the spacer material layer 08 fills the gap between the two storage tubes (i.e., the two polysilicon gates 05') above the first lightly doped region a, and the spacer material layer 08 also covers the upper surface and side surfaces of the two polysilicon gates 05' and the surface of the charge storage layer 04. The spacer material layer 08 can be a silicon oxide-silicon nitride-silicon oxide composite layer, or a silicon oxide layer. The spacer material layer 08 can be grown using a deposition process, such as at least one of a chemical vapor deposition process, a physical vapor deposition process, and an atomic layer deposition process.

[0077] Then, if Fig.12As shown, the sidewall material layer 08 is self-alignedly etched, and the remaining sidewall material layer 08 is defined as the sidewall 08'. The sidewall 08' includes an isolation sidewall 80 and a side sidewall. The side sidewall includes a sidewall 1 81 and a sidewall 2 82. The isolation sidewall 80 fills the gap between the two storage tubes (i.e., the two polysilicon gates 05') above the first lightly doped region a. The side sidewall covers the side surfaces of the outer sides of the two polysilicon gates 05' (each away from the isolation sidewall 80). The side sidewall also covers the surface of the charge storage layer 04 of a portion of the width of each side of the two polysilicon gates 05' away from the isolation sidewall 80. The charge storage layer 04 on each side of the two side sidewalls away from the isolation sidewall 80 is removed by etching, exposing the surface of the substrate 01. The two polysilicon gates 05' are the polysilicon gate 1 51 and the polysilicon gate 2 52. The two storage tubes are formed using a self-alignment process, which has higher consistency than existing processes, is beneficial to improving the uniformity of the storage unit and facilitates controlling operational interference.

[0078] Then, if Fig.13 As shown, heavily doped ions are implanted into the substrate 01 on the two side sidewalls away from the middle isolation sidewall 80 to form a first heavily doped region P1 and a second heavily doped region P2.

[0079] Then, if Fig.13 and Fig.14 As shown, an interlayer dielectric layer (not shown) is formed, and the interlayer dielectric layer covers the substrate 01, the sidewalls and the two polysilicon gates. A contact hole is formed in the interlayer dielectric layer, and a metal (plug) is filled in the contact hole to lead out the electrical signals of each pole. Exemplarily, the SONOS memory is composed of a plurality of storage units, and the storage unit includes a first storage tube and a second storage tube. The first heavily doped region P1 serves as the source region of the first storage tube, and the first lightly doped region a serves as the drain region of the first storage tube; moreover, the first lightly doped region a also serves as the source region of the second storage tube, and the second heavily doped region P2 serves as the drain region of the second storage tube. The first contact hole 10 penetrates the interlayer dielectric layer to expose the first heavily doped region P1 and leads out the first heavily doped region P1 through the metal in the contact hole. In the first storage tube, the second contact hole 11 penetrates the interlayer dielectric layer to expose the polysilicon gate 151 and leads out the polysilicon gate 151 through the metal in the contact hole. In the second storage tube, the third contact hole 12 penetrates the interlayer dielectric layer to expose the second polysilicon gate 52 and leads the second polysilicon gate 52 out through the metal in the contact hole. The fourth contact hole 13 penetrates the interlayer dielectric layer to expose the second heavily doped region P2 and leads the second heavily doped region P2 out through the metal in the contact hole.

[0080] The present invention provides a novel method for preparing a two-tube two-bit SONOS memory device, wherein each memory cell can store two bits of data, thereby increasing the storage density. The source end shared by the two memory cells and the manufacturing process of heavily doping the source end are omitted, and the side walls of the two memory cells close to the source end are omitted. The two memory cells are directly isolated by an isolation side wall 80, which can effectively reduce the area of ​​the memory cell. The two memory cells are formed by a self-alignment process, and the consistency is higher than that of the existing process, which is conducive to improving the uniformity of the memory cell and facilitating the control of the interference of the operation.

[0081] The present invention also provides a SONOS storage device, such as Fig.14 As shown, the SONOS memory device includes a plurality of memory cells, and the memory cells include:

[0082] A substrate 01, on which a first storage tube and a second storage tube are formed; the first storage tube includes a charge storage layer 1 41 and a polysilicon gate 1 51 from bottom to top on the substrate 01; the second storage tube includes a charge storage layer 2 42 and a polysilicon gate 2 52 from bottom to top on the substrate 01; the charge storage layer 1 41 and the charge storage layer 2 42 are connected to form a charge storage layer 04;

[0083] The sidewalls include an isolation sidewall 80 and a side sidewall; the side sidewalls include a sidewall 1 81 and a sidewall 2 82; the sidewalls are located on the charge storage layer 04, and the isolation sidewall 80 fills the gap between the polysilicon gate 1 51 and the polysilicon gate 2 52; the sidewall 1 81 covers the sidewall of the polysilicon gate 1 51 away from the isolation sidewall 80; the sidewall 2 82 covers the sidewall of the polysilicon gate 2 52 away from the isolation sidewall 80; the sidewall 1 81 also covers a portion of the width of the charge storage layer 04 surface on the side of the polysilicon gate 1 51 away from the isolation sidewall 80; the sidewall 2 82 also covers a portion of the width of the charge storage layer 04 surface on the side of the polysilicon gate 2 52 away from the isolation sidewall 80;

[0084] The first heavily doped region P1 and the second heavily doped region P2 are located in the substrate 01 on the side of the first sidewall 81 away from the isolation sidewall 80 , and the second heavily doped region P2 is located in the substrate 01 on the side of the second sidewall 82 away from the isolation sidewall 80 .

[0085] Specifically, the memory cell may further include: a first lightly doped region a and a second lightly doped region LDD, wherein the first lightly doped region a is located in the substrate 01 below the gap between the polysilicon gate 1 51 and the polysilicon gate 2 52. The second lightly doped region LDD is located in the memory well 02 on one side of the polysilicon gate 1 51 and the polysilicon gate 2 52, respectively, away from the isolation sidewall 80.

[0086] The first heavily doped region P1 serves as the source region of the first storage tube, and the first lightly doped region a serves as the drain region of the first storage tube; moreover, the first lightly doped region a also serves as the source region of the second storage tube, and the second heavily doped region P2 serves as the drain region of the second storage tube. In the present invention, a storage unit is composed of two storage tubes (a first storage tube and a second storage tube), and when one storage tube is read, the other storage tube is forced to be turned on or off to act as a selection tube. The present invention provides a novel two-tube two-bit SONOS storage unit structure, and each storage unit stores two bits of data, which can increase the storage density. The source end shared between the two storage tubes and the manufacturing process of heavily doping the source end are omitted, and the side walls of the two storage tubes close to the source end are omitted. The two storage tubes are directly isolated by using the isolation side wall, which can effectively reduce the area of ​​the storage unit. The two storage tubes are formed using a self-alignment process, and the consistency is higher than that of the existing process, which is conducive to improving the uniformity of the storage unit and facilitating the control of the interference of the operation.

[0087] In this embodiment, the substrate 01 is, for example, a silicon wafer, and it is a doped silicon wafer. The charge storage layer 04 can be a multi-layer film structure, such as an ONO (first oxide layer, silicon nitride layer, and second oxide layer from bottom to top) stacked structure. A storage unit is composed of two storage tubes (first storage tube and second storage tube). The storage tube device uses a gate stack layer structure of silicon substrate-tunneling oxide layer-silicon nitride layer-blocking oxide layer-polysilicon (Silicon-Oxide-Nitride-Oxide-Silicon), which is a charge trap type memory. Specifically, the silicon substrate corresponds to Fig.14 The substrate 01 in the storage pipe region, the tunneling oxide layer corresponds to the first oxide layer in the charge storage layer 04, and the silicon nitride layer corresponds to Fig.14 The silicon nitride layer in the charge storage layer 04, the blocking oxide layer corresponds to Fig.14 The second oxide layer is located in the charge storage layer 04. When storing data, the charge (electron or hole) is injected into the silicon nitride layer through the tunneling oxide layer by using the quantum tunneling effect or the hot carrier injection effect. The charge entering the silicon nitride layer is blocked by the blocking oxide layer and captured by the charge trap in the silicon nitride layer, thereby storing data information in the SONOS memory; when erasing data, the charge is moved from the silicon nitride layer to the silicon substrate through the tunneling oxide layer, thereby erasing the data information in the SONOS memory.

[0088] The storage unit also includes: an interlayer dielectric layer (not shown), which covers the substrate 01, the sidewalls and the two polysilicon gates. Contact holes are formed in the interlayer dielectric layer, and the contact holes are filled with metal (plugs) to lead out the electrical signals of each pole. The first contact hole 10 penetrates the interlayer dielectric layer to expose the first heavily doped region P1 and leads out the first heavily doped region P1 through the metal in the contact hole. In the first storage tube, the second contact hole 11 penetrates the interlayer dielectric layer to expose the polysilicon gate 1 51 and leads out the polysilicon gate 1 51 through the metal in the contact hole. In the second storage tube, the third contact hole 12 penetrates the interlayer dielectric layer to expose the polysilicon gate 2 52 and leads out the polysilicon gate 2 52 through the metal in the contact hole. The fourth contact hole 13 penetrates the interlayer dielectric layer to expose the second heavily doped region P2 and leads out the second heavily doped region P2 through the metal in the contact hole.

[0089] In summary, the present invention provides a SONOS memory device and a preparation method thereof, the preparation method comprising: providing a substrate, sequentially forming a charge storage layer, a polysilicon gate material layer and a hard mask layer on the surface of the substrate; etching the hard mask layer to form an opening to define the total channel length of two storage tubes; forming two discrete oxide layers in the opening using a self-aligned etching process; etching and removing the hard mask layer; self-aligned etching and removing the polysilicon gate material layers exposed by the two oxide layers to form two discrete polysilicon gates; and removing the oxide layer; forming side walls, the side walls comprising an isolation side wall and a side side wall; the isolation side wall fills the gap between the two polysilicon gates; the side side wall covers the side walls of the two polysilicon gates on one side away from the isolation side wall; and performing source and drain heavy doping ion implantation into the substrate on one side of the side side wall away from the isolation side wall to form a first heavily doped region and a second heavily doped region.

[0090] The present invention provides a novel two-tube two-bit SONOS memory device and a preparation method thereof, which can increase the storage density, and each storage unit can store two bits of data. The source end shared by the two storage tubes and the manufacturing process of the heavily doped source end are omitted, and the side walls of the two storage tubes close to the source end are omitted. The isolation side walls are directly used to isolate the two storage tubes and fill the gap between the two storage tubes, which can effectively reduce the area of ​​the storage unit. The two storage tubes are formed using a self-alignment process, and the consistency is higher than that of the existing process, which is conducive to improving the uniformity of the storage unit and facilitating the control of the interference of the operation.

[0091] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the method disclosed in the embodiment, since it corresponds to the device disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0092] The above description is only a description of the preferred embodiment of the present invention, and is not any limitation on the scope of rights of the present invention. Any technical personnel in this field can make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims

1. A method for preparing a SONOS memory device, characterized in that: include: Providing a substrate, and sequentially forming a charge storage layer, a polysilicon gate material layer and a hard mask layer on the surface of the substrate; Etching the hard mask layer to form an opening to define a total channel length of two storage tubes; forming two separate oxide layers in the opening using a self-aligned etching process; Etching and removing the hard mask layer; Self-aligned etching is used to remove the polysilicon gate material layer exposed by the two oxide layers to form two separate polysilicon gates; and removing the oxide layer; Forming a sidewall, the sidewall comprising an isolation sidewall and a side sidewall; the isolation sidewall fills the gap between the two polysilicon gates; the side sidewall covers the sidewalls of the two polysilicon gates away from the isolation sidewall; Source and drain heavy doping ions are implanted into the substrate at a side of each of the side sidewalls away from the isolation sidewall to form a first heavily doped region and a second heavily doped region.

2. The method for preparing a SONOS memory device according to claim 1, wherein: The two oxide layers are formed by a self-aligned etching process, specifically comprising: Growing an oxide material layer, the oxide material layer covers the surface of the hard mask layer and the surface of the polysilicon gate material layer exposed by the opening, and the oxide material layer forms a recess in the middle area of ​​the opening; The oxide material layer is self-alignedly etched to remove the oxide material layer above the upper surface of the hard mask layer and the oxide material layer below the recess to expose the polysilicon gate material layer of a preset width. The oxide material layer after the self-aligned etching is defined as the oxide layer.

3. The method for preparing a SONOS memory device according to claim 1, wherein: After removing the oxide layer and before forming the sidewall, the preparation method further comprises: Light doping is performed into the substrate to form a first lightly doped region and a second lightly doped region; the first lightly doped region is located in the substrate below the gap between the two polysilicon gates; the second lightly doped region is located in a storage well in the substrate on one side of each of the two polysilicon gates away from the gap.

4. The method for preparing a SONOS memory device according to claim 1, wherein: After providing the substrate and before forming the charge storage layer, the preparation method further includes: Forming a pad oxide layer on the surface of the substrate, and performing ion implantation on the substrate to form a storage well; The pad oxide layer formed on the entire surface of the substrate is removed by an etching process.

5. The method for preparing a SONOS memory device according to claim 1, wherein: Forming the sidewall specifically includes: Growing a spacer material layer, wherein the spacer material layer fills the gap between the two polysilicon gates, and the spacer material layer also covers the upper surfaces and side surfaces of the two polysilicon gates and the surface of the charge storage layer; The sidewall material layer is etched in a self-aligned manner, and the remaining sidewall material layer is defined as the sidewall.

6. A SONOS memory device, comprising a plurality of memory cells, characterized in that: The storage unit comprises: A substrate, on which a first storage tube and a second storage tube are formed; the first storage tube comprises a charge storage layer 1 and a polysilicon gate 1 from bottom to top on the substrate; the second storage tube comprises a charge storage layer 2 and a polysilicon gate 2 from bottom to top on the substrate; Sidewalls, the sidewalls include isolation sidewalls and side sidewalls; the side sidewalls include sidewall 1 and sidewall 2; the isolation sidewalls fill the gap between the polysilicon gate 1 and the polysilicon gate 2; the sidewall 1 covers the sidewall of the polysilicon gate 1 away from the isolation sidewall; the sidewall 2 covers the sidewall of the polysilicon gate 2 away from the isolation sidewall; A first heavily doped region and a second heavily doped region, wherein the first heavily doped region is located in the substrate on a side of the sidewall 1 away from the isolation sidewall, and the second heavily doped region is located in the substrate on a side of the sidewall 2 away from the isolation sidewall.

7. The SONOS memory device according to claim 6, wherein: The storage unit also includes: A first lightly doped region, wherein the first lightly doped region is located in the substrate below the gap between the first polysilicon gate and the second polysilicon gate; A second lightly doped region, wherein the second lightly doped region is located in a storage well in the substrate on one side of the polysilicon gate 1 and the polysilicon gate 2 respectively away from the isolation sidewall.

8. The SONOS memory device according to claim 7, wherein: The first heavily doped region serves as the source region of the first storage tube, and the first lightly doped region serves as the drain region of the first storage tube; moreover, the first lightly doped region also serves as the source region of the second storage tube, and the second heavily doped region serves as the drain region of the second storage tube.

9. The SONOS memory device according to claim 6, wherein: One of the storage units is composed of two storage tubes, namely the first storage tube and the second storage tube; wherein when one storage tube is read, the other storage tube is forced to be turned on or off to act as a selection tube.

10. The SONOS memory device according to claim 6, wherein: The storage unit further includes: an interlayer dielectric layer, the interlayer dielectric layer covers the substrate, the sidewall, the polysilicon gate 1 and the polysilicon gate 2; a plurality of contact holes are formed in the interlayer dielectric layer, the contact holes are filled with metal to lead out the electrical signals corresponding to each electrode; The first contact hole penetrates the interlayer dielectric layer to expose the first heavily doped region; in the first storage tube, the second contact hole penetrates the interlayer dielectric layer to expose the polysilicon gate 1; in the second storage tube, the third contact hole penetrates the interlayer dielectric layer to expose the polysilicon gate 2; and the fourth contact hole penetrates the interlayer dielectric layer to expose the second heavily doped region.

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