MRAM (Magnetic Random Access Memory) storage device based on vertically stacked 1T1M and preparation method thereof

Abstract

The invention provides a vertically stacked 1T1M-based MRAM (Magnetic Random Access Memory) storage device and a preparation method thereof. The device is formed by vertically stacking field effect transistors (FETs) on a magnetic tunnel junction (MTJ); the magnetic tunnel junction is composed of multiple layers of stacked magnetic materials growing on a Si / SiO2 substrate, the magnetic tunnel junction sequentially comprises a bottom electrode, a pinning layer, a reference layer, a barrier layer, a free layer and a top electrode from bottom to top, and the exterior of the magnetic tunnel junction is surrounded by a first passivation layer. The field effect transistor is a vertical channel FET adopting a surrounding channel (CAA) configuration, and is formed by vertically stacking a first metal layer, an isolation layer and a second metal layer from bottom to top; the first metal layer of the field effect transistor is connected with the top electrode of the magnetic tunnel junction through the interconnection layer to form a 1T1M vertically stacked vertical structure storage device, so that the storage density of the MRAM can be effectively improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to an MRAM storage device based on vertically stacked 1T1M and a preparation method thereof. Background Art

[0002] Magnetic Random Access Memory (MRAM) is a non-volatile storage technology that uses magnetoresistance effect to store data. The core of MRAM is a magnetic tunnel junction (MTJ) composed of two ferromagnetic layers and a non-magnetic isolation layer. Among them, the magnetization direction of one ferromagnetic layer is fixed, called the fixed layer; the magnetization direction of the other ferromagnetic layer is variable, called the free layer. Data is stored in the magnetization direction of the free layer, and the data is read by detecting the resistance change of the MTJ. When the magnetization directions of the two layers are consistent, the resistance is low, and when they are inconsistent, the resistance is high. MRAM usually includes a 1T1M structure composed of interconnected magnetic tunnel junctions and driver transistors. In the existing 1T1M structure, the driver transistor uses a traditional planar transistor. The size of the traditional planar FET (6F2-20 F2) cannot be further miniaturized due to the structure of the transistor itself, which also restricts the scaling of MRAM, and thus cannot achieve high-density MRAM. Therefore, how to reduce the size of the transistor and improve the storage density of MRAM is a technical problem that technicians in this professional field need to solve. Summary of the invention

[0003] In view of this, an object of the present invention is to provide an MRAM storage device based on vertically stacked 1T1M and a preparation method thereof, so as to effectively improve the storage density of MRAM.

[0004] To achieve the above-mentioned purpose, the present invention adopts the following technical scheme: an MRAM storage device based on vertical stacking 1T1M, comprising a vertical structure formed by stacking a magnetic tunnel junction MTJ and a field effect transistor up and down, wherein the magnetic tunnel junction MTJ is composed of a multi-layer stacked magnetic material grown on a Si / SiO2 substrate, wherein the order of the layers from bottom to top is a bottom electrode (2), a pinning layer (3), a reference layer (4), a barrier layer (5), a free layer (6) and a top electrode (8), and the outside of the magnetic tunnel junction MTJ is surrounded by a first passivation layer (7); and the field effect transistor is a vertical channel FET with a surround channel CAA configuration.

[0005] In a preferred embodiment, an interconnection layer (9) is located above the top electrode (8).

[0006] In a preferred embodiment, the field effect transistor is prepared above the magnetic tunnel junction MTJ, and the field effect transistor includes: a stacked structure, and the stacked structure includes a first metal layer (10), a second passivation layer (11) and a second metal layer (12).

[0007] In a preferred embodiment, a groove is etched in the stacked structure, the groove passes through the first metal layer (10), the second passivation layer (11) and the second metal layer (12), and the groove partially passes through the first metal layer (10), and a channel layer (13), a gate dielectric layer (14) and a gate electrode layer (15) are arranged in the groove; the channel layer (13) forms source-drain contact with the first metal layer (10) and the second metal layer (12), respectively, one of the first metal layer (10) and the second metal layer (12) is a source, and the other is a drain; the channel layer (13) contacts the first metal layer (10) and the second metal layer (12), respectively, and the gate dielectric layer (14) is arranged between the semiconductor channel layer (13) and the gate electrode layer (15).

[0008] In a preferred embodiment, the first metal layer (10) of the field effect transistor is connected to the top electrode (8) of the magnetic tunnel junction MTJ via an interconnection layer (9).

[0009] In a preferred embodiment, the characteristic size area of ​​the MRAM storage device based on vertical stacking 1T1M is 4F 2 .

[0010] In a preferred embodiment, the MRAM storage device based on vertical stacking 1T1M uses the leakage current of the vertical channel FET with the surrounding channel CAA structure above as the driving current to control the magnetization state flipping of the free layer of the magnetic tunnel junction MTJ below. Due to its vertical stacking structure, its plane size reaches 4F. 2 , improve integration.

[0011] The present invention also provides a method for preparing an MRAM storage device based on vertical stacking 1T1M, and prepares the MRAM storage device based on vertical stacking 1T1M; the method comprises the following steps: Step S1: cleaning the Si / SiO2 (1) insulating substrate; Step S2: defining the bottom electrode region on the substrate by electron beam lithography, and forming the bottom electrode by physical vapor deposition (2) Step S3: Based on step S2, a MTJ thin film stack including a pinned layer (3), a reference layer (4), a barrier layer (5), and a free layer (6) is grown by magnetron sputtering; Step S4: Based on step S3, an etching area is defined by electron beam lithography, and a columnar magnetic tunnel junction MTJ is etched by dry etching; Step S5: Based on step S4, a first passivation layer (7) is deposited by physical vapor deposition, and then the photolithography mask glue and the passivation layer above it are removed; Step S6: Based on step S5, a stripping region is defined by electron beam lithography, and a top electrode (8) and an interconnection layer (9) are deposited by physical vapor deposition; Step S7: Based on step S6, a first metal layer (10) of a vertical surrounding channel field effect transistor is prepared by magnetron sputtering, and connected to the top electrode of the magnetic tunnel junction MTJ through an interconnection layer; Step S8: Based on step S7, a second passivation layer (11) is deposited by physical vapor deposition; Step S9: Based on step S8, a second metal layer (12) of a vertical surrounding channel field effect transistor is prepared by magnetron sputtering; Step S10: Spin-coat photoresist on the basis of step S9, use electron beam lithography to define the etching area, use dry etching to etch out the groove, and then remove the photoresist mask; Step S11: Based on step S10, a channel layer (13) is deposited on the surface and sidewall of the groove by atomic layer deposition; Step S12: Spin-coating photoresist based on step S11, using electron beam lithography to define the etching area, using wet etching to isolate the device, and then removing the photoresist mask glue; Step S13: Based on step S12, a gate dielectric layer (14) is deposited on the surface and sidewall of the groove by atomic layer deposition; Step S14: Based on step S13, a gate electrode layer (15) is deposited on the surface and sidewall of the groove by using atomic layer deposition.

[0012] In a preferred embodiment, in step S3, the material of the pinning layer (3) includes: Ru, Co, [Pt / Co] x , Pt, Ta; the materials used for the reference layer (4) include: CoFeB, Ta, W, [Co / Pt] x , Co; the material of the barrier layer (5) is MCO; the material of the free layer (6) includes: MCO, CoFeB, Ta.

[0013] In a preferred embodiment, the materials of the first passivation layer (7) and the second passivation layer (11) are one or more of SiN, SiO2, Al2O3, HfO2, the first passivation layer (7) isolates the side wall of the magnetic tunnel junction MTJ, and the second passivation layer (11) isolates the source and drain.

[0014] Compared with the prior art, the present invention has the following beneficial effects: The present invention adopts a vertical oxide semiconductor transistor with a surround channel (CAA) configuration connected to the MTJ, which has a smaller occupied area (4F2) compared with the traditional 1T1M using a planar transistor, and improves the integration and storage density.

[0015] The present invention uses atomic layer deposition technology to deposit the channel layer, gate dielectric layer and gate electrode layer. The atomic layer deposition technology has excellent three-dimensional conformality, so that the channel layer, gate dielectric layer and gate layer can be uniformly deposited on the surface of the groove.

[0016] The present invention uses oxide semiconductor as the channel material of the transistor. Oxide semiconductor has the characteristics of wide bandgap, high mobility, low leakage current and low temperature deposition. It not only shows excellent stability and response speed in high-performance display technology, but also can realize more compact device design in the field of three-dimensional storage. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Attached Figure 1 This is a schematic diagram of the stack structure of the MTJ thin film grown on the substrate of the present invention; Attached Figure 2 This is a schematic diagram of etching a columnar MTJ structure according to the present invention; Attached Figure 3 This is a schematic diagram of the device structure after the first passivation layer is deposited in the present invention; Attached Figure 4 This is a schematic diagram of the device structure after depositing the top electrode and the interconnection layer of the present invention; Attached Figure 5 This is a schematic diagram of the device structure after the first metal layer is deposited in the present invention; Attached Figure 6 This is a schematic diagram of the device structure after the second passivation layer is deposited in the present invention; Attached Figure 7 This is a schematic diagram of the device structure after the second metal layer is deposited in the present invention; Attached Figure 8 This is a schematic diagram of the device structure after etching the channel groove of the present invention; Attached Fig. 9 It is a schematic diagram of the device structure after the channel layer is deposited in the present invention; Attached Fig.10 This is a schematic diagram of the device structure after the gate dielectric layer is deposited in the present invention; Attached Fig.11 This is a schematic diagram of the device structure after the gate layer is deposited in the present invention; In the figure: 1-Si / SiO2 substrate; 2-bottom electrode; 3-pinning layer; 4-reference layer; 5-barrier layer; 6-free layer; 7-first passivation layer; 8-top electrode; 9-interconnection layer; 10-first metal layer; 11-second passivation layer; 12-second metal layer; 13-channel layer; 14-gate dielectric layer; 15-gate electrode layer. DETAILED DESCRIPTION

[0018] The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0019] It should be noted that the following detailed descriptions are illustrative and are intended to provide further explanation of the present application. Unless otherwise specified, all technical and scientific terms used herein have the same meanings as those commonly understood by those skilled in the art to which the present application belongs.

[0020] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application; as used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, they indicate the presence of features, steps, operations, devices, components and / or their combinations.

[0021] like Figure 1-11 As shown, an MRAM storage device based on vertical stacking 1T1M includes a vertical structure formed by stacking a magnetic tunnel junction MTJ and a field effect transistor up and down, wherein the magnetic tunnel junction is composed of a multi-layer stacked magnetic material grown on a Si / SiO2 substrate, and the order of the layers from bottom to top are a bottom electrode, a pinned layer, a reference layer, a barrier layer, a free layer, and a top electrode, and the outside is surrounded by a first passivation layer; the field effect transistor is a vertical channel FET with a surround channel (CAA) configuration.

[0022] The magnetic tunnel junction MTJ, see Figure 3 , which is composed of multi-layer stacked magnetic materials grown on a Si / SiO2 substrate and formed into a vertical internal multi-layer material through a series of micro-nano processing processes. The order of the layers from bottom to top is bottom electrode (2), pinned layer (3), reference layer (4), barrier layer (5), free layer (6), top electrode (8), and the outside is the first passivation layer (7). The internal multi-layer magnetic material contacts the external first passivation layer to form a magnetic tunnel junction MTJ, and the interconnection layer (9) is above the top electrode.

[0023] The field effect transistor is a vertical channel FET of a surround channel (CAA) configuration, which is prepared above the MTJ. The transistor structure comprises: a stacked structure, which comprises a first metal layer (10), a second passivation layer (11), and a second metal layer (12); a groove is etched in the stacked structure, the groove passes through the first metal layer, the second passivation layer, and the second metal layer, and the groove partially passes through the first metal layer, and a channel layer (13), a gate dielectric layer (14), and a gate electrode layer (15) are arranged in the groove; the channel layer forms source-drain contacts with the first metal layer and the second metal layer respectively, one of the first metal layer and the second metal layer is a source, and the other is a drain; the channel layer contacts the first metal layer and the second metal layer respectively, and the gate dielectric layer is arranged between the semiconductor channel layer and the gate electrode layer.

[0024] The first metal layer of the field effect transistor is connected to the top electrode of the magnetic tunnel junction through an interconnection layer.

[0025] The characteristic size area of ​​the vertically stacked 1T1M MRAM memory cell is 4F 2 .

[0026] The 1T1M vertical structure memory cell stacked up and down uses the leakage current of the vertical channel FET with a surround channel (CAA) configuration on the top as the driving current to control the magnetization state flipping of the free layer of the magnetic tunnel junction MTJ below. Due to its vertical stacking structure, its plane size can reach 4F. 2 , improve integration.

[0027] The method for preparing an MRAM storage device based on vertical stacking of 1T1M is to prepare the vertical structure storage device of 1T1M stacked up and down as described above, comprising the following steps: Step S1: cleaning the Si / SiO2 (1) insulating substrate; Step S2: defining the bottom electrode region on the substrate by electron beam lithography, and forming the bottom electrode by physical vapor deposition (2) Step S3: Based on step S2, a MTJ thin film stack including a pinned layer (3), a reference layer (4), a barrier layer (5), and a free layer (6) is grown by magnetron sputtering; Step S4: Based on step S3, an etching area is defined by electron beam lithography, and a columnar magnetic tunnel junction is etched by dry etching; Step S5: Based on step S4, a first passivation layer (7) is deposited by physical vapor deposition, and then the photolithography mask glue and the passivation layer above it are removed; Step S6: Based on step S5, a stripping region is defined by electron beam lithography, and a top electrode (8) and an interconnection layer (9) are deposited by physical vapor deposition; Step S7: Based on step S6, a first metal layer (10) of a vertical surround channel field effect transistor is prepared by magnetron sputtering, and connected to the MTJ top electrode through an interconnection layer; Step S8: Based on step S7, a second passivation layer (11) is deposited by physical vapor deposition; Step S9: Based on step S8, a second metal layer (12) of a vertical surrounding channel field effect transistor is prepared by magnetron sputtering; Step S10: Spin-coat photoresist on the basis of step S9, use electron beam lithography to define the etching area, use dry etching to etch out the groove, and then remove the photoresist mask; Step S11: Based on step S10, a channel layer (13) is deposited on the surface and sidewall of the groove by atomic layer deposition; Step S12: Spin-coating photoresist based on step S11 to define the etching area by electron beam lithography, and using wet etching to isolate the device, and then removing the photoresist mask glue; Step S13: Based on step S12, a gate dielectric layer (14) is deposited on the surface and sidewall of the groove by atomic layer deposition; Step S14: Based on step S13, a gate electrode layer (15) is deposited on the surface and sidewall of the groove by atomic layer deposition; Step S3: The pinning layer material includes: Ru, Co, [Pt / Co] x , Pt, Ta; the reference layer materials include: CoFeB, Ta, W, [Co / Pt] x , Co; the barrier layer material is MCO; the free layer material includes: MCO, CoFeB, Ta.

[0028] In steps S5 and S8, the materials of the first passivation layer and the second passivation layer are one or more of SiN, SiO2, Al2O3, HfO2, the first passivation layer isolates the MTJ sidewall, and the second passivation layer isolates the source and drain.

[0029] In steps S7 and S9, the materials of the first metal layer and the second metal layer are one or more of Ti, Mo, Au, ITO, and TiN.

[0030] The channel layer material in step S11 includes one or more of oxide semiconductor, polycrystalline silicon, and amorphous silicon; the oxide semiconductor is one or more of zinc oxide ZnO, indium oxide In2O3, tin oxide SnO2, gallium oxide Ga2O3, indium tin oxide ITO, indium zinc oxide IZO, indium gallium oxide IGO, indium gallium zinc oxide IGZO, and indium aluminum zinc oxide IAZO.

[0031] Step S13: The gate dielectric layer includes Al2O3, HfO2, ZrO2, La2O3, HfAlOx 、HfSiO x 、HfLaO x 、HfZrO x , or one or more of HfSiON.

[0032] In step S14, the gate layer material is one of IZO and ITO.

[0033] Furthermore, the specific process steps for preparing the above device are as follows: Step 1: Clean the Si / SiO2 substrate in a cleaning agent at 70 °C for 10 min. The cleaning agent is a mixed solution of deionized water / hydrogen peroxide / ammonium hydroxide in a volume ratio of 5:1:1. Then rinse in deionized water for 1 min to remove organic particles and adsorbents on the surface. Finally, blow dry the sample surface with a nitrogen gun.

[0034] Step 2: Prepare the MTJ bottom electrode on the substrate, including coating, baking, exposure, deposition, and stripping processes. (1) Spin-coat PMMA A4 photoresist based on step 1, with the coating parameters of 3000 rpm / 60 s, and bake at 180 °C for 90 s after spin coating; (2) Use Raith150 electron beam exposure system to define the bottom electrode area, and denature the electron beam glue in the exposure area; (3) Development: The developer is MIBK:IPA=1:3, the development time is 50 s, and the IPA fixation is 40 s. At this time, the denatured glue in the exposure area is dissolved in the developer, and the glue in the non-exposure area is retained, and the layout pattern is transferred to the sample; (4) Use an electron beam evaporation coating instrument to deposit a 60 nm bottom electrode; (5) Heat bath in the degumming solution NMP at 100 °C for 1 h, and finally soak in IPA for 5 min and blow dry with nitrogen.

[0035] Step 3: Based on step 2, a 150 nm thick MTJ thin film stack is formed by magnetron sputtering deposition of multiple metal layers including a pinning layer (3), a reference layer (4), a barrier layer (5), and a free layer (6).

[0036] Step 4: Make a columnar magnetic tunnel junction structure, including process steps such as coating, baking, exposure, and etching. (1) Spin-coat the mask ZEP electron beam glue on the basis of step 3, with the coating parameters of 500 rpm / 5 s + 2000 rpm / 2 min, and bake at 180 °C for 3 min after spin coating; (2) Use Raith150 electron beam exposure system to define the etching area, even if the electron beam glue in the exposure area is denatured; (3) Development: The developer is amyl acetate, the development time is 70 s, IPA fixation is 40 s, and nitrogen is blown dry. At this time, the denatured glue in the exposure area is dissolved in the developer, and the glue in the non-exposure area is retained, and the layout pattern is transferred to the sample; (4) Use ion beam etching IBE to etch a columnar magnetic tunnel junction with a height of 40 nm and a size of 100 nm~5 μm.

[0037] Step 5: Based on step 4, an electron beam evaporation coating apparatus is used to deposit a 50 nm first passivation layer to wrap the cylindrical magnetic tunnel junction to insulate its side walls and facilitate subsequent process steps; the ZEP glue is removed and the passivation layer above the ZEP glue is peeled off in a 100 °C hot bath in the degumming liquid NMP for 1 h, and finally, it is soaked in IPA for 5 min and blown dry with nitrogen.

[0038] Step 6: Deposit the MTJ top electrode and interconnect layer based on step 5, including coating, baking, exposure, deposition, and stripping processes. (1) Spin-coat PMMA A4 photoresist based on step 1, with a coating parameter of 3000 rpm / 60 s, and bake at 180 °C for 90 s after spin coating; (2) Use Raith150 electron beam exposure system to define the bottom electrode area, and denature the electron beam glue in the exposure area; (3) Development: The developer is MIBK:IPA=1:3, the development time is 50 s, and the IPA fixation is 40 s. At this time, the denatured glue in the exposure area is dissolved in the developer, while the glue in the non-exposure area is retained, and the layout pattern is transferred to the sample; (4) Use an electron beam evaporation coating instrument to deposit a 60 nm bottom electrode and a 60 nm interconnect layer; (5) Heat bath in the degumming solution NMP at 100 °C for 1 h, and finally soak in IPA for 5 min and blow dry with nitrogen.

[0039] Step 7: Prepare the first metal layer of the vertical surround channel field effect transistor above the interconnection layer, including coating, baking, exposure, deposition, stripping and other processes. (1) Spin-coat PMMA A4 photoresist on the basis of step 4, with the coating parameters of 3000rpm / 60s, and bake at 180℃ for 90s after spin coating; (2) Use Raith150 electron beam exposure system to define the etching area, and denature the electron beam glue in the exposure area; (3) Development: The developer is MIBK:IPA=1:3, the development time is 50s, and the IPA fixation is 40s. At this time, the denatured glue in the exposure area is dissolved in the developer, and the glue in the non-exposure area is retained, and the layout pattern is transferred to the sample; (4) Use magnetron sputtering to deposit a 50 nm first metal layer; (5) Heat bath in the degumming solution NMP at 100℃ for 1h, and finally soak in IPA for 5min and blow dry with nitrogen.

[0040] Step 8: Prepare the second passivation layer, including coating, baking, exposure, deposition and other processes. (1) Spin-coat PMMA A4 photoresist based on step 7, with the coating parameters of 2000 rpm / 60 s, and bake at 180 °C for 90 s after spin coating; (2) Use Raith150 electron beam exposure system to define the etching area, even if the electron beam glue in the exposure area is denatured; (3) Development: The developer is MIBK:IPA=1:3, the development time is 50 s, and the IPA fixation is 40 s. At this time, the denatured glue in the exposure area is dissolved in the developer, and the glue in the non-exposure area is retained, and the layout pattern is transferred to the sample; (4) Use magnetron sputtering to deposit a 50~100 nm second passivation layer.

[0041] Step 9: Deposit a second metal layer of a vertically surrounding channel field effect transistor on the second passivation layer. Deposit a 50 nm second metal layer by magnetron sputtering based on step 8; heat bath in NMP degumming solution at 100°C for 1 h, soak in IPA for 5 min, and blow dry with nitrogen.

[0042] Step 10: Prepare etching grooves, including processes such as photoresist coating, baking, exposure, deposition, and photoresist stripping. (1) Spin-coat ZEP520A photoresist based on step 7, with the spin-coating parameters of 500 rpm / 5 s + 2000 rpm / 2 min, and bake at 180℃ for 1 min after spin-coating; (2) Use Raith150 electron beam exposure system to define the etching area, even if the electron beam glue in the exposure area is denatured; (3) Development: The developer is amyl acetate, the development time is 70 s, IPA fixation is 40 s, and nitrogen blow-drying. At this time, the denatured glue in the exposure area is dissolved in the developer while the glue in the non-exposure area is retained, and the layout pattern is transferred to the sample; (4) Use ion beam etching IBE and inductively coupled plasma etching ICP to etch the exposure area, with an etching depth of 125~175 nm, that is, etching through the second metal layer and the second passivation layer to part of the first metal layer to form a groove structure; (5) Heat bath in the degumming solution NMP at 100℃ for 1 h, soak in IPA for 5 min, and blow dry with nitrogen.

[0043] Step 11: Based on step 10, a channel layer is deposited on the groove surface and sidewall using atomic layer deposition technology. In an optional case, the channel material is ITO, which is composed of In2O3 and Sn2O3 in a certain proportion. The precursor source selected for the In source is DimethylAminopropyl-Dimethyl Indium (DADI), and the precursor source selected for the Sn source is Tetrakis(dimethylamino)tin (TDMASn). The oxygen source is generated by passing O2 into an ozone generator, and the generated O3 is used as the oxygen source. The deposition temperature is 300°C.

[0044] Step 12: Based on step 11, the channel layer is etched for device isolation, including process steps such as coating, baking, exposure, etching, and stripping. (1) Based on step 11, the mask PMMA A4 electron beam glue is spin-coated, and the spin coating parameters are 500rpm / 5 s + 2000 rpm / 2 min. After spin coating, it is baked at 180 ℃ for 90 s; (2) The etching area is defined by the Raith150 electron beam exposure system, even if the electron beam glue in the exposure area is denatured; (3) Development: The developer is MIBK:IPA=1:3, the development time is 50s, IPA is fixed for 40 s, and nitrogen is blown dry. At this time, the denatured glue in the exposure area is dissolved in the developer, and the glue in the non-exposure area is retained, and the layout pattern is transferred to the sample; (4) The exposure area is etched using a wet solution; (5) Heat bath in the stripping solution NMP at 100 ℃ for 1h, soak in IPA for 5 min, and blow dry with nitrogen.

[0045] Step 13: Based on step 12, a gate dielectric layer is deposited by atomic layer deposition. Atomic layer deposition has the advantage of good sidewall coverage.

[0046] Step 14: Based on step 13, a gate electrode layer is deposited by atomic layer deposition. Atomic layer deposition has the advantage of good sidewall coverage.

Claims

1. An MRAM storage device based on vertical stacking 1T1M, characterized in that: The invention comprises a vertical structure formed by stacking a magnetic tunnel junction MTJ and a field effect transistor up and down, wherein the magnetic tunnel junction MTJ is composed of a multi-layer stacked magnetic material grown on a Si / SiO2 substrate, wherein the order of the layers from bottom to top is a bottom electrode (2), a pinning layer (3), a reference layer (4), a barrier layer (5), a free layer (6) and a top electrode (8), and the outside of the magnetic tunnel junction MTJ is surrounded by a first passivation layer (7); and the field effect transistor is a vertical channel FET of a surround channel CAA configuration.

2. The MRAM storage device based on vertical stacking 1T1M according to claim 1, characterized in that: Above the top electrode (8) is an interconnection layer (9).

3. The MRAM storage device based on vertical stacking 1T1M according to claim 1, characterized in that: The field effect transistor is prepared above the magnetic tunnel junction MTJ, and comprises a stacked structure, wherein the stacked structure comprises a first metal layer (10), a second passivation layer (11) and a second metal layer (12).

4. The MRAM storage device based on vertical stacking 1T1M according to claim 3, characterized in that: The stacked structure is provided with an etched groove, the groove passes through the first metal layer (10), the second passivation layer (11) and the second metal layer (12), and the groove partially passes through the first metal layer (10), and a channel layer (13), a gate dielectric layer (14) and a gate electrode layer (15) are provided in the groove; the channel layer (13) forms source-drain contact with the first metal layer (10) and the second metal layer (12), respectively, one of the first metal layer (10) and the second metal layer (12) is a source, and the other is a drain; the channel layer (13) contacts the first metal layer (10) and the second metal layer (12), respectively, and the gate dielectric layer (14) is provided between the semiconductor channel layer (13) and the gate electrode layer (15).

5. The MRAM storage device based on vertically stacked 1T1M according to claim 4, characterized in that: The first metal layer (10) of the field effect transistor is connected to the top electrode (8) of the magnetic tunnel junction MTJ through an interconnection layer (9).

6. The MRAM storage device based on vertical stacking 1T1M according to claim 1, characterized in that: The characteristic size area of ​​the MRAM storage device based on vertical stacking 1T1M is 4F 2 .

7. The MRAM storage device based on vertically stacked 1T1M according to claim 1, characterized in that: The MRAM storage device based on vertical stacking 1T1M uses the leakage current of the vertical channel FET with the surrounding channel CAA structure as the driving current to control the magnetization state flipping of the free layer of the magnetic tunnel junction MTJ below. Due to its vertical stacking structure, its plane size reaches 4F. 2 , improve integration.

8. A method for preparing an MRAM storage device based on vertical stacking 1T1M, characterized in that An MRAM storage device based on vertical stacking 1T1M as described in any one of claims 1 to 7 is prepared; comprising the following steps: Step S1: cleaning the Si / SiO2 (1) insulating substrate; Step S2: defining the bottom electrode region on the substrate by electron beam lithography, and forming the bottom electrode by physical vapor deposition (2) Step S3: Based on step S2, a MTJ thin film stack including a pinned layer (3), a reference layer (4), a barrier layer (5), and a free layer (6) is grown by magnetron sputtering; Step S4: Based on step S3, an etching area is defined by electron beam lithography, and a columnar magnetic tunnel junction MTJ is etched by dry etching; Step S5: Based on step S4, a first passivation layer (7) is deposited by physical vapor deposition, and then the photolithography mask glue and the passivation layer above it are removed; Step S6: Based on step S5, a stripping region is defined by electron beam lithography, and a top electrode (8) and an interconnection layer (9) are deposited by physical vapor deposition; Step S7: Based on step S6, a first metal layer (10) of a vertical surrounding channel field effect transistor is prepared by magnetron sputtering, and connected to the top electrode of the magnetic tunnel junction MTJ through an interconnection layer; Step S8: Based on step S7, a second passivation layer (11) is deposited by physical vapor deposition; Step S9: Based on step S8, a second metal layer (12) of a vertical surrounding channel field effect transistor is prepared by magnetron sputtering; Step S10: Spin-coat photoresist on the basis of step S9, use electron beam lithography to define the etching area, use dry etching to etch out the groove, and then remove the photoresist mask; Step S11: Based on step S10, a channel layer (13) is deposited on the surface and sidewall of the groove by atomic layer deposition; Step S12: Spin-coating photoresist based on step S11 to define the etching area by electron beam lithography, and using wet etching to isolate the device, and then removing the photoresist mask glue; Step S13: Based on step S12, a gate dielectric layer (14) is deposited on the surface and sidewall of the groove by atomic layer deposition; Step S14: Based on step S13, a gate electrode layer (15) is deposited on the surface and sidewall of the groove by using atomic layer deposition.

9. The method for preparing a vertically stacked 1T1M MRAM storage device according to claim 8, characterized in that: In step S3, the material of the pinning layer (3) includes: Ru, Co, [Pt / Co] x , Pt, Ta; the materials used for the reference layer (4) include: CoFeB, Ta, W, [Co / Pt] x , Co; the material of the barrier layer (5) is MCO; the material of the free layer (6) includes: MCO, CoFeB, Ta.

10. The method for preparing a vertically stacked 1T1M MRAM storage device according to claim 8, characterized in that: The materials of the first passivation layer (7) and the second passivation layer (11) are one or more of SiN, SiO2, Al2O3, HfO2, the first passivation layer (7) isolates the side wall of the magnetic tunnel junction MTJ, and the second passivation layer (11) isolates the source and drain.

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