Display device

Abstract

A display device includes: a display panel including: a base layer having a first region, a second region, and a third region, the first region having an active region, the second region being bent about a bending axis; a pixel overlapping the active area; a shield disposed in the second region; and a pad disposed in the third region; an input sensor disposed on the display panel and including a sensing electrode and a ground portion; and a flexible circuit film connected to the pads, in which the ground portion is connected to a ground pad among the pads, and the shield portion includes a pattern portion exposed to the outside and a connection portion connected to the pattern portion and the ground pad.

Description

[0001] This application claims priority to and all benefits derived from Korean Patent Application No. 10-2023-0082929, filed on June 27, 2023, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] The present invention relates to a display device, and more particularly, to a display device having an improved electrostatic shielding function. Background Art

[0003] Various display devices are being developed for multimedia devices such as televisions, mobile phones, tablet computers, navigation systems, and game consoles. In particular, display devices having flexible display members that can be folded or rolled are being developed recently to facilitate portability and improve user convenience. Resin may be applied to a bent portion of a display panel in order to prevent the inflow of static electricity. Summary of the invention

[0004] The present disclosure describes a display panel in which static electricity is prevented from flowing into the display panel through a bent portion of the display panel.

[0005] An embodiment of the present invention provides a display device, the display device comprising: a display panel, comprising: a substrate layer having a first area, a second area, and a third area, the first area having an effective area, the second area bending about a bending axis, the third area being separated from the first area, and the second area being arranged between the first area and the third area; a pixel overlapping the effective area; a shielding portion arranged in the second area; and a pad arranged in the third area. The display device further comprises: an input sensor arranged on the display panel and comprising a sensing electrode overlapping the effective area and a grounding portion arranged in a peripheral area adjacent to the effective area; and a flexible circuit film connected to the pad, wherein the grounding portion is connected to a grounding pad among the pads, and wherein the shielding portion comprises a pattern portion exposed to the outside and a connecting portion connected to the pattern portion and the grounding pad.

[0006] In an embodiment, the display panel may further include a covering portion defining an opening exposing the pattern portion and disposed in the second region to cover the connection portion, wherein the covering portion may include an organic material.

[0007] In an embodiment, the display panel may further include: a grounding line, which is arranged in the first area to the third area and has one end connected to the grounding portion through a contact hole defined in the first area and the other end connected to the grounding pad, wherein the grounding portion can be connected to the grounding pad through the grounding line.

[0008] In an embodiment, the connection portion may be connected to the ground pad through a ground line.

[0009] In an embodiment, the display panel may further include: a data line disposed in the first to third regions and connected to the pixel pad among the pixels and the pads, wherein the connection portion may cross the data line on a plane.

[0010] In an embodiment, the shielding portion may further include: a connecting pattern, which is arranged on a different layer from the layer in which the connecting portion is arranged and overlaps with the place where the data line and the connecting portion cross each other, wherein the connecting portion may be disconnected at the place where the connecting portion crosses the data line, and the disconnected and spaced-apart portions of the connecting portion with the data line therebetween may be connected by the connecting pattern.

[0011] In an embodiment, the ground connection pad may include a first pattern and a second pattern disposed on the first pattern and in contact with the flexible circuit film.

[0012] In an embodiment, the shielding part may be disposed on the same layer as the layer where the first pattern is disposed.

[0013] In an embodiment, the shielding part may be disposed on the same layer as the layer where the second pattern is disposed.

[0014] In an embodiment, the input sensor may include a first sensing insulating layer directly disposed on the display panel, a first conductive layer disposed on the first sensing insulating layer and constituting a portion of the sensing electrode, a second sensing insulating layer covering the first conductive layer and disposed on the first sensing insulating layer, and a second conductive layer disposed on the second sensing insulating layer and constituting the remainder of the sensing electrode.

[0015] In an embodiment, the shielding part may include the same material as that of the second conductive layer, and the connecting part may be connected to the ground line by passing through at least one of the first sensing insulating layer and the second sensing insulating layer.

[0016] In an embodiment, the pattern part may be provided in plurality, and the connection part may be connected to each of the plurality of pattern parts, wherein each of the plurality of pattern parts are spaced apart from each other.

[0017] In an embodiment, the display panel may further include a driving chip disposed in the third region, wherein the driving chip may be disposed between the ground pad and the plurality of pattern parts on a plane.

[0018] In an embodiment, the driving chip may be connected to a driving ground pad among the pads, and the connection part may be connected to the driving ground pad.

[0019] In an embodiment, the display panel may further include an alignment mark disposed in the first region and including a conductive material.

[0020] In an embodiment, the connection portion may be connected to the alignment mark.

[0021] In an embodiment, a pixel may include a thin film transistor and a light emitting element connected to the thin film transistor, the thin film transistor including a semiconductor pattern, a control electrode overlapping the semiconductor pattern, and a source and a drain connected to the semiconductor pattern, wherein the display panel may further include: a blocking layer arranged on a base layer, a buffer layer arranged on the blocking layer, a first insulating layer arranged on the buffer layer and covering the semiconductor pattern, a second insulating layer arranged on the first insulating layer and covering the control electrode, a third insulating layer arranged on the second insulating layer and covering an upper electrode overlapping the control electrode, a fourth insulating layer arranged on the third insulating layer and on which the source and the drain are arranged, a fifth insulating layer arranged on the fourth insulating layer and covering the source and the drain, and a sixth insulating layer arranged on the fifth insulating layer.

[0022] In an embodiment, the display panel may further include a connection electrode connected to the source electrode through a contact hole defined in the fifth insulating layer and covered by the sixth insulating layer.

[0023] In an embodiment, a groove passing through the barrier layer, the buffer layer, and the first to fourth insulating layers to expose the base layer may be defined in the second region, and the fifth insulating layer may be disposed inside the groove.

[0024] In an embodiment, at least a portion of the shield may be covered by a sixth insulating layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The accompanying drawings are included to provide an understanding of the present invention and are incorporated into and constitute a part of this specification. The accompanying drawings illustrate embodiments of the present invention and together with the description serve to explain the principles of the present invention. In the drawings:

[0026] Figure 1 is a perspective view of an electronic device according to an embodiment;

[0027] Figure 2 is an exploded perspective view of a display device according to an embodiment;

[0028] Figure 3 According to the embodiment along Figure 2 The line I-I' intercepts Figure 2 A cross-sectional view of a display device;

[0029] Figure 4 is a cross-sectional view illustrating a bent display panel of a display device according to an embodiment;

[0030] Figure 5 is a plan view of a display panel according to an embodiment;

[0031] Figure 6 is a plan view of an input sensor according to an embodiment;

[0032] Fig. 7A According to the embodiment along Figure 5 The line II-II' is intercepted Figure 5 A cross-sectional view of a display module;

[0033] Figure 7B According to the embodiment along Figure 5 The line III-III' is intercepted Figure 5 A cross-sectional view of a display module;

[0034] Figure 8 is a plan view of a display module according to an embodiment;

[0035] Fig.9A According to the embodiment along Figure 8 The line IV-IV' is intercepted Figure 8 A cross-sectional view of a display module;

[0036] Fig. 9B According to the embodiment along Figure 8 The line V-V' intercepts Figure 8 A cross-sectional view of a display module;

[0037] Fig.10 is a cross-sectional view of a display module according to an embodiment;

[0038] Fig.11 is a cross-sectional view of a display module according to an embodiment;

[0039] Fig.12 is a plan view of a display module according to an embodiment;

[0040] Fig.13 is a plan view of a display module according to an embodiment;

[0041] Fig.14 is a plan view of a display module according to an embodiment; and

[0042] Fig.15 is a plan view of a display module according to an embodiment. DETAILED DESCRIPTION

[0043] The present invention will now be described more fully below with reference to the accompanying drawings in which various embodiments are shown. However, the present invention can be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art.

[0044] In this specification, it will be understood that when an element (or region, layer, portion, etc.) is referred to as being "on", "connected to" or "coupled to" another element, it can be directly disposed on, directly connected to or directly coupled to the other element, or intervening elements may be disposed therebetween.

[0045] The same reference numerals or symbols always refer to the same elements. In the accompanying drawings, the thickness, ratio and size of the elements are exaggerated in order to effectively describe the technical content. As used in this article, the term "and / or" includes any combination and all combinations of one or more of the related listed items.

[0046] It will be understood that, although the terms first, second, etc. can be used to describe various elements, components, regions, layers and / or parts in this article, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish an element, component, region, layer or part from another element, component, region, layer or part. Therefore, the first element, component, region, layer or part discussed below can be referred to as the second element, component, region, layer or part, without departing from the scope of the present invention. Similarly, the second element, component, region, layer or part can be referred to as the first element, component, region, layer or part. As used in this article, unless the context clearly indicates otherwise, the singular form "one" and "the (described)" are intended to also include plural forms.

[0047] In addition, terms such as "below", "on the lower side", "above", or "on the upper side" may be used to describe the relationship of elements illustrated in the drawings. These terms have relative concepts and are described based on directions indicated in the drawings.

[0048] It will be further understood that when used in this specification, the terms “including” and / or “having” indicate the presence of stated features, integers, steps, operations, elements, parts and / or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups thereof.

[0049] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those generally understood by those of ordinary skill in the art to which the present invention belongs. It will be further understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and will not be interpreted in an idealized or excessive sense unless explicitly defined in this article.

[0050] Hereinafter, embodiments of the present invention are described with reference to the accompanying drawings.

[0051] Figure 1is a perspective view of an electronic device according to an embodiment. Figure 2 is an exploded perspective view of a display device according to an embodiment. Figure 3 According to the embodiment along Figure 2 A cross-sectional view taken along line II'.

[0052] In the examples and with reference to Figures 1 to 3 , the electronic device ED may be activated in response to the electrical signal. The electronic device ED may include various embodiments. For example, the electronic device ED may be an electronic device such as a smart watch, a computer (eg, a tablet computer, a laptop computer), a smart TV, etc.

[0053] In an embodiment, the electronic device ED may display an image IM toward a third direction DR3 on a display surface IS oriented parallel to each of the first direction DR1 and the second direction DR2. The display surface IS on which the image IM is displayed may correspond to a front surface of the electronic device ED. The image IM may include a static image as well as a dynamic image.

[0054] In an embodiment, the front surface (or upper surface) and the rear surface (or lower surface) of each of the components are defined based on a third direction DR3 in which the image IM is displayed. The front surface and the rear surface may be arranged to be opposite to each other in the third direction DR3, and the normal direction of each of the front surface and the rear surface may be parallel to the third direction DR3.

[0055] In an embodiment, the distance between the front surface and the rear surface in the third direction DR3 may correspond to the thickness of the electronic device ED in the third direction DR3. Meanwhile, the directions indicated by the first to third directions DR1, DR2 and DR3, respectively, may be relative concepts and thus may be changed to other directions.

[0056] In an embodiment, the electronic device ED may detect an external input applied from the outside. The external input may include various types of inputs provided from the outside of the electronic device ED. For example, the external input may include not only an external input applied by contact with a part of the user's body (such as a hand), but also an external input applied close to the electronic device ED or adjacent to the electronic device ED at a predetermined distance (e.g., hovering). In addition, the external input may include various forms such as electricity, pressure, temperature, and light.

[0057] In an embodiment, the display surface IS of the electronic device ED may be divided into a transmission area TA and a frame area BZA. The transmission area TA may be an area in which an image IM is displayed. A user views the image IM through the transmission area TA. In an embodiment, the transmission area TA is illustrated as a quadrilateral shape with rounded corners. However, the transmission area TA may have various shapes and is not limited to any one embodiment.

[0058] In an embodiment, the border area BZA is disposed adjacent to the transmission area TA. The border area BZA may have a predetermined color. The border area BZA may surround the transmission area TA. Accordingly, the shape of the transmission area TA may be substantially defined by the border area BZA. However, in another embodiment, the border area BZA may be disposed adjacent to only one side of the transmission area TA, or may also be omitted. The electronic device ED may include various embodiments and is not limited to any one embodiment.

[0059] In an embodiment, the electronic device ED may include a display device DD and a housing EDC. The display device DD may include a window WM, a display module DM, a driving module EM, an optical film OTF, and a lower module LM.

[0060] In an embodiment, the window WM may be formed of a transparent material capable of projecting an image. For example, the window WM may include glass, sapphire, plastic, etc. The window WM is illustrated as a single layer, but is not limited thereto and may include multiple layers. Meanwhile, although not illustrated in the drawings, the bezel area BZA of the electronic device ED described previously may be substantially provided as an area in which a material having a predetermined color is printed on an area of ​​the window WM.

[0061] In an embodiment, the display module DM may include a display panel DP and an input sensor ISP. The display panel DP generates an image IM, and the input sensor ISP obtains coordinate information about an external input (e.g., a touch event). The display panel DP according to an embodiment may be an emissive display panel, but is not particularly limited thereto. For example, the display panel DP may be an organic light-emitting display panel, an inorganic light-emitting display panel, or a quantum dot light-emitting display panel. The light-emitting layer of the organic light-emitting display panel may include an organic light-emitting material, and the light-emitting layer of the inorganic light-emitting display panel may include an inorganic light-emitting material. The light-emitting layer of the quantum dot light-emitting display panel may include quantum dots and / or quantum rods, etc. Hereinafter, the display panel DP is described as an organic light-emitting display panel.

[0062] In an embodiment, the input sensor ISP may be directly disposed on the display panel DP. According to an embodiment, the input sensor ISP may be formed on the display panel DP through a continuous process. That is, when the input sensor ISP is directly disposed on the display panel DP, an adhesive film for bonding the input sensor ISP to the display panel DP is not disposed between the input sensor ISP and the display panel DP.

[0063] In an embodiment, the optical film OTF reduces the reflectivity of external light incident from above the window WM. The optical film OTF according to an embodiment may include a retarder and a polarizer. The retarder may be a film type or a liquid crystal coating type, and include a λ / 2 retarder and / or a λ / 4 retarder. The polarizer may also be a film type or a liquid crystal coating type. The film type may include a stretched synthetic resin film, and the liquid crystal coating type may include liquid crystals arranged in a predetermined arrangement. The retarder and the polarizer may be provided as a polarizing film. The optical film OTF may further include a protective film disposed above or below the polarizing film.

[0064] In an embodiment, the optical film OTF may be disposed on the input sensor ISP. That is, the optical film OTF may be disposed between the input sensor ISP and the window WM. The input sensor ISP, the optical film OTF, and the window WM may be bonded to each other by an adhesive layer. Figure 3 , the optical adhesive layer AF1 is disposed between the input sensor ISP and the optical film OTF, and the window adhesive layer AF2 is disposed between the optical film OTF and the window WM. Therefore, the optical film OTF is bonded to the input sensor ISP through the optical adhesive layer AF1, and the window WM is bonded to the optical film OTF through the window adhesive layer AF2.

[0065] According to an embodiment, the adhesive layers AF1 and AF2 may each include an optically clear adhesive (OCA) film. However, the material of each of the adhesive layers AF1 and AF2 is not limited thereto, and may include a general adhesive or adhesive. For example, the adhesive layers AF1 and AF2 may each include a pressure-sensitive adhesive (PSA), an optically clear adhesive (OCA), or an optically clear resin (OCR).

[0066] In an embodiment, in addition to the optical film OTF, a functional layer (eg, a protective layer) for performing another function may be further disposed between the display module DM and the window WM.

[0067] In an embodiment, the display module DM may display an image in response to an electrical signal and transmit / receive information about an external input. The display module DM may be defined as an active area AA and a peripheral area NAA. The active area AA may be defined as an area where an image provided from the display module DM is projected.

[0068] In an embodiment, the peripheral area NAA is disposed adjacent to the active area AA. For example, the peripheral area NAA may surround the active area AA. However, this is illustrated exemplarily, and the peripheral area NAA may be defined in various shapes and is not limited to any one embodiment. According to an embodiment, the active area AA of the display module DM may correspond to at least a portion of the transmissive area TA.

[0069] According to an embodiment, the display module DM may include a first area A1, a second area A2, and a third area A3 arranged in a second direction DR2. The first area A1 may include a portion of the peripheral area NAA and the active area AA, and the second area A2 and the third area A3 may include the remaining portion of the peripheral area NAA. The second area A2 may be a bending area bent about a bending axis, and the first area A1 and the third area A3 may be non-bending areas.

[0070] In an embodiment, the length of each of the second and third regions A2 and A3 in the first direction DR1 may be less than or equal to the length of the first region A1 in the first direction DR1. A short region in the bending axis direction may be more easily bent.

[0071] In an embodiment, the display module DM may include a shielding portion ES disposed in the second area A2. When the second area A2 is bent, the shielding portion ES may block static electricity from flowing into the display panel DP through the bent area. This will be described later.

[0072] In an embodiment, the driving module EM may control the operation of the display module DM. The driving module EM may include a flexible circuit film FCB and a driving chip DIC. The flexible circuit film FCB may be electrically connected to the display panel DP. The flexible circuit film FCB may be bonded to the end of the third area A3 of the display module DM by a bonding process. The flexible circuit film FCB may be electrically connected to the display module DM by an anisotropic conductive adhesive layer. The driving chip DIC may be installed in the third area A3 of the display module DM. The driving chip DIC may include a driving circuit (e.g., a data driving circuit) for driving pixels of the display panel DP.

[0073] According to an embodiment, the flexible circuit film FCB may include a ground line for discharging static electricity flowing into the flexible circuit film FCB or static electricity flowing into the input sensor ISP.

[0074] In an embodiment, the driving module EM may further include a plurality of driving elements mounted on the flexible circuit film FCB. The plurality of driving elements may include a circuit portion for converting a signal input from the outside into a signal required by the driving chip DIC or into a signal required to drive the display module DM. When the second area A2 of the display module DM is bent, the flexible circuit film FCB may be disposed under the display module DM.

[0075] In an embodiment, the lower module LM is disposed on the rear surface of the display module DM. Since the lower module LM is disposed on the rear surface of the display module DM, the impact resistance of the display device DD can be improved. The lower module LM can be fixed to the rear surface of the display module DM by an adhesive layer.

[0076] In an embodiment, when the second area A2 of the display module DM is bent, the third area A3 of the display module DM and the flexible circuit film FCB may be disposed on the rear surface of the lower module LM.

[0077] In an embodiment, the housing EDC may be coupled to the window WM to define the appearance of the electronic device ED. The housing EDC accommodates the display device DD. The housing EDC absorbs external impacts and prevents foreign matter / moisture, etc. from penetrating into the display device DD, and thus protects the components accommodated in the housing EDC. Meanwhile, in an embodiment, the housing EDC may be provided in the form of a plurality of accommodating members coupled to each other.

[0078] Figure 4 is a cross-sectional view illustrating a bent display panel of a display device according to an embodiment. Figure 4 2 is a cross-sectional view illustrating a portion of the display device DD disposed adjacent to the second area A2 in a state in which the second area A2 is bent about a bending axis AX extending along the first direction DR1 according to an embodiment.

[0079] In an embodiment, the display device DD may include a window WM, an optical film OTF, a display module DM, and a lower module LM. The lower module LM may include a first protective member PF1, a second protective member PF2, and a functional layer MP.

[0080] The window WM according to the embodiment may include a base WB, a hard coating layer HC and a frame pattern BP. The base WB may include an optically transparent insulating material. For example, the base WB may include a glass substrate or a synthetic resin film. The hard coating layer HC may be disposed on the front surface or the rear surface of the base WB to protect the base WB. The hard coating layer HC may prevent the base WB from being damaged by scratches, etc. In addition, an anti-fingerprint layer may be further disposed on the base WB.

[0081] In an embodiment, the border pattern BP defines a border area BZA (see Figure 1 ). The bezel pattern BP may be disposed adjacent to an edge of the rear surface of the base portion WB.

[0082] In an embodiment, the frame pattern BP, which is a coloring layer, may be formed by coating. The frame pattern BP may include a polymer resin and a pigment mixed in the polymer resin. The polymer resin may be, for example, an acrylic resin or polyester, and the pigment may be a carbon-based pigment.

[0083] According to an embodiment, an edge of the front surface or the rear surface of the base portion WB may have a chamfered shape. For example, an edge of the front surface of the base portion WB may have a rounded shape.

[0084] In an embodiment, the optical film OTF may be disposed under the window WM. The optical film OTF may reduce the reflectivity of external light incident from the window WM. The window WM and the optical film OTF may be bonded to each other through the window adhesive layer AF2. The display module DM and the optical film OTF may be bonded to each other through the optical adhesive layer AF1.

[0085] In an embodiment, the first protective member PF1 may be disposed on the rear surface of the display module DM to overlap with the first area A1. The display module DM and the first protective member PF1 may be bonded to each other by a first adhesive layer AM1.

[0086] In an embodiment, the functional layer MP may be disposed under the first protective member PF1. The functional layer MP and the first protective member PF1 may be bonded to each other by a second adhesive layer AM2. The functional layer MP may be provided in the form of a plate. The functional layer MP may include a plurality of layers. For example, the functional layer MP may include a light blocking layer, a heat dissipation layer, a cushion layer, and a plurality of adhesive layers.

[0087] In an embodiment, the light blocking layer can be used to improve the problem that the components set in the display module DM are reflected on the window WM through the active area AA. The light blocking layer may include a binder and a plurality of pigment particles dispersed therein. The pigment particles may include carbon black, etc. By including the light blocking layer, the electronic device ED according to the embodiment may have an improved light shielding effect.

[0088] In an embodiment, the heat dissipation layer can effectively dissipate the heat generated from the display module DM. The heat dissipation layer may include at least one of graphite, copper (Cu), and aluminum (Al) having good heat dissipation characteristics, but embodiments of the present invention are not limited thereto. The heat dissipation layer may not only improve the heat dissipation characteristics, but may also have electromagnetic shielding or absorption characteristics.

[0089] In an embodiment, the cushion layer may be a synthetic resin foam. The cushion layer may include a matrix and a plurality of pores. The cushion layer may be elastic and have a porous structure.

[0090] In an embodiment, the substrate may include a flexible material. The substrate includes a synthetic resin. For example, the substrate may include at least one of acrylonitrile butadiene styrene copolymer (ABS), polyurethane (PU), polyethylene (PE), ethylene vinyl acetate (EVA), and polyvinyl chloride (PVC).

[0091] In an embodiment, the plurality of pores easily absorbs impact applied to the cushion layer. When the cushion layer has a porous structure, a plurality of pores may be defined.

[0092] According to an embodiment, at least one of the light blocking layer, the heat dissipation layer, and the pad layer included in the functional layer MP may be omitted, and the functional layer MP may be provided as a single layer instead of a plurality of layers, but is not limited to any one embodiment.

[0093] In an embodiment, the functional layer MP and the second protection member PF2 may be bonded to each other through the third adhesive layer AM3. The second protection member PF2 may be disposed on the rear surface of the display module DM overlapping the third area A3. The display module DM and the second protection member PF2 may be bonded to each other through the fourth adhesive layer AM4.

[0094] The electronic device ED according to the embodiment may include a protective layer RM. When the display module DM is bent, the protective layer RM may be disposed in an inner space defined by a rear surface of the display module DM overlapping the second area A2, a side surface of the first protective member PF1, a side surface of the functional layer MP, a side surface of the second protective member PF2, and a side surface of each of the adhesive layers AM1, AM2, AM3, and AM4.

[0095] In an embodiment, when disposed in the inner space, the protective layer RM can support the display module DM when the display module DM is bent so that the second area A2 maintains the shape. In addition, foreign matter or the like can be prevented from entering the interior of the display module DM through the second area A2. The protective layer RM according to an embodiment may include a resin.

[0096] The display device DD according to the embodiment may further include a conductive film CV disposed in the third area A3. The conductive film CV may cover the driving chip DIC to prevent static electricity introduced from the outside from damaging the driving chip DIC and prevent foreign matter, etc. from entering the inside of the driving chip DIC. In addition, impact may be prevented from being applied to the driving chip DIC.

[0097] Figure 5 is a plan view of a display panel according to an embodiment.

[0098] exist Figure 5 In, omit reference Figure 2 The shielding portion ES described above will be described later.

[0099] According to an embodiment, the display panel DP may be divided into first, second, and third areas A1, A2, and A3 arranged along the second direction DR2. Figure 4 The first to third areas A1, A2 and A3 of the display panel DP shown in FIG. Figure 2 The first to third areas A1, A2 and A3 of the described display module DM correspond. In this specification, "area / part corresponds to area / part" means that area / part overlaps area / part, and is not limited to the meaning of having the same area.

[0100] The display panel DP according to the embodiment may include an active area AA in which the pixel PX is disposed and a peripheral area NAA adjacent to the active area AA. The active area AA and the peripheral area NAA are respectively connected to the reference Figure 2 The described active area AA corresponds to the area where the pixels PX are arranged in the first area A1, and the peripheral area NAA is defined as the remaining area except the area where the pixels PX are arranged, and the peripheral area NAA includes a part of the first area A1, the second area A2, and the third area A3.

[0101] In an embodiment, the display panel DP may include a scan driver SDV, an emission driver EDV, and a driving chip DIC in the peripheral area NAA. In an embodiment, the driving chip DIC may be a data driver.

[0102] In an embodiment, the display panel DP may include a plurality of pixels PX, a plurality of scan lines SL1 to SLm, a plurality of data lines DL1 to DLn, a plurality of emission lines EL1 to ELm, a first control line CSL1 and a second control line CSL2, a power line PL, and a plurality of pads PD. Herein, m and n are natural numbers greater than 0. The pixels PX may be connected to the scan lines SL1 to SLm, the data lines DL1 to DLn, and the emission lines EL1 to ELm.

[0103] In an embodiment, the scan lines SL1 to SLm may extend in the first direction DR1 to be connected to the scan driver SDV. The data lines DL1 to DLn may extend from the first area A1 in the second direction DR2 via the second area A2 to be connected to the driving chip DIC disposed in the third area A3. The emission lines EL1 to ELm may extend in the first direction DR1 to be connected to the emission driver EDV.

[0104] In an embodiment, the power line PL may include a portion extending in the first direction DR1 and a portion extending in the second direction DR2. The portion extending in the first direction DR1 and the portion extending in the second direction DR2 may be provided at different layers. The portion of the power line PL extending in the second direction DR2 may extend from the first area A1 to the third area A3 via the second area A2. The power line PL may provide a reference voltage to the pixel PX.

[0105] In an embodiment, the first control line CSL1 may be connected to the scan driver SDV and extend from the first area A1 to the third area A3 via the second area A2. The second control line CSL2 may be connected to the emission driver EDV and extend from the first area A1 to the third area A3 via the second area A2.

[0106] In an embodiment, the pad PD may be disposed adjacent to the end of the third area A3. The driving chip DIC, the power line PL, the first control line CSL1, and the second control line CSL2 may be connected to the pad PD. The flexible circuit film FCB may be disposed on the display panel DP while overlapping the end of the third area A3 of the display panel DP. The flexible circuit film FCB may include a pad corresponding to the pad PD and may be electrically connected to the pad PD through an anisotropic conductive film (ACF).

[0107] In the present specification, among the pads PD, pads connected to the data lines DL1 to DLn may be defined as “pixel pads”, and pads connected to the ground line GCL may be defined as “ground pads GP-L and GP-R”.

[0108] The display panel DP according to the embodiment may include a first contact hole CN-H1 defined in the first area A1. The display panel DP may include an extended sensing line TL-L. The extended sensing line TL-L may extend to the third area A3 via the first area A1 and the second area A2. The extended sensing line TL-L may be respectively connected to sensing lines TL1, TL2, and TL3 (see FIG. 1 ) to be described later through the first contact hole CN-H1. Figure 6 ) among the corresponding sensing lines. For example, one end of the extended sensing line TL-L may be exposed from the first contact hole CN-H1 to be respectively connected to the sensing lines TL1, TL2, and TL3 (see Figure 6 ), and the other ends of the extended sensing lines TL-L may be connected to the pads PD, respectively.

[0109] In an embodiment, Figure 5 The extended sensing line TL-L is shown to be disposed between the data lines DL1 to DLn, but the present invention is not limited thereto. The data lines DL1 to DLn may be disposed between the extended sensing lines TL-L, and accordingly, a plurality of first contact holes CN-H1 may be provided with the data lines DL1 to DLn therebetween, and the arrangement is not limited to any one embodiment.

[0110] The display panel DP according to the embodiment may further include a ground line GCL. The ground line GCL may include a first ground line GC-L and a second ground line GC-R. The first ground line GC-L and the second ground line GC-R may each extend from the first area A1 to the third area A3 via the second area A2.

[0111] In an embodiment, one end of the first ground line GC-L disposed in the first area A1 may be exposed by the first ground contact hole CN-G1, and the other end of the first ground line GC-L disposed in the third area A3 may be connected to the first ground pad GP-L among the pads PD. The one end of the first ground line GC-L exposed by the first ground contact hole CN-G1 may be connected to a first ground pattern GN-L (see FIG. 1 ) to be described later. Figure 6 ).

[0112] In an embodiment, one end of the second ground line GC-R disposed in the first area A1 may be exposed by the second ground contact hole CN-G2, and the other end of the second ground line GC-R disposed in the third area A3 may be connected to the second ground pad GP-R among the pads PD. The one end of the second ground line GC-R exposed by the second ground contact hole CN-G2 may be connected to a second ground pattern GN-R (see FIG. 1 ) to be described later. Figure 6 ).

[0113] Accordingly, in the embodiment, the ground portion GNL (see Figure 6 ) may be connected to the ground pads GP-L and GP-R through the ground lines GCL provided in the display panel DP, and connected to the flexible circuit film FCB.

[0114] According to an embodiment, a shielding part ES (see FIG. 5 ) disposed in the second area A2 of the display panel DP may be included. Figure 2 ). This will be described later.

[0115] Figure 6 is a plan view of an input sensor according to an embodiment.

[0116] Reference Figure 6 The input sensor ISP according to the embodiment may include sensing electrodes TE1 and TE2 and sensing lines TL1, TL2 and TL3. When the input sensor ISP is directly formed on the display panel DP through a continuous process, the sensing electrodes TE1 and TE2 may be formed only in the active area AA overlapping the first area A1 of the display panel DP.

[0117] In an embodiment, the input sensor ISP may acquire information about an external input through a change in capacitance between the first sensing electrode TE1 and the second sensing electrode TE2. The first sensing electrodes TE1 are arranged along a first direction DR1, and each of the first sensing electrodes TE1 extends along a second direction DR2. The first sensing electrodes TE1 may each include a first sensing pattern SP1 and a first connection pattern CP1.

[0118] In an embodiment, the first sensing pattern SP1 is disposed in the active area AA. The first sensing pattern SP1 included in one first sensing electrode TE1 may be arranged along the second direction DR2. The first sensing pattern SP1 may have a diamond shape. However, this is exemplarily illustrated, and the first sensing pattern SP1 may have various shapes and is not limited to any one embodiment.

[0119] In an embodiment, the first connection pattern CP1 is disposed in the active area AA. The first connection pattern CP1 may be disposed between adjacent first sensing patterns SP1. The first connection pattern CP1 may be disposed at a different layer from a layer where the first sensing pattern SP1 is disposed and connected to the first sensing pattern SP1 through a contact hole.

[0120] In an embodiment, the second sensing electrodes TE2 are arranged along the second direction DR2, and each of the second sensing electrodes TE2 extends along the first direction DR1. The second sensing electrodes TE2 may each include a second sensing pattern SP2 and a second connection pattern CP2.

[0121] In an embodiment, the second sensing pattern SP2 may be spaced apart from the first sensing pattern SP1. The first sensing pattern SP1 and the second sensing pattern SP2 may not contact each other, and may transmit / receive electrical signals independently of each other.

[0122] In an embodiment, the second sensing pattern SP2 is disposed in the active area AA. The second sensing pattern SP2 included in one second sensing electrode TE2 may be arranged along the first direction DR1. The second sensing pattern SP2 may have the same shape as that of the first sensing pattern SP1. For example, the second sensing pattern SP2 may have a rhombus shape. However, this is exemplarily illustrated, and the second sensing pattern SP2 may have various shapes, and the shape is not limited to any one embodiment.

[0123] In an embodiment, the second connection pattern CP2 may be disposed between adjacent second sensing patterns SP2. Substantially, the second sensing pattern SP2 and the second connection pattern CP2 included in one second sensing electrode TE2 may be formed in an integral shape or an integral pattern.

[0124] According to an embodiment, the second sensing patterns SP2 and the second connection patterns CP2 may be disposed in the same layer, and the first sensing patterns SP1 may be disposed in a different layer from the layer in which the second sensing patterns SP2 and the second connection patterns CP2 are disposed. The first sensing patterns SP1, the second sensing patterns SP2, and the second connection patterns CP2 may be provided as a plurality of grid lines extending in an oblique direction in each of the first direction DR1 and the second direction DR2.

[0125] In an embodiment, the sensing lines TL1 , TL2 , and TL3 are disposed in the peripheral area NAA. The sensing lines TL1 , TL2 , and TL3 may include a first sensing line TL1 , a second sensing line TL2 , and a third sensing line TL3 .

[0126] In an embodiment, one end of the first sensing line TL1 is respectively connected to the first sensing electrode TE1. In an embodiment, the first sensing line TL1 is respectively connected to the lower end among the two ends of the first sensing electrode TE1. One end of the second sensing line TL2 is respectively connected to the upper end among the two ends of the first sensing electrode TE1. According to an embodiment, the first sensing electrode TE1 may be connected to each of the first sensing line TL1 and the second sensing line TL2. Accordingly, for the first sensing electrode TE1 which is relatively long compared to the second sensing electrode TE2, the sensitivity according to the area may be uniformly maintained.

[0127] In an embodiment, in the input sensor ISP, the first sensing line TL1 or the second sensing line TL2 may be omitted, and the input sensor ISP is not limited to any one embodiment.

[0128] In the embodiment, one end of the third sensing line TL3 is connected to one end of the second sensing electrode TE2, respectively. In the present embodiment, the third sensing line TL3 is connected to the left end among the two ends of the second sensing electrode TE2, respectively.

[0129] In an embodiment, a second contact hole CN-H2 may be defined in the input sensor ISP, the second contact hole CN-H2 being defined by passing through at least one of the insulating layers included in the input sensor ISP. The second contact hole CN-H2 may overlap with the first contact hole CN-H1 defined in the first area A1 of the display panel DP.

[0130] In an embodiment, the other ends of the sensing lines TL1, TL2, and TL3 may be respectively disposed in the second contact hole CN-H2. The other ends of the sensing lines TL1, TL2, and TL3 disposed in the second contact hole CN-H2 may be respectively connected to the extended sensing line TL-L (see Figure 5 ). The sensing lines TL1, TL2 and TL3 can be arranged on the display panel DP (see Figure 5 ) is connected to the extended sensing line TL-L in the pad PD (see Figure 5 ).

[0131] According to an embodiment, the input sensor ISP may include a ground portion GNL disposed in the peripheral area NAA The ground portion GNL may prevent static electricity applied to the input sensor ISP from entering the sensing electrodes TE1 and TE2 .

[0132] In an embodiment, the ground portion GNL may include a first ground pattern GN-L and a second ground pattern GN-R. The first ground pattern GN-L may be disposed in the peripheral area NAA on the left side of the active area AA, and the second ground pattern GN-R may be disposed in the peripheral area NAA on the right side of the active area AA.

[0133] In an embodiment, ground contact holes CN-G3 and CN-G4 may be defined in the input sensor ISP, and the ground contact holes CN-G3 and CN-G4 are defined by passing through at least one of the insulating layers included in the input sensor ISP. The ground contact holes CN-G3 and CN-G4 may include a third ground contact hole CN-G3 and a fourth ground contact hole CN-G4.

[0134] In an embodiment, the third ground contact hole CN-G3 may be connected to the display panel DP (see Figure 5 ) defined in the first ground contact hole CN-G1 (see Figure 5 ), and the fourth ground contact hole CN-G4 may overlap with the display panel DP (see Figure 5 ) defined in the second ground contact hole CN-G2 (see Figure 5 )overlapping.

[0135] In an embodiment, one end of the first ground pattern GN-L may be disposed on the third ground contact hole CN-G3 and connected to the first ground contact hole CN-G1 (see FIG. Figure 5 ) The first ground line GC-L exposed Figure 5 ). Accordingly, the first ground pattern GN-L may be connected to the first ground pad GP-L (see Figure 5 ) and connected to the flexible circuit film FCB (see Figure 5 ).

[0136] In an embodiment, one end portion of the second ground pattern GN-R may be disposed on the fourth ground contact hole CN-G4 and connected to the ground contact hole CN-G2 (see FIG. Figure 5 ) The exposed second ground line GC-R (see Figure 5 ). Accordingly, the second ground pattern GN-R may be connected to the second ground pad GP-R (see Figure 5 ) and connected to the flexible circuit film FCB (see Figure 5 ).

[0137] Fig. 7A According to the embodiment along Figure 5 A cross-sectional view taken along line II-II'. Figure 7B According to the embodiment along Figure 5 A cross-sectional view taken along line III-III'. Fig. 7A is a diagram illustrating Figure 5 The line II-II' corresponds to a cross-sectional view of the display module DM.

[0138] In an embodiment, Fig. 7A The figure is similar to the pixel PX (see Figure 5 ) corresponding to the cross section of the first thin film transistor T1, the second thin film transistor T2 and the light emitting element OLED of the partially constructed structure. The first thin film transistor T1 may include a first semiconductor pattern OSP1, a first control electrode GE1 overlapping the first semiconductor pattern OSP1, and a first input electrode DE1 (also referred to as a first drain) and a first output electrode SE1 (also referred to as a first source) connected to the first semiconductor pattern OSP1. The second thin film transistor T2 may include a second semiconductor pattern OSP2, a second control electrode GE2 overlapping the second semiconductor pattern OSP2, and a second input electrode DE2 (also referred to as a second drain) and a second output electrode SE2 (also referred to as a second source) connected to the second semiconductor pattern OSP2.

[0139] In an embodiment, the display panel DP may include a base layer BL and a circuit element layer DP-CL, a display element layer DP-OLED and a thin film encapsulation layer TFE arranged on the base layer BL. The display panel DP may further include functional layers such as an anti-reflection layer and a refractive index control layer. The circuit element layer DP-CL includes at least a circuit element and a plurality of insulating layers. Hereinafter, the insulating layer may include an organic layer and / or an inorganic layer.

[0140] In an embodiment, the circuit element includes a signal line and a driving circuit of a pixel, etc. The circuit element layer DP-CL may be formed through a formation process of an insulating layer, a semiconductor layer, and a conductive layer by coating, deposition, etc. and through a patterning process of the insulating layer, the semiconductor layer, and the conductive layer by photolithography. The display element layer DP-OLED may include a light emitting element OLED and a pixel defining film PDL.

[0141] In an embodiment, the base layer BL may include a synthetic resin layer. The synthetic resin layer may include a thermosetting resin. In particular, the synthetic resin layer may be a polyimide resin layer, and the material is not particularly limited thereto. The synthetic resin layer may include at least one of an acrylate resin, a methacrylate resin, a polyisoprene resin, a vinyl resin, an epoxy resin, a urethane resin, a cellulose resin, a siloxane resin, a polyamide resin, and a perylene resin. In addition, the base layer BL may include a glass substrate, a metal substrate, an organic / inorganic composite material substrate, and the like.

[0142] In the embodiments, reference Figure 2 The described first, second, and third regions A1, A2, and A3 may be included in the base layer BL.

[0143] In an embodiment, at least one inorganic layer is formed on the upper surface of the base layer BL. The inorganic layer may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. The inorganic layer may be formed into a plurality of layers. The multilayer inorganic layer may include a barrier layer BRL and / or a buffer layer BFL to be described later. The barrier layer BRL and the buffer layer BFL may be selectively provided.

[0144] In an embodiment, the barrier layer BRL prevents foreign matter from entering from the outside. The barrier layer BRL may include a silicon oxide layer and a silicon nitride layer. Each of these layers may be provided in plural, and the silicon oxide layer and the silicon nitride layer may be alternately stacked.

[0145] In an embodiment, a buffer layer BFL may be disposed on the barrier layer BRL. The buffer layer BFL improves the bonding force between the base layer BL and the conductive pattern or the semiconductor pattern. The buffer layer BFL may include a silicon oxide layer and a silicon nitride layer. The silicon oxide layer and the silicon nitride layer may be alternately stacked.

[0146] In an embodiment, the first semiconductor pattern OSP1 is disposed on the buffer layer BFL. The first semiconductor pattern OSP1 may include a silicon semiconductor. The first semiconductor pattern OSP1 may be a polycrystalline silicon semiconductor. However, the embodiment is not limited thereto, and the first semiconductor pattern OSP1 may include amorphous silicon.

[0147] In an embodiment, the first semiconductor pattern OSP1 may include an input region (or a first portion), an output region (or a second portion), and a channel region (or a third portion) defined between the input region and the output region. The channel region of the first semiconductor pattern OSP1 may be defined corresponding to a first control electrode GE1 to be described later. The input region and the output region are doped with a dopant and thus have a conductivity relatively higher than that of the channel region. The input region and the output region may be doped with an N-type dopant. In an embodiment, an N-type first thin film transistor T1 is exemplarily described, but the first thin film transistor T1 may also be a P-type thin film transistor.

[0148] In the embodiment, the first insulating layer 10 is disposed on the buffer layer BFL. The first insulating layer 10 is connected to the plurality of pixels PX (see Figure 5 ) commonly overlap and cover the first semiconductor pattern OSP1. The first insulating layer 10 may be an inorganic layer and / or an organic layer, and may have a single layer or a multilayer structure. The first insulating layer 10 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. In an embodiment, the first insulating layer 10 may be a single-layer silicon oxide layer.

[0149] In an embodiment, the first control electrode GE1 is disposed on the first insulating layer 10. The first control electrode GE1 overlaps the channel region of the first semiconductor pattern OSP1.

[0150] In the embodiment, the second insulating layer 20 covering the first control electrode GE1 is disposed on the first insulating layer 10. The second insulating layer 20 is connected to the plurality of pixels PX (see Figure 5 ) are commonly overlapped. The second insulating layer 20 may be an inorganic layer and / or an organic layer, and may have a single layer or a multilayer structure. The second insulating layer 20 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. In an embodiment, the second insulating layer 20 may be a single layer silicon oxide layer.

[0151] In an embodiment, the upper electrode UE may be further disposed on the second insulating layer 20. The upper electrode UE may overlap the first control electrode GE1.

[0152] In an embodiment, a third insulating layer 30 covering the upper electrode UE is disposed on the second insulating layer 20. The third insulating layer 30 may be an inorganic layer and / or an organic layer, and may have a single layer or a multilayer structure. The third insulating layer 30 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. In an embodiment, the third insulating layer 30 may be a single layer silicon oxide layer.

[0153] In an embodiment, the second semiconductor pattern OSP2 is disposed on the third insulating layer 30. The second semiconductor pattern OSP2 may include an oxide semiconductor. The second semiconductor pattern OSP2 may include a crystalline oxide semiconductor or an amorphous oxide semiconductor. For example, the oxide semiconductor may include an oxide of a metal such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti) or a mixture of metals such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti) and oxides thereof. The oxide semiconductor may include indium tin oxide (ITO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium zinc oxide (IZO), indium oxide (InO), or the like. 2 O 3 ), titanium oxide (TiO 2 ), indium zinc tin oxide (IZTO), zinc tin oxide (ZTO), etc.

[0154] In an embodiment, the second semiconductor pattern OSP2 may include an input region (or first portion), an output region (or second portion), and a channel region (or third portion) defined between the input region and the output region. The input region and the output region may include impurities. The channel region of the second semiconductor pattern OSP2 may be defined to correspond to a second control electrode GE2 to be described later.

[0155] In an embodiment, the impurities of the second semiconductor pattern OSP2 may be reduced metal materials. The input region and the output region may include metal materials reduced from metal oxides constituting the channel region. Accordingly, the second thin film transistor T2 may reduce leakage current and may thus act as a switching element with improved on-off characteristics.

[0156] In an embodiment, the insulating pattern GIP is disposed on the channel region of the second semiconductor pattern OSP2. The second control electrode GE2 is disposed on the insulating pattern GIP. The second control electrode GE2 at least overlaps with the insulating pattern GIP. The edge of the insulating pattern GIP may be arranged along the edge of the second control electrode GE2. The second control electrode GE2 may have the same shape as the insulating pattern GIP on a plane. The second control electrode GE2 may be disposed inside the insulating pattern GIP on a plane.

[0157] In an embodiment, a fourth insulating layer 40 covering the second semiconductor pattern OSP2 and the second control electrode GE2 is disposed on the third insulating layer 30. The fourth insulating layer 40 may be an inorganic layer and / or an organic layer, and may have a single-layer or multi-layer structure. The fourth insulating layer 40 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. In an embodiment, the fourth insulating layer 40 may include a silicon oxide layer and a silicon nitride layer. The fourth insulating layer 40 may include a plurality of silicon oxide layers and a plurality of silicon nitride layers alternately stacked.

[0158] In the embodiment, the first input electrode DE1, the first output electrode SE1, the second input electrode DE2, and the second output electrode SE2 are disposed on the fourth insulating layer 40. The first input electrode DE1 and the first output electrode SE1 are connected to the first semiconductor pattern OSP1 through first and second contact holes CH1 and CH2 that expose the input region and the output region of the first semiconductor pattern OSP1, respectively. The first and second contact holes CH1 and CH2 pass through the first, second, third, and fourth insulating layers 10, 20, 30, and 40.

[0159] In an embodiment, the second input electrode DE2 and the second output electrode SE2 are connected to the second semiconductor pattern OSP2 through third and fourth contact holes CH3 and CH4 respectively exposing the input and output regions of the second semiconductor pattern OSP2 . The third and fourth contact holes CH3 and CH4 pass through the fourth insulating layer 40 .

[0160] In an embodiment, a fifth insulating layer 50 covering the first input electrode DE1, the first output electrode SE1, the second input electrode DE2, and the second output electrode SE2 is disposed on the fourth insulating layer 40. The fifth insulating layer 50 may be an organic layer and may have a single layer or multi-layer structure.

[0161] In an embodiment, the connection electrode CNE is disposed on the fifth insulating layer 50. The connection electrode CNE may be connected to the first output electrode SE1 through a fifth contact hole CH5 passing through the fifth insulating layer 50. A sixth insulating layer 60 (or a passivation layer) covering the connection electrode CNE is disposed on the fifth insulating layer 50. The sixth insulating layer 60 may be an organic layer and may have a single-layer or multi-layer structure.

[0162] In an embodiment, the fifth insulating layer 50 and the sixth insulating layer 60 may each be a single-layer polyimide resin layer. The embodiment is not limited thereto, and the fifth insulating layer 50 and the sixth insulating layer 60 may each include at least one of acrylate resin, methacrylate resin, polyisoprene resin, vinyl resin, epoxy resin, urethane resin, cellulose resin, siloxane resin, polyamide resin, and perylene resin.

[0163] In the embodiment, the light emitting element OLED is disposed on the sixth insulating layer 60. The anode AE ​​of the light emitting element OLED is disposed on the sixth insulating layer 60. The anode AE ​​is connected to the connection electrode CNE through the sixth contact hole CH6 passing through the sixth insulating layer 60. The pixel defining layer PDL is disposed on the sixth insulating layer 60.

[0164] In an embodiment, the opening OP of the pixel defining film PDL exposes at least a portion of the anode AE. The opening OP of the pixel defining film PDL may define the pixel PX (see Figure 5 ) of the light emitting area PXA. For example, in a specific embodiment, a plurality of pixels PX (see Figure 5 ). An area where a plurality of pixels PX are disposed may be defined as a pixel area, and one pixel area may include a light emitting area PXA and a non-light emitting area NPXA disposed adjacent to the light emitting area PXA. The non-light emitting area NPXA may surround the light emitting area PXA.

[0165] In an embodiment, the hole control layer HCL may be commonly disposed in the light emitting area PXA and the non-light emitting area NPXA. A common layer such as the hole control layer HCL may span across a plurality of pixels PX (see Figure 5 The hole control layer HCL may include a hole transport layer and a hole injection layer.

[0166] In an embodiment, the organic light emitting layer EML is disposed on the hole control layer HCL. The organic light emitting layer EML may be disposed only in a region corresponding to the opening OP. The organic light emitting layer EML may be provided for a plurality of pixels PX (see Figure 5 ) are each formed separately.

[0167] In the embodiment, the patterned organic light emitting layer EML is exemplarily illustrated, but the organic light emitting layer EML may be commonly provided in a plurality of pixels PX. In this case, the organic light emitting layer EML may generate white light. In addition, the organic light emitting layer EML may have a multi-layer structure.

[0168] In an embodiment, the electron control layer ECL is disposed on the organic light emitting layer EML. The electron control layer ECL may include an electron transport layer and an electron injection layer. The cathode CE is disposed on the electron control layer ECL. The electron control layer ECL and the cathode CE are commonly disposed in a plurality of pixels PX (see Figure 5 )middle.

[0169] In an embodiment, the thin film encapsulation layer TFE is disposed on the cathode CE. The thin film encapsulation layer TFE is commonly disposed in a plurality of pixels PX. In an embodiment, the thin film encapsulation layer TFE directly covers the cathode CE. According to an embodiment, a cover layer covering the cathode CE may be further provided. The stacked structure of the light emitting element OLED according to an embodiment may also be from Fig. 7A The structure shown in the figure is a vertical inversion of the structure.

[0170] In an embodiment, the thin film encapsulation layer TFE may cover the light emitting element OLED. The thin film encapsulation layer TFE may include two inorganic layers LIL and UIL and an organic layer OL disposed therebetween. According to an embodiment, the thin film encapsulation layer TFE may include a plurality of inorganic layers and a plurality of organic layers alternately stacked.

[0171] In an embodiment, the inorganic layers LIL and UIL protect the light emitting element OLED from moisture / oxygen, and the organic layer OL protects the light emitting element OLED from foreign matter such as dust particles. The inorganic layers LIL and UIL may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer, etc., and the type of the layer is not particularly limited thereto. The organic layer OL may include an acrylic organic layer, and is not particularly limited thereto.

[0172] According to an embodiment, the first thin film transistor T1 may include a silicon semiconductor (and in particular, a polysilicon semiconductor), and may therefore have high electron mobility. The second thin film transistor T2 may include an oxide semiconductor, thereby reducing leakage current. Therefore, the pixel PX (see Figure 5 ) driving voltage and prevent malfunction.

[0173] According to an embodiment, the first electrode and the second electrode of the capacitor may be formed by the same process as the process of the components of the first thin film transistor T1. For example, the first electrode of the capacitor may be disposed on the first insulating layer 10. The first electrode may be formed by the same process as the process of the first control electrode GE1. The first electrode may be connected to the first control electrode GE1. The second insulating layer 20 covers the first electrode. The second electrode of the capacitor may be disposed on the second insulating layer 20.

[0174] In an embodiment, the upper electrode UE may be electrically connected to the second electrode. In addition, the upper electrode UE and the second electrode of the capacitor may be formed by the same process and may therefore have an integral shape. A third insulating layer 30 covering the second electrode and the upper electrode UE is disposed on the second insulating layer 20.

[0175] In an embodiment, the input sensor ISP may be directly disposed on the display panel DP. The input sensor ISP may include at least one of the conductive layers TML1 and TML2 and sensing insulating layers TIL1, TIL2, and TIL3. The sensing insulating layers TIL1, TIL2, and TIL3 may include an inorganic material or an organic material.

[0176] In an embodiment, the first sensing insulating layer TIL1 may be directly disposed on the second inorganic layer UIL of the thin film encapsulation layer TFE. The first conductive layer TML1 is disposed on the first sensing insulating layer TIL1. The second sensing insulating layer TIL2 may be disposed on the first sensing insulating layer TIL1 and cover the first conductive layer TML1. The second conductive layer TML2 is disposed on the second sensing insulating layer TIL2. The third sensing insulating layer TIL3 may be disposed on the second sensing insulating layer TIL2 and cover the second conductive layer TML2. However, the embodiment is not limited thereto, the first sensing insulating layer TIL1 may be omitted, and the first conductive layer TML1 may be directly disposed on the second inorganic layer UIL, and the arrangement is not limited to any one embodiment.

[0177] According to an embodiment, the third sensing insulation layer TIL3 may include an organic material.

[0178] In the embodiments, referring to Figure 6 Among the described sensing electrodes TE1 and TE2, the first connection pattern CP1 may be included in the first conductive layer TML1. The first sensing pattern SP1, the second sensing pattern SP2, and the second connection pattern CP2 may be included in the second conductive layer TML2. Therefore, the adjacent first sensing patterns SP1 may be connected to the first connection pattern CP1 through the contact holes defined in the second sensing insulating layer TIL2.

[0179] In the examples and with reference to Figure 7BThe second area A2 has a stack structure similar to that of the active area AA in cross section. The barrier layer BRL, the buffer layer BFL, and the first to sixth insulating layers 10 to 60 are sequentially stacked on the upper surface of the base layer BL.

[0180] In an embodiment, the groove GV may be defined in the second area A2 of the display panel DP. In an embodiment, the groove GV may be formed by passing through layers from the barrier layer BRL to the fourth insulating layer 40. The groove GV may expose the base layer BL overlapping the second area A2.

[0181] In an embodiment, the lower groove GV-1 overlapping the second area A2 is defined in the barrier layer BRL and / or the buffer layer BFL. The lower groove GV-1 is defined in the bending area CA. The bending area CA may be defined as when the second area A2 is about the bending axis AX (see Figure 4 The width of the base layer BL exposed by the lower groove GV-1 in the second direction DR2 may be smaller than the width of the bending area CA in the second direction DR2.

[0182] In an embodiment, an upper groove GV-2 overlapping the second area A2 is defined in the first to fourth insulating layers 10 to 40, respectively. The upper groove GV-2 is defined in the bending area CA. The upper surface of the uppermost inorganic layer among the inorganic layers constituting the barrier layer BRL and the buffer layer BFL may be partially exposed from the first to fourth insulating layers 10 to 40, respectively.

[0183] In an embodiment, side surfaces of the barrier layer BRL and the buffer layer BFL defining the lower groove GV-1 may each have a predetermined slope in cross section. Side surfaces of the first to fourth insulating layers 10 to 40 defining the upper groove GV-2 may each have a predetermined slope in cross section.

[0184] According to an embodiment, Figure 7B Different from that shown in FIG. 4 , the width of the upper groove GV- 2 corresponding to the fourth insulating layer 40 in the second direction DR2 may be greater than the width of the bending area CA in the second direction DR2.

[0185] In an embodiment, a fifth insulating layer 50, which is an organic layer, is disposed inside the lower groove GV-1 and the upper groove GV-2. The fifth insulating layer 50 contacts the upper surface of the base layer BL, the inclined surface of the lower groove GV-1, and the inclined surface of the upper groove GV-2. The fifth insulating layer 50 may contact a portion of the upper surface of the buffer layer BFL exposed from the first insulating layer 10 to the fourth insulating layer 40. Since the fifth insulating layer 50 including an organic material is filled in the groove GV defined in the second area A2, the flexibility of the second area A2 is improved.

[0186] In an embodiment, at least a portion of the first data line DL1 may be disposed on the fifth insulating layer 50. The first data line DL1 may be aligned with the reference Figure 5 The data lines DL1 to DLn described above correspond to any one of the data lines DL1 to DLn described above. The data lines DL1 to DLn may be connected to the data lines disposed in the third area A3 (see FIG. 1 ) via the second area A2. Figure 5 ) in the pad PD (see Figure 5 ).

[0187] According to an embodiment, another portion of the first data line DL1 may be disposed on a different layer. For example, the other portion of the first data line DL1 may also be disposed on the fourth insulating layer 40. The at least one portion of the first data line DL1 and the other portion may be connected to each other through a contact hole passing through the fifth insulating layer 50. The contact hole may be disposed in the peripheral area NAA of the first area A1 (see Fig. 7A ). The sixth insulating layer 60 protects the first data line DL1 by covering the first data line DL1. The sixth insulating layer 60 may include an organic material.

[0188] Figure 8 is a plan view of a display module according to an embodiment. Fig.9A According to the embodiment along Figure 8 A cross-sectional view taken along line IV-IV'. Fig. 9B According to the embodiment along Figure 8 A cross-sectional view taken along line V-V'.

[0189] Figure 8 Only illustrations are included in the reference Figure 5 The display panel DP described and included in the reference Figure 6 Some of the components in the input sensor ISP are described.

[0190] In an embodiment, the pixel PX is connected to Figure 5 ) may extend from the first area A1 to the third area A3 via the second area A2. The data line DL may be connected to a driving chip DIC disposed in the third area A3 and connected to the pixel pad.

[0191] In an embodiment, the first ground pattern GN-L included in the ground portion GNL may be connected to one end of the first ground line GC-L through the left contact hole CN-GL, and the other end of the first ground line GC-L may be connected to the first ground pad GP-L.

[0192] In an embodiment, the left contact hole CN-GL may be formed by overlapping the display panel DP (see Figure 5 ) defined in the first ground contact hole CN-G1 (see Figure 5 ) and input sensor ISP (see Figure 6) defined in the third ground contact hole CN-G3 (see Figure 6 )limited.

[0193] In an embodiment, the second ground pattern GN-R included in the ground portion GNL may be connected to one end of the second ground line GC-R through the right contact hole CN-GR, and the other end of the second ground line GC-R may be connected to the second ground pad GP-R.

[0194] In an embodiment, the right contact hole CN-GR may be formed by overlapping the display panel DP (see Figure 5 ) defined in the second ground contact hole CN-G2 (see Figure 5 ) and input sensor ISP (see Figure 6 ) defined in the fourth ground contact hole CN-G4 (see Figure 6 )limited.

[0195] In the embodiment, the display module DM according to the embodiment may include a shielding portion ES. The shielding portion ES may be disposed in the second area A2 and the third area A3 of the display panel DP. Therefore, the shielding portion ES may be bent corresponding to the second area A2.

[0196] In an embodiment, the shielding portion ES may include pattern portions EP1 and EP2 and a connecting portion EC. The pattern portions EP1 and EP2 may be exposed to the outside in the second area A2. The pattern portions EP1 and EP2 may be spaced apart from each other in the first direction DR1. The first pattern portion EP1 may be disposed adjacent to the first ground pad GP-L, and the second pattern portion EP2 may be disposed adjacent to the second ground pad GP-R.

[0197] In an embodiment, the connection portion EC may connect the pattern portions EP1 and EP2 spaced apart from each other. According to an embodiment, one portion of the connection portion EC extending from the first pattern portion EP1 may be connected to the first ground line GC-L, and the first pattern portion EP1 may be connected to the first ground pad GP-L through the one portion of the connection portion EC and the first ground line GC-L.

[0198] In an embodiment, a portion of the connection portion EC extending from the second pattern portion EP2 can be connected to the second ground line GC-R, and the second pattern portion EP2 can be connected to the second ground pad GP-R through the portion of the connection portion EC and the second ground line GC-R. Accordingly, when a signal is applied to the ground portion GNL, the same signal can also be provided to the shielding portion ES.

[0199] According to an embodiment, the driving chip DIC may be disposed between the ground pads GP-L and GP-R and the pattern parts EP1 and EP2 .

[0200] Fig.9AThe connection relationship among the shielding portion ES, the first ground line GC-L, and the first ground pad GP-L according to the embodiment is illustrated.

[0201] In the examples and with reference to Fig.9A , the first ground pad GP-L may include a first pattern P1 disposed on the fourth insulating layer 40 and a second pattern P2 overlapping the first pattern P1. The second pattern P2 may be disposed on the pad hole defined in the fifth insulating layer 50 and contact the first pattern P1. Figure 2 The described pads in the flexible circuit film FCB may be connected to the second pattern P2.

[0202] In the present specification, the insulating layer disposed on the uppermost side of the insulating layer disposed in the second area A2 of the display module DM may be defined as a cover portion CVL. In an embodiment, the cover portion CVL may be the same as that of the reference Figure 7B The sixth insulating layer 60 described corresponds to . Therefore, the cover part CVL may include an organic material.

[0203] In an embodiment, the shielding portion ES may be disposed on the fifth insulating layer 50, and at least a portion of the shielding portion ES may be covered by the cover portion CVL. The first pattern portion EP1 and the second pattern portion EP2 of the shielding portion ES (see FIG. 5 ) may be provided on the fifth insulating layer 50, and at least a portion of the shielding portion ES may be covered by the cover portion CVL. Fig. 9B ) may be exposed to the outside through the opening C-OP defined in the cover portion CVL. The connection portion EC may be covered by the cover portion CVL.

[0204] In an embodiment, the shielding portion ES may include a conductive material. For example, the shielding portion ES may be Fig. 7A The connection electrode CNE is formed by the same process as described above and may include the same process as described in reference Fig. 7A The material of the connecting electrode CNE is the same material as described.

[0205] According to an embodiment, the shielding portion ES and the second pattern P2 may be disposed on the same layer. That is, the shielding portion ES and the second pattern P2 may be disposed on the fifth insulating layer 50.

[0206] Fig. 9B FIG. 1 shows an embodiment of the shielding portion ES overlapping the data line DL. Figure 7B As described, since the data line DL is disposed on the fifth insulating layer 50, the data line DL is disposed on the same layer as the layer where the shielding portion ES is disposed. Therefore, a portion of the connection portion EC of the shielding portion ES may cross the data line DL on a plane. According to an embodiment, the portion of the connection portion EC that crosses the data line DL may be disconnected.

[0207] The shielding portion ES according to an embodiment may further include a connection pattern ER. The connection pattern ER may be provided at a different layer from the layer where the connection portion EC is provided and overlap with a place where the data line DL and the connection portion EC cross each other. The connection pattern ER may be connected to a portion of the connection portion EC that is disconnected and spaced apart from each other with the data line DL therebetween. According to an embodiment, an additional covering portion covering the connection pattern ER and provided in the second area A2 may be further included.

[0208] According to an embodiment, static electricity flowing from the outside into the second area A2 may first flow into the pattern parts EP1 and EP2 exposed to the outside, and then flow through the connection part EC, the ground lines GC-L and GC-R, the ground pads GP-L and GP-R, and the flexible circuit film FCB (see Figure 2 ) is dissipated to the outside. Therefore, a display device DD having improved electrostatic discharge (ESD) characteristics can be provided (see Figure 1 ).

[0209] Fig.10 is a cross-sectional view of a display module according to an embodiment. Fig.11 is a cross-sectional view of a display module according to an embodiment. Figures 1 to 9B The same / similar components to the components described are denoted by the same / similar reference numerals or symbols, and duplicate descriptions are omitted. Fig.10 and Fig.11 FIG. 1 shows a diagram of a method according to an embodiment of the present invention. Fig.9A The corresponding cross section of the zone.

[0210] In the examples and with reference to Fig.10 , the first ground pad GP-L may include a first pattern P1 disposed on the fourth insulating layer 40 and a second pattern P2 overlapping the first pattern P1. The second pattern P2 may be disposed on the pad hole defined in the fifth insulating layer 50 and contact the first pattern P1. Figure 2 The described pads in the flexible circuit film FCB may be connected to the second pattern P2.

[0211] In an embodiment, the shielding portion ES-A may be disposed on the fourth insulating layer 40. The fourth insulating layer 40 may be filled in the groove GV and contact the base layer BL. The shielding portion ES-A may include a first pattern portion EP1 and a connection portion EC. The first pattern portion EP1 and the connection portion EC may be disposed on the same layer as the layer in which the first pattern P1 is disposed. That is, the shielding portion ES-A may be disposed on the fourth insulating layer 40. The shielding portion ES-A may be disposed on the base layer BL by contacting the base layer BL. Fig. 7A The first input electrode DE1, the first output electrode SE1, the second input electrode DE2, and the second output electrode SE2 are formed by the same process as described above and may include the same process as described above. Fig. 7AThe material of the first input electrode DE1 , the first output electrode SE1 , the second input electrode DE2 , and the second output electrode SE2 described above are the same material.

[0212] According to an embodiment, the first pattern part EP1 may be exposed to the outside through the seventh contact hole 50-OP defined in the fifth insulating layer 50 and the opening C-OP defined in the cover part CVL. The connection part EC may be directly connected to the first pattern P1.

[0213] In the examples and with reference to Fig.11 , the shielding portion ES-B may be disposed on the second sensing insulating layer TIL2. Fig. 7A The described first and second sensing insulating layers TIL1 and TIL2 may extend from the first area A1 to the second area A2. The shielding part ES-B may include the same material as that of the second conductive layer TML2.

[0214] In an embodiment, the first pattern portion EP1 may be exposed to the outside through the opening C-OP defined in the cover portion CVL. The cover portion CVL may include an organic material. In an embodiment, the cover portion CVL may be connected to the reference Fig. 7A However, the embodiment is not limited thereto, and the cover part CVL is not limited to any one embodiment as long as it has an opening exposing the first pattern part EP1 and defined therein and includes an organic material.

[0215] In an embodiment, the connection portion EC may be disposed on the contact hole CN-B passing through at least one of the first sensing insulating layer TIL1, the second sensing insulating layer TIL2, the first inorganic layer LIL, the second inorganic layer UIL, and the sixth insulating layer 60, and may thus be connected to the first ground line GC-L. Therefore, through the connection portion EC connected to the first ground line GC-L, the first pattern portion EP1 may be connected to the first ground pad GP-L.

[0216] Fig.12 is a plan view of a display module according to an embodiment. Fig.13 is a plan view of a display module according to an embodiment. Fig.14 is a plan view of a display module according to an embodiment. Fig.15 is a plan view of a display module according to an embodiment.

[0217] With reference Figures 1 to 9B The same / similar components to the components described are denoted by the same / similar reference numerals or symbols, and duplicate descriptions are omitted. Figures 12 to 15 Only illustrations are included in the reference Figure 5 The display panel DP described and included in the reference Figure 6The description of the data line DL, the ground lines GC-L and GC-R, the driving chip DIC, the ground pads GP-L and GP-R, and the contact holes CN-GL and CN-GR can be the same as that of the reference Figure 8 The description corresponds to .

[0218] In the examples and with reference to Fig.12 , the shielding part ES- 1 may include first to third pattern parts EP1 , EP2 , and EP3 and a connection part EC.

[0219] In an embodiment, the first to third pattern portions EP1 to EP3 may be arranged along the first direction DR1. The third pattern portion EP3 may be disposed between the first and second pattern portions EP1 and EP2. When viewed from the second direction DR2, the third pattern portion EP3 may overlap the driving chip DIC.

[0220] In the embodiment, the first pattern portion EP1 to the third pattern portion EP3 can each be referred to as Fig.9A The opening C-OP of the cover portion CVL is described to be exposed to the outside.

[0221] In an embodiment, the connection portion EC may connect the first to third pattern portions EP1 to EP3 to each other. A portion of the connection portion EC extending from the first pattern portion EP1 may be connected to the first ground line GC-L, and a portion of the connection portion EC extending from the second pattern portion EP2 may be connected to the second ground line GC-R.

[0222] In the examples and with reference to Fig.13 , the shielding portion ES-2 may include a first group of pattern portions and a second group of pattern portions. The first group of pattern portions and the second group of pattern portions may be spaced apart from each other along the second direction DR2.

[0223] In an embodiment, the first group of pattern parts may include 1-1th to 1-3th pattern parts EP1-1, EP1-2, and EP1-3.

[0224] In an embodiment, the 1-1st to 1-3rd pattern portions EP1-1 to EP1-3 may be arranged along the first direction DR1. The 1-2nd pattern portion EP1-2 may be disposed between the 1-1st and 1-3rd pattern portions EP1-3. When viewed from the second direction DR2, the 1-2nd pattern portion EP1-2 may overlap the driving chip DIC.

[0225] In an embodiment, the second group of pattern parts may include 2-1 to 2-3 pattern parts EP2-1, EP2-2, and EP2-3.

[0226] In an embodiment, the 2-1st to 2-3rd pattern portions EP2-3 may be arranged along the first direction DR1. The 2-2nd pattern portion EP2-2 may be disposed between the 2-1st and 2-3rd pattern portions EP2-3. When viewed from the second direction DR2, the 2-2nd pattern portion EP2-2 may overlap the driving chip DIC.

[0227] In an embodiment, the 1-1th pattern portion EP1-1 and the 2-1th pattern portion EP2-1 may be arranged along the second direction DR2, the 1-2th pattern portion EP1-2 and the 2-2nd pattern portion EP2-2 may be arranged along the second direction DR2, and the 1-3th pattern portion EP1-3 and the 2-3rd pattern portion EP2-3 may be arranged along the second direction DR2.

[0228] In an embodiment, the pattern portions included in the first group of pattern portions and the second group of pattern portions can each be represented by reference to Fig.9A The opening C-OP of the cover portion CVL is exposed to the outside. According to an embodiment, at least one of the pattern portions may be referred to as Fig.9A The covering portion CVL is described to cover the pattern portion, and is not limited to any one embodiment.

[0229] Fig.13 The pattern parts are arranged in two rows and three columns, but the embodiment is not limited thereto. In the embodiment, from the cover part CVL (see Fig.9A )The number of exposed pattern portions and their arrangement can be changed.

[0230] In an embodiment, the connection portion EC may connect the pattern portions included in the first group of pattern portions and the second group of pattern portions together. A portion of the connection portion EC extending from the 2-1st pattern portion EP2-1 may be connected to the first ground line GC-L, and a portion of the connection portion EC extending from the 2-3rd pattern portion EP2-3 may be connected to the second ground line GC-R.

[0231] In the examples and with reference to Fig.14 , the driver chip DIC can be connected to the driver ground pad DI-P. The static electricity flowing into the driver chip DIC can be dissipated to the flexible circuit film FCB through the driver ground pad DI-P (see Figure 2 ).

[0232] In an embodiment, the shielding portion ES- 3 may include first to third pattern portions EP1 , EP2 , and EP3 and a connection portion EC.

[0233] In an embodiment, the first to third pattern portions EP1 to EP3 may be arranged along the first direction DR1. The third pattern portion EP3 may be disposed between the first pattern portion EP1 and the second pattern portion EP2. The first to third pattern portions EP1 to EP3 may each be arranged by referring to Fig.9A The opening C-OP of the cover portion CVL is described to be exposed to the outside.

[0234] In an embodiment, the connection portion EC may connect the first to third pattern portions EP1 to EP3 to each other. A portion of the connection portion EC extending from the first pattern portion EP1 may be connected to the first ground line GC-L, and a portion of the connection portion EC extending from the second pattern portion EP2 may be connected to the second ground line GC-R.

[0235] According to an embodiment, one portion of the connection portion EC extending from the third pattern portion EP3 may be connected to the driving chip DIC. Therefore, the third pattern portion EP3 may be connected to the driving ground pad DI-P through the connection portion EC.

[0236] In the examples and with reference to Fig.15 The display module DM may include a display panel DP (see Figure 5 ) and includes alignment marks AL-1 and AL-2 of conductive material. For example, the alignment marks AL-1 and AL-2 may be arranged at the reference Fig. 7A The fourth insulating layer 40 or the fifth insulating layer 50 is described. The alignment marks AL-1 and AL-2 may be disposed in the first area A1 located adjacent to the second area A2, but the present invention is not limited thereto.

[0237] In an embodiment, the alignment marks AL-1 and AL-2 may be formed in the bonding window WM (see Figure 3 ) process, in combination with optical film OTF (see Figure 3 ) process, in combination with the functional layer MP (see Figure 4 ) process and in the process of combining the driver chip DIC for component alignment.

[0238] The shielding part ES- 4 according to the embodiment may include first and second pattern parts EP1 and EP2 and a connection part EC.

[0239] In an embodiment, the first pattern portion EP1 and the second pattern portion EP2 may be arranged along the first direction DR1. The first pattern portion EP1 and the second pattern portion EP2 may each be arranged by referring to Fig.9A The opening C-OP of the cover portion CVL is described to be exposed to the outside.

[0240] In an embodiment, the connection portion EC may connect the first pattern portion EP1 and the second pattern portion EP2 to each other. A portion of the connection portion EC extending from the first pattern portion EP1 may be connected to the first ground line GC-L, and a portion of the connection portion EC extending from the second pattern portion EP2 may be connected to the second ground line GC-R.

[0241] According to an embodiment, another portion of the connection portion EC extending from the first pattern portion EP1 may be connected to the first alignment mark AL- 1 , and another portion of the connection portion EC extending from the second pattern portion EP2 may be connected to the second alignment mark AL- 2 .

[0242] According to the embodiment, a display device having improved electrostatic discharge (ESD) characteristics may be provided by including a shielding part disposed in a bending region of a display panel and having one portion exposed to the outside.

[0243] Although some embodiments of the present invention have been described, it is understood that the present invention should not be limited to these embodiments, but those of ordinary skill in the art can make various changes and modifications within the spirit and scope of the present invention. Therefore, the technical scope of the present invention should not be limited to the content described herein. Moreover, the embodiments or parts of the embodiments can be combined in whole or in part without departing from the scope of the present invention.

Claims

1. A display device, comprising: The display panel comprises: a substrate layer including a first area, a second area and a third area, the first area having an effective area, the second area being bent about a bending axis, the third area being spaced apart from the first area, and the second area being arranged between the first area and the third area; a pixel overlapping the effective area; a shielding portion being arranged in the second area; and a pad being arranged in the third area; an input sensor disposed on the display panel and comprising a sensing electrode overlapping the active area and a ground portion disposed in a peripheral area adjacent to the active area; and The flexible circuit film is connected to the pads, wherein the grounding portion is connected to a ground pad among the pads, and The shielding portion includes a pattern portion exposed to the outside and a connecting portion connected to the pattern portion and the ground pad.

2. The display device according to claim 1, wherein: The display panel further comprises: a covering portion defining an opening exposing the pattern portion and disposed in the second region to cover the connecting portion, Wherein, the covering portion comprises an organic material.

3. The display device according to claim 2, wherein: The display panel further comprises: a ground line disposed in the first region, the second region, and the third region and having one end connected to the ground portion through a contact hole defined in the first region and the other end connected to the ground pad, Wherein, the grounding portion is connected to the grounding pad through the grounding wire.

4. The display device according to claim 3, wherein: The connection portion is connected to the ground pad through the ground line.

5. The display device according to claim 4, wherein: The display panel further comprises: a data line disposed in the first area, the second area, and the third area and connected to a pixel pad among the pixels and the pads, Wherein, the connecting portion crosses the data line on a plane.

6. The display device according to claim 5, wherein: The shielding portion further comprises: a connection pattern disposed in a different layer from a layer in which the connection portion is disposed and overlapping a location where the data line and the connection portion cross each other, wherein the connecting portion is disconnected at the location where the connecting portion crosses the data line, and The connection parts are disconnected and spaced apart from each other and portions of the data lines therebetween are connected by the connection pattern.

7. The display device according to claim 3, wherein: The ground pad includes a first pattern and a second pattern disposed on the first pattern, wherein the second pattern contacts the flexible circuit film.

8. The display device according to claim 7, wherein: The shielding part is disposed on the same layer as the layer where the first pattern is disposed.

9. The display device according to claim 7, wherein: The shielding part is disposed on the same layer as the layer where the second pattern is disposed.

10. The display device according to claim 3, wherein: The input sensor includes a first sensing insulating layer directly disposed on the display panel, a first conductive layer disposed on the first sensing insulating layer and constituting a portion of the sensing electrode, a second sensing insulating layer covering the first conductive layer and disposed on the first sensing insulating layer, and a second conductive layer disposed on the second sensing insulating layer and constituting the remaining portion of the sensing electrode.

11. The display device according to claim 10, wherein: The shielding part includes the same material as that of the second conductive layer, and the connecting part is connected to the ground line by passing through at least one of the first sensing insulating layer and the second sensing insulating layer.

12. The display device according to claim 1, wherein: The pattern part includes a plurality of pattern parts spaced apart from each other, and wherein the connection part is connected to each of the plurality of pattern parts.

13. The display device according to claim 12, wherein: The display panel further includes a driving chip disposed in the third area, wherein: The driving chip is disposed between the ground pad and the plurality of pattern parts on a plane.

14. The display device according to claim 13, wherein: The driving chip is connected to a driving ground pad among the pads, and the connecting portion is connected to the driving ground pad.

15. The display device according to claim 1, wherein: The display panel further includes an alignment mark disposed in the first region and including a conductive material.

16. The display device according to claim 15, wherein: The connection portion is connected to the alignment mark.

17. The display device according to any one of claims 1 to 16, wherein: The pixel includes a thin film transistor and a light emitting element connected to the thin film transistor, the thin film transistor includes a semiconductor pattern, a control electrode overlapping the semiconductor pattern, and a source and a drain connected to the semiconductor pattern, wherein: The display panel further comprises: A blocking layer is arranged on the base layer, a buffer layer is arranged on the blocking layer, a first insulating layer is arranged on the buffer layer and covers the semiconductor pattern, a second insulating layer is arranged on the first insulating layer and covers the control electrode, a third insulating layer is arranged on the second insulating layer and covers the upper electrode overlapping the control electrode, a fourth insulating layer is arranged on the third insulating layer and the source and the drain are arranged thereon, a fifth insulating layer is arranged on the fourth insulating layer and covers the source and the drain, and a sixth insulating layer is arranged on the fifth insulating layer.

18. The display device according to claim 17, wherein: The display panel further includes a connection electrode connected to the source electrode through a contact hole defined in the fifth insulating layer and covered by the sixth insulating layer.

19. The display device according to claim 18, wherein: A groove passing through the barrier layer, the buffer layer, the first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer to expose the base layer is defined in the second region, and wherein the fifth insulating layer is disposed inside the groove.

20. The display device according to claim 19, wherein: At least a portion of the shielding portion is covered by the sixth insulating layer.

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