Semiconductor structure and forming method thereof
By designing the groove structure of multi-layer electrodes and dielectric layers in the semiconductor structure and optimizing the via interconnect structure, the problem of insufficient capacitance density of existing MIM capacitors is solved, and the performance of the semiconductor structure is significantly improved.
Patent Information
- Application Number
- CN202310772178.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-06-27
- Publication Date
- 2024-12-27
AI Technical Summary
The equivalent capacitance density of existing MIM capacitors has not yet reached a satisfactory level, and it is difficult to improve the performance of semiconductor structures.
A semiconductor structure is designed, including a substrate, a multi-layer electrode and a dielectric layer. By forming a groove structure between the electrode layer and the dielectric layer, the arrangement and process of the through-hole interconnection structure are optimized, and the relative of the electrode layer is increased. area, thereby increasing the capacitance density of MIM capacitors.
By optimizing the structure and process, the capacitance density of MIM capacitors is significantly improved and the performance of semiconductor structures is enhanced.
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Figure CN119212548A_ABST
Abstract
Description
Technical Field
[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art
[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in materials and design have produced successive generations of integrated circuits. Each generation features smaller and more complex circuits than the previous one. However, these advances have increased the complexity of processing and manufacturing integrated circuits, and these advances have necessitated similar advances in processing and manufacturing. Throughout the evolution of integrated circuits, functional density (i.e., the number of interconnected devices per chip area) has steadily increased, while geometry size (i.e., the smallest component that can be created using a manufacturing process) has steadily decreased.
[0003] One type of capacitor is the Metal Insulator Metal (MIM) capacitor, which is commonly used in mixed-signal and logic devices (such as embedded memory and RF devices). MIM capacitors are commonly used to store charge in various semiconductor devices. To meet the performance requirements of devices, the capacitance density of MIM capacitors is gradually increasing.
[0004] However, the equivalent capacitance density of MIM capacitors still needs to be improved. Summary of the Invention
[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which are beneficial to improving the working performance of the semiconductor structure.
[0006] To solve the above problems, an embodiment of the present invention provides a semiconductor structure, comprising: a substrate, including a first hole location and a second hole location; a first electrode layer, located on the substrate; a first dielectric layer, covering the first electrode layer; a second electrode layer, covering the first dielectric layer, and at the first hole location, the second electrode layer has a first groove exposing the top of the first dielectric layer; the second dielectric layer, covering the second electrode layer and the top of the first dielectric layer exposed by the first groove; a third electrode layer, covering the second dielectric layer, and at the second hole location, the third electrode layer has a second groove exposing the top of the second dielectric layer; a first through-hole interconnect structure, located at the first hole location and penetrating the first electrode layer, the first dielectric layer, the second dielectric layer, and the third electrode layer stacked in sequence, the first through-hole interconnect structure being electrically connected to the first electrode layer and the third electrode layer; and a second through-hole interconnect structure, located on the first dielectric layer at the second hole location and penetrating the second electrode layer and the second dielectric layer, the second through-hole interconnect structure being electrically connected to the second electrode layer.
[0007] Optionally, the semiconductor structure further includes: an etch stop layer located on the first dielectric layer at the location where the second hole is located; and the second through-hole interconnect structure is located on the etch stop layer.
[0008] Optionally, the material of the second electrode layer and the material of the etch stop layer have an etching selectivity ratio.
[0009] Optionally, the etching selectivity ratio is greater than or equal to 1e^1.
[0010] Optionally, the material of the etch stop layer is a metal material.
[0011] Optionally, the material of the etch stop layer includes TaN, Ta or Al.
[0012] Optionally, the thickness of the etch stop layer is 1e^1 nm to 1e^2 nm.
[0013] Optionally, in the substrate, the first hole positions are arranged in a matrix, the second hole positions are arranged in a matrix, and along the diagonal direction of the matrix, the first hole positions and the second hole positions are arranged alternately.
[0014] Optionally, the first dielectric layer includes one or more of HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, BaSrTiO and SiN; the material of the second dielectric layer includes one or more of HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, ZrO2, ZrSiO2, Al2O 3. One or more of SrTiO3, BaSrTiO and SiN; the material of the first electrode layer includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al; the material of the second electrode layer includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al; the material of the third electrode layer includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al.
[0015] Accordingly, an embodiment of the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, including a first hole positioning and a second hole positioning; forming a first electrode layer on the substrate; forming a first dielectric layer covering the first electrode layer; forming a second electrode layer covering the first dielectric layer, and at the first hole positioning, the second electrode layer has a first groove exposing the top of the first dielectric layer; forming a second dielectric layer covering the second electrode layer and the top of the first dielectric layer exposed by the first groove; forming a third electrode layer covering the second dielectric layer, and at the second hole positioning, the third electrode layer has a second groove exposing the top of the second dielectric layer; forming a first through-hole interconnect structure penetrating the first electrode layer, the first dielectric layer, the second dielectric layer, and the third electrode layer stacked in sequence at the first hole positioning, the first through-hole interconnect structure being electrically connected to the first electrode layer and the third electrode layer; forming a second through-hole interconnect structure penetrating the second electrode layer and the second dielectric layer on the first dielectric layer at the second hole positioning, the second through-hole interconnect structure being electrically connected to the second electrode layer.
[0016] Optionally, after forming the second dielectric layer and before forming the second electrode layer, the forming method further includes: forming an etch stop layer on the first dielectric layer at the second hole positioning location; in the step of forming the second through-hole interconnection structure, the second through-hole interconnection structure is located on the etch stop layer.
[0017] Optionally, the step of forming the etch stop layer includes: forming an etch stop material layer covering the first dielectric layer; patterning the etch stop material layer, and retaining the etch stop material layer located at the second hole as the etch stop layer.
[0018] Optionally, the step of forming a first through-hole interconnection structure includes: forming a first through-hole at the first hole positioning, penetrating the first electrode layer, the first dielectric layer, the second dielectric layer and the third electrode layer stacked in sequence; filling the first through-hole to form a first through-hole interconnection structure; the step of forming a second through-hole interconnection structure includes: forming a second through-hole at the second hole positioning, penetrating the second electrode layer and the second dielectric layer with the etch stop layer as the etch stop position; filling the second through-hole to form a second through-hole interconnection structure.
[0019] Optionally, the first through hole and the second through hole are formed in the same step; and the first through hole and the second through hole are filled in the same step.
[0020] Optionally, the first through hole is formed by a dry etching process; and the second through hole is formed by a dry etching process.
[0021] Optionally, in the step of forming the second through hole, etching of the second electrode layer and the etch stop layer has an etching selectivity ratio.
[0022] Optionally, in the step of forming the second through hole, the etching selection ratio is greater than or equal to 1e^1.
[0023] Optionally, the step of forming the second electrode layer includes: forming a first electrode material layer covering the first dielectric layer; patterning the first electrode material layer to form a first groove exposing the top of the first dielectric layer at the first hole positioning, and retaining the remaining first electrode material layer as the second electrode layer.
[0024] Optionally, the step of forming the third electrode layer includes: forming a second electrode material layer covering the second dielectric layer; patterning the second electrode material layer to form a second groove exposing the top of the second dielectric layer at the second hole positioning, and retaining the remaining second electrode material layer as the third electrode layer.
[0025] Optionally, in the step of providing a substrate, in the substrate, the first hole positions are arranged in a matrix, the second hole positions are arranged in a matrix, and along the diagonal direction of the matrix, the first hole positions and the second hole positions are arranged alternately.
[0026] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:
[0027] In the semiconductor structure provided by an embodiment of the present invention, a first through-hole interconnect structure is located at a first hole location and penetrates a first electrode layer, a first dielectric layer, a second dielectric layer, and a third electrode layer stacked in sequence. The first through-hole interconnect structure is electrically connected to the first electrode layer and the third electrode layer. A second through-hole interconnect structure is located on the first dielectric layer at a second hole location and penetrates the second electrode layer and the second dielectric layer. The second through-hole interconnect structure is electrically connected to the second electrode layer. In the embodiment of the present invention, the second through-hole interconnect structure does not penetrate the first electrode layer, so there is no need to reserve a groove position in the first electrode layer for forming the second through-hole interconnect structure, which is beneficial to increasing the area of the first electrode layer, and correspondingly beneficial to increasing the relative area of the first electrode layer and the second electrode layer, thereby beneficial to increasing the capacitance density of the metal-insulator-metal (MIM) capacitor formed by the first electrode layer, the second electrode layer, and the third electrode layer, thereby improving the performance of the semiconductor structure.
[0028] In the method for forming a semiconductor structure provided by an embodiment of the present invention, a first through-hole interconnect structure is formed at a first hole location, penetrating a first electrode layer, a first dielectric layer, a second dielectric layer, and a third electrode layer stacked in sequence, and the first through-hole interconnect structure is electrically connected to the first electrode layer and the third electrode layer. A second through-hole interconnect structure is formed on the first dielectric layer at a second hole location, penetrating the second electrode layer and the second dielectric layer, and the second through-hole interconnect structure is electrically connected to the second electrode layer. In the embodiment of the present invention, the second through-hole interconnect structure does not penetrate the first electrode layer, so there is no need to reserve a groove position in the first electrode layer for forming the second through-hole interconnect structure, which is beneficial to increasing the area of the first electrode layer and correspondingly increasing the relative area of the first electrode layer and the second electrode layer, thereby facilitating an increase in the capacitance density of the metal-insulator-metal (MIM) capacitor formed by the first electrode layer, the second electrode layer, and the third electrode layer, thereby improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0029] Figures 1 to 3 It is a structural diagram of a semiconductor structure;
[0030] Figures 4 to 6 is a schematic structural diagram of an embodiment of a semiconductor structure of the present invention;
[0031] Figures 7 to 17 1 is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION
[0032] The performance of current semiconductor structures needs to be improved. This article analyzes the reasons why the performance needs to be improved by combining a semiconductor structure.
[0033] Figures 1 to 3 It is a structural diagram of a semiconductor structure.
[0034] Combined with reference Figures 1 to 3 , Figure 2 for Figure 1 Cross-sectional view along AA direction, Figure 3 for Figure 1The cross-sectional view along the BB direction shows a semiconductor structure comprising: a substrate 10, including a first hole positioning 11 and a second hole positioning 12; a first electrode layer 21, located on the substrate 10, wherein the first electrode layer 21 has a first groove exposing the top of the substrate 10 at the second hole positioning 12; a first dielectric layer 31, covering the first electrode layer 21; a second electrode layer 22, covering the first dielectric layer 31, wherein the second electrode layer 22 has a second groove exposing the top of the first dielectric layer 31 at the first hole positioning 11; a second dielectric layer 32, covering the second electrode layer 22 and the first dielectric layer 31 exposed by the second groove; a third electrode layer 23, covering the second dielectric layer 22; The dielectric layer 32 has a third groove at the second hole location 12, and the third electrode layer 23 has a third groove exposing the top of the second dielectric layer 32; the first through-hole interconnection structure 51 is located at the first hole location 11 and penetrates the first electrode layer 21, the first dielectric layer 31, the second dielectric layer 32 and the third electrode layer 23 stacked in sequence, and the first through-hole interconnection structure 51 is electrically connected to the first electrode layer 21 and the third electrode layer 23; the second through-hole interconnection structure 52 is located at the second hole location 12 and penetrates the first dielectric layer 31, the second electrode layer 22 and the second dielectric layer 32 stacked in sequence, and the second through-hole interconnection structure 52 is electrically connected to the second electrode layer 22.
[0035] In order to ensure that the first through-hole interconnect structure 51 contacts only the first electrode layer 21 and the third electrode layer 23 but not the second electrode layer 22, and the second through-hole interconnect structure 52 contacts only the second electrode layer 22 but not the first electrode layer 21 and the third electrode layer 23, it is necessary to form a first groove exposing the top of the substrate 10 in the first electrode layer 21 at the second hole positioning 12, form a third groove exposing the top of the second dielectric layer 32 in the third electrode layer 23 at the second hole positioning 12, and form a second groove exposing the top of the first dielectric layer 31 in the second electrode layer 22 at the first hole positioning 11, thereby reducing the relative area between the adjacent first electrode layer 21 and the second electrode layer 22, and between the second electrode layer 22 and the third electrode layer 23, making it difficult to increase the capacitance density of the metal-insulator-metal capacitor formed by the first electrode layer, the second electrode layer and the third electrode layer, and thus making it difficult to improve the performance of the semiconductor structure.
[0036] In order to solve the technical problem, an embodiment of the present invention provides a semiconductor structure, including: a substrate, including a first hole positioning and a second hole positioning; a first electrode layer, located on the substrate; a first dielectric layer, covering the first electrode layer; a second electrode layer, covering the first dielectric layer, and at the first hole positioning, the second electrode layer has a first groove exposing the top of the first dielectric layer; a second dielectric layer, covering the second electrode layer and the top of the first dielectric layer exposed by the first groove; a third electrode layer, covering the second dielectric layer, and at the second hole positioning, the third electrode layer has a second groove exposing the top of the second dielectric layer; a first through-hole interconnect structure, located at the first hole positioning and penetrating the first electrode layer, the first dielectric layer, the second dielectric layer, and the third electrode layer stacked in sequence, the first through-hole interconnect structure being electrically connected to the first electrode layer and the third electrode layer; a second through-hole interconnect structure, located on the first dielectric layer at the second hole positioning and penetrating the second electrode layer and the second dielectric layer, the second through-hole interconnect structure being electrically connected to the second electrode layer.
[0037] In the embodiment of the present invention, the second through-hole interconnection structure does not penetrate the first electrode layer, so there is no need to reserve a groove position in the first electrode layer for forming the second through-hole interconnection structure, which is beneficial to increasing the area of the first electrode layer, and correspondingly beneficial to increasing the relative area of the first electrode layer and the second electrode layer, thereby facilitating increasing the capacitance density of the metal-insulator-metal (MIM) capacitor formed by the first electrode layer, the second electrode layer and the third electrode layer, thereby improving the performance of the semiconductor structure.
[0038] In order to make the above-mentioned objects, features and advantages of the embodiments of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below with reference to the accompanying drawings. Figures 4 to 6 , showing a structural schematic diagram of an embodiment of a semiconductor structure of the present invention.
[0039] Combined with reference Figures 4 to 6 , Figure 5 for Figure 4 Cross-sectional view along AA direction, Figure 6 for Figure 4 The cross-sectional view along the BB direction is for clarity. Figure 4Only the positions of the first hole positioning, the second hole positioning and the etch stop layer are shown. The semiconductor structure includes: a substrate 100, including a first hole positioning 110 and a second hole positioning 120; a first electrode layer 210, located on the substrate 100; a first dielectric layer 310, covering the first electrode layer 210; a second electrode layer 220, covering the first dielectric layer 310, and at the first hole positioning 110, the second electrode layer 220 has a first groove exposing the top of the first dielectric layer 310; the second dielectric layer 320, covering the second electrode layer 220 and the top of the first dielectric layer 310 exposed by the first groove; a third electrode layer 230, covering the second dielectric layer 220, and at At the second hole location 120, the third electrode layer 230 has a second groove that exposes the top of the second dielectric layer 320; the first through-hole interconnect structure 510 is located at the first hole location 110 and penetrates the first electrode layer 210, the first dielectric layer 310, the second dielectric layer 320 and the third electrode layer 230 stacked in sequence, and the first through-hole interconnect structure 510 is electrically connected to the first electrode layer 210 and the third electrode layer 230; the second through-hole interconnect structure 520 is located on the first dielectric layer 310 at the second hole location 120 and penetrates the second electrode layer 220 and the second dielectric layer 320, and the second through-hole interconnect structure 520 is electrically connected to the second electrode layer 220.
[0040] The substrate 100 is used to provide a process platform for forming a MIM capacitor.
[0041] Specifically, in this embodiment, the first electrode layer 210 , the second electrode layer 220 and the third electrode layer 230 form a metal-insulator-metal (MIM) capacitor.
[0042] In this embodiment, the substrate 100 includes a first hole positioning 110 and a second hole positioning 120 .
[0043] The first hole positioning 110 is used for positioning the formation of the first through-hole interconnect structure 510 , and the second hole positioning 120 is used for positioning the formation of the second through-hole interconnect structure 520 .
[0044] In this embodiment, the first hole positioning holes 110 are arranged in a matrix, and the second hole positioning holes 120 are arranged in a matrix. Along the diagonal direction of the matrix, the first hole positioning holes 110 and the second hole positioning holes 120 are alternately arranged.
[0045] The first hole positioning 110 is arranged in a matrix, and the second hole positioning 120 is arranged in a matrix. Along the diagonal direction of the matrix, the first hole positioning 110 and the second hole positioning 120 are arranged alternately. Then, the first hole positioning 110 and the second hole positioning 120 are arranged in a regular pattern, so that the first through-hole interconnection structure 510 and the second through-hole interconnection structure 520 formed according to the first hole positioning 110 and the second hole positioning 120 are arranged in a regular pattern.
[0046] The first electrode layer 210 is used as an electrode plate of the MIM capacitor.
[0047] In this embodiment, the material of the first electrode layer 210 is a conductive material. As an example, the material of the first electrode layer 210 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN, and Al.
[0048] The first dielectric layer 310 serves as an insulating layer in forming the MIM capacitor, and is used to isolate the first electrode layer 210 from the second electrode layer 220 .
[0049] In this embodiment, the material of the first dielectric layer 310 is a high-k dielectric material. A high-k dielectric material refers to a dielectric material having a relative dielectric constant greater than that of silicon oxide. The use of a high-k dielectric material can help increase the capacitance value of the MIM capacitor and, accordingly, the capacitance density.
[0050] Specifically, the first dielectric layer 310 is a stacked high-k dielectric layer, i.e., the first dielectric layer 310 is a high-k composite dielectric layer. When the thickness of a high-k dielectric layer reaches a certain value, its formation quality tends to deteriorate. Therefore, by using a high-k composite dielectric layer, the thickness of the first dielectric layer 310 can be ensured to meet process requirements while maintaining good formation quality. To this end, the high-k dielectric material includes one or more of HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, BaSrTiO, and SiN.
[0051] In this embodiment, the first dielectric layer 310 is a ZAZ layer. The ZAZ layer includes a stacked first ZrO2 layer, an Al2O3 layer, and a second ZrO2 layer. In other embodiments, depending on process requirements, the dielectric layer may be made of one or more of silicon oxide, silicon oxynitride, and silicon nitride.
[0052] The second electrode layer 220 is used as an electrode plate of the MIM capacitor.
[0053] In this embodiment, at the first hole location 110, the second electrode layer 220 has a first groove that exposes the top of the first dielectric layer 310. In the first groove, the first dielectric layer 310 contacts the second dielectric layer 320, and the second electrode layer 220 is not formed between the first dielectric layer 310 and the second dielectric layer 320. At the same time, the first groove is filled with the third electrode layer 230. When the first through-hole interconnect structure 510 passes through the first groove, the first through-hole interconnect structure 510 contacts the third electrode layer 230 but does not contact the second electrode layer 220. As a result, the first through-hole interconnect structure 510 is electrically connected to the second electrode layer 230 but not to the second electrode layer 220.
[0054] In this embodiment, the material of the second electrode layer 220 is a conductive material. As an example, the material of the second electrode layer 220 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN, and Al.
[0055] The second dielectric layer 320 serves as an insulating layer in forming the MIM capacitor, and is used to isolate the second electrode layer 220 from the third electrode layer 230 .
[0056] In this embodiment, the second dielectric layer 320 is made of a high-k dielectric material. A high-k dielectric material is a dielectric material having a relative dielectric constant greater than that of silicon oxide. The use of a high-k dielectric material can increase the capacitance of the MIM capacitor and, consequently, the capacitance density.
[0057] Specifically, the second dielectric layer 320 is a stacked high-k dielectric layer, i.e., the second dielectric layer 320 is a high-k composite dielectric layer. When the thickness of a high-k dielectric layer reaches a certain value, its formation quality tends to deteriorate. Therefore, by using a high-k composite dielectric layer, the thickness of the second dielectric layer 320 can be ensured to meet process requirements while maintaining good formation quality. To this end, the high-k dielectric material includes one or more of HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, BaSrTiO, and SiN.
[0058] In this embodiment, the second dielectric layer 320 is a ZAZ layer. The ZAZ layer includes a stacked first ZrO2 layer, an Al2O3 layer, and a second ZrO2 layer. In other embodiments, depending on process requirements, the dielectric layer may be made of one or more of silicon oxide, silicon oxynitride, and silicon nitride.
[0059] The third electrode layer 230 is used as an electrode plate of the MIM capacitor.
[0060] In this embodiment, at the second hole positioning 120, the third electrode layer 230 has a second groove exposing the top of the second dielectric layer 320. When the second through-hole interconnect structure 520 passes through the second groove, the second through-hole interconnect structure 520 will not contact the third electrode layer 230, so the second through-hole interconnect structure 520 will not be electrically connected to the third electrode layer 230.
[0061] In this embodiment, the material of the third electrode layer 230 is a conductive material. As an example, the material of the third electrode layer 230 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN, and Al.
[0062] The first through-hole interconnect structure 510 is used to electrically connect the first electrode layer 210 and the third electrode layer 230 , thereby loading electrical signals to the first electrode layer 210 and the third electrode layer 230 .
[0063] In this embodiment, the material of the first through-hole interconnection structure 510 includes one or more of aluminum, copper, titanium nitride, cobalt, and tantalum nitride.
[0064] The second through-hole interconnect structure 520 is used to electrically connect the second electrode layer 220 , thereby supplying an electrical signal to the second electrode layer 220 .
[0065] In this embodiment, the material of the second through-hole interconnection structure 520 includes one or more of aluminum, copper, titanium nitride, cobalt, and tantalum nitride.
[0066] Specifically, in this embodiment, an electrical signal is loaded to the first electrode layer 210 and the third electrode layer 230 through the first through-hole interconnection structure 510, and an electrical signal is loaded to the second electrode layer 220 through the second through-hole interconnection structure 520, so that there is a potential difference between the first electrode layer 210 and the second electrode layer 220, and at the same time, there is a potential difference between the second electrode layer 220 and the third electrode layer 230, so that the first electrode layer 210, the second electrode layer 220 and the third electrode layer 230 constitute a MIM capacitor.
[0067] In this embodiment, the second through-hole interconnection structure 520 does not penetrate the first electrode layer 210, so there is no need to reserve a groove position in the first electrode layer 210 for forming the second through-hole interconnection structure 520, which is beneficial to increasing the area of the first electrode layer 210, and correspondingly beneficial to increasing the relative area of the first electrode layer 210 and the second electrode layer 220, thereby facilitating an increase in the capacitance density of the MIM capacitor formed by the first electrode layer 210, the second electrode layer 220 and the third electrode layer 230, thereby improving the performance of the semiconductor structure.
[0068] In this embodiment, the semiconductor structure further includes an etch stop layer 400 located on the first dielectric layer 310 at the second hole location 120 .
[0069] The etch stop layer 400 is used as an etch stop position for forming the second through-hole interconnect structure 520 .
[0070] Accordingly, in this embodiment, the second through-hole interconnect structure 520 is located on the etch stop layer 400 .
[0071] Using the etch stop layer 400 as the etch stop position for forming the second through-hole interconnect structure 520 is beneficial for better controlling the etch stop position of the second through-hole when forming the second through-hole for forming the second through-hole interconnect structure 520, so that the second through-hole passes through the second electrode layer 220 while ensuring that it stops above the first dielectric layer 310, making the second through-hole easy to obtain. Moreover, the etch stop layer 400 is formed at the position where the second through-hole is formed, so that the first through-hole and the second through-hole for forming the first through-hole interconnect structure 510 can be formed in the same step. Although the depths of the first through-hole and the second through-hole are different, when forming the first through-hole, the etch stop layer 400 blocks the continued etching of the first through-hole. Therefore, the first through-hole and the second through-hole can be formed in the same step, which is beneficial to improving process efficiency.
[0072] In this embodiment, the material of the second electrode layer 220 and the material of the etch stop layer 400 have an etching selectivity ratio.
[0073] The material of the etch stop layer 400 and the material of the second electrode layer 220 have an etching selectivity ratio, which is beneficial to reducing damage to the etch stop layer 400 when etching the second electrode layer 220 when forming the second through hole, so that the second through hole stops better on the etch stop layer 400.
[0074] It should be noted that in this embodiment, the etching selectivity should not be too small. If the etching selectivity is too small, during the step of etching the second electrode layer 220 to form the second through hole, a large amount of the etch stop layer 400 may be etched away, making it difficult for the second through hole to stop on the etch stop layer 400. It is also easy to damage the first dielectric layer 310, affecting the performance of the semiconductor structure. It may even penetrate the first dielectric layer 310 to expose the first electrode layer 210, causing the second through hole interconnect structure 520 in the formed second through hole to mistakenly contact and electrically connect with the first electrode layer 210, thereby damaging the basic operating performance of the semiconductor structure. To this end, in this embodiment, the etching selectivity is greater than or equal to 1e^1.
[0075] It should also be noted that in this embodiment, the thickness of the etch-stop layer 400 should not be too large or too small. If the thickness of the etch-stop layer 400 is too large, it will easily cause the etch-stop layer 400 to occupy too much space, resulting in material waste and difficulty in improving the integration of the semiconductor structure. If the thickness of the etch-stop layer 400 is too small, it will easily lead to poor etching stopping effect of the etch-stop layer 400. During the step of forming the second through hole, it will be difficult to ensure that the second through hole stops on the etch-stop layer 400, affecting the performance of the semiconductor structure. Therefore, in this embodiment, the thickness of the etch-stop layer 400 is 1e^1nm to 1e^2nm.
[0076] In this embodiment, the etch stop layer 400 is made of metal.
[0077] The material of the etch stop layer 400 is a metal material, which is beneficial to improving the etching resistance of the etch stop layer 400, so that the etch stop layer 400 plays a better etching stopping role and makes the etch stop layer 400 easy to form.
[0078] Specifically, in this embodiment, the material of the etch stop layer 400 includes TaN, Ta or Al.
[0079] Correspondingly, the present invention also provides a method for forming a semiconductor structure. Figures 7 to 17 1 is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.
[0080] The method for forming the semiconductor structure of this embodiment will be described in detail below with reference to the accompanying drawings.
[0081] Combined with reference Figures 7 to 9 , Figure 8 for Figure 7 Cross-sectional view along AA direction, Figure 9 for Figure 7 A cross-sectional view along the BB direction shows a substrate 100 including a first hole positioning 110 and a second hole positioning 120 .
[0082] The substrate 100 is used to provide a process platform for forming a MIM capacitor.
[0083] Specifically, in this embodiment, the first electrode layer, the second electrode layer, and the third electrode layer formed subsequently constitute a metal-insulator-metal (MIM) capacitor.
[0084] In this embodiment, the substrate 100 includes a first hole positioning 110 and a second hole positioning 120 .
[0085] The first hole positioning 110 is used for positioning for the subsequent formation of a first through-hole interconnection structure, and the second hole positioning 120 is used for positioning for the subsequent formation of a second through-hole interconnection structure.
[0086] In this embodiment, in the step of providing the substrate 100 , the first hole positioning 110 and the second hole positioning 120 are arranged in a matrix in the substrate 100 . The first hole positioning 110 and the second hole positioning 120 are arranged alternately along the diagonal direction of the matrix.
[0087] The first hole positioning 110 is arranged in a matrix, and the second hole positioning 120 is arranged in a matrix. Along the diagonal direction of the matrix, the first hole positioning 110 and the second hole positioning 120 are arranged alternately. The first hole positioning 110 and the second hole positioning 120 are arranged regularly, so that the first through-hole interconnection structure and the second through-hole interconnection structure formed subsequently according to the first hole positioning 110 and the second hole positioning 120 are arranged regularly.
[0088] Combined with reference Figure 10 and Figure 11 , Figure 10 for Figure 8 The corresponding cross-sectional view, Figure 11 for Figure 9 Corresponding to the cross-sectional view, a first electrode layer 210 is formed on the substrate 100 .
[0089] The first electrode layer 210 is used as an electrode plate of the MIM capacitor.
[0090] In this embodiment, the material of the first electrode layer 210 is a conductive material. As an example, the material of the first electrode layer 210 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN, and Al.
[0091] Continue to combine references Figure 10 and Figure 11 , forming a first dielectric layer 310 covering the first electrode layer 210 .
[0092] The first dielectric layer 310 serves as an insulating layer in forming the MIM capacitor, and is used to isolate the first electrode layer 210 from the subsequently formed second electrode layer.
[0093] In this embodiment, the material of the first dielectric layer 310 is a high-k dielectric material. A high-k dielectric material refers to a dielectric material having a relative dielectric constant greater than that of silicon oxide. The use of a high-k dielectric material can help increase the capacitance value of the MIM capacitor and, accordingly, the capacitance density.
[0094] Specifically, the first dielectric layer 310 is a stacked high-k dielectric layer, i.e., the first dielectric layer 310 is a high-k composite dielectric layer. When the thickness of a high-k dielectric layer reaches a certain value, its formation quality tends to deteriorate. Therefore, by using a high-k composite dielectric layer, the thickness of the first dielectric layer 310 can be ensured to meet process requirements while maintaining good formation quality. To this end, the high-k dielectric material includes one or more of HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, BaSrTiO, and SiN.
[0095] In this embodiment, the first dielectric layer 310 is a ZAZ layer. The ZAZ layer includes a stacked first ZrO2 layer, an Al2O3 layer, and a second ZrO2 layer. In other embodiments, depending on process requirements, the dielectric layer may be made of one or more of silicon oxide, silicon oxynitride, and silicon nitride.
[0096] refer to Figure 12 , Figure 12 for Figure 10 In the corresponding cross-sectional view, after forming the first dielectric layer 310 and before subsequently forming the second electrode layer, the forming method further includes: forming an etch stop layer 400 on the first dielectric layer 310 at the second hole location 120 .
[0097] The etch stop layer 400 is used as an etch stop position for subsequently forming a second through-hole interconnection structure.
[0098] It should be noted that in this embodiment, the thickness of the etch-stop layer 400 should not be too large or too small. If the thickness of the etch-stop layer 400 is too large, it will easily cause the etch-stop layer 400 to occupy too much space, resulting in material waste and difficulty in improving the integration of the semiconductor structure. If the thickness of the etch-stop layer 400 is too small, it will easily lead to poor etching stopping effect of the etch-stop layer 400. In the subsequent step of forming the second through hole, it will be difficult to make the second through hole stop properly on the etch-stop layer 400, affecting the performance of the semiconductor structure. For this reason, in this embodiment, the thickness of the etch-stop layer 400 is 1e^1nm to 1e^2nm.
[0099] In this embodiment, the etch stop layer 400 is made of metal.
[0100] The material of the etch stop layer 400 is a metal material, which is beneficial to improving the etching resistance of the etch stop layer 400, so that the etch stop layer 400 plays a better etching stopping role and makes the etch stop layer 400 easy to form.
[0101] Specifically, in this embodiment, the material of the etch stop layer 400 includes TaN, Ta or Al.
[0102] In this embodiment, the step of forming the etch stop layer 400 includes: forming an etch stop material layer (not shown) covering the first dielectric layer 310 ; patterning the etch stop material layer, and retaining the etch stop material layer located at the second hole positioning 120 as the etch stop layer 400 .
[0103] In this embodiment, a dry etching process is used to pattern the etch stop material layer.
[0104] The dry etching process has the characteristic of anisotropic etching, which is beneficial for reducing damage to the first dielectric layer 310 when patterning the etch stop material layer, and makes the formed etch stop layer 400 have a better morphology accuracy.
[0105] Combined with reference Figure 13 and Figure 14 , Figure 13 for Figure 12 The corresponding cross-sectional view, Figure 14 for Figure 11 In the corresponding cross-sectional view, the second electrode layer 220 is formed to cover the first dielectric layer 310 , and at the first hole location 110 , the second electrode layer 220 has a first groove exposing the top of the first dielectric layer 310 .
[0106] The second electrode layer 220 is used as an electrode plate of the MIM capacitor.
[0107] In this embodiment, at the first hole location 110, the second electrode layer 220 has a first groove that exposes the top of the first dielectric layer 310. In the first groove, the first dielectric layer 310 contacts the second dielectric layer 320, and the second electrode layer 220 is not formed between the first dielectric layer 310 and the second dielectric layer 320. At the same time, the first groove is filled with the third electrode layer 230. When the subsequently formed first through-hole interconnect structure passes through the first groove, the first through-hole interconnect structure contacts the third electrode layer 230 but does not contact the second electrode layer 220. As a result, the first through-hole interconnect structure is electrically connected to the second electrode layer 230 but not to the second electrode layer 220.
[0108] In this embodiment, the material of the second electrode layer 220 is a conductive material. As an example, the material of the second electrode layer 220 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN, and Al.
[0109] Specifically, in this embodiment, the step of forming the second electrode layer 220 includes: forming a first electrode material layer (not shown) covering the first dielectric layer 310; patterning the first electrode material layer to form a first groove exposing the top of the first dielectric layer 310 at the first hole positioning 110, and retaining the remaining first electrode material layer as the second electrode layer 220.
[0110] Continue to combine references Figure 13 and Figure 14 , forming a second dielectric layer 320 covering the second electrode layer 220 and the top of the first dielectric layer 310 exposed by the first groove.
[0111] The second dielectric layer 320 serves as an insulating layer in forming the MIM capacitor, and is used to isolate the second electrode layer 220 from the subsequently formed third electrode layer.
[0112] In this embodiment, the second dielectric layer 320 is made of a high-k dielectric material. A high-k dielectric material is a dielectric material having a relative dielectric constant greater than that of silicon oxide. The use of a high-k dielectric material can increase the capacitance of the MIM capacitor and, consequently, the capacitance density.
[0113] Specifically, the second dielectric layer 320 is a stacked high-k dielectric layer, i.e., the second dielectric layer 320 is a high-k composite dielectric layer. When the thickness of a high-k dielectric layer reaches a certain value, its formation quality tends to deteriorate. Therefore, by using a high-k composite dielectric layer, the thickness of the second dielectric layer 320 can be ensured to meet process requirements while maintaining good formation quality. To this end, the high-k dielectric material includes one or more of HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, BaSrTiO, and SiN.
[0114] In this embodiment, the second dielectric layer 320 is a ZAZ layer. The ZAZ layer includes a stacked first ZrO2 layer, an Al2O3 layer, and a second ZrO2 layer. In other embodiments, depending on process requirements, the dielectric layer may be made of one or more of silicon oxide, silicon oxynitride, and silicon nitride.
[0115] Continue to combine references Figure 13 and Figure 14 , forming a third electrode layer 230 covering the second dielectric layer 320 , and at the second hole positioning 120 , the third electrode layer 230 has a second groove exposing the top of the second dielectric layer 320 .
[0116] The third electrode layer 230 is used as an electrode plate of the MIM capacitor.
[0117] In this embodiment, at the second hole positioning 120, the third electrode layer 230 has a second groove exposing the top of the second dielectric layer 320. When the second through-hole interconnect structure formed subsequently passes through the second groove, the second through-hole interconnect structure will not contact the third electrode layer 230, and thus the second through-hole interconnect structure will not be electrically connected to the third electrode layer 230.
[0118] In this embodiment, the material of the third electrode layer 230 is a conductive material. As an example, the material of the third electrode layer 230 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN, and Al.
[0119] Specifically, in this embodiment, the step of forming the third electrode layer 230 includes: forming a second electrode material layer (not shown) covering the second dielectric layer 320; patterning the second electrode material layer to form a second groove exposing the top of the second dielectric layer 320 at the second hole positioning 120, and retaining the remaining second electrode material layer as the third electrode layer 230.
[0120] Combined with reference Figures 15 to 17 , Figure 16 for Figure 15 Cross-sectional view along AA direction, Figure 17 for Figure 15 The cross-sectional view along the BB direction is for clarity. Figure 15 Only the positions of the first hole positioning, the second hole positioning and the etching stop layer are shown. At the first hole positioning 110, a first through-hole interconnection structure 510 is formed, which penetrates the first electrode layer 210, the first dielectric layer 310, the second dielectric layer 320 and the third electrode layer 230 stacked in sequence. The first through-hole interconnection structure 510 is electrically connected to the first electrode layer 210 and the third electrode layer 230. On the first dielectric layer 310 at the second hole positioning 120, a second through-hole interconnection structure 520 is formed, which penetrates the second electrode layer 220 and the second dielectric layer 320. The second through-hole interconnection structure 520 is electrically connected to the second electrode layer 220.
[0121] The first through-hole interconnect structure 510 is used to electrically connect the first electrode layer 210 and the third electrode layer 230 , thereby loading electrical signals to the first electrode layer 210 and the third electrode layer 230 .
[0122] In this embodiment, the material of the first through-hole interconnection structure 510 includes one or more of aluminum, copper, titanium nitride, cobalt, and tantalum nitride.
[0123] The second through-hole interconnect structure 520 is used to electrically connect the second electrode layer 220 , thereby supplying an electrical signal to the second electrode layer 220 .
[0124] In this embodiment, the material of the second through-hole interconnection structure 520 includes one or more of aluminum, copper, titanium nitride, cobalt, and tantalum nitride.
[0125] Specifically, in this embodiment, an electrical signal is loaded to the first electrode layer 210 and the third electrode layer 230 through the first through-hole interconnection structure 510, and an electrical signal is loaded to the second electrode layer 220 through the second through-hole interconnection structure 520, so that there is a potential difference between the first electrode layer 210 and the second electrode layer 220, and at the same time, there is a potential difference between the second electrode layer 220 and the third electrode layer 230, so that the first electrode layer 210, the second electrode layer 220 and the third electrode layer 230 constitute a MIM capacitor.
[0126] In this embodiment, the second through-hole interconnection structure 520 does not penetrate the first electrode layer 210, so there is no need to reserve a groove position in the first electrode layer 210 for forming the second through-hole interconnection structure 520, which is beneficial to increasing the area of the first electrode layer 210, and correspondingly beneficial to increasing the relative area of the first electrode layer 210 and the second electrode layer 220, thereby facilitating an increase in the capacitance density of the MIM capacitor formed by the first electrode layer 210, the second electrode layer 220 and the third electrode layer 230, thereby improving the performance of the semiconductor structure.
[0127] Accordingly, in this embodiment, in the step of forming the second through-hole interconnection structure 520 , the second through-hole interconnection structure 520 is located on the etch stop layer 400 .
[0128] Using the etch stop layer 400 as the etch stop position for forming the second through-hole interconnect structure 520 is beneficial for better controlling the etch stop position of the second through-hole when forming the second through-hole for forming the second through-hole interconnect structure 520, so that the second through-hole passes through the second electrode layer 220 while ensuring that it stops above the first dielectric layer 310, making the second through-hole easy to obtain. Moreover, the etch stop layer 400 is formed at the position where the second through-hole is formed, so that the first through-hole and the second through-hole for forming the first through-hole interconnect structure 510 can be formed in the same step. Although the depths of the first through-hole and the second through-hole are different, when forming the first through-hole, the etch stop layer 400 blocks the continued etching of the first through-hole. Therefore, the first through-hole and the second through-hole can be formed in the same step, which is beneficial to improving process efficiency.
[0129] In this embodiment, the steps of forming the first through-hole interconnection structure 510 include: forming a first through-hole (not shown) at the first hole positioning 110, which penetrates the first electrode layer 210, the first dielectric layer 310, the second dielectric layer 320 and the third electrode layer 230 stacked in sequence; and filling the first through-hole to form the first through-hole interconnection structure 510.
[0130] In this embodiment, a dry etching process is used to form the first through hole.
[0131] The dry etching process has the characteristics of anisotropic etching and directionality, which is beneficial to reducing damage to the substrate 100 during the process of etching to form the first through hole and is beneficial to improving the size and morphology accuracy of the formed first through hole.
[0132] In this embodiment, the steps of forming the second through-hole interconnect structure 520 include: forming a second through-hole (not shown) penetrating the second electrode layer 220 and the second dielectric layer 320 at the second hole positioning 120 with the etch stop layer 400 as the etch stop position; and filling the second through-hole to form the second through-hole interconnect structure 520.
[0133] In this embodiment, a dry etching process is used to form the second through hole.
[0134] The dry etching process has the characteristics of anisotropic etching and directionality, which is beneficial to reducing damage to the etch stop layer 400 during the process of etching to form the second through hole and is beneficial to improving the size and morphology accuracy of the formed second through hole.
[0135] In this embodiment, in the step of forming the second through hole, etching of the second electrode layer 220 and the etch stop layer 400 has an etching selectivity ratio.
[0136] The etching of the second electrode layer 220 and the etch stop layer 400 has an etching selectivity ratio, which is beneficial for reducing damage to the etch stop layer 400 when etching the second electrode layer 220 when forming the second through hole, so that the second through hole stops better on the etch stop layer 400.
[0137] It should be noted that in this embodiment, in the step of forming the second through hole, the etching selectivity should not be too small. If the etching selectivity is too small, then in the step of etching the second electrode layer 220 to form the second through hole, it is easy to cause a large amount of etching and removal of the etch stop layer 400, making it difficult for the second through hole to stop on the etch stop layer 400, and it is easy to damage the first dielectric layer 310, affecting the performance of the semiconductor structure, and even penetrating the first dielectric layer 310 to expose the first electrode layer 210, thereby causing the first through hole interconnect structure 510 in the formed first through hole to mistakenly contact and electrically connect with the first electrode layer 210, destroying the basic working performance of the semiconductor structure. For this reason, in this embodiment, in the step of forming the second through hole, the etching selectivity is greater than or equal to 1e^1.
[0138] In this embodiment, the first through hole and the second through hole are formed in the same step.
[0139] Although the first through hole and the second through hole have different depths, when forming the first through hole, the etch stop layer 400 blocks further etching of the first through hole. Therefore, the first through hole and the second through hole can be formed in the same step, which is beneficial to improving process efficiency.
[0140] In this embodiment, the first through hole and the second through hole are filled in the same step.
[0141] Filling the first through-hole and the second through-hole in the same step is beneficial to improving the process efficiency of the first through-hole interconnection structure 510 and the second through-hole interconnection structure 520 .
[0142] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.
Claims
1. A semiconductor structure, characterized in that: include: A substrate including a first hole location and a second hole location; A first electrode layer, located on the substrate; a first dielectric layer, covering the first electrode layer; a second electrode layer, covering the first dielectric layer, and having a first groove exposing the top of the first dielectric layer at the location where the first hole is located; a second dielectric layer, covering the second electrode layer and a top portion of the first dielectric layer exposed by the first groove; a third electrode layer, covering the second dielectric layer, and having a second groove exposing the top of the second dielectric layer at the location where the second hole is located; A first through-hole interconnection structure is located at the first hole location and penetrates the first electrode layer, the first dielectric layer, the second dielectric layer and the third electrode layer stacked in sequence, and the first through-hole interconnection structure is electrically connected to the first electrode layer and the third electrode layer; The second through-hole interconnection structure is located on the first dielectric layer at the location of the second hole and penetrates the second electrode layer and the second dielectric layer. The second through-hole interconnection structure is electrically connected to the second electrode layer.
2. The semiconductor structure according to claim 1, wherein: The semiconductor structure further includes: an etch stop layer located on the first dielectric layer where the second hole is located; The second through-hole interconnect structure is located on the etch stop layer.
3. The semiconductor structure according to claim 2, wherein: The material of the second electrode layer and the material of the etch stop layer have an etching selectivity ratio.
4. The semiconductor structure according to claim 3, characterized in that The etching selectivity ratio is greater than or equal to 1e^1.
5. The semiconductor structure according to claim 2, wherein: The material of the etching stop layer is a metal material.
6. The semiconductor structure according to claim 2, wherein: The material of the etch stop layer includes TaN, Ta or Al.
7. The semiconductor structure according to claim 2, characterized in that The thickness of the etch stop layer is 1e^1nm to 1e^2nm.
8. The semiconductor structure according to claim 1, wherein: In the substrate, the first hole positions are arranged in a matrix, the second hole positions are arranged in a matrix, and along the diagonal direction of the matrix, the first hole positions and the second hole positions are arranged alternately.
9. The semiconductor structure according to claim 1, wherein: The first dielectric layer includes one or more of HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, BaSrTiO and SiN; The material of the second dielectric layer includes one or more of HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, BaSrTiO and SiN; The material of the first electrode layer includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al; The material of the second electrode layer includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al; The material of the third electrode layer includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al.
10. A method for forming a semiconductor structure, characterized in that: include: providing a substrate including a first hole location and a second hole location; forming a first electrode layer on the substrate; forming a first dielectric layer covering the first electrode layer; forming a second electrode layer covering the first dielectric layer, wherein the second electrode layer has a first groove exposing the top of the first dielectric layer at the location where the first hole is located; forming a second dielectric layer covering the second electrode layer and the top of the first dielectric layer exposed by the first groove; forming a third electrode layer covering the second dielectric layer, wherein the third electrode layer has a second groove exposing the top of the second dielectric layer at the location where the second hole is located; At the first hole location, a first through-hole interconnection structure is formed that penetrates the first electrode layer, the first dielectric layer, the second dielectric layer, and the third electrode layer stacked in sequence, and the first through-hole interconnection structure is electrically connected to the first electrode layer and the third electrode layer; A second through-hole interconnection structure penetrating the second electrode layer and the second dielectric layer is formed on the first dielectric layer at the location of the second hole, and the second through-hole interconnection structure is electrically connected to the second electrode layer.
11. The method for forming a semiconductor structure according to claim 10, wherein: After forming the first dielectric layer and before forming the second electrode layer, the forming method further comprises: forming an etching stop layer on the first dielectric layer at the location where the second hole is located; In the step of forming the second through-hole interconnection structure, the second through-hole interconnection structure is located on the etch stop layer.
12. The method for forming a semiconductor structure according to claim 11, wherein: The step of forming the etch stop layer includes: forming an etch stop material layer covering the first dielectric layer; The etch stop material layer is patterned, and the etch stop material layer located at the second hole is retained as the etch stop layer.
13. The method for forming a semiconductor structure according to claim 11, wherein: The step of forming the first through-hole interconnection structure includes: forming a first through-hole penetrating the first electrode layer, the first dielectric layer, the second dielectric layer and the third electrode layer stacked in sequence at the first hole location; filling the first through-hole to form the first through-hole interconnection structure; The step of forming the second through-hole interconnection structure includes: forming a second through-hole penetrating the second electrode layer and the second dielectric layer at the second hole positioning position with the etch stop layer as the etch stop position; and filling the second through-hole to form the second through-hole interconnection structure.
14. The method for forming a semiconductor structure according to claim 13, wherein: In the same step, forming the first through hole and the second through hole; In the same step, the first through hole and the second through hole are filled.
15. The method for forming a semiconductor structure according to claim 13, wherein: The first through hole is formed by a dry etching process; and the second through hole is formed by a dry etching process.
16. The method for forming a semiconductor structure according to claim 15, wherein: In the step of forming the second through hole, etching of the second electrode layer and the etching stop layer has an etching selectivity ratio.
17. The method for forming a semiconductor structure according to claim 16, wherein: In the step of forming the second through hole, the etching selection ratio is greater than or equal to 1e^1.
18. The method for forming a semiconductor structure according to claim 10, wherein: The step of forming the second electrode layer includes: forming a first electrode material layer covering the first dielectric layer; The first electrode material layer is patterned to form a first groove exposing the top of the first dielectric layer at the location of the first hole, and the remaining first electrode material layer is retained as the second electrode layer.
19. The method for forming a semiconductor structure according to claim 10, wherein: The step of forming the third electrode layer includes: forming a second electrode material layer covering the second dielectric layer; The second electrode material layer is patterned to form a second groove exposing the top of the second dielectric layer at the location where the second hole is located, and the remaining second electrode material layer is retained as the third electrode layer.
20. The method for forming a semiconductor structure according to claim 10, wherein: In the step of providing the substrate, in the substrate, the first hole positions are arranged in a matrix, the second hole positions are arranged in a matrix, and along the diagonal direction of the matrix, the first hole positions and the second hole positions are arranged alternately.