Three-dimensional memory devices and methods of making same using etch stop structures between layers

Abstract

The etch stop structure forms a sacrificial memory opening fill structure formed within a first layer memory opening of a first layer alternating stack extending vertically through the first insulating layer and the first spacer material layer. The etch stop structure may include a conductive etch stop plate formed over sacrificial memory opening fill material portions inside the first layer memory openings, or may include a semiconductor plug selectively grown from sidewalls of etch stop semiconductor material layers formed over the first layer alternating stack. A second layer alternating stack of second insulating layers and second spacer material layers is formed over the first layer alternating stack and the etch stop structure.

Description

[0001] Related Applications

[0002] This application claims the benefit of priority to U.S. Provisional Patent Application No. 63 / 380,307 filed on October 20, 2022 and U.S. Provisional Patent Application No. 63 / 380,309 filed on October 20, 2022, the entire contents of which are hereby incorporated by reference for all purposes. Technical Field

[0003] The present disclosure relates generally to the field of semiconductor devices, and in particular to methods for fabricating three-dimensional memory devices employing etch stop structures and structures formed by the methods. Background Art

[0004] A three-dimensional memory device including three-dimensional vertical NAND strings with one bit per cell is disclosed in an article by T. Endoh et al. entitled "Novel Ultra High Density Memory With A Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell", IEDM Proc. (2001) 33-36. Summary of the invention

[0005] According to one aspect of the present disclosure, a method for forming a memory device is provided, the method comprising: forming a first layer alternating stack of a first insulating layer and a first spacer material layer above a substrate, wherein the first spacer material layer is formed as a first conductive layer or is subsequently replaced with the first conductive layer; forming a first layer memory opening through the first layer alternating stack; forming a sacrificial first layer memory opening filling structure in the first layer memory opening, the sacrificial first layer memory opening filling structure comprising a stack of a first carbon-based filling material portion and a first conductive material portion; forming a second layer alternating stack of a second insulating layer and a second spacer material layer above the first layer alternating stack, wherein the second spacer material layer is formed as a second conductive layer; layer or subsequently replaced with a second conductive layer; forming a second layer memory opening through the alternating stack of the second layers by performing an anisotropic etching process, the anisotropic etching process having an etching chemistry that selectively etches the material of the second insulating layer and the second spacer material layer with respect to the material of the first conductive material portion; selectively removing the first conductive material portion with respect to the first carbon-based filling material portion; forming an inter-layer memory opening by removing a remaining portion of the sacrificial first layer memory opening filling structure below the second layer memory opening; and forming a memory opening filling structure in the inter-layer memory opening, wherein the memory opening filling structure includes a vertical stack of memory elements and a vertical semiconductor channel.

[0006] According to one aspect of the present disclosure, a memory device is provided, which includes: a first layer of an alternating stack of a first insulating layer and a first conductive layer; an etch stop semiconductor material layer, which is located above the first layer of the alternating stack; a second layer of an alternating stack of a second insulating layer and a second conductive layer, which is overlying the etch stop semiconductor material layer; an interlayer memory opening, which vertically extends through the second layer of the alternating stack, the etch stop semiconductor material layer and the first layer of the alternating stack; and a memory opening filling structure, which is located in the interlayer memory opening and includes a vertical semiconductor channel and a vertical stack of memory elements.

[0007] According to another aspect of the present disclosure, a method for forming a memory device is provided, the method comprising: forming a first layer alternating stack of a first insulating layer and a first spacer material layer over a substrate, wherein the first spacer material layer is formed as a first conductive layer or is subsequently replaced with the first conductive layer; forming a first layer memory opening through the first layer alternating stack; forming a sacrificial first layer memory opening filling structure within the first layer memory opening; forming an etch stop semiconductor material layer over the first layer alternating stack and the sacrificial first layer memory opening filling structure; forming a second layer alternating stack of a second insulating layer and a second spacer material layer over the etch stop semiconductor material layer, wherein the second spacer material layer Formed as a second conductive layer or subsequently replaced with a second conductive layer; forming a second layer memory opening through the second layer alternating stack and through the etch stop semiconductor material layer; forming a semiconductor plug on the cylindrical sidewall of the etch stop semiconductor material layer above the sacrificial first layer memory opening filling structure; laterally expanding the second layer memory opening when the semiconductor plug covers the sacrificial first layer memory opening filling structure; forming an inter-layer memory opening by removing the semiconductor plug and the sacrificial first layer memory opening filling structure; and forming a memory opening filling structure in the inter-layer memory opening, wherein the memory opening filling structure includes a vertical semiconductor channel and a vertical stack of memory elements. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1A is a vertical cross-sectional view of the first exemplary structure after forming a semiconductor device, a lower level dielectric layer, a lower level metal interconnect structure, and a source level material layer in process according to the first embodiment of the present disclosure.

[0009] Figure 1B yes Figure 1A A top view of the first exemplary structure of FIG. The vertical plane A-A' is Figure 1A A plane of a vertical section.

[0010] Figure 1C It is along Figure 1B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane CC'.

[0011] Figure 2 is a vertical cross-sectional view of the first exemplary structure after forming a first vertical alternating sequence of first insulating layers and first spacer material layers according to the first embodiment of the present disclosure.

[0012] Figure 3 is a vertical cross-sectional view of the first exemplary structure after patterning the first stepped surface and the first backward stepped dielectric material portion according to the first embodiment of the present disclosure.

[0013] Figure 4A is a vertical cross-sectional view of the first exemplary structure after forming a first layer memory opening and a first layer support opening according to the first embodiment of the present disclosure.

[0014] Figure 4B yes Figure 4A A top view of the first exemplary structure. The sawtooth vertical plane AA' corresponds to Figure 4A A plane of a vertical section.

[0015] FIG. 5A to FIG. 5D is a vertical cross-sectional view of a first layer memory opening during formation of a sacrificial first layer memory opening filling structure in a first configuration of a first exemplary structure according to a first embodiment of the present disclosure.

[0016] FIG. 6A to FIG. 6C is a vertical cross-sectional view of a first layer memory opening during formation of a sacrificial first layer memory opening filling structure in a second configuration of the first exemplary structure according to the first embodiment of the present disclosure.

[0017] Figure 7 is a vertical cross-sectional view of the first exemplary structure after forming a sacrificial first layer memory opening filling structure and a sacrificial first layer support opening filling structure according to the first embodiment of the present disclosure.

[0018] Figure 8 is a vertical cross-sectional view of the first exemplary structure after forming a second vertical alternating sequence of second insulating layers and second spacer material layers, a second stepped surface, and a second backward stepped dielectric material portion according to the first embodiment of the present disclosure.

[0019] Fig. 9A is a vertical cross-sectional view of the first exemplary structure after forming a second layer memory opening and a second layer support opening according to the first embodiment of the present disclosure.

[0020] Fig. 9B It is along Fig. 9A The horizontal cross-sectional view of the first exemplary structure is taken along the horizontal plane BB'. The sawtooth vertical plane AA' corresponds to Fig. 9A A plane of a vertical section.

[0021] FIG. 10A to FIG. 10G is a vertical cross-sectional view of a first layer memory opening and a second layer memory opening during formation of a sacrificial second layer memory opening filling structure in a first configuration of a first exemplary structure according to a first embodiment of the present disclosure.

[0022] FIG. 11A to FIG. 11Gis a vertical cross-sectional view of a first layer memory opening and a second layer memory opening during formation of a sacrificial second layer memory opening filling structure in a second configuration of the first exemplary structure according to the first embodiment of the present disclosure.

[0023] Fig.12 is a vertical cross-sectional view of the first exemplary structure after forming a sacrificial second layer memory opening filling structure and a sacrificial second layer support opening filling structure according to the first embodiment of the present disclosure.

[0024] Fig.13 is a vertical cross-sectional view of the first exemplary structure after forming a third vertical alternating sequence of third insulating layers and third spacer material layers, a third stepped surface, a third backward stepped dielectric material portion, and a drain select level isolation structure according to the first embodiment of the present disclosure.

[0025] Fig.14 is a vertical cross-sectional view of the first exemplary structure after forming a third-level memory opening and a third-level support opening according to the first embodiment of the present disclosure.

[0026] FIG. 15A to FIG. 15G is a vertical cross-sectional view of first, second, and third level memory openings in a first configuration of a first exemplary structure during formation of inter-level memory openings and a memory opening filling structure according to a first embodiment of the present disclosure.

[0027] FIG. 16A to FIG. 16D is a vertical cross-sectional view of first, second, and third level memory openings in a second configuration of the first exemplary structure during formation of inter-level memory openings and a memory opening filling structure according to the first embodiment of the present disclosure.

[0028] Fig.17A is a vertical cross-sectional view of the first exemplary structure after forming a memory opening filling structure and a support pillar structure according to the first embodiment of the present disclosure.

[0029] Fig. 17B It is along Fig.17A The horizontal cross-sectional view of the first exemplary structure is taken along the horizontal plane BB'. The sawtooth vertical plane AA' corresponds to Fig.17A A plane of a vertical section.

[0030] Fig.18A is a vertical cross-sectional view of the first exemplary structure after forming a contact-level dielectric layer and backside trenches according to the first embodiment of the present disclosure.

[0031] Fig.18B It is along Fig.18AThe horizontal cross-sectional view of the first exemplary structure is taken along the horizontal plane BB'. The sawtooth vertical plane AA' corresponds to Fig.18A A plane of a vertical section.

[0032] FIG. 19A to FIG. 19H Sequential vertical cross-sectional views of regions of a first exemplary structure are shown during formation of a source level material layer and replacement of a sacrificial material layer with a conductive layer according to a first embodiment of the present disclosure.

[0033] Fig. 20A is a vertical cross-sectional view of the first exemplary structure after forming a backside trench fill structure in the backside trench according to the first embodiment of the present disclosure.

[0034] Fig. 20B yes Fig. 20A An enlarged vertical cross-sectional view of a region of a first exemplary structure.

[0035] Fig.21A is a vertical cross-sectional view of the first exemplary structure after forming a drain contact via structure and a layer contact via structure according to the first embodiment of the present disclosure.

[0036] Fig. 21B Yes Fig.21A A vertical cross-sectional view of a region of a memory opening filling structure in a first exemplary structure of FIG.

[0037] FIG. 22A to FIG. 22D is a vertical cross-sectional view of a first level memory opening during formation of a sacrificial first level memory opening filling structure, a first etch stop semiconductor material layer, and a first etch stop conductive material layer in a first configuration of a second exemplary structure according to a second embodiment of the present disclosure.

[0038] Fig.22E is a vertical cross-sectional view of a first level memory opening after forming a sacrificial first level memory opening filling structure and a first etch stop semiconductor material layer in a second configuration of a second exemplary structure according to a second embodiment of the present disclosure.

[0039] Fig.23 is a vertical cross-sectional view of a second exemplary structure after forming a second vertical alternating sequence of second insulating layers and second spacer material layers, a second stepped surface, and a second backward stepped dielectric material portion according to a second embodiment of the present disclosure.

[0040] Fig.24 is a vertical cross-sectional view of a first configuration of a second exemplary structure after forming a second layer memory opening and a second layer support opening according to a second embodiment of the present disclosure.

[0041] Fig.25is a vertical cross-sectional view of a second configuration of a second exemplary structure after forming a second layer memory opening and a second layer support opening according to a second embodiment of the present disclosure.

[0042] FIG. 26A to FIG. 26G is a vertical cross-sectional view of a first level memory opening and a second level memory opening during formation of a sacrificial second level memory opening filling structure, a second etch stop semiconductor material layer, and a second etch stop conductive material layer in a first configuration of a second exemplary structure according to a second embodiment of the present disclosure.

[0043] Fig.26H is a vertical cross-sectional view of a first level memory opening after forming a sacrificial second level memory opening filling structure and a second etch stop semiconductor material layer in a second configuration of a second exemplary structure according to a second embodiment of the present disclosure.

[0044] Fig. 27 is a vertical cross-sectional view of a first configuration of a second exemplary structure after forming a third vertical alternating sequence of a third insulating layer and a third spacer material layer, a third stepped surface, a third backward stepped dielectric material portion, a drain select level isolation structure, a third level memory opening, and a third level support opening according to a second embodiment of the present disclosure.

[0045] FIG. 28A to FIG. 28H is a vertical cross-sectional view of first, second, and third layer memory openings in a first configuration of a second exemplary structure during formation of inter-layer memory openings and a memory opening filling structure according to a second embodiment of the present disclosure.

[0046] Fig.28I is a vertical cross-sectional view of first, second, and third level memory openings in a second configuration of a second exemplary structure after forming inter-level memory openings and a memory opening filling structure according to a second embodiment of the present disclosure.

[0047] Fig.29A and Fig.29B is a vertical cross-sectional view of a memory opening filling structure in a first configuration of a second exemplary structure after replacing the sacrificial material layer with a conductive layer according to the second embodiment of the present disclosure.

[0048] Fig. 30A and Fig. 30B is a vertical cross-sectional view of a memory opening filling structure in a second configuration of a second exemplary structure after replacing the sacrificial material layer with a conductive layer according to the second embodiment of the present disclosure. DETAILED DESCRIPTION

[0049] Embodiments of the present disclosure relate to methods for fabricating three-dimensional memory devices using etch stop structures and structures formed by the methods, various aspects of which are described in detail herein. Embodiments of the present disclosure can be used to form various semiconductor devices, such as three-dimensional memory array devices including multiple NAND memory strings.

[0050] The drawings are not drawn to scale. Multiple instances of an element may be repeated where a single instance of an element is shown, unless explicitly described or otherwise clearly indicated that there is no repetition of an element. Serial numbers such as "first," "second," and "third" are used only to identify similar elements, and different serial numbers may be used throughout the specification and claims of this disclosure. The term "at least one" element refers to all possibilities including the possibility of a single element and the possibility of multiple elements.

[0051] The same reference numerals represent the same element or similar element. Unless otherwise specified, elements with the same reference numerals are assumed to have the same composition and the same function. Unless otherwise specified, "contact" between elements refers to direct contact between elements providing an edge or surface shared by the elements. If two or more elements are not in direct contact with each other or with each other, the two elements are "separated" from each other or "separated" from each other. As used herein, a first element positioned "on" a second element can be positioned on the outer side of the surface of the second element or on the inner side of the second element. As used herein, if there is physical contact between the surface of the first element and the surface of the second element, the first element is "directly" positioned on the second element. As used herein, if there is a conductive path composed of at least one conductive material between the first element and the second element, the first element is "electrically connected to" the second element. As used herein, a "prototype" structure or a "process" structure refers to a transient structure that is subsequently modified in the shape or composition of at least one of the components.

[0052] As used herein, "layer" refers to a portion of a material including a region having a thickness. A layer may extend over the entirety of an underlying or overlying structure, or may have an extent that is less than the extent of an underlying or overlying structure. In addition, a layer may be a region of a uniform or non-uniform continuous structure having a thickness that is less than the thickness of the continuous structure. For example, a layer may be positioned between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may include one or more layers therein, or may have one or more layers thereon, above, and / or below.

[0053] As used herein, a first surface and a second surface "vertically coincide" with each other if the second surface is above or below the first surface and if there is a vertical plane or a substantially vertical plane that includes the first surface and the second surface. A substantially vertical plane is a plane that extends straight along a direction that deviates from the vertical direction at an angle of less than 5 degrees. A vertical plane or a substantially vertical plane is straight along the vertical direction or a substantially vertical direction and may or may not include curvature along a direction perpendicular to the vertical direction or the substantially vertical direction.

[0054] As used herein, a "memory level" or "memory array level" refers to a level corresponding to the general area between a first horizontal plane (i.e., a plane parallel to the top surface of the substrate) including the topmost surface of the array of memory elements and a second horizontal plane including the bottommost surface of the array of memory elements. As used herein, a "through-stack" element refers to an element that extends vertically through a memory level.

[0055] As used herein, "semiconductor material" refers to a semiconductor material having a -5 S / m to 1.0×10 5 S / m. As used herein, "semiconductor material" refers to a material having an electrical conductivity in the range of 1.0×10 -5 S / m to 1.0 S / m, and can produce materials with electrical conductivity in the range of 1.0 S / m to 1.0×10 7 S / m. As used herein, "electrical dopant" refers to a p-type dopant that adds holes to the valence band within the energy band structure, or an n-type dopant that adds electrons to the conduction band within the energy band structure. As used herein, "conductive material" refers to a material having an electrical conductivity greater than 1.0×10 5 S / m. As used herein, "insulator material" or "dielectric material" refers to a material having an electrical conductivity of less than 1.0×10 -5 As used herein, "heavily doped semiconductor material" refers to a material doped with electrical dopants at a sufficiently high atomic concentration to become a conductive material (i.e., providing a conductivity greater than 1.0×10 5 S / m) of a semiconductor material. A "doped semiconductor material" may be a heavily doped semiconductor material, or may include a semiconductor material that provides a conductivity of 1.0×10 -5 S / m to 1.0×10 7S / m in the range of 1000 Å / s. A semiconductor material having an electrical dopant (i.e., a p-type dopant and / or an n-type dopant) with a conductivity in the range of 1000 Å / s. An "intrinsic semiconductor material" refers to a semiconductor material that is not doped with an electrical dopant. Thus, a semiconductor material can be semiconducting or conductive, and can be an intrinsic semiconductor material or a doped semiconductor material. A doped semiconductor material can be semiconducting or conductive, depending on the atomic concentration of the electrical dopant therein. As used herein, a "conductive material" refers to a conductive material that includes at least one conductive element therein. All conductivity measurements are performed under standard conditions.

[0056] Generally speaking, a semiconductor package (or "package") refers to a unit semiconductor device that can be attached to a circuit board by a set of pins or solder balls. A semiconductor package may include one or more semiconductor chips (or "chips") that are bonded through, for example, by flip chip bonding or another chip-to-chip bonding. A package or chip may include a single semiconductor die (or "die") or multiple semiconductor dies. A die is the smallest unit that can independently execute external commands or report status. Typically, a package or chip with multiple dies is capable of simultaneously executing as many external commands as the total number of dies therein. Each die includes one or more planes. The same concurrent operation can be performed in each plane within the same die, but there may be some restrictions. In the case where the die is a memory die (i.e., a die including a memory element), concurrent read operations, concurrent write operations, or concurrent erase operations can be performed in each plane within the same memory die. In a memory die, each plane contains multiple storage blocks (or "blocks"), which are the smallest units that can be erased by a single erase operation. Each memory block contains multiple pages, which are the smallest units that can be selected for programming. A page is also the smallest unit that can be selected for a read operation.

[0057] refer to Figures 1A to 1C , showing a first exemplary structure according to a first embodiment of the present disclosure. Figure 1C yes Figure 1A and Figure 1BAn enlarged view of the source level material layer 110' in the process shown. The first exemplary structure includes a substrate 8 and a semiconductor device 710 formed thereon. The substrate 8 includes a substrate semiconductor layer 9 at least at its upper portion. A shallow trench isolation structure 720 can be formed in the upper portion of the substrate semiconductor layer 9 to provide electrical isolation from other semiconductor devices. The semiconductor device 710 may include, for example, field effect transistors, which include corresponding transistor active regions 742 (i.e., source regions and drain regions), channel regions 746, and gate structures 750. The field effect transistors may be arranged in a CMOS configuration. Each gate structure 750 may include, for example, a gate dielectric 752, a gate electrode 754, a dielectric gate spacer 756, and a gate cap dielectric 758. The semiconductor device 710 may include any semiconductor circuit to support the operation of the memory structure to be formed subsequently, which is generally referred to as a driver circuit, and the driver circuit is also referred to as a peripheral circuit. As used herein, peripheral circuits refer to any, each, or all of word line decoder circuits, word line switching circuits, bit line decoder circuits, bit line sensing and / or switching circuits, power supply / distribution circuits, data buffers, and / or latches, or may be any other semiconductor circuit that may be implemented outside of a memory array structure of a memory device. For example, a semiconductor device may include a word line switching device for electrically biasing a word line of a three-dimensional memory structure to be subsequently formed.

[0058] A dielectric material layer is formed over the semiconductor device, which is referred to herein as a lower-level dielectric material layer 760. The lower-level dielectric material layer 760 may include, for example, a dielectric liner 762 (such as a silicon nitride liner that blocks diffusion of mobile ions and / or applies appropriate stress to the underlying structure), a first dielectric material layer 764 overlying the dielectric liner 762, a silicon nitride layer (e.g., a hydrogen diffusion barrier) 766 overlying the first dielectric material layer 764, and at least one second dielectric layer 768.

[0059] The dielectric layer stack (which includes the lower level dielectric material layer 760) serves as a matrix of lower level metal interconnect structures 780 that provide electrical routing to and from various nodes of the semiconductor device and landing pads of subsequently formed through-memory level contact via structures. The lower level metal interconnect structures 780 are formed within the dielectric layer stack of the lower level dielectric material layer 760 and include lower level metal line structures positioned below and optionally contacting the bottom surface of the silicon nitride layer 766.

[0060] For example, the lower level metal interconnect structure 780 may be formed within the first dielectric material layer 764. The first dielectric material layer 764 may be a plurality of dielectric material layers in which various elements of the lower level metal interconnect structure 780 are sequentially formed. Each dielectric material layer selected from the first dielectric material layer 764 may include any one of doped silicate glass, undoped silicate glass, organic silicate glass, silicon nitride, silicon oxynitride, and a dielectric metal oxide such as aluminum oxide. In one embodiment, the first dielectric material layer 764 may include or consist essentially of a dielectric material layer having a dielectric constant not exceeding 3.9 of the dielectric constant of undoped silicate glass (silicon oxide). The lower level metal interconnect structure 780 may include various device contact via structures 782 (e.g., source and drain electrodes contacting corresponding source and drain nodes or gate electrodes of the contact device), intermediate lower level metal line structures 784, lower level metal via structures 786, and landing pad level metal line structures 788, wherein the landing pad level metal line structures are configured to serve as landing pads for subsequently formed through memory level via structures.

[0061] A landing pad level metal line structure 788 may be formed within the topmost dielectric material layer of the first dielectric material layer 764 (which may be a plurality of dielectric material layers). Each of the lower level metal interconnect structures 780 may include a conductive nitride liner and a metal fill structure. The top surface of the landing pad level metal line structure 788 and the topmost surface of the first dielectric material layer 764 may be planarized by a planarization process such as chemical mechanical planarization. A silicon nitride layer 766 may be formed directly on the top surface of the landing pad level metal line structure 788 and the topmost surface of the first dielectric material layer 764.

[0062] At least one second dielectric material layer 768 may include a single dielectric material layer or a plurality of dielectric material layers. Each dielectric material layer selected from at least one second dielectric material layer 768 may include any one of doped silicate glass, undoped silicate glass, and organic silicate glass. In one embodiment, at least one second dielectric material layer 768 may include or consist essentially of a dielectric material layer having a dielectric constant not exceeding 3.9 of the dielectric constant of undoped silicate glass (silicon oxide).

[0063] An optional layer of conductive material and a layer of semiconductor material may be deposited above or within the patterned recess of the at least one second dielectric material layer 768 and patterned photolithographically to provide an optional conductive plate layer 6 and a source level material layer 110' in the process. The optional conductive plate layer 6 (if present) provides a high conductivity conduction path for current flowing into or out of the source level material layer 110' in the process. The optional conductive material layer 6 includes a conductive material such as a metal or a heavily doped semiconductor material. The optional conductive plate layer 6 may, for example, include a tungsten layer having a thickness in the range of 3nm to 100nm, but smaller and larger thicknesses may also be used. A metal nitride layer (not shown) may be provided on top of the conductive plate layer 6 as a diffusion barrier. The conductive plate layer 6 may be used as a special source line in the completed device. In addition, the conductive plate layer 6 may include an etch stop layer and may include any suitable conductive, semiconductor or insulating layer. The optional conductive plate layer 6 may include a conductive compound material such as a conductive nitride (e.g., TiN) and / or a metal (e.g., W). The thickness of the optional conductive plate layer 6 may be in the range of 5 nm to 100 nm, although lesser and greater thicknesses may also be used.

[0064] The source level material layer 110' in the process may include various layers that are subsequently modified to form the source level material layer. The source level material layer includes a source contact layer when formed, which is used as a common source region of the vertical field effect transistor of the three-dimensional memory device. In one embodiment, the source level material layer 110' in the process may include, from bottom to top, a lower source level semiconductor layer 112, a lower sacrificial liner 103, a source level sacrificial layer 104, a higher sacrificial liner 105, a higher source level semiconductor layer 116, a source level insulating layer 117, and an optional source selection level conductive layer 118.

[0065] The lower source level semiconductor layer 112 and the upper source level semiconductor layer 116 may include a doped semiconductor material, such as doped polysilicon or doped amorphous silicon. The conductivity type of the lower source level semiconductor layer 112 and the upper source level semiconductor layer 116 may be opposite to the conductivity of the vertical semiconductor channel to be formed subsequently. For example, if the vertical semiconductor channel to be formed subsequently has a doping of a first conductivity type, the lower source level semiconductor layer 112 and the upper source level semiconductor layer 116 have a doping of a second conductivity type opposite to the first conductivity type. The thickness of each of the lower source level semiconductor layer 112 and the upper source level semiconductor layer 116 may be in the range of 10 nm to 300 nm, such as 20 nm to 150 nm, but smaller and larger thicknesses may also be used.

[0066] The source level sacrificial layer 104 includes sacrificial material that can be selectively removed for the lower sacrificial pad 103 and the upper sacrificial pad 105. In one embodiment, the source level sacrificial layer 104 can include a semiconductor material, such as undoped amorphous silicon or a silicon-germanium alloy with an atomic concentration of germanium greater than 20%. The thickness of the source level sacrificial layer 104 can be in the range of 30nm to 400nm, such as 60nm to 200nm, but smaller and larger thicknesses can also be used.

[0067] The lower sacrificial liner 103 and the upper sacrificial liner 105 include materials that can be used as etch stop materials during the removal of the source level sacrificial layer 104. For example, the lower sacrificial liner 103 and the upper sacrificial liner 105 can include silicon oxide, silicon nitride, and / or dielectric metal oxide. In one embodiment, each of the lower sacrificial liner 103 and the upper sacrificial liner 105 can include a silicon oxide layer having a thickness in the range of 2nm to 30nm, although smaller and larger thicknesses can also be used.

[0068] The source level insulating layer 117 may include a dielectric material, such as silicon oxide. The thickness of the source level insulating layer 117 may be in the range of 20nm to 400nm, such as 40nm to 200nm, but smaller and larger thicknesses may also be used. The optional source select level conductive layer 118 may include a conductive material that may be used as a source select level gate electrode. For example, the optional source select level conductive layer 118 may include a doped semiconductor material, such as doped polysilicon or doped amorphous silicon, which may subsequently be converted into doped polysilicon through an annealing process. The thickness of the optional source select level conductive layer 118 may be in the range of 30nm to 200nm, such as 60nm to 100nm, but smaller and larger thicknesses may also be used.

[0069] The source level material layer 110' may be formed directly above a subset of semiconductor devices on a substrate 8 (e.g., a silicon wafer) during the process. As used herein, a first element is positioned "directly above" a second element if the first element is positioned above a horizontal plane that includes the topmost surface of the second element and an area of ​​the first element and the area of ​​the second element has an area overlap in a plan view (i.e., along a vertical plane or direction perpendicular to the top surface of the substrate 8).

[0070] The optional conductive plate layer 6 and the in-process source level material layer 110' may be patterned to provide openings in areas where through memory level contact via structures and through dielectric contact via structures are subsequently formed. Patterned portions of the stack of conductive plate layer 6 and in-process source level material layer 110' are present in each memory array region 100 where a three-dimensional memory stack structure is subsequently formed.

[0071] The optional conductive plate layer 6 and the in-process source level material layer 110' may be patterned so that the opening extends above the staircase region 200 where the contact via structure for contacting the word line conductive layer is to be subsequently formed. In one embodiment, the staircase region 200 may be laterally spaced apart from the memory array region 100 along a first horizontal direction hd1. The horizontal direction perpendicular to the first horizontal direction hd1 is referred to herein as the second horizontal direction hd2. In one embodiment, additional openings in the optional conductive plate layer 6 and the in-process source level material layer 110' may be formed in the region of the memory array region 100 where a three-dimensional memory array including a memory stack structure will be subsequently formed. A peripheral device region 400 subsequently filled with a field dielectric material portion may be provided adjacent to the staircase region 200.

[0072] The area of ​​the semiconductor device 710 and the combination of the lower level dielectric material layer 760 and the lower level metal interconnect structure 780 is referred to herein as the lower level peripheral device area 700, which is positioned below the memory level components to be formed later and includes peripheral devices for the memory level components. The lower level metal interconnect structure 780 is formed in the lower level dielectric material layer 760.

[0073] The lower level metal interconnect structure 780 can be electrically connected to an active node (e.g., a transistor active region 742 or a gate electrode 754) of the semiconductor device 710 (e.g., a CMOS device) and is positioned at the level of the lower level dielectric material layer 760. A through-memory level contact via structure can then be formed directly on the lower level metal interconnect structure 780 to provide an electrical connection to a memory device to be subsequently formed. In one embodiment, the pattern of the lower level metal interconnect structure 780 can be selected so that a landing pad level metal line structure 788 (which is a subset of the lower level metal interconnect structure 780 positioned at the topmost portion of the lower level metal interconnect structure 780) can provide a landing pad structure for a through-memory level contact via structure to be subsequently formed.

[0074] refer to Figure 2 , forming a first layer structure including a first vertical alternating sequence of insulating layers and spacer material layers. The second vertical alternating sequence is also referred to as a first alternating stack of first material layers and second material layers. Each first material layer may include a first material, and each second material layer may include a second material different from the first material. In the case where at least another alternating stack of material layers is subsequently formed above the alternating stack of the first material layer and the second material layer, the alternating stack is referred to herein as a first layer alternating stack. The level of the first layer alternating stack is referred to herein as a first layer level, and the level of the alternating stack to be subsequently formed directly above the first layer level is referred to herein as a second layer level, etc.

[0075] The first layer alternate stack may include a first insulating layer 132 as a first material layer and a first spacer material layer as a second material layer. In one embodiment, the first spacer material layer may be a sacrificial material layer that is subsequently replaced by a conductive layer. In another embodiment, the first spacer material layer may be a conductive layer that is not subsequently replaced by other layers. Although the present disclosure is described using an embodiment in which the sacrificial material layer is replaced by a conductive layer, embodiments in which the spacer material layer is formed as a conductive layer (thereby eliminating the need to perform a replacement process) are clearly contemplated herein.

[0076] In one embodiment, the first material layer and the second material layer may be a first insulating layer 132 and a first sacrificial material layer 142, respectively. In one embodiment, each first insulating layer 132 may include a first insulating material, and each first sacrificial material layer 142 may include a first sacrificial material. Alternating multiple first insulating layers 132 and first sacrificial material layers 142 may be formed over the source level material layer 110' during the process. As used herein, "sacrificial material" refers to a material that is removed during subsequent processing steps.

[0077] As used herein, the alternating stacking of the first element and the second element refers to a structure in which an instance of the first element and an instance of the second element are alternating. Each instance of the first element that is not an end element of the alternating plurality of elements adjoins two instances of the second element on both sides, and each instance of the second element that is not an end element of the alternating plurality of elements adjoins two instances of the first element on both ends. The first element may always have the same thickness, or may have different thicknesses. The second element may always have the same thickness, or may have different thicknesses. The alternating plurality of first material layers and second material layers may start with an instance of the first material layer or an instance of the second material layer, and may end with an instance of the first material layer or an instance of the second material layer. In one embodiment, an instance of the first element and an instance of the second element may form a unit that is periodically repeated within the alternating plurality of elements.

[0078] The first layer alternating stack (132, 142) may include a first insulating layer 132 composed of a first material, and a first sacrificial material layer 142 composed of a second material, the second material being different from the first material. The first material of the first insulating layer 132 may be at least one insulating material. Insulating materials that may be used for the first insulating layer 132 include, but are not limited to, silicon oxide (including doped silicate glass or undoped silicate glass), silicon nitride, silicon oxynitride, organic silicate glass (OSG), spin-on dielectric materials, dielectric metal oxides commonly referred to as high dielectric constant (high-k) dielectric oxides (e.g., aluminum oxide, hafnium oxide, etc.) and their silicates, dielectric metal oxynitrides and their silicates, and organic insulating materials. In one embodiment, the first material of the first insulating layer 132 may be silicon oxide.

[0079] The second material of the first sacrificial material layer 142 is a sacrificial material that can be removed selectively to the first material of the first insulating layer 132. As used herein, removal of a first material is "selective to" a second material if the removal process removes the first material at a rate that is at least twice the removal rate of the second material. The ratio of the removal rate of the first material to the removal rate of the second material is referred to herein as the "selectivity" of the removal process of the first material relative to the second material.

[0080] The first sacrificial material layer 142 may include an insulating material, a semiconductor material, or a conductive material. The second material of the first sacrificial material layer 142 may then be replaced by a conductive electrode, which may be used as, for example, a control gate electrode of a vertical NAND device. In one embodiment, the first sacrificial material layer 142 may be a material layer comprising silicon nitride.

[0081] In one embodiment, the first insulating layer 132 may include silicon oxide, and the sacrificial material layer may include a silicon nitride sacrificial material layer. The first material of the first insulating layer 132 may be deposited, for example, by chemical vapor deposition (CVD). For example, if silicon oxide is used for the first insulating layer 132, tetraethyl orthosilicate (TEOS) may be used as a precursor material for the CVD process. The second material of the first sacrificial material layer 142 may be formed, for example, by CVD or atomic layer deposition (ALD).

[0082] The thickness of the first insulating layer 132 and the first sacrificial material layer 142 may be in the range of 20 nm to 50 nm, although smaller and larger thicknesses may be used for each first insulating layer 132 and each first sacrificial material layer 142. The number of repetitions of the first insulating layer 132 and the first sacrificial material layer 142 pair may be in the range of 2 to 1,024, and typically in the range of 8 to 256, although greater numbers of repetitions may also be used. In one embodiment, each first sacrificial material layer 142 in the first layer alternating stack (132, 142) may have a uniform thickness that is substantially constant within each respective first sacrificial material layer 142.

[0083] A first insulating capping layer 170 is then formed over the first layer alternating stack (132, 142). The first insulating capping layer 170 comprises a dielectric material, which can be any dielectric material that can be used for the first insulating layer 132. In one embodiment, the first insulating capping layer 170 comprises the same dielectric material as the first insulating layer 132. The thickness of the first insulating capping layer 170 can range from 20 nm to 300 nm, although lesser and greater thicknesses can also be used.

[0084] refer to Figure 3 , the first insulating capping layer 170 and the first layer alternately stacked (132, 142) may be patterned to form a first stepped surface in the stepped region 200. The stepped region 200 may include a corresponding first stepped region and a second stepped region, in which a first stepped surface is formed, and in which an additional stepped surface is subsequently formed in a second layer structure (which is subsequently formed above the first layer structure) and / or an additional layer structure. The first stepped surface may be formed, for example, by forming a mask layer (not shown) having an opening therein, etching a cavity within the level of the first insulating capping layer 170 and iteratively extending the etching region, and vertically recessing the cavity by etching each first insulating layer 132 and first sacrificial material layer 142 pair directly below the bottom surface of the etching cavity positioned in the etching region. In one embodiment, the top surface of the first sacrificial material layer 142 may be physically exposed at the first stepped surface. The cavity covering the first stepped surface is referred to herein as a first stepped cavity.

[0085] A dielectric fill material (such as undoped silicate glass or doped silicate glass) may be deposited to fill the first stepped cavity. Excess portions of the dielectric fill material may be removed from above a horizontal plane including the top surface of the first insulating cap layer 170. The remaining portion of the dielectric fill material filling the area overlying the first stepped surface constitutes a first backward stepped dielectric material portion 165. As used herein, a "backward stepped" element refers to an element having a stepped surface and a horizontal cross-sectional area that increases monotonically according to the vertical distance from the top surface of the substrate on which the element is present. The first layer of alternating stacks (132, 142) and the first backward stepped dielectric material portion 165 together constitute a first layer structure, which is a process structure that is subsequently modified.

[0086] An interlayer dielectric layer 180 may be optionally deposited over the first layer structure (132, 142, 170, 165). The interlayer dielectric layer 180 includes a dielectric material, such as silicon oxide. In one embodiment, the interlayer dielectric layer 180 may include a doped silicate glass having a greater etching rate than the material of the first insulating layer 132 (which may include undoped silicate glass). For example, the interlayer dielectric layer 180 may include phosphosilicate glass. The thickness of the interlayer dielectric layer 180 may be in the range of 30 nm to 300 nm, but smaller and larger thicknesses may also be used.

[0087] refer to Figure 4A and Figure 4B , various first layer openings (149, 129) may be formed through the interlayer dielectric layer 180 and the first layer structure (132, 142, 170, 165) and into the in-process source level material layer 110'. A photoresist layer (not shown) may be applied over the interlayer dielectric layer 180 and may be photolithographically patterned to form various openings therethrough. The pattern of the openings in the photoresist layer may be transferred through the interlayer dielectric layer 180 and the first layer structure (132, 142, 170, 165) and into the in-process source level material layer 110' by a first anisotropic etching process to form the various first layer openings (149, 129) simultaneously (i.e., during the first isotropic etching process). The various first layer openings (149, 129) may include a first layer memory opening 149 and a first layer support opening 129. In Figure 4B The position of the step S in the first layer of alternating stacking (132, 142) is shown by a dotted line.

[0088] The first layer memory openings 149 are openings formed in the memory array area 100 through each layer within the first layer alternating stack (132, 142) and are subsequently used to form a memory stack structure therein. The first layer memory openings 149 may be formed as clusters of first layer memory openings 149 that are laterally spaced apart along the second horizontal direction hd2. Each cluster of first layer memory openings 149 may be formed as a two-dimensional array of first layer memory openings 149.

[0089] The first level support openings 129 are openings formed in the stair region 200 and are subsequently used to form support post structures. A subset of the first level support openings 129 formed through the first rear stepped dielectric material portion 165 may be formed through corresponding horizontal surfaces of the first stepped surface.

[0090] In one embodiment, the first anisotropic etching process may include an initial step in which the material of the first layer alternating stack (132, 142) is etched simultaneously with the material of the first backward stepped dielectric material portion 165. The chemistry of the initial etching step may be alternating to optimize the etching of the first material and the second material in the first layer alternating stack (132, 142) while providing an average etching rate comparable to the material of the first backward stepped dielectric material portion 165. The first anisotropic etching process may use, for example, a series of reactive ion etching processes or a single reactive etching process (e.g., CF4 / O2 / Ar etching). The sidewalls of the various first layer openings (149, 129) may be substantially vertical, or may be tapered.

[0091] After etching through the alternating stacks (132, 142) and the first backward stepped dielectric material portion 165, the chemistry of the final portion of the first anisotropic etching process may be selected to etch through the one or more dielectric materials of the at least one second dielectric layer 768 at a higher etch rate than the average etch rate of the source level material layer 110' during the process. For example, the final portion of the anisotropic etching process may include a step of etching the one or more dielectric materials of the at least one second dielectric layer 768 selectively to the semiconductor material within the component layer in the source level material layer 110' during the process. In one embodiment, the final portion of the first anisotropic etching process may etch through the source select level conductive layer 118, the source level insulating layer 117, the upper source level semiconductor layer 116, the upper sacrificial liner 105, the source level sacrificial layer 104, and the lower sacrificial liner 103, and at least partially into the lower source level semiconductor layer 112. The final portion of the first anisotropic etching process may include at least one etching chemistry for the various semiconductor materials of the source level material layer 110' during the etching process.The photoresist layer may then be removed, for example, by ashing.

[0092] Optionally, the portion of the first layer memory opening 149 and the first layer support opening 129 at the level of the interlayer dielectric layer 180 can be expanded laterally by isotropic etching. In this case, the interlayer dielectric layer 180 may include a dielectric material (such as borosilicate glass) having a greater etching rate in dilute hydrofluoric acid than the first insulating layer 132 (which may include undoped silicate glass). Isotropic etching (such as wet etching using HF) can be used to expand the lateral size of the first layer memory opening 149 at the level of the interlayer dielectric layer 180. The portion of the first layer memory opening 149 positioned at the level of the interlayer dielectric layer 180 can be optionally widened to provide a larger landing pad for the second layer memory opening that will be subsequently formed through the second layer alternating stack (subsequently formed before forming the second layer memory opening).

[0093] FIG. 5A to FIG. 5D is a vertical cross-sectional view of a first layer memory opening 149 during formation of a sacrificial first layer memory opening filling structure 148 in a first configuration of a first exemplary structure according to a first embodiment of the present disclosure.

[0094] refer to Figure 5A , as shown in Figure 4A and Figure 4B A first layer memory opening 149 in the memory array region 100 is formed at the processing step of FIG.

[0095] refer to Figure 5B A conformal deposition process may be used to form the first dielectric liner layer 1481. The first dielectric liner layer 1481 includes a dielectric material such as silicon oxide and may have a thickness in the range of 2 nm to 12 nm, such as 3 nm to 8 nm, although smaller and larger thicknesses may also be used.

[0096] refer to Figure 5C, a first carbon-based filling material may be deposited in the first layer memory opening 149 and the first layer support opening 129. The first carbon-based filling material contains carbon with an atomic percentage greater than 50%. For example, the first carbon-based filling material may include amorphous carbon, diamond-like carbon, or a doped derivative thereof and / or may be substantially composed of amorphous carbon, diamond-like carbon, or a doped derivative thereof. Excess portions of the first carbon-based filling material may be removed from above the top surface of the horizontally extending portion of the first dielectric liner layer 1481 by performing a recess etching process. The duration of the recess etching process may be selected so that the top surface of the remaining portion of the first carbon-based filling material is formed below a horizontal plane including the topmost surface of the first layer alternating stack (132, 142). Each remaining portion of the first carbon-based filling material in the first layer memory opening 149 and the first layer support opening 129 constitutes a first carbon-based filling material portion 148F. The vertical distance between a horizontal plane including the topmost surface of the first layer alternating stack (132, 142) and the top surface of the first carbon-based filling material portion 148F can be in the range of 10nm to 200nm, such as 20nm to 100nm, but smaller and larger vertical distances can also be used. Generally speaking, the first carbon-based filling material portion 148F is formed by depositing the first carbon-based filling material in the first layer memory opening 149 and above the first layer alternating stack (132, 142), and by removing at least a portion of the first carbon-based filling material from above the first layer alternating stack (132, 142) and by recessing the first carbon-based filling material in the first layer memory opening 149 and the upper portion of the first layer support opening 129.

[0097] refer to Figure 5D , a first conductive material may be deposited in the void overlying the first layer memory opening 149 and the first layer support opening 129. The first conductive material includes a transition metal or a conductive metal compound. In one embodiment, the first conductive material may include and / or may consist essentially of a metal such as tungsten, molybdenum, ruthenium, cobalt, another transition metal element or an alloy thereof; or a conductive compound such as a metal silicide or a metal nitride, such as titanium silicide, tungsten silicide, cobalt silicide, nickel silicide, titanium nitride, tantalum nitride, molybdenum nitride, tungsten nitride, etc. The first conductive material may also include multiple conductive layers, such as titanium nitride and tungsten layers.

[0098] Portions of the first conductive material and the first dielectric liner layer 1481 that are overlying a horizontal plane including a top surface of the topmost layer of the first layer alternating stack (132, 142) may be removed by performing a planarization process, such as a chemical mechanical polishing (CMP) process and / or a recess etching process. Each remaining portion of the first conductive material constitutes a first conductive material portion 148M. Generally speaking, the first conductive material portion 148M may be formed by depositing a layer of the first conductive material over the first carbon-based filling material portion 148F and by removing a portion of the layer of the first conductive material from above a horizontal plane including a top surface of the first layer alternating stack (132, 142) by performing a planarization process, which may include a chemical mechanical polishing process and / or a recess etching process. Each remaining portion of the first dielectric liner layer 1481 constitutes a first dielectric liner 148L formed on a sidewall of a respective one of the first layer memory opening 149 and the first layer support opening 129.

[0099] Generally, a sacrificial first level memory opening filling structure 148 is formed in each first level memory opening 149, and a sacrificial first level support opening filling structure is formed in each first level support opening 129. Each of the sacrificial first level memory opening filling structure 148 and the sacrificial first level support opening filling structure includes an optional first dielectric liner 148L and a stack of a first carbon-based filling material portion 148F and a first conductive material portion 148M.

[0100] FIG. 6A to FIG. 6C is a vertical cross-sectional view of a first layer memory opening 149 during formation of a sacrificial first layer memory opening filling structure 148 in the second configuration of the first exemplary structure according to the first embodiment of the present disclosure.

[0101] refer to Fig. 6A , the second configuration of the first exemplary structure can be Figure 5C The first configuration of the first exemplary structure shown is the same. The top surface of the first carbon-based filler material portion 148F may be recessed to a depth in the range of 20 nm to 300 nm, such as 40 nm to 150 nm, relative to a horizontal plane including the topmost surface of the first layer alternating stack (132, 142), although smaller and larger vertical distances may also be employed.

[0102] refer to Figure 6B , executable reference Figure 5DThe processing steps described are to deposit the first conductive material. Portions of the first conductive material and the first dielectric liner layer 1481 that are overlying a horizontal plane including the top surface of the topmost layer of the first layer alternating stack (132, 142) can be removed by performing a planarization process such as a chemical mechanical polishing (CMP) process and / or a recess etching process. Each remaining portion of the first conductive material constitutes a first conductive material portion 148M.

[0103] Subsequently, the first conductive material portion 148M may be thinned by performing a recess etching process that selectively etches the first conductive material to the material of the first layer of insulating layer 132. The first conductive material may be vertically recessed below a horizontal plane that includes the topmost surface of the first layer of alternating stacks (132, 142). The recess depth of the top surface of the first conductive material portion 148M relative to the horizontal plane that includes the topmost surface of the first layer of alternating stacks (132, 142) may be in the range of 10nm to 200nm, such as 20nm to 100nm, but smaller and larger vertical distances may also be used. In general, the first conductive material portion 148M may be formed by depositing a first conductive material layer over the first carbon-based filling material portion 148F and by removing a portion of the layer of the first conductive material from above the horizontal plane that includes the top surface of the first layer of alternating stacks (132, 142) and from the upper portion of the first layer of memory openings 149 and the first layer of support openings 129. Each remaining portion of the first dielectric liner layer 1481 constitutes a first dielectric liner 148L formed on a sidewall of a corresponding one of the first-layer memory opening 149 and the first-layer supporting opening 129 .

[0104] refer to Figure 6C , a first carbon-based capping material containing an atomic percentage of greater than 50% carbon may be deposited in a recessed cavity, overlying the thinned first conductive material portion 148M, and may be subsequently recessed to form a first carbon-based capping material portion 148C. The carbon-based capping material portion may be selected from any material of the first carbon-based filling material that may be used for the first carbon-based filling material portion 148F. Each first carbon-based capping material portion 148C may be formed on the top surface of a corresponding first conductive material portion in the thinned first conductive material portion 148M. In one embodiment, the top surface of the first carbon-based capping material portion 148C may be formed at or near a horizontal plane including the topmost surface of the first layer alternating stack (132, 142). A stack of the first carbon-based filling material portion 148F, the first conductive material portion 148M, and the first carbon-based capping material portion 148C may be formed on the interior and inner sidewalls of each first dielectric liner 148L.

[0105] Generally, a sacrificial first level memory opening filling structure 148 is formed in each first level memory opening 149, and a sacrificial first level support opening filling structure is formed in each first level support opening 129. Each of the sacrificial first level memory opening filling structure 148 and the sacrificial first level support opening filling structure includes an optional first dielectric liner 148L and a stack of a first carbon-based filling material portion 148F, a first conductive material portion 148M, and a first carbon-based capping material portion 148C.

[0106] refer to Figure 7 , shows a first exemplary structure after forming sacrificial first layer opening filling structures (148, 128) in the first layer openings (149, 129). Each first layer memory opening 149 is filled with a sacrificial first layer memory opening filling structure 148, and each first layer support opening 129 is filled with a sacrificial first layer support opening filling structure 128.

[0107] refer to Figure 8 , a second layer structure may be formed above the first layer structure (132, 142, 165, 148, 128). The second layer structure may include an additional vertical alternating sequence of additional insulating layers and additional spacer material layers, which may be additional sacrificial material layers. The second vertical alternating sequence is also referred to as a second alternating stack. For example, a second alternating stack (232, 242) of material layers may be subsequently formed on the top surface of the first alternating stack (132, 142). The second alternating stack (232, 242) includes alternating multiple third material layers and fourth material layers. Each third material layer may include a third material, and each fourth material layer may include a fourth material different from the third material. In one embodiment, the third material may be the same as the first material of the first insulating layer 132, and the fourth material may be the same as the second material of the first sacrificial material layer 142.

[0108] In one embodiment, the third material layer may be a second insulating layer 232, and the fourth material layer may be a second spacer material layer providing a vertical spacing between each vertically adjacent pair of second insulating layers 232. In one embodiment, the third material layer and the fourth material layer may be a second insulating layer 232 and a second sacrificial material layer 242, respectively. The third material of the second insulating layer 232 may be at least one insulating material. The fourth material of the second sacrificial material layer 242 may be a sacrificial material that may be selectively removed for the third material of the second insulating layer 232. The second sacrificial material layer 242 may include an insulating material, a semiconductor material, or a conductive material. The fourth material of the second sacrificial material layer 242 may then be replaced with a conductive electrode, which may be used as, for example, a control gate electrode of a vertical NAND device.

[0109] In one embodiment, each second insulating layer 232 may include a second insulating material, and each second sacrificial material layer 242 may include a second sacrificial material. In this case, the second alternating stack (232, 242) may include alternating multiple second insulating layers 232 and second sacrificial material layers 242. The third material of the second insulating layer 232 may be deposited, for example, by chemical vapor deposition (CVD). The fourth material of the second sacrificial material layer 242 may be formed, for example, by CVD or atomic layer deposition (ALD).

[0110] The third material of the second insulating layer 232 may be at least one insulating material. The insulating material that may be used for the second insulating layer 232 may be any material that may be used for the first insulating layer 132. The fourth material of the second sacrificial material layer 242 is a sacrificial material that may be selectively removed with respect to the third material of the second insulating layer 232. The sacrificial material that may be used for the second sacrificial material layer 242 may be any material that may be used for the first sacrificial material layer 142. In one embodiment, the second insulating material may be the same as the first insulating material, and the second sacrificial material may be the same as the first sacrificial material.

[0111] The thickness of the second insulating layer 232 and the second sacrificial material layer 242 can be in the range of 20 nm to 50 nm, but smaller and larger thicknesses can be used for each second insulating layer 232 and each second sacrificial material layer 242. The number of repetitions of the second insulating layer 232 and the second sacrificial material layer 242 pair can be in the range of 2 to 1,024, and typically in the range of 8 to 256, but more repetitions can also be used. In one embodiment, each second sacrificial material layer 242 in the second alternating stack (232, 242) can have a uniform thickness that is substantially constant within each corresponding second sacrificial material layer 242.

[0112] The same set of processing steps as those used to form the first stepped surface in the first stepped region may be used while appropriately adjusting the pattern of at least one mask layer to form a second stepped surface in the second stepped region of the staircase region 200. A second rear stepped dielectric material portion 265 may be formed over the second stepped surface in the staircase region 200.

[0113] refer to Fig. 9A and Fig. 9B, a patterned etch mask layer 287 may be formed over the second layer alternating stack (232, 242) and the second backward stepped dielectric material portion 265. For example, a blanket etch mask material layer including a carbon-based material (such as a patterned film material) may be applied over the second layer alternating stack (232, 242) and the second backward stepped dielectric material portion 265. In one embodiment, the carbon-based material of the blanket etch mask material layer may include amorphous carbon, diamond-like carbon, or a doped derivative thereof. A photoresist layer (not shown) may be applied over the blanket etch mask material layer and may be photolithographically patterned to form openings having the same pattern as the first layer openings (149, 129) formed at the processing steps of 4A and 4B, which is the same as the sacrificial first layer opening filling structure (148, 128). Therefore, the photoresist layer may be patterned using a photolithographic mask for patterning the first layer openings (149, 129). The opening pattern in the photoresist layer may be transferred into the blanket etch mask material layer to form a patterned etch mask layer 287. The photoresist layer may be consumed during the pattern transfer into the blanket etch mask material layer, or may be consumed in parallel during a subsequent anisotropic etching process.

[0114] The pattern in the patterned etching mask layer 287 can be transferred through the second layer structure (232, 242, 265, 270) by a second anisotropic etching process to form a second layer opening (249, 229). The second layer opening (249, 229) may include a second layer memory opening 249 and a second layer support opening 229. The second layer memory opening 249 is directly formed on the top surface of a corresponding one of the sacrificial first layer memory opening filling structures 148. The second layer support opening 229 is directly formed on the top surface of a corresponding one of the sacrificial first layer support opening filling structures 128. Fig. 9B The positions of the steps S in the first vertical alternating sequence (132, 142) and the second vertical alternating sequence (232, 242) are shown in dashed lines.

[0115] Generally speaking, a patterned etching mask layer 287 can be formed above the second layer alternating stack (232, 242), and a second layer memory opening 249 and a second layer support opening 229 can be formed below the opening in the patterned etching mask layer 287 by performing an anisotropic etching process having an etching chemistry that selectively etches the material of the second insulating layer 232 and the second spacer material layer with respect to the material of the first conductive material portion 148M.

[0116] FIG. 10A to FIG. 10Gis a vertical cross-sectional view of the first layer memory opening 149 and the second layer memory opening 249 during formation of a sacrificial second layer memory opening filling structure 248 in the first configuration of the first exemplary structure according to the first embodiment of the present disclosure.

[0117] refer to Fig. 10A , showing a region of a first configuration of the first exemplary structure after forming the second level memory opening 249. The first conductive material portion 148M may be used as an etch stop structure for an anisotropic etching process used to form the second level memory opening 249.

[0118] refer to Fig. 10B And according to one aspect of the present disclosure, at least one isotropic etching process may be performed to laterally recess the second spacer material layer (such as the second sacrificial material layer 242) and / or the second insulating layer 232. In one embodiment, the at least one isotropic etching process may include: a first isotropic etching process that laterally recesses the second spacer material layer (such as the second sacrificial material layer 242) around the second layer memory opening 249; and a second isotropic etching process that laterally recesses the second insulating layer 232 around the second layer memory opening 249. For example, if the second insulating layer 232 includes silicon oxide and the second sacrificial material layer 242 includes silicon nitride, the first isotropic etching process may include a wet etching process using hot phosphoric acid, and the second isotropic etching process may include a wet etching process using dilute hydrofluoric acid. The first conductive material portion 148M blocks the diffusion of the etchant of the isotropic etching process toward the first carbon-based filling material portion 148F. Thus, the second layer memory opening 249 can be laterally expanded without expanding any portion of the first layer memory opening 149 and without removing the first carbon-based filling material portion 148F. The patterned etch mask layer 287 can be removed before or after the at least one isotropic etching process, for example, by performing an ashing process that volatilizes the carbon-based material of the patterned etch mask layer 287.

[0119] refer to Fig. 10C, a selective etching process may be performed to remove the first conductive material portion 148M. For example, if the first conductive material portion 148M includes tungsten, a wet etching process based on sulfuric acid and / or hydrogen peroxide may be performed, which selectively etches the conductive material of the first conductive material portion 148M with respect to the materials of the second insulating layer 232 and the second sacrificial material layer 242 and the first carbon-based filling material portion 148F. In another example, if the first conductive material portion 148M includes ruthenium or titanium silicide, a reactive ion etching process using corresponding oxygen and chlorine chemistry or fluorocarbon chemistry may be performed, which selectively etches the conductive material of the first conductive material portion 148M with respect to the materials of the second insulating layer 232 and the second sacrificial material layer 242 and the first carbon-based filling material portion 148F.

[0120] refer to Fig. 10D A conformal deposition process may be used to form the second dielectric liner layer 2481. The second dielectric liner layer 2481 includes a dielectric material such as silicon oxide and may have a thickness in the range of 2 nm to 12 nm, such as 3 nm to 8 nm, although smaller and larger thicknesses may also be used.

[0121] refer to Fig. 10E , an anisotropic etching process may be performed to remove the horizontally extending portion of the second dielectric liner layer 2481. Each remaining portion of the second dielectric liner layer 2481 remaining in the second layer memory opening 249 or in the second layer support opening 229 constitutes a second dielectric liner 248L. Each second dielectric liner 248L may have a tubular configuration. The top surface of the first carbon-based filling material portion 148F may be physically exposed at the bottom of each cavity in the second layer memory opening 249 and the second layer support opening 229.

[0122] refer to Fig.10F, a second carbon-based filling material may be deposited in the unfilled volume of the second layer memory opening 249 and the second layer support opening 229. The second carbon-based filling material contains carbon with an atomic percentage greater than 50%. For example, the second carbon-based filling material may include amorphous carbon, diamond-like carbon, or a doped derivative thereof and / or may be substantially composed of amorphous carbon, diamond-like carbon, or a doped derivative thereof. Excess portions of the second carbon-based filling material may be removed from above the top surface of the horizontally extending portion of the second dielectric liner layer 2481 by performing a recess etching process. The duration of the recess etching process may be selected so that the top surface of the remaining portion of the second carbon-based filling material is formed below a horizontal plane including the topmost surface of the second layer alternating stack (232, 242). Each remaining portion of the second carbon-based filling material in the second layer memory opening 249 and the second layer support opening 229 constitutes a second carbon-based filling material portion 248F. The vertical distance between a horizontal plane including the topmost surface of the second layer alternating stack (232, 242) and the top surface of the second carbon-based filling material portion 248F may be in the range of 10 nm to 200 nm, such as 20 nm to 100 nm, but smaller and larger vertical distances may also be used. Generally speaking, the second carbon-based filling material portion 248F is formed by depositing the second carbon-based filling material in the second layer memory opening 249 and above the second layer alternating stack (232, 242), and by removing at least a portion of the second carbon-based filling material from above the second layer alternating stack (232, 242) and by recessing the second carbon-based filling material in the second layer memory opening 249 and the upper portion of the second layer support opening 229.

[0123] refer to Figure 10G , a second conductive material may be deposited in the void overlying the second layer memory opening 249 and the second layer support opening 229. The second conductive material includes a transition metal or a conductive metal compound. In one embodiment, the second conductive material may include and / or may consist essentially of a metal such as tungsten, molybdenum, ruthenium, cobalt, another transition metal element or an alloy thereof; or a conductive compound such as a metal silicide or a metal nitride, such as titanium silicide, tungsten silicide, cobalt silicide, nickel silicide, titanium nitride, tantalum nitride, molybdenum nitride, tungsten nitride, etc. The second conductive material may also include multiple conductive layers, such as titanium nitride and tungsten layers.

[0124] Portions of the second conductive material overlying a horizontal plane including a top surface of a topmost layer of the second layer alternating stack (232, 242) may be removed by performing a planarization process, such as a chemical mechanical polishing (CMP) process and / or a recess etching process. Each remaining portion of the second conductive material constitutes a second conductive material portion 248M. Generally, the second conductive material portion 248M may be formed by depositing a layer of the second conductive material over the second carbon-based filler material portion 248F and by removing a portion of the layer of the second conductive material from above a horizontal plane including a top surface of the second layer alternating stack (232, 242) by performing a planarization process, which may include a chemical mechanical polishing process and / or a recess etching process. The second dielectric liner 248L is located on a sidewall of a respective one of the second layer memory opening 249 and the second layer support opening 229.

[0125] Generally, a sacrificial second-layer memory opening filling structure 248 is formed in each second-layer memory opening 249, and a sacrificial second-layer support opening filling structure is formed in each second-layer support opening 229. Each of the sacrificial second-layer memory opening filling structure 248 and the sacrificial second-layer support opening filling structure includes an optional second dielectric liner 248L and a stack of a second carbon-based filling material portion 248F and a second conductive material portion 248M. In one embodiment, after selectively removing the first conductive material portion 148M for the first carbon-based filling material portion 148F, a sacrificial second-layer memory opening filling structure 248 including a stack of a second carbon-based filling material portion 248F and a second conductive material portion 248M may be formed in an upper portion of each second-layer memory opening 249.

[0126] FIG. 11A to FIG. 11G is a vertical cross-sectional view of the first layer memory opening 149 and the second layer memory opening 249 during formation of a sacrificial second layer memory opening filling structure 248 in the second configuration of the first exemplary structure according to the first embodiment of the present disclosure.

[0127] refer to Fig.11A , shown in reference Fig. 9A and Fig. 9B A second configuration of the first exemplary structure after an anisotropic etching process is described. In this case, the first carbon-based capping material portion 148C can be etched through by an anisotropic etching process that forms the second layer memory opening 249 and the second layer support opening 229. The first conductive material portion 148M can be used as an etch stop structure for the anisotropic etching process that forms the second layer memory opening 249.

[0128] refer to Fig. 11B , executable reference Fig. 10BThe processing steps are described to laterally expand the second level memory openings 249 and the second level support openings 229. The patterned etch mask layer 287 and the remaining portions of the first carbon-based capping material portions 148C may then be removed, for example, by ashing.

[0129] refer to Fig. 11C , executable reference Fig. 10C The processing steps are described to remove the first conductive material portion 148M.

[0130] refer to Fig.11D , executable reference Fig. 10D The processing steps are described to form the second dielectric liner layer 2481.

[0131] refer to Fig.11E , executable reference Fig.10E The processing steps are described to remove the horizontally extending portions of the second dielectric liner layer 2481. Each remaining portion of the second dielectric liner layer 2481 remaining in the second layer memory opening 249 or in the second layer support opening 229 constitutes a second dielectric liner 248L.

[0132] refer to Fig.11F , executable reference Fig.10F The processing steps are described to form the second carbon-based fill material portion 248F.

[0133] Then, you can execute the reference Figure 10G The processing steps described are to deposit the second conductive material. Portions of the second conductive material overlying a horizontal plane including a top surface of the topmost layer of the second layer alternating stack (232, 242) may be removed by performing a planarization process such as a chemical mechanical polishing (CMP) process and / or a recess etching process. Each remaining portion of the second conductive material constitutes a second conductive material portion 248M.

[0134] The second conductive material portion 248M may be thinned (i.e., recessed) by performing a recess etching process that selectively etches the second conductive material to the material of the second layer of insulating layer 232. The second conductive material may be vertically recessed below a horizontal plane that includes the topmost surface of the second layer of alternating stacks (232, 242). The top surface of the second conductive material portion 248M may be recessed to a depth relative to a horizontal plane that includes the topmost surface of the second layer of alternating stacks (232, 242) in a range of 10 nm to 200 nm, such as 20 nm to 100 nm, although smaller and larger vertical distances may also be employed. Generally speaking, the second conductive material portion 248M may be formed by depositing a second conductive material layer over the second carbon-based filling material portion 248F and by removing a portion of the layer of the second conductive material from above a horizontal plane that includes the top surface of the second layer of alternating stacks (232, 242) and from an upper portion of the second layer of memory openings 249 and the second layer of support openings 229.

[0135] refer to Fig.11G , a second carbon-based capping material containing an atomic percentage of greater than 50% carbon may be deposited in the recessed cavity, overlying the thinned second conductive material portion 248M, and may be subsequently recessed to form a second carbon-based capping material portion 248C. The carbon-based capping material portion may be selected from any material of the second carbon-based filling material that can be used for the second carbon-based filling material portion 248F. Each second carbon-based capping material portion 248C may be formed on the top surface of a corresponding second conductive material portion in the thinned second conductive material portion 248M. In one embodiment, the top surface of the second carbon-based capping material portion 248C may be formed at or near a horizontal plane including the topmost surface of the second layer alternating stack (232, 242). The stack of the second carbon-based filling material portion 248F, the second conductive material portion 248M, and the second carbon-based capping material portion 248C may be formed on the interior and inner sidewalls of each second dielectric liner 248L.

[0136] Generally, a sacrificial second level memory opening filling structure 248 is formed in each second level memory opening 249, and a sacrificial second level support opening filling structure is formed in each second level support opening 229. Each of the sacrificial second level memory opening filling structure 248 and the sacrificial second level support opening filling structure includes an optional second dielectric liner 248L and a stack of a second carbon-based filling material portion 248F, a second conductive material portion 248M, and a second carbon-based capping material portion 248C.

[0137] refer to Fig.12, shows a first exemplary structure after forming sacrificial second layer opening filling structures (248, 228) in the second layer openings (249, 229). Each second layer memory opening 249 is filled with a sacrificial second layer memory opening filling structure 248, and each second layer support opening 229 is filled with a sacrificial second layer support opening filling structure 128.

[0138] refer to Fig.13 , a third layer structure may be formed above the second layer structure (232, 242, 265, 248, 228). The third layer structure may include an additional vertical alternating sequence of additional insulating layers and additional spacer material layers, which may be additional sacrificial material layers. The third vertical alternating sequence is also referred to as a third alternating stack. For example, a third alternating stack (332, 342) of material layers may then be formed on the top surface of the second alternating stack (232, 242). The third alternating stack (332, 342) includes alternating multiple fifth material layers and sixth material layers. Each fifth material layer may include a fifth material, and each sixth material layer may include a sixth material different from the fifth material. In one embodiment, the fifth material may be the same as the first material of the first insulating layer 132, and the sixth material may be the same as the second material of the first sacrificial material layer 142.

[0139] In one embodiment, the third material layer may be a third insulating layer 332, and the fourth material layer may be a third spacer material layer that provides a vertical spacing between each vertically adjacent pair of third insulating layers 332. In one embodiment, the third material layer and the fourth material layer may be a third insulating layer 332 and a third sacrificial material layer 342, respectively. The third material of the third insulating layer 332 may be at least one insulating material. The fourth material of the third sacrificial material layer 342 may be a sacrificial material that may be selectively removed for the third material of the third insulating layer 332. The third sacrificial material layer 342 may include an insulating material, a semiconductor material, or a conductive material. The fourth material of the third sacrificial material layer 342 may then be replaced with a conductive electrode that may be used, for example, as a control gate electrode of a vertical NAND device.

[0140] In one embodiment, each third insulating layer 332 may include a third insulating material, and each third sacrificial material layer 342 may include a third sacrificial material. In this case, the third alternating stack (332, 342) may include alternating multiple third insulating layers 332 and third sacrificial material layers 342. The third material of the third insulating layer 332 may be deposited, for example, by chemical vapor deposition (CVD). The fourth material of the third sacrificial material layer 342 may be formed, for example, by CVD or atomic layer deposition (ALD).

[0141] The fifth material of the third insulating layer 332 may be at least one insulating material. The insulating material that may be used for the third insulating layer 332 may be any material that may be used for the second insulating layer 232. The sixth material of the third sacrificial material layer 342 is a sacrificial material that may be selectively removed for the fifth material of the third insulating layer 332. The sacrificial material that may be used for the third sacrificial material layer 342 may be any material that may be used for the second sacrificial material layer 242. In one embodiment, the third insulating material may be the same as the second insulating material, and the third sacrificial material may be the same as the second sacrificial material.

[0142] The thickness of the third insulating layer 332 and the third sacrificial material layer 342 may be in the range of 30 nm to 50 nm, but smaller and larger thicknesses may be used for each third insulating layer 332 and each third sacrificial material layer 342. The number of repetitions of the third insulating layer 332 and the third sacrificial material layer 342 pair may be in the range of 3 to 1,024, and typically in the range of 8 to 356, but more repetitions may also be used. In one embodiment, each third sacrificial material layer 342 in the third alternating stack (332, 342) may have a uniform thickness that is substantially constant within each respective third sacrificial material layer 342.

[0143] The same set of processing steps as those used to form the second stepped surface in the second stepped region may be used while appropriately adjusting the pattern of at least one mask layer to form a third stepped surface in the third stepped region of the staircase region 200. A third rear stepped dielectric material portion 365 may be formed over the third stepped surface in the staircase region 300.

[0144] Optionally, a drain select level isolation structure (not shown) may be formed through a subset of the layers in the upper portion of the third vertical alternating sequence (332, 342). The third sacrificial material layer 342 cut by the select drain level shallow trench isolation structure corresponds to a level in which a drain select level conductive layer is subsequently formed. The drain select level isolation structure includes a dielectric material such as silicon oxide. The drain select level isolation structure may extend laterally along a first horizontal direction hd1 and may be spaced laterally along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1.

[0145] In some embodiments, the bottommost third insulating layer 33' may include an insulating material having a higher etching rate than the rest of the third insulating layer 332, and the bottommost third sacrificial material layer 34' may include a sacrificial material having a higher etching rate than the rest of the third sacrificial material layer 342. In one embodiment, all third insulating layers 332 except the bottommost third insulating layer 33' include a first silicon oxide material, and the bottommost third insulating layer 33' includes a second silicon oxide material having a higher etching rate in dilute hydrofluoric acid than the first silicon oxide material. For example, the second silicon oxide material may include a dopant such as boron and / or phosphorus, and / or may be formed using different process parameters (such as temperature, pressure, RF power, etc.) during the deposition process. In one embodiment, all third spacer material layers (such as the third sacrificial material layer 342) except the bottommost third spacer material layer (such as the bottommost third sacrificial material layer 34') include a first silicon nitride material, and the bottommost third spacer material layer 34' includes a second silicon nitride material having a higher etching rate in hot phosphoric acid than the first silicon nitride material. For example, the second silicon nitride material may be formed during the deposition process using different process parameters such as temperature, pressure, RF power, etc. The composition change in the bottommost third insulating layer 33' and / or the bottommost third sacrificial material layer 34' may be advantageously used to cause the formation of a lateral protrusion in the memory opening filling structure to enhance the electrical properties of the vertical semiconductor channel to be formed subsequently.

[0146] refer to Fig.14 , a patterned etch mask layer 387 may be formed over the third layer alternating stack (332, 342) and the third backward stepped dielectric material portion 365. For example, a blanket etch mask material layer including a carbon-based material (such as a patterned film material) may be applied over the third layer alternating stack (332, 342) and the third backward stepped dielectric material portion 365. In one embodiment, the carbon-based material of the blanket etch mask material layer may include amorphous carbon, diamond-like carbon, or a doped derivative thereof. A photoresist layer (not shown) may be applied over the blanket etch mask material layer and may be photolithographically patterned to form openings having the same pattern as the first layer openings (149, 129) formed at the processing steps of 4A and 4B, which is the same as the sacrificial first layer opening filling structure (148, 128). Therefore, the photoresist layer may be patterned using a photolithographic mask for patterning the first layer openings (149, 129). The opening pattern in the photoresist layer may be transferred into the blanket etch mask material layer to form a patterned etch mask layer 387. The photoresist layer may be consumed during the pattern transfer into the blanket etch mask material layer, or may be consumed in parallel during a subsequent anisotropic etching process.

[0147] The pattern in the patterned etching mask layer 387 can be transferred through the third layer structure (332, 342, 365) by a third anisotropic etching process to form a third layer opening (349, 329). The third layer opening (349, 329) may include a third layer memory opening 349 and a third layer support opening 329. The third layer memory opening 349 is directly formed on the top surface of a corresponding one of the sacrificial second layer memory opening filling structures 248. The third layer support opening 329 is directly formed on the top surface of a corresponding one of the sacrificial second layer support opening filling structures 228.

[0148] Generally speaking, a patterned etching mask layer 387 can be formed above the third layer alternating stack (332, 342), and a third layer memory opening 349 and a third layer support opening 329 can be formed below the opening in the patterned etching mask layer 387 by performing an anisotropic etching process having an etching chemistry that selectively etches the material of the third insulating layer 332 and the third spacer material layer with respect to the material of the second conductive material portion 248M.

[0149] FIG. 15A to FIG. 15G is a vertical cross-sectional view of first layer memory openings 149 , second layer memory openings 249 , and third layer memory openings 349 in a first configuration of a first exemplary structure during formation of interlayer memory openings 49 and memory opening filling structures 58 according to the first embodiment of the present disclosure.

[0150] refer to Fig.15A , showing a region of a first configuration of the first exemplary structure after forming the third level memory opening 349. The second conductive material portion 248M may be used as an etch stop structure for an anisotropic etching process used to form the third level memory opening 349.

[0151] refer to Fig. 15B, at least one isotropic etching process may be optionally performed to laterally recess the third spacer material layer (such as the third sacrificial material layer 342) and / or the third insulating layer 332. In one embodiment, the at least one isotropic etching process may include: a first isotropic etching process that laterally recesses the third spacer material layer (such as the third sacrificial material layer 342) around the third layer memory opening 349; and a second isotropic etching process that laterally recesses the third insulating layer 332 around the third layer memory opening 349. For example, if the third insulating layer 332 includes silicon oxide and the third sacrificial material layer 342 includes silicon nitride, the first isotropic etching process may include a wet etching process using hot phosphoric acid, and the second isotropic etching process may include a wet etching process using dilute hydrofluoric acid. The second conductive material portion 248M blocks the diffusion of the etchant of the isotropic etching process toward the second carbon-based filling material portion 248F. Thus, the third layer memory opening 349 may be laterally expanded without expanding any portion of the second layer memory opening 249. The patterned etch mask layer 387 may be removed before or after the at least one isotropic etching process, for example, by performing an ashing process that volatilizes the carbon-based material of the patterned etch mask layer 387.

[0152] refer to Fig. 15C , a selective etching process may be performed to remove the second conductive material portion 248M. For example, the above-described selective etching process may be performed, which selectively etches the conductive material of the second conductive material portion 248M with respect to the materials of the third insulating layer 332 and the third sacrificial material layer 342 and the second carbon-based filling material portion 248F. In general, the second conductive material portion 248M may be selectively removed with respect to the second carbon-based filling material portion 248F.

[0153] refer to Fig.15D , the second carbon-based filling material portion 248F and the first carbon-based filling material portion 148F may be removed, for example, by performing an ashing or selective etching process. Generally speaking, the second carbon-based filling material portion 248F may be removed after the second carbon-based filling material portion 248F is removed. Fig. 15C A remaining portion of the sacrificial first level memory opening fill structure 148 remains after the processing steps.

[0154] refer to Fig.15E , an isotropic etching process may be performed to remove the first dielectric liner 148L and the second dielectric liner 248L. In one embodiment, the first dielectric liner 148L and the second dielectric liner 248L include a silicon oxide material, and the isotropic etching process may include a wet etching process using dilute hydrofluoric acid.

[0155] Inter-layer memory openings 49 (also referred to as memory openings 49) may be formed by removing a remaining portion of a sacrificial first-layer memory opening filling structure 148 beneath a second-layer memory opening 249. Inter-layer support openings (also referred to as support openings) may be formed by removing a portion of a sacrificial first-layer support opening filling structure beneath a second-layer support opening.

[0156] refer to Fig.15F , a layer stack including an optional blocking dielectric layer 52, a charge storage layer 54, a tunneling dielectric layer 56, and a semiconductor channel material layer 60L may be sequentially deposited in the memory opening 49. The blocking dielectric layer 52 may include a single dielectric material layer or a stack of multiple dielectric material layers. In one embodiment, the blocking dielectric layer may include a dielectric metal oxide layer, which is substantially composed of a dielectric metal oxide. As used herein, a dielectric metal oxide refers to a dielectric material including at least one conductive element and at least oxygen. The dielectric metal oxide may be substantially composed of at least one conductive element and oxygen, or may be substantially composed of at least one conductive element, oxygen, and at least one non-conductive element (such as nitrogen). In one embodiment, the blocking dielectric layer 52 may include a dielectric metal oxide having a dielectric constant greater than 7.9 (i.e., having a dielectric constant greater than the dielectric constant of silicon nitride). The thickness of the dielectric metal oxide layer may be in the range of 1nm to 20nm, but smaller and larger thicknesses may also be used. Subsequently, the dielectric metal oxide layer may be used as a dielectric material portion that blocks the stored charge from leaking to the control gate electrode. In one embodiment, the blocking dielectric layer 52 includes aluminum oxide.Alternatively or additionally, the blocking dielectric layer 52 can include a dielectric semiconductor compound such as silicon oxide, silicon oxynitride, silicon nitride, or a combination thereof.

[0157] Subsequently, a charge storage layer 54 may be formed. In one embodiment, the charge storage layer 54 may be a continuous layer or patterned discrete portions of a charge trapping material including a dielectric charge trapping material (e.g., which may be silicon nitride). Alternatively, the charge storage layer 54 may include a continuous layer or patterned discrete portions of a conductive material such as doped polysilicon or a conductive material that is patterned into a plurality of electrically isolated portions (e.g., floating gates), for example, by being formed as a sacrificial material layer (142, 242) within a lateral recess. In one embodiment, the charge storage layer 54 includes a silicon nitride layer. In one embodiment, the sacrificial material layer (142, 242) and the insulating layer (132, 232) may have vertically coinciding sidewalls, and the charge storage layer 54 may be formed as a single continuous layer. As used herein, a first surface and a second surface "vertically coincide" if there is a second surface overlying or underlying the first surface and if there is a vertical plane that intersects both the first surface and the second surface. Alternatively, the sacrificial material layer (142, 242) may be laterally recessed relative to the sidewalls of the insulating layer (132, 232), and a combination of a deposition process and anisotropic etching process may be used to form the charge storage layer 54 as a plurality of vertically spaced memory material portions. The thickness of the charge storage layer 54 may be in the range of 2 nm to 20 nm, although lesser and greater thicknesses may also be used.

[0158] The tunneling dielectric layer 56 includes a dielectric material through which charge tunneling can be performed under suitable electrical bias conditions. Charge tunneling can be performed by hot carrier injection or by Fowler-Nordheim tunneling induced charge transfer, depending on the operating mode of the single three-dimensional NAND string memory device to be formed. The tunneling dielectric layer 56 may include silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxides (such as aluminum oxide and hafnium oxide), dielectric metal oxynitrides, dielectric metal silicates, alloys thereof, and / or combinations thereof. In one embodiment, the tunneling dielectric layer 56 may include a stack of a first silicon oxide layer, a silicon oxynitride layer, and a second silicon oxide layer, which is generally referred to as an ONO stack. In one embodiment, the tunneling dielectric layer 56 may include a substantially carbon-free silicon oxide layer or a substantially carbon-free silicon oxynitride layer. The thickness of the tunneling dielectric layer 56 may be in the range of 2nm to 20nm, but smaller and larger thicknesses may also be employed. The stack of the blocking dielectric layer 52, the charge storage layer 54, and the tunneling dielectric layer 56 constitutes a memory film 50 that stores a memory bit.

[0159] The semiconductor channel material layer 60L includes a semiconductor material, such as at least one element semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the semiconductor channel material layer 60L includes amorphous silicon or polycrystalline silicon. The semiconductor channel material layer 60L can be formed by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD). The thickness of the semiconductor channel material layer 60L can be in the range of 2nm to 10nm, but smaller and larger thicknesses can also be used. The cavity 49' is formed in the volume of each memory opening 49 that is not filled with the deposited material layer (52, 54, 56, 60L).

[0160] refer to Figure 15G , in the case where the cavity 49' in each memory opening is not completely filled with the semiconductor channel material layer 60L, a dielectric core layer can be deposited in the cavity 49' to fill any remaining portion of the cavity 49' within each memory opening. The dielectric core layer includes a dielectric material, such as silicon oxide or organic silicate glass. The dielectric core layer can be deposited by a conformal deposition method (such as low pressure chemical vapor deposition (LPCVD)), or by a self-planarization deposition process (such as spin coating). The horizontal portion of the dielectric core layer overlying the third layer alternating stack (332, 342) can be removed, for example, by recess etching. The recess etching continues until the top surface of the remaining portion of the dielectric core layer is recessed to a height between the top surface of the topmost third insulating layer 332 and the bottom surface of the topmost third insulating layer 332. Each remaining portion of the dielectric core layer constitutes a dielectric core 62.

[0161] A doped semiconductor material may be deposited in a cavity overlying the dielectric core 62. The doped semiconductor material has a doping of a conductivity type opposite to the doping conductivity type of the semiconductor channel material layer 60L. Thus, the doped semiconductor material has a doping of a second conductivity type. Portions of the deposited doped semiconductor material, semiconductor channel material layer 60L, tunneling dielectric layer 56, charge storage layer 54, and blocking dielectric layer 52 overlying a horizontal plane including the top surface of the third layer alternating stack (332, 342) may be removed by a planarization process such as a chemical mechanical planarization (CMP) process.

[0162] Each remaining portion of the doped semiconductor material having the doping of the second conductivity type constitutes a drain region 63. The drain region 63 may have a doping of the second conductivity type opposite to the first conductivity type. For example, if the first conductivity type is p-type, the second conductivity type is n-type, and vice versa. The dopant concentration in the drain region 63 may be in the range of 5.0×1018 / cm3 to 2.0×1021 / cm3, but smaller and larger dopant concentrations may also be used. The doped semiconductor material may be, for example, doped polysilicon.

[0163] Each remaining portion of the semiconductor channel material layer 60L constitutes a vertical semiconductor channel 60, through which current can flow when the vertical NAND device including the vertical semiconductor channel 60 is turned on. The tunneling dielectric layer 56 is surrounded by the charge storage layer 54 and laterally surrounds the vertical semiconductor channel 60. Each group of adjacent blocking dielectric layers 52, charge storage layers 54, and tunneling dielectric layers 56 together constitute a memory film 50, which can store charge for a macroscopic retention time. In some embodiments, the blocking dielectric layer 52 may not be present in the memory film 50 at this step, and the blocking dielectric layer may be subsequently formed after the backside recess is formed. As used herein, the macroscopic retention time refers to a retention time suitable for the operation of a memory device as a permanent memory device, such as a retention time of more than 24 hours.

[0164] Generally speaking, a memory film 50 is formed in each interlayer memory opening 49. The memory film 50 includes a vertical stack of memory elements. For example, the vertical stack of memory elements includes a portion of the memory film 50 located at the level of various spacer material layers (such as various sacrificial material layers (142, 242, 342)). A vertical semiconductor channel 60 is formed inside the memory film 50. A drain region 63 may be formed at the top of the vertical semiconductor channel 60.

[0165] Each combination of the memory film 50 and the vertical semiconductor channel 60 within the memory opening 49 constitutes a memory stack structure. The memory stack structure is a combination of the vertical semiconductor channel 60, the tunneling dielectric layer 56, a plurality of memory elements including portions of the charge storage layer 54, and an optional blocking dielectric layer 52. Each combination of the memory stack structure, the dielectric core 62, and the drain region 63 within the memory opening 49 constitutes a memory opening filling structure 58. Each combination of the memory stack structure, the dielectric core 62, and the drain region 63 within the support opening constitutes a support column structure. In the process, the source level material layer 10', the first layer structure (132, 142, 165), the second layer structure (232, 242, 265), the third layer structure (332, 342, 365), and the memory opening filling structure 58 together constitute a memory level component.

[0166] FIG. 16A to FIG. 16D is a vertical cross-sectional view of first layer memory openings 149 , second layer memory openings 249 , and third layer memory openings 349 in a second configuration of the first exemplary structure during formation of interlayer memory openings 49 and memory opening filling structures 58 according to the first embodiment of the present disclosure.

[0167] refer to Fig.16A , shown in reference Fig.15A A second configuration of the first exemplary structure after the anisotropic etching process is described. In this case, the second carbon-based capping material portion 248C can be etched through by an anisotropic etching process that forms the third layer memory opening 349 and the third layer support opening 329. The second conductive material portion 248M can be used as an etch stop structure for the anisotropic etching process that forms the third layer memory opening 349.

[0168] refer to Fig. 16B , optionally perform a reference Fig. 15B The processing steps are described to laterally expand the third level memory opening 349 and the third level support opening 329. The patterned etch mask layer 387 and the remaining portion of the second carbon-based capping material portion 248C may then be removed, for example, by ashing or selective etching.

[0169] refer to Fig. 16C , executable reference Fig. 15C Processing steps are described to remove the second conductive material portion 248M.

[0170] refer to Fig.15D , executable reference FIG. 15D to FIG. 15G The processing steps are described to form a memory opening fill structure 58 within each memory opening 49 and to form a support post structure within each support opening.

[0171] refer to Fig.17A and Fig. 17B , shows a first exemplary structure after forming a memory opening filling structure 58 in the memory opening 49 and forming a support pillar structure 20 in the support opening 19. While forming the memory opening filling structure 58, each of the support openings 19 is filled with a corresponding support pillar structure 20. Each support pillar structure 20 may have the same structural elements as the memory opening filling structure 58. Each support pillar structure 20 is a dummy structure (i.e., an electrically inactive structure) and therefore is not subsequently in contact with any contact via structure. The drain select level isolation structure 72 may extend laterally through the topmost portion of the third layer of alternating stacks (332, 342) along the first horizontal direction hd1.

[0172] refer to Fig.18A and Fig.18BA contact-level dielectric layer 380 may be formed over the third layer structure (232, 242, 265). The contact-level dielectric layer 380 includes a dielectric material such as silicon oxide and may be formed by a conformal or non-conformal deposition process. For example, the contact-level dielectric layer 380 may include undoped silicate glass and may have a thickness in the range of 100 nm to 600 nm, although smaller and larger thicknesses may also be employed.

[0173] A photoresist layer (not shown) may be applied over the contact level dielectric layer 380 and may be photolithographically patterned to form openings in areas extending across the memory array region 100 and the staircase region 200. The openings in the photoresist layer may extend laterally along the first horizontal direction hd1 between each adjacent cluster of memory opening fill structures 58. The backside trenches 79 may be formed by transferring the pattern in the photoresist layer through the contact level dielectric layer 380, the second alternating stack (232, 242, 265), the first alternating stack (132, 142, 165), and the in-process source level material layer 110'. Portions of the contact level dielectric layer 380, the second alternating stack (232, 242, 265), the first alternating stack (132, 142, 165), and the in-process source level material layer 110' that underlie the openings in the photoresist layer may be removed to form the backside trenches 79. In one embodiment, backside trenches 79 can be formed between clusters of memory opening filling structures 58. The clusters of memory opening filling structures 58 can be laterally spaced apart by the backside trenches 79 along the second horizontal direction hd2.

[0174] In general, at least one vertical alternating sequence of continuous insulating layers (132, 232, 332) and continuous spacer material layers (such as continuous sacrificial material layers (142, 242, 342)) can be divided into alternating stacks {(132, 142), (232, 242), (332, 342)} of insulating layers (132, 232, 332) and spacer material layers (such as sacrificial material layers (142, 242, 342)) by forming backside trenches 79 extending laterally along a first horizontal direction hd1 and spaced laterally along a second horizontal direction hd2. The contact-level dielectric layer 380 is divided into a plurality of contact-level dielectric layers 380 by the backside trenches 380. Each of the contact-level dielectric layers 380 overlies a respective alternating stack of insulating layers ( 132 , 232 , 332 ) and spacer material layers, such as sacrificial material layers ( 142 , 242 , 342 ), and overlies a respective array of memory opening fill structures 58 .

[0175] refer to Fig.19A, a backside trench spacer 74 may be formed on the sidewalls of each backside trench 79. For example, a conformal spacer material layer may be deposited in the backside trench 79 and over the contact-level dielectric layer 380, and may be anisotropically etched to form the backside trench spacers 74. The backside trench spacers 74 include a material different from that of the source-level sacrificial layer 104. For example, the backside trench spacers 74 may include silicon oxide, a dielectric metal oxide, or silicon nitride.

[0176] refer to Fig.19B , an etchant may be introduced into the backside trenches 79 in an isotropic etching process, the etchant selectively etching the material of the source level sacrificial layer 104 to the material of the first alternating stack (132, 142), the second alternating stack (232, 242), the third alternating stack (332, 342), the upper dielectric liner layer 105, and the lower dielectric liner layer 103. For example, if the source level sacrificial layer 104 comprises undoped amorphous silicon or an undoped amorphous silicon germanium alloy, the backside trench spacers 74 comprise silicon nitride, and the upper and lower dielectric liner layers (105, 103) comprise silicon oxide, a wet etching process employing hot trimethyl-2-hydroxyethylammonium hydroxide (“hot TMY”) or tetramethylammonium hydroxide (TMAH) may be employed to selectively remove the source level sacrificial layer 104 to the backside trench spacers 74 and the upper and lower dielectric liner layers (105, 103). Alternatively, if the source level sacrificial material layer 104 comprises silicon nitride, the backside trench spacers 74 comprise silicon oxide or dielectric metal oxide, and the upper and lower dielectric liner layers (105, 103) comprise silicon oxide, a wet etching process (which employs hot phosphoric acid) may be employed to selectively remove the source level sacrificial layer 104 with respect to the backside trench spacers 74 and the upper and lower dielectric liner layers (105, 103). A source cavity 109 is formed in the volume from which the source level sacrificial layer 104 is removed.

[0177] refer to Fig.19C, a series of isotropic etchants (such as wet etchants) may be applied to the physically exposed portions of the memory film 50 through the backside trenches 79 and the source cavity 109 to sequentially etch the various component layers of the memory film 50 from the outside to the inside, and physically expose the bottom surface and cylindrical side surfaces of the vertical semiconductor channel 60 at the level of the source cavity 109. The upper and lower dielectric liner layers (105, 103) may be incidentally etched during the removal of the portion of the memory film 50 positioned at the level of the source cavity 109. The source cavity 109 may be expanded in volume by removing portions of the memory film 50 at the level of the source cavity 109 and the upper and lower dielectric liner layers (105, 103). The top surface of the lower source level material layer 112 and the bottom surface of the upper source level material layer 116 may be physically exposed to the source cavity 109. After removing the physically exposed portion of the memory film 50, the outer sidewall of each vertical semiconductor channel 60 is physically exposed to the source cavity 109. A dielectric material stack 150 is formed under each physically exposed cylindrical surface of the vertical semiconductor channel 60. Each dielectric material stack 150 is a remaining portion of the memory film 50 and includes the same dielectric material stack as the memory film 50.

[0178] Therefore, the upper source level material layer 116 can act as an etch stop during the selective etching of the memory film 50 through the source cavity 109 and can prevent lateral expansion of the source cavity 109. This prevents a short circuit between the source select level conductive layer 118 and a source contact layer that is subsequently formed in the source cavity 109 during a subsequent step.

[0179] refer to Fig.19D , the source contact layer 114 can be formed by a selective deposition process of depositing a doped semiconductor material having a second conductivity type, which is referred to herein as a third doped semiconductor material. The doped semiconductor material may include amorphous silicon, polycrystalline silicon, or a silicon-germanium alloy. The third doped semiconductor material of the source contact layer 114 may grow from a physically exposed semiconductor surface surrounding the source cavity 109. The average atomic concentration of the second conductivity type dopant in the source contact layer 114 may be in the range of 5.0×1019 / cm3 to 2.0×1021 / cm3, although smaller and larger dopant concentrations may also be used.

[0180] In-process source-level material layer 110' is replaced with source-level material layer 10. Source-level material layer 110 includes a layer stack, which includes, from bottom to top, a lower source-level material layer 112, a source contact layer 114, an upper source-level material layer 116, a source-level insulating layer 117, and an optional source-select-level conductive layer 118. The combination of lower source-level material layer 112, source contact layer 114, and upper source-level material layer 116 constitutes a source layer (112, 114, 116). When source-level sacrificial layer 104 is replaced with source contact layer 114, in-process source-level material layer 110' is converted into a source-level material layer 110 including source layers (112, 114, 116).

[0181] refer to Fig.19E , the backside trench spacers 74 may be removed selectively to the semiconductor material of the source contact layer 114. For example, if the backside trench spacers 74 include silicon nitride, a wet etching process using hot phosphoric acid may be used to remove the backside trench spacers 74. If the backside trench spacers 74 include silicon oxide, a wet etching process using dilute hydrofluoric acid may be used to remove the backside trench spacers 74. The sidewalls of the alternating stack (132, 142, 232, 242), the upper source level material layer 116, the source level insulating layer 117, and the optional source select level conductive layer 118 may be physically exposed after removing the backside trench spacers 74.

[0182] A thermal oxidation process may be performed to convert physically exposed surface portions of various semiconductor materials into semiconductor oxide portions. Specifically, physically exposed surface portions of source contact layer 114, upper source level material layer 116, and source select level conductive layer 118 (if present) are converted into thermal semiconductor oxide material portions. As used herein, "thermal semiconductor oxide" refers to a material formed by thermal oxidation of a semiconductor material. Unlike semiconductor oxide materials formed by chemical vapor deposition, thermal semiconductor oxide materials do not include carbon or hydrogen above trace levels unless the semiconductor material from which the semiconductor oxide material is derived includes carbon prior to the thermal oxidation process.

[0183] The thermal oxidation process forms a semiconductor oxide plate 122 at the bottom of each backside trench 79 and forms a semiconductor oxide guide 124 on the sidewalls of the source select level conductive layer 118. The semiconductor oxide plate 122 includes various thermal semiconductor oxide material portions formed by thermal conversion of surface portions of the source contact layer 114 and the upper source level material layer 116.

[0184] The layer stack including the lower source level material layer 112, the source contact layer 114 and the upper source level material layer 116 constitutes a source layer (112, 114, 116), which is a buried source layer used as a common source region that connects each of the vertical semiconductor channels 60 and has a second conductivity type of doping. The average dopant concentration of the buried source layer (112, 114, 116) can be in the range of 5.0×1019 / cm3 to 2.0×1021 / cm3, but smaller and larger dopant concentrations can also be used.

[0185] refer to Fig.19F , an etchant that selectively etches the material of the sacrificial material layer (142, 242, 342) relative to the material of the insulating layer (132, 232, 332), the material of the backward stepped dielectric material portion (165, 265, 365), and the material of the outermost layer of the memory film 50 can be introduced into the backside trench 79, for example, using an isotropic etching process. For example, the sacrificial material layer (142, 242, 342) can include silicon nitride, and the material of the insulating layer (132, 232, 332), the material of the backward stepped dielectric material portion (165, 265, 365), and the material of the outermost layer of the memory film 50 can include silicon oxide material. The first backside recess 143 is formed in the volume from which the first sacrificial material layer 142 is removed. The second backside recess 243 is formed in the volume from which the second sacrificial material layer 242 is removed. The third backside recess 343 is formed in the volume from which the third sacrificial material layer 342 is removed.

[0186] The isotropic etching process may be a wet etching process using a wet etching solution, or may be a vapor phase (dry) etching process in which an etchant is introduced in a vapor phase into the backside trench 79. For example, if the sacrificial material layer (142, 242, 342) includes silicon nitride, the etching process may be a wet etching process in which the first exemplary structure is immersed in a wet etching bath including phosphoric acid, which selectively etches silicon nitride over silicon oxide, silicon, and various other materials used in the art.

[0187] Each of the backside recesses (143, 243, 343) can be a laterally extending cavity having a lateral dimension greater than the vertical extent of the cavity. In other words, the lateral dimension of each of the backside recesses (143, 243, 343) can be greater than the height of the corresponding backside recesses (143, 243, 343). A plurality of first backside recesses 143 can be formed in a volume from which the material of the first sacrificial material layer 142 is removed. A plurality of second backside recesses 243 can be formed in a volume from which the material of the second sacrificial material layer 242 is removed. A plurality of third backside recesses 343 can be formed in a volume from which the material of the third sacrificial material layer 342 is removed. Each of the backside recesses (143, 243, 343) can extend substantially parallel to the top surface of the substrate 8. The backside recess (143, 243, 343) can be vertically defined by the top surface of the underlying insulating layer (132, 232 or 332) and the bottom surface of the overlying insulating layer (132, 232 or 332). In one embodiment, each of the backside recesses (143, 243, 343) can have a uniform height throughout.

[0188] refer to Figure 19G , a backside blocking dielectric layer (not shown) may be optionally deposited in the backside recesses and backside trenches 79 and over the contact-level dielectric layer 380. At least one conductive material may be deposited in the plurality of backside recesses (143, 243, 343), on the sidewalls of the backside trenches 79 and over the contact-level dielectric layer 380. The at least one conductive material may include at least one conductive material, i.e., a conductive material including at least one conductive element.

[0189] refer to Fig.19H , showing that in Figure 19G . A plurality of first conductive layers 146 may be formed in the plurality of first backside recesses 143, a plurality of second conductive layers 246 may be formed in the plurality of second backside recesses 243, a plurality of third conductive layers 346 may be formed in the plurality of third backside recesses 343, and a continuous conductive material layer (not shown) may be formed on the sidewalls of each backside trench 79 and over the contact-level dielectric layer 380. Thus, the sacrificial material layers (142, 242, 342) may be replaced with conductive material layers (146, 246, 346), respectively. Specifically, each first sacrificial material layer 142 may be replaced with an optional portion of a backside blocking dielectric layer and the first conductive layer 146, each second sacrificial material layer 242 may be replaced with an optional portion of a backside blocking dielectric layer and the second conductive layer 246, and each third sacrificial material layer 342 may be replaced with an optional portion of a backside blocking dielectric layer and the third conductive layer 346. A backside cavity exists within the portion of each backside trench 79 that is not filled with the continuous layer of conductive material.

[0190] The conductive material can be deposited by a conformal deposition method, which can be, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), chemical plating, electroplating, or a combination thereof. The conductive material can be an elemental metal, an intermetallic alloy of at least two elemental metals, a conductive nitride of at least one elemental metal, a conductive metal oxide, a conductive doped semiconductor material, a conductive metal semiconductor alloy such as a metal silicide, an alloy thereof, and a combination or stack thereof. Non-limiting exemplary conductive materials that can be deposited in the back side recess include tungsten, tungsten nitride, titanium, titanium nitride, tantalum, tantalum nitride, cobalt, and ruthenium. In one embodiment, the conductive material may include a metal such as tungsten and / or a metal nitride. In one embodiment, the conductive material for filling the back side recess may be a combination of a titanium nitride layer and a tungsten filling material. In one embodiment, the conductive material may be deposited by chemical vapor deposition or atomic layer deposition.

[0191] The deposited conductive material of the continuous conductive material layer may be etched back, for example, by anisotropic or isotropic etching, from the sidewalls of each backside trench 79 and from above the contact-level dielectric layer 380. Each remaining portion of the deposited conductive material in the first backside recess constitutes a first conductive layer 146. Each remaining portion of the deposited conductive material in the second backside recess constitutes a second conductive layer 246. Each conductive layer (146, 246, 346) may be a conductive line structure.

[0192] In one embodiment, a subset of the third conductive layer 346 positioned at the level of the drain select level isolation structure 72 constitutes a drain select gate electrode. A subset of the conductive layers (146, 246, 346) positioned below the drain select gate electrode can be used as a combination of a control gate and a word line positioned at the same level. The control gate electrode within each conductive layer (146, 246, 346) is a control gate electrode for a vertical memory device including a memory stack structure. The source select level conductive layer 118 is used as a source select gate electrode.

[0193] Each memory opening filling structure in the memory opening filling structure 58 (which includes a corresponding memory stacking structure) includes a vertical stack of memory elements at each level of the conductive layer (146, 246, 346). A subset of the conductive layers (146, 246, 346) may include word lines for the memory elements. The semiconductor devices in the peripheral device area 700 below may include word line switch devices that are configured to control bias voltages to corresponding word lines. The memory level component includes all structures located above the topmost surface of the lower level metal interconnect structure 780, and is located above the substrate semiconductor layer 9 and vertically spaced apart from the substrate semiconductor layer. The memory level component includes at least one alternating stack {(132, 146), (232, 246), (332, 346)} and a memory stacking structure that vertically extends through at least one alternating stack {(132, 146), (232, 246), (332, 346)}. Each of at least one alternating stack {(132, 146), (232, 246), (332, 346)} includes alternating layers of a respective insulating layer (132, 232, or 332) and a respective conductive layer (146, 246, or 346). At least one alternating stack {(132, 146), (232, 246), (332, 346)} includes a staircase region including steps in which each underlying conductive layer (146, 246, 346) extends further along a first horizontal direction hd1 than any overlying conductive layer (146, 246, 346) in the memory level assembly.

[0194] An alternating stack {(132, 146), (232, 246), (332, 346)} of insulating layers (132, 232, 332) and conductive layers (146, 246, 346) is formed, the alternating stack being laterally spaced apart from each other along a second horizontal direction hd1 by backside trenches 79. The source layer (112, 114, 116) includes: a lower source level material layer 112, the lower source level material layer including a first doped semiconductor material; an upper source level material layer 116, the upper source level material layer including a second doped semiconductor material; and a source contact layer 114, the source contact layer including a third doped semiconductor material and located between the upper source level material layer 116 and the lower source level material layer 112. In one embodiment, each of the vertical semiconductor channels 60 is in contact with the source contact layer 114. In one embodiment, each of the memory opening filling structures 58 includes a corresponding memory film 50 laterally surrounding a corresponding vertical semiconductor channel 60, having a corresponding annular concave bottom surface contacting the source contact layer 114, and having a corresponding cylindrical outer surface contacting the upper source level material layer 116 and each insulating layer within a corresponding one of the alternating stacks {(132, 146), (232, 246), (332, 346)}.

[0195] refer to Fig. 20A and Fig. 20B , a layer of insulating spacer material such as a silicon oxide layer may be formally deposited in the first subset of backside trenches 79 and over the contact level dielectric layer 380. An anisotropic etching process may be performed to remove horizontally extending portions of the insulating spacer material layer from over the contact level dielectric layer 380 and at the bottom of the first subset of backside trenches 79. In one embodiment, a central portion of the semiconductor oxide plate 122 may be incidentally etched to physically expose a top surface segment of an underlying portion of the source contact layer 114. Each remaining vertically extending tubular portion of the insulating spacer material layer constitutes a backside insulating spacer 74.

[0196] At least one conductive material (such as at least one conductive material) may then be deposited in the cavities in the first subset of backside trenches 79. The at least one conductive material may include at least one conductive barrier material (e.g., a conductive nitride material such as TiN, TaN, and / or WN) and at least one conductive fill material (e.g., W, Cu, Co, Ru, Mo, etc.). Excess portions of the at least one conductive material may be removed from above a horizontal plane including the top surface of the contact-level dielectric layer 380 by a planarization process, which may employ a recess etching process and / or a chemical mechanical polishing process. Each remaining portion of the at least one conductive material constitutes a backside contact via structure 76. Each continuous combination of a backside insulating spacer 74 and a backside contact via structure 76 constitutes a backside trench filling structure (74, 76). Each backside trench 79 within the first subset of backside trenches 79 may be filled with a corresponding backside trench filling structure (74, 76).

[0197] In general, backside trench filling structures (74, 76) may be formed in a second subset of backside trenches 79. Each of the backside trench filling structures (74, 76) includes a respective backside insulating spacer 74 and a respective backside contact via structure 76. In one embodiment, each of the backside contact via structures 76 is formed directly on a respective surface of the source contact layer 114. In one embodiment, each recessed surface segment of the source layer (112, 114, 116) contacted by the respective backside contact via structure 76 is a surface of the source contact layer 114. In one embodiment, each backside contact via structure 76 is laterally surrounded by a respective backside insulating spacer 74 and laterally spaced apart from a respective adjacent pair of alternating stacks {(132, 146), (232, 246), (332, 346)} by the respective backside insulating spacer. Each backside insulating spacer 74 laterally surrounds a respective backside contact via structure 76 therein.

[0198] refer to Fig.21A and Fig. 21B, a via-level dielectric layer 382 may be formed over the contact-level dielectric layer 380. A photoresist layer (not shown) may be applied over the via-level dielectric layer 382 and may be photolithographically patterned to form various contact via openings. For example, an opening for forming a drain contact via structure may be formed through the via-level dielectric layer 382 and the contact-level dielectric layer in the memory array region 100, and an opening for forming a layer contact via structure may be formed through the via-level dielectric layer 382, ​​the contact-level dielectric layer 380, and the backward stepped dielectric material portion (165, 265, 365) in the staircase region 200. An anisotropic etching process is performed to transfer the pattern in the photoresist layer through the via-level dielectric layer 382, ​​the contact-level dielectric layer 380, and the underlying dielectric material portion. The drain region 63 and the conductive layer (146, 246, 346) may be used as an etch stop structure. A drain contact via cavity may be formed over each drain region 63, and a layer contact via cavity may be formed over each conductive layer (146, 246, 346) at a stepped surface underlying the backward stepped dielectric material portion (165, 265, 365). The photoresist layer may then be removed, such as by ashing.

[0199] At least one conductive material may be deposited in the layer contact via cavity and the drain contact via cavity. The at least one conductive material may include at least one conductive material. Excess portions of the at least one conductive material may be removed from above a horizontal plane including the top surface of the via level dielectric layer 382 by a planarization process. The planarization process may employ a recess etching process and / or a chemical mechanical planarization process. The remaining portion of the at least one conductive material in the drain contact via cavity constitutes the drain contact via structure 88. The remaining portion of the at least one conductive material in the layer contact via cavity constitutes the layer contact via structure 86. The layer contact through-hole structure 86 may include: a first contact through-hole structure, which vertically extends through the third backward stepped dielectric material portion 365, the second backward stepped dielectric material portion 265 and the first backward stepped dielectric material portion 165 and contacts a corresponding first conductive layer in the first conductive layer 146; a second contact through-hole structure, which vertically extends through the third backward stepped dielectric material portion 365 and the second backward stepped dielectric material portion 265 and contacts a corresponding second conductive layer in the second conductive layer 246; and a third contact through-hole structure, which vertically extends through the third backward stepped dielectric material portion 365 and contacts a corresponding third conductive layer in the third conductive layer 346.

[0200] An upper level metal interconnect structure (not shown) and an upper level dielectric material layer (not shown) may be formed over the via level dielectric layer 382. For example, the upper level dielectric material layer may include a bit line level dielectric layer (not shown) and an additional dielectric material layer (not shown). The upper level metal interconnect structure may include a bit line and additional metal lines and a via structure (not shown).

[0201] According to a second embodiment of the present disclosure, an etch stop semiconductor material layer and an optional etch stop conductive material layer may be used as at least one etch stop structure during the formation of various openings through the alternating stack of material layers.

[0202] FIG. 22A to FIG. 22D is a vertical cross-sectional view of a first level memory opening 149 during formation of a sacrificial first level memory opening filling structure 148 , a first etch stop semiconductor material layer 180 , and a first etch stop conductive material layer 182 in a first configuration of a second exemplary structure according to a second embodiment of the present disclosure.

[0203] refer to Fig.22A , shows the first configuration of the second exemplary structure after forming the first layer memory opening 149 and the first layer support opening. The first configuration of the second exemplary structure at this processing step can be compared to Figure 5A The first configuration of the first exemplary structure shown is the same.

[0204] refer to Fig. 22B , a first dielectric liner layer 1481 may be formed by performing a conformal deposition process. The first dielectric liner layer 1481 includes a dielectric material such as silicon oxide and may have a thickness in the range of 2 nm to 12 nm, such as 3 nm to 8 nm, although smaller and larger thicknesses may also be employed.

[0205] The first carbon-based filling material layer 1482 may be formed by depositing a first carbon-based filling material in the first layer memory opening 149 and the first layer support opening 129. The first carbon-based filling material contains carbon with an atomic percentage greater than 50%. For example, the first carbon-based filling material may include amorphous carbon, diamond-like carbon, or a doped derivative thereof and / or may be substantially composed of amorphous carbon, diamond-like carbon, or a doped derivative thereof.

[0206] refer to Fig. 22C, portions of the first carbon-based filling material layer 1482 and the first dielectric liner layer 1481 overlying the topmost surface of the first layer alternating stack (132, 142) may be removed by performing a planarization process. The planarization process may employ at least one recess etching process and / or a chemical mechanical polishing process. Each remaining portion of the first carbon-based filling material in the first layer memory opening 149 and the first layer support opening 129 constitutes a first carbon-based filling material portion 148F. Generally speaking, the first carbon-based filling material portion 148F is formed by depositing the first carbon-based filling material in the first layer memory opening 149 and over the first layer alternating stack (132, 142) and by removing portions of the first carbon-based filling material from over the first layer alternating stack (132, 142). Each remaining portion of the first dielectric liner layer 1481 constitutes a first dielectric liner 148L. Each continuous combination of the first dielectric liner 148L and the first carbon-based filling material portion 148F that fills the first layer memory opening 149 constitutes a sacrificial first layer memory opening filling structure 148. Each continuous combination of the first dielectric liner 148L and the first carbon-based filling material portion 148F filling the first-level support opening 129 constitutes a sacrificial first-level memory opening filling structure.

[0207] refer to Fig.22D , a first etch stop semiconductor material layer 180 may be formed over the first layer alternating stack (132, 146) and the sacrificial first layer memory opening filling structure 148. The first etch stop semiconductor material layer 180 includes a semiconductor material such as amorphous silicon, polycrystalline silicon, silicon germanium alloy or doped derivatives thereof. The first etch stop semiconductor material layer 180 may be deposited by a conformal or non-conformal deposition process and may have a thickness in the range of 5 nm to 50 nm, such as 10 nm to 30 nm, although lesser and greater thicknesses may also be employed.

[0208] Subsequently, a first etch stop conductive material layer 182 may be optionally formed over the first etch stop semiconductor material layer 180. The first etch stop conductive material layer 182 includes and / or consists essentially of a transition metal or a conductive metal compound. In one embodiment, the first etch stop conductive material layer 182 may include and / or may consist essentially of a metal such as tungsten, molybdenum, ruthenium, cobalt, another transition metal element or an alloy thereof; or a conductive compound such as a metal silicide or a metal nitride such as titanium silicide, tungsten silicide, cobalt silicide, nickel silicide, titanium nitride, tantalum nitride, molybdenum nitride, tungsten nitride, etc. The thickness of the first etch stop conductive material layer 182 may be in the range of 5 nm to 50 nm, such as 10 nm to 30 nm, but smaller and larger thicknesses may also be used.

[0209] refer to Fig.22EThe second configuration of the second exemplary structure according to the second embodiment of the present disclosure can be obtained by omitting the formation of the first etch stop conductive material layer 182. Fig.22D The first embodiment of the second exemplary structure shown results.

[0210] refer to Fig.23 , executable reference Figure 8 The processing steps are described to form a second layer structure, which includes a second alternating stack of second insulating layers 232 and second sacrificial material layers 242, a second stepped surface, and a second backward stepped dielectric material portion 265. The second layer alternating stack (232, 242) is formed above the first etch stop semiconductor material layer 180. In the case where the first etch stop conductive material layer 182 is present above the first etch stop semiconductor material layer 180 (such as Fig.22D In the case of the first configuration shown in FIG. 1 ), the second layer alternating stack (232, 242) is formed above the first etch stop conductive material layer 182. In the case where the first etch stop conductive material layer 182 does not exist (such as Fig.22E In the case of the first configuration shown), the second layer alternating stack (232, 242) is formed directly on the top surface of the first etch stop semiconductor material layer 180.

[0211] refer to Fig.24 , executable reference Fig. 9A and Fig. 9B The processing steps are described to form a patterned etch mask layer 287 over the second layer alternating stack (232, 242), and to form a second layer memory opening 249 and a second layer support opening 229 under the opening in the patterned etch mask layer 287. The main etch step of the anisotropic etch process for forming the second layer memory opening 249 and the second layer support opening 229 may have an etch chemistry that selectively etches the material of the second insulating layer 232 and the second spacer material layer with respect to at least one material of the first etch stop material layer (180, 182). As discussed above, the patterned etch mask layer 287 may include a carbon-based material that contains greater than 50 atomic percent carbon.

[0212] FIG. 26A to FIG. 26G is a vertical cross-sectional view of the first layer memory opening 149 and the second layer memory opening 249 during the formation of a sacrificial second layer memory opening filling structure 248, a second etch stop semiconductor material layer 280 and a second etch stop conductive material layer 282 in the first configuration of the second exemplary structure according to the second embodiment of the present disclosure.

[0213] refer to Fig.26A , shows that in reference Fig.25The second layer memory opening 249 after the described processing steps. The anisotropic etching process for forming the second layer memory opening 249 and the second layer support opening 229 may include a main etching step having an etching chemistry that selectively etches the material of the second insulating layer 232 and the second spacer material layer 242 to at least one material of the first etch stop material layer (180, 182). In the case where the at least one material of the first etch stop material layer (180, 182) includes a stack of the first etch stop conductive material layer 182 and the first etch stop semiconductor material layer 180, the etching chemistry of the main etching step may be selective to the material of the first etch stop conductive material layer 182 and / or the material of the first etch stop semiconductor material layer 180. In one embodiment, the main etching step of the anisotropic etching process may etch through the first etch stop conductive material layer 182 and may terminate before etching through the first etch stop semiconductor material layer 180. In another embodiment, the main etching step of the anisotropic etching process may terminate when etching the first etch stop conductive material layer 182.

[0214] The terminal etching step of the anisotropic etching process may etch through any unmasked remaining portions of the first etch stop conductive material layer 182 (if present), and etch through the first etch stop semiconductor material layer 180. The etching chemistry of the terminal etching step of the anisotropic etching process may be selective to the material of the first carbon-based fill material portion 148F.

[0215] refer to Fig.26B, a first selective semiconductor deposition process may be performed to grow semiconductor material from the physically exposed cylindrical sidewalls of the first etch stop semiconductor material layer 180 surrounding the bottom portion of the second layer memory opening 249 and the second layer support opening 229. The first selective semiconductor deposition process grows semiconductor material from physically exposed semiconductor surfaces while inhibiting semiconductor material from growing from physically exposed dielectric surfaces (such as the surfaces of the second insulating layer 232, the second sacrificial material layer 242, and the patterned etching mask layer 287). The semiconductor material deposited by the first selective semiconductor deposition process may include amorphous silicon, polycrystalline silicon, silicon germanium alloy, or other semiconductor materials. During the first selective semiconductor deposition process, reactants including precursor gases for the semiconductor material to be deposited and etchant gases may flow simultaneously or alternatively into the process change in which the second exemplary structure is placed. Generally speaking, semiconductor surfaces provide a higher nucleation rate and a higher growth rate for semiconductor materials than dielectric surfaces. In contrast, the etching rate is generally independent of the underlying surface. The flow rates of the reactant gas and the etchant gas may be selected so that the deposition rate on the semiconductor surface is greater than the etching rate on the semiconductor surface, while the deposition rate on the dielectric surface is less than the etching rate. Thus, semiconductor material may grow only from physically exposed semiconductor surfaces of the first etch stop semiconductor layer 180 while inhibiting growth of semiconductor material from surfaces of the second insulating layer 232 , the second sacrificial material layer 242 , and the patterned etch mask layer 287 during selective semiconductor deposition.

[0216] The duration of the first selective semiconductor deposition process is selected so that the top surface of the first carbon-based filling material portion 148F is completely covered with the semiconductor material portion grown by the first selective semiconductor deposition process, which is referred to herein as the first semiconductor plug 211. In one embodiment, each of the first semiconductor plugs 211 may be formed on a corresponding cylindrical sidewall of the first etch stop semiconductor material layer 180 above a corresponding one of the sacrificial first layer memory opening filling structures 148. In general, the first semiconductor plugs 211 may be formed by performing a selective semiconductor material deposition process that grows semiconductor material from the cylindrical sidewall of the first etch stop semiconductor material layer 180 while inhibiting semiconductor material from growing from physically exposed surfaces of the second layer alternating stack (232, 242). The semiconductor material of the first semiconductor plugs 211 may be the same as or different from the semiconductor material of the first etch stop semiconductor material layer 180. In one embodiment, each of the first semiconductor plugs 211 may have a convex top surface having a generally tapered direction that provides a central recess.

[0217] refer to Fig.26C, at least one isotropic etching process may be performed to laterally recess the second spacer material layer (such as the second sacrificial material layer 242) and / or the second insulating layer 232. In one embodiment, the at least one isotropic etching process may include: a first isotropic etching process that laterally recesses the second spacer material layer (such as the second sacrificial material layer 242) around the second layer memory opening 249; and a second isotropic etching process that laterally recesses the second insulating layer 232 around the second layer memory opening 249. For example, if the second insulating layer 232 includes silicon oxide and the second sacrificial material layer 242 includes silicon nitride, the first isotropic etching process may include a wet etching process using a mixture of hot phosphoric acid, and the second isotropic etching process may include a wet etching process using dilute hydrofluoric acid. The first semiconductor plug 211 serves as an etch stop region and blocks the etchant of the isotropic etching process from diffusing toward the first carbon-based filling material portion 148F and blocks the etching of the sacrificial first-layer memory opening filling structure 148 .

[0218] In general, the second-level memory opening 249 may be laterally expanded when the first semiconductor plug 211 covers the sacrificial first-level memory opening filling structure 148. Therefore, the second-level memory opening 249 may be laterally expanded without expanding any portion of the first-level memory opening 149. The patterned etching mask layer 287 may be removed before or after at least one isotropic etching process, for example, by performing an ashing process that volatilizes the carbon-based material of the patterned etching mask layer 287. In one embodiment, the patterned etching mask layer 287 is removed when the first semiconductor plug 211 covers the sacrificial first-level memory opening filling structure 148.

[0219] refer to Fig.26D , a conformal deposition process may be used to form the second dielectric liner layer. The second dielectric liner layer includes a dielectric material such as silicon oxide, and may have a thickness in the range of 2nm to 12nm, such as in the range of 3nm to 8nm, but smaller and larger thicknesses may also be used. An anisotropic etching process may be performed to remove the horizontally extending portion of the second dielectric liner layer. Each remaining portion of the second dielectric liner layer retained in the second layer memory opening 249 or in the second layer support opening 229 constitutes a second dielectric liner 248L. Each second dielectric liner 248L may have a tubular configuration. After forming the second dielectric liner 248L, the top surface of the first semiconductor plug 211 may be physically exposed.

[0220] refer to Fig.26E, an etching process may be performed to selectively remove the first semiconductor plug 211 for the material of the second dielectric liner 248L and the first carbon-based filling material portion 148F. The etching process may include a wet etching process or a dry etching process. For example, a wet etching process using hot trimethyl-2-hydroxyethylammonium hydroxide (“hot TMY”) or tetramethylammonium hydroxide (TMAH) may be performed to remove the amorphous silicon first semiconductor plug 211. Alternatively or additionally, a dry etching process using vapor-phase hydrochloric acid may be performed to remove the first semiconductor plug 211.

[0221] In one embodiment, the etching process that removes the first semiconductor plug 211 may incidentally recess each proximal portion of the first etch stop semiconductor material layer 180 around the bottom portion of the second layer memory opening 249 and the second layer support opening 219 after removing the first semiconductor plug 211. The lateral recess distance of the recessed cylindrical surface of the first etch stop semiconductor material layer 180 as measured from the bottom perimeter of the outer sidewall of the corresponding overlying second dielectric liner 248L may be in the range of 5 nm to 100 nm and / or 10 nm to 50 nm, although smaller and larger lateral recess distances may also be employed.

[0222] refer to Fig.26F , a second carbon-based filling material may be deposited in the unfilled volume of the second layer memory opening 249 and the second layer support opening 229. The second carbon-based filling material contains carbon with an atomic percentage greater than 50%. For example, the second carbon-based filling material may include amorphous carbon, diamond-like carbon, or a doped derivative thereof and / or may be substantially composed of amorphous carbon, diamond-like carbon, or a doped derivative thereof. Excess portions of the second carbon-based filling material may be removed from above the topmost surface of the second alternating stack (232, 242) by performing a planarization process, which may include a recess etching process and / or a chemical mechanical polishing (CMP) process. Each remaining portion of the second carbon-based filling material in the second layer memory opening 249 and the second layer support opening 229 constitutes a second carbon-based filling material portion 248F. Generally speaking, the second carbon-based filling material portion 248F is formed by depositing the second carbon-based filling material in the second layer memory opening 249 and above the second layer alternating stack (232, 242) and by removing at least a portion of the second carbon-based filling material from above the second layer alternating stack (232, 242). The top surface of the second carbon-based fill material portion 248F may be coplanar with the topmost surface of the second alternating stack (232, 242).

[0223] refer to Figure 26G, a second etch stop semiconductor material layer 280 may be formed over the second layer alternating stack (232, 246), the sacrificial second layer memory opening filling structure 248, and the sacrificial second layer support opening filling structure. The second etch stop semiconductor material layer 280 includes a semiconductor material such as amorphous silicon, polycrystalline silicon, silicon germanium alloy, or doped derivatives thereof. The second etch stop semiconductor material layer 280 may be deposited by a conformal or non-conformal deposition process and may have a thickness in the range of 5 nm to 50 nm, such as 20 nm to 30 nm, although lesser and greater thicknesses may also be employed.

[0224] Subsequently, a second etch stop conductive material layer 282 may be optionally formed over the second etch stop semiconductor material layer 280. The second etch stop conductive material layer 282 includes and / or consists essentially of a transition metal or a conductive metal compound. In one embodiment, the first etch stop conductive material layer 182 may include and / or may consist essentially of a metal such as tungsten, molybdenum, ruthenium, cobalt, another transition metal element or an alloy thereof; or a conductive compound such as a metal silicide or a metal nitride such as titanium silicide, tungsten silicide, cobalt silicide, nickel silicide, titanium nitride, tantalum nitride, molybdenum nitride, tungsten nitride, etc. The thickness of the second etch stop conductive material layer 282 may be in the range of 5 nm to 50 nm, such as 10 nm to 30 nm, but smaller and larger thicknesses may also be used.

[0225] refer to Fig.26H The second configuration of the second exemplary structure according to the second embodiment of the present disclosure can be obtained by omitting the formation of the second etch stop conductive material layer 282. Figure 26G The second embodiment of the second exemplary structure shown results.

[0226] refer to Fig. 27 , executable reference Fig.13 and Fig.14 The processing steps are described to form a third alternating stack of third insulating layers 332 and third spacer material layers (such as third sacrificial material layers 342), a third stepped surface, a third backward stepped dielectric material portion 365, a patterned etch mask layer 387, a third layer of memory openings 349 and a third layer of support openings 329.

[0227] refer to Fig.28A , shows that in reference Fig. 27The third layer memory opening 349 after the described processing steps. The anisotropic etching process for forming the third layer memory opening 349 and the third layer support opening 329 may include a main etching step having an etching chemistry that selectively etches the materials of the third insulating layer 332 and the third spacer material layer to at least one material of the second etch stop material layer (280, 282). In the case where the at least one material of the second etch stop material layer (280, 282) includes a stack of a second etch stop conductive material layer 282 and a second etch stop semiconductor material layer 280, the etching chemistry of the main etching step may be selective to the material of the second etch stop conductive material layer 282 and / or the material of the second etch stop semiconductor material layer 280. In one embodiment, the main etching step of the anisotropic etching process may etch through the second etch stop conductive material layer 282 and may terminate before etching through the second etch stop semiconductor material layer 280. In another embodiment, the main etching step of the anisotropic etching process may terminate when etching the second etch stop conductive material layer 282.

[0228] The terminal etching step of the anisotropic etching process may etch through any unmasked remaining portions of the second etch stop conductive material layer 282 (if present), and etch through the second etch stop semiconductor material layer 280. The etching chemistry of the terminal etching step of the anisotropic etching process may be selective to the material of the second carbon-based fill material portion 248F.

[0229] refer to Fig.28B , a second selective semiconductor deposition process may be performed to grow semiconductor material from the physically exposed cylindrical sidewalls of the second etch stop semiconductor material layer 280 surrounding the bottom portion of the third layer memory opening 349 and the third layer support opening 329. The second selective semiconductor deposition process grows semiconductor material from the physically exposed semiconductor surface while suppressing the growth of semiconductor material from physically exposed dielectric surfaces (such as the surface of the third insulating layer 332, the third sacrificial material layer 342, and the patterned etching mask layer 387). The semiconductor material deposited by the second selective semiconductor deposition process may include amorphous silicon, polycrystalline silicon, silicon germanium alloy, or other semiconductor materials. The second selective semiconductor deposition process may adopt the same type of process as the first selective semiconductor deposition process. The semiconductor material may grow only from the physically exposed semiconductor surface of the second etch stop semiconductor layer 280, while suppressing the growth of semiconductor material from the surface of the third insulating layer 332, the third sacrificial material layer 342, and the patterned etching mask layer 387 during the selective semiconductor deposition.

[0230] The duration of the second selective semiconductor deposition process is selected so that the top surface of the second carbon-based filling material portion 248F is completely covered with the semiconductor material portion grown by the second selective semiconductor deposition process, which is referred to herein as the second semiconductor plug 311. In one embodiment, each of the second semiconductor plugs 311 may be formed on a corresponding cylindrical sidewall of the second etch stop semiconductor material layer 280 above a corresponding one of the sacrificial second layer memory opening filling structures 248. In general, the second semiconductor plugs 311 may be formed by performing a selective semiconductor material deposition process that grows semiconductor material from the cylindrical sidewall of the second etch stop semiconductor material layer 280 while inhibiting semiconductor material from growing from the physically exposed surface of the third layer alternating stack (332, 342). The semiconductor material of the second semiconductor plugs 311 may be the same as or different from the semiconductor material of the second etch stop semiconductor material layer 282. Each second semiconductor plug 311 may have a convex top surface having a generally tapered direction that provides a central recess.

[0231] refer to Fig.28C , at least one isotropic etching process may be performed to laterally recess the third spacer material layer (such as the third sacrificial material layer 342) and / or the third insulating layer 332. In one embodiment, the at least one isotropic etching process may include: a second isotropic etching process that laterally recesses the third spacer material layer (such as the third sacrificial material layer 342) around the third layer memory opening 349; and a third isotropic etching process that laterally recesses the third insulating layer 332 around the third layer memory opening 349. For example, if the third insulating layer 332 includes silicon oxide and the third sacrificial material layer 342 includes silicon nitride, the second isotropic etching process may include a wet etching process using hot phosphoric acid, and the third isotropic etching process may include a wet etching process using dilute hydrofluoric acid. The second semiconductor plug 311 blocks the etchant of the isotropic etching process from diffusing toward the second carbon-based filling material portion 248F and blocks the etching of the sacrificial second layer memory opening filling structure 248.

[0232] In general, the third-level memory opening 349 may be laterally expanded when the second semiconductor plug 311 covers the sacrificial second-level memory opening filling structure 248. Therefore, the third-level memory opening 349 may be laterally expanded without expanding any portion of the second-level memory opening 249. The patterned etching mask layer 387 may be removed before or after at least one isotropic etching process, for example, by performing an ashing process that volatilizes the carbon-based material of the patterned etching mask layer 387. In one embodiment, the patterned etching mask layer 387 is removed when the second semiconductor plug 311 covers the sacrificial second-level memory opening filling structure 248.

[0233] refer to Fig.28D , a conformal deposition process may be used to form the third dielectric liner layer. The third dielectric liner layer includes a dielectric material such as silicon oxide, and may have a thickness in the range of 3nm to 22nm, such as in the range of 3nm to 8nm, but smaller and larger thicknesses may also be used. An anisotropic etching process may be performed to remove the horizontally extending portion of the third dielectric liner layer. Each remaining portion of the third dielectric liner layer retained in the third layer memory opening 349 or the third layer support opening 329 constitutes a third dielectric liner 348L. Each third dielectric liner 348L may have a tubular configuration. After forming the third dielectric liner 348L, the top surface of the second semiconductor plug 311 may be physically exposed.

[0234] refer to Fig.28E , an etching process may be performed to selectively remove the second semiconductor plug 311 for the material of the third dielectric liner 348L and the second carbon-based filling material portion 248F. The etching process may include a wet etching process or a dry etching process. For example, a wet etching process using hot trimethyl-2-hydroxyethylammonium hydroxide (“hot TMY”) or tetramethylammonium hydroxide (TMAH) may be performed to remove the amorphous silicon second semiconductor plug 311. Alternatively or additionally, a dry etching process using vapor phase hydrochloric acid may be performed to remove the second semiconductor plug 311.

[0235] In one embodiment, the etching process for removing the second semiconductor plug 311 may incidentally recess each proximal portion of the second etch stop semiconductor material layer 280 around the bottom portion of the third layer memory opening 349 and the third layer support opening 319 after removing the second semiconductor plug 311. The lateral recess distance of the recessed cylindrical surface of the second etch stop semiconductor material layer 280 as measured from the bottom perimeter of the outer sidewall of the corresponding overlying third dielectric liner 348L may be in the range of 5 nm to 200 nm and / or 20 nm to 50 nm, although smaller and larger lateral recess distances may also be employed.

[0236] refer to Fig.28FThe second carbon-based filling material portion 248F and the first carbon-based filling material portion 148F may be removed, for example, by performing an ashing process. Generally, the remaining portion of the sacrificial first-level memory opening filling structure 148 may be removed after removing the second carbon-based filling material portion 248F.

[0237] refer to Figure 28G , an isotropic etching process may then be performed to remove the first dielectric liner 148L, the second dielectric liner 248L, and the third dielectric liner 348L. In one embodiment, the first dielectric liner 148L, the second dielectric liner 248L, and the third dielectric liner 348L include a silicon oxide material, and the isotropic etching process may include a wet etching process using dilute hydrofluoric acid.

[0238] Inter-layer memory openings 49 (also referred to as memory openings 49) may be formed by removing remaining portions of sacrificial first and second layer memory opening filling structures (148, 248) beneath third layer memory openings 349. Inter-layer support openings (also referred to as support openings) may be formed by removing portions of sacrificial first and second layer support opening filling structures beneath third layer support openings.

[0239] refer to Fig.28H , executable reference Fig.15F and Figure 15G The processing steps are described to form a memory opening filling structure 59 in each inter-level memory opening 49 and to form a support pillar structure 20 in each inter-level support opening 19. Each memory opening filling structure 58 includes a vertical semiconductor channel 60 and a vertical stack of memory elements.

[0240] Fig.28I is a vertical cross-sectional view of a second configuration of the second exemplary structure after forming an interlayer memory opening 49 and a memory opening filling structure 58 according to a second embodiment of the present disclosure. The second configuration of the second exemplary structure can be obtained from the first configuration of the second exemplary structure by omitting the formation of an etch stop conductive material layer (182, 282) and by omitting steps during the formation of second layer openings (249, 219) and third layer openings (349, 319) for etching unmasked portions of the etch stop conductive material layer (182, 282).

[0241] refer to Fig.29A and Fig.29B as well as Fig. 30A and Fig. 30B , respectively, show the execution of reference Fig.18A and Fig.18B , FIG. 19A to FIG. 19H , Fig. 20A and Fig. 20B as well as Fig.21A and Fig. 21B First and second configurations of the second exemplary structure after additional processing steps are described. Generally speaking, each of the etch stop semiconductor material layers ( 180 , 280 ) can be in direct contact with a corresponding surface segment of the outer sidewall of the memory film 50 .

[0242] exist Fig.29A and Fig. 30A In the configuration shown, the backside blocking dielectric layer 44 may be formed before forming the conductive layer (146, 246, 346) in the backside recess (143, 243, 343). In this case, the etch stop semiconductor material layer (180, 280) may be electrically isolated from each of the conductive layers (146, 246, 346). For example, for each memory opening filling structure 58, the bottom-most second conductive layer 246 of the second conductive layer 246 may be electrically isolated from the first etch stop semiconductor material layer 180 by the backside blocking dielectric layer 44 contacting the sidewalls of the memory opening filling structure 58. Similarly, the bottom-most third conductive layer 346 of the third conductive layer 346 may be electrically isolated from the second etch stop semiconductor material layer 280 by another backside blocking dielectric layer 44 contacting the sidewalls of the memory opening filling structure 58.

[0243] exist Fig.29B In the configuration shown, no backside blocking dielectric layer is used. Fig.29B If an etch stop conductive material layer (182, 282) is present, the etch stop conductive material layer (182, 282) may contact the bottom surface of a corresponding one of the conductive layers (246, 346). For example, the top surface of the first etch stop conductive material layer 182 may be in direct contact with the bottom surface of the bottom-most second conductive layer 246, and the top surface of the second etch stop conductive material layer 282 may be in direct contact with the bottom surface of the bottom-most third conductive layer 346. In addition, the first etch stop conductive material layer 182 may be electrically connected to the bottom-most second conductive layer 246, and the second etch stop conductive material layer 282 may be electrically connected to the bottom-most third conductive layer 346.

[0244] exist Fig. 30BIn the configuration shown, an etch stop conductive layer and a backside blocking dielectric layer are not used. In this case, the etch stop semiconductor material layer (180, 280) can contact the bottom surface of a corresponding one of the conductive layers (246, 346). For example, the top surface of the first etch stop semiconductor material layer 180 can be in direct contact with the bottom surface of the bottom-most second conductive layer 246, and the top surface of the second etch stop semiconductor material layer 280 can be in direct contact with the bottom surface of the bottom-most third conductive layer 346. In addition, the first etch stop semiconductor material layer 180 can be electrically connected to the bottom-most second conductive layer 246, and the second etch stop semiconductor material layer 280 can be electrically connected to the bottom-most third conductive layer 346.

[0245] Common Reference Figures 1A to 4B and FIG. 22A to FIG. 30B And according to the second embodiment, a memory device is provided, which includes: a first layer alternating stack (132, 146) of a first insulating layer 132 and a first conductive layer 146; an etch stop semiconductor material layer 180, which is located above the first layer alternating stack (132, 146); a second layer alternating stack (232, 246) of a second insulating layer 232 and a second conductive layer 246, which is overlying the etch stop semiconductor material layer 180; an interlayer memory opening 49, which vertically extends through the second layer alternating stack (232, 246), the etch stop semiconductor material layer 180 and the first layer alternating stack (132, 146); and a memory opening filling structure 58, which is located in the interlayer memory opening 49 and includes a vertical semiconductor channel 60 and a vertical stack of memory elements.

[0246] In one embodiment, the memory opening filling structure 58 includes a memory film 50 that extends vertically and continuously from at least the bottommost layer within the first layer alternating stack (132, 146) to the topmost layer within the second layer alternating stack (232, 246); and the vertical stack of memory elements includes a portion of the memory film 50 at the level of the first conductive layer 146 and the second conductive layer 246. In one embodiment, the etch stop semiconductor material layer 180 is in direct contact with a surface segment of the outer sidewall of the memory film 50.

[0247] In one embodiment, the etch stop semiconductor material layer 180 is electrically connected to the bottom-most second conductive layer 246 of the conductive layers. In one embodiment, the top surface of the etch stop semiconductor material layer 180 is in direct contact with the bottom surface of the bottom-most second conductive layer 246. In one embodiment, the memory device includes an etch stop conductive material layer 182 that is in direct contact with the top surface of the etch stop semiconductor material layer 180 and with the bottom surface of the bottom-most second conductive layer 246.

[0248] In one embodiment, the etch stop semiconductor material layer 180 is electrically isolated from each of the second conductive layers 246 .

[0249] In one embodiment, the bottom-most second conductive layer 246 of the second conductive layer 246 is electrically isolated from the etch stop semiconductor material layer 180 by the backside blocking dielectric layer 44 that contacts the sidewalls of the memory opening filling structure 58. In one embodiment, the etch stop semiconductor material layer 180 contacts the bottom surface of the backside blocking dielectric layer 44. In one embodiment, the memory device includes an etch stop conductive material layer 182 that is in direct contact with the top surface of the etch stop semiconductor material layer 180 and with the bottom surface of the backside blocking dielectric layer 44.

[0250] In one embodiment, second conductive layer 246 consists essentially of at least one conductive material. In one embodiment, an interface between memory opening filling structure 58 and etch stop semiconductor material layer 180 is laterally offset from a vertical axis VA passing through a geometric center GC of memory opening filling structure 58 more than an interface between memory opening filling structure 58 and a bottommost one of second insulating layers 232 is laterally offset from vertical axis VA.

[0251] Although embodiments are described using a three-layer structure, embodiments are expressly contemplated herein in which only a two-layer structure or a four-layer or more-layer structure is used to form a three-dimensional memory device.

[0252] Various embodiments of the present disclosure can be used to provide a reliable etch stop structure that can be used as an etch barrier during an isotropic etching process that can be used to widen the topmost memory opening and the topmost support opening. Thus, each layer level opening can be expanded laterally only once, and repeated widening of lower level openings can be avoided, and the lateral size and vertical profile of the memory opening can be controlled to achieve optimal performance of the memory stack structure.

[0253] Although specific embodiments are mentioned above, it should be understood that the present disclosure is not limited thereto. It will be appreciated by those of ordinary skill in the art that various modifications may be made to the disclosed embodiments, and such modifications are intended to fall within the scope of the present disclosure. Compatibility is assumed in all embodiments that are not alternatives to each other. Unless otherwise expressly stated, the words "comprising" or "including" contemplate all embodiments in which the words "consisting essentially of..." or the words "consisting of..." replace the words "comprising" or "including". Embodiments using specific structures and / or configurations are shown in the present disclosure, and it should be understood that the present disclosure can be practiced with any other compatible structures and / or configurations that are functionally equivalent, provided that such substitutions are not explicitly prohibited or otherwise considered impossible by those of ordinary skill in the art. All publications, patent applications, and patents cited herein are incorporated herein by reference in their entirety.

Claims

1. A method of forming a memory device, the method comprising: forming a first layer alternating stack of first insulating layers and first spacer material layers over a substrate, wherein the first spacer material layer is formed as a first conductive layer or is subsequently replaced with the first conductive layer; forming a first layer memory opening through the first layer alternating stack; forming a sacrificial first-level memory opening filling structure in the first-level memory opening, the sacrificial first-level memory opening filling structure comprising a stack of a first carbon-based filling material portion and a first conductive material portion; forming a second layer alternating stack of a second insulating layer and a second layer of a spacer material over the first layer alternating stack, wherein the second layer of spacer material is formed as a second conductive layer or is subsequently replaced with the second conductive layer; forming a second layer memory opening through the second layer alternating stack by performing an anisotropic etching process having an etching chemistry that etches the material of the second insulating layer and the second spacer material layer selective to the material of the first conductive material portion; removing the first conductive material portion selectively to the first carbon-based filler material portion; forming an inter-level memory opening by removing a remaining portion of the sacrificial first-level memory opening filling structure below the second-level memory opening; as well as A memory opening filling structure is formed in the inter-level memory opening, wherein the memory opening filling structure includes a vertical stack of memory elements and a vertical semiconductor channel.

2. The method of claim 1 , further comprising performing an isotropic etching process after performing the anisotropic etching process and before removing the first conductive material portion, the isotropic etching process laterally recessing the second spacer material layer around the second layer memory opening.

3. The method according to claim 1, further comprising: forming a patterned etch mask layer over the second layer alternating stack, wherein the second layer memory openings are formed below the openings in the patterned etch mask layer; as well as The patterned etch mask layer is removed prior to removing the first conductive material portion.

4. The method according to claim 3, wherein: The patterned etch mask layer includes a carbon-based material containing at least 50 atomic percent carbon atoms; and The patterned etching mask layer is removed by performing an ashing process to volatilize the carbon-based material. The method of claim 1 , wherein the first conductive material comprises a transition metal or a conductive metal compound.

6. The method of claim 5, wherein the first conductive material portion is formed at least by: depositing a layer of the first conductive material over the first carbon-based filler material portion; and A portion of the layer of the first conductive material is removed from above a horizontal plane including a top surface of the alternating stack of the first layers by performing a planarization process. 7 . The method of claim 1 , further comprising thinning the first conductive material portion by performing a recess etching process that etches the first conductive material selective to a material of the first insulating layer. 8 . The method of claim 7 , further comprising forming a carbon-based capping material portion on the top surface of the thinned first conductive material portion by depositing and recessing a carbon-based capping material containing greater than 50 atomic percent carbon.

9. The method of claim 8, wherein the carbon-based capping material portion is etched by the anisotropic etching process.

10. The method of claim 1, wherein the first carbon-based fill material portion is formed by depositing a carbon-based fill material in the first layer memory opening and over the first layer alternating stack and by removing at least a portion of the carbon-based fill material from over the first layer alternating stack.

11. The method of claim 1, wherein the carbon-based filler material of the first carbon-based filler material portion comprises greater than 50 atomic percent carbon.

12. The method of claim 1, wherein: The sacrificial first-level memory opening filling structure further includes a dielectric liner formed on a sidewall of the first-level memory opening; and The stack of the first carbon-based filler material portion and the first conductive material portion is formed on the interior and inner sidewalls of the dielectric liner.

13. The method according to claim 1, further comprising: After selectively removing the first conductive material portion with respect to the first carbon-based fill material portion, forming a sacrificial second-level memory opening filling structure including a stack of a second carbon-based fill material portion and a second conductive material portion in an upper portion of the first-level memory opening and in the second-level memory opening; forming a third alternating stack of a third insulating layer and a third spacer material layer over the second alternating stack of layers; as well as A third layer memory opening is formed through the third layer alternating stack by performing an additional anisotropic etching process having an etching chemistry that etches the material of the third insulating layer and the third spacer material layer selective to the material of the second conductive material portion.

14. The method according to claim 13, further comprising: performing an additional isotropic etching process after performing the additional anisotropic etching process, the additional isotropic etching process laterally recessing the third spacer material layer around the third level memory opening; removing the second conductive material portion selectively to the second carbon-based filler material portion after performing the additional isotropic etching process; as well as The second carbon-based fill material portion is removed, wherein the remaining portion of the sacrificial first level memory opening filling structure is removed after removing the second carbon-based fill material portion.

15. The method of claim 13, wherein: All of the third insulating layers except the bottom third insulating layer include a first silicon oxide material; The bottom third insulating layer includes a second silicon oxide material having a higher etching rate in dilute hydrofluoric acid than the first silicon oxide material; All of the third spacer material layers except the bottommost third spacer material layer include a first silicon nitride material; and The bottommost third spacer material layer includes a second silicon nitride material having a higher etch rate in phosphoric acid than the first silicon nitride material.

16. The method of claim 1, wherein: The first spacer material layer includes a first sacrificial material layer that is replaced with the first conductive layer after forming the memory opening filling structure; and The second spacer material layer includes a second sacrificial material layer that is replaced with the second conductive layer after forming the memory opening filling structure.

17. The method according to claim 1, further comprising: forming a layer stack, the layer stack comprising a lower source level semiconductor layer, a source level sacrificial layer, and an upper source level semiconductor layer, wherein the first layer alternating stack is formed above the layer stack, and the first layer memory opening extends vertically through the upper source level semiconductor layer and into the source level sacrificial layer; forming a source cavity by removing the source level sacrificial layer; as well as A source contact layer is formed in the source cavity and on the sidewalls of the vertical semiconductor channel.

18. The method according to claim 1, further comprising: forming a memory film in the inter-layer memory opening, wherein the vertical stack of memory elements includes a portion of the memory film at the level of the first spacer material layer and the second spacer material layer, and wherein the vertical semiconductor channel is formed inside the memory film; as well as A drain region is formed at a top end of the vertical semiconductor channel.

19. The method according to claim 1, further comprising: forming a first stepped surface by patterning an alternating stack of the first layers, wherein the lateral extent of the first spacer material layers decreases with vertical distance from the substrate; forming a first backward stepped dielectric material portion on the first stepped surface; forming a second stepped surface by patterning the second layers in an alternating stack, wherein the lateral extent of the second spacer material layers decreases with the vertical distance from the substrate; and A second backward stepped dielectric material portion is formed on the second stepped surface.

20. The method according to claim 19, further comprising: forming a first contact via structure on a corresponding one of the first conductive layers, passing through the second backward stepped dielectric material portion and the first backward stepped dielectric material portion; as well as A second contact via structure is formed on a corresponding one of the second conductive layers through the second backward stepped dielectric material portion.

21. A memory device, comprising: The first insulating layer and the first conductive layer are alternately stacked; an etch stop semiconductor material layer, the etch stop semiconductor material layer being located above the alternating stack of the first layers; a second insulating layer and a second conductive layer alternately stacked, the second alternately stacked layers overlying the etch stop semiconductor material layer; an inter-layer memory opening extending vertically through the second layer alternating stack, the etch stop semiconductor material layer, and the first layer alternating stack; and A memory opening filling structure is located in the inter-layer memory opening and includes a vertical semiconductor channel and a vertical stack of memory elements.

22. The memory device of claim 21, wherein: The memory opening filling structure includes a memory film that extends vertically and continuously from at least a bottommost layer within the first layer alternating stack to a topmost layer within the second layer alternating stack; and The vertical stack of memory elements includes portions of the memory film at the level of the first and second conductive layers.

23. The memory device of claim 22, wherein the etch stop semiconductor material layer is in direct contact with a surface segment of an outer sidewall of the memory film. 24 . The memory device of claim 22 , wherein the etch stop semiconductor material layer is electrically connected to a bottommost second conductive layer of the second conductive layers.

25. The memory device of claim 24, wherein a top surface of the etch stop semiconductor material layer is in direct contact with a bottom surface of the bottommost second conductive layer. 26 . The memory device of claim 24 , further comprising an etch stop conductive material layer directly contacting a top surface of the etch stop semiconductor material layer and a bottom surface of the bottommost second conductive layer.

27. The memory device of claim 22, wherein the etch stop semiconductor material layer is electrically isolated from each of the second conductive layers.

28. The memory device of claim 21, wherein a bottommost one of the second conductive layers is electrically isolated from the etch stop semiconductor material layer by a backside blocking dielectric layer contacting a sidewall of the memory opening filling structure.

29. The memory device of claim 28, wherein the etch stop semiconductor material layer contacts a bottom surface of the backside blocking dielectric layer.

30. The memory device of claim 28, further comprising an etch stop conductive material layer directly contacting a top surface of the etch stop semiconductor material layer and a bottom surface of the backside blocking dielectric layer.

31. The memory device of claim 21, wherein the conductive material layer comprises a metal layer or a conductive metal compound.

32. A memory device according to claim 21, wherein the interface between the memory opening filling structure and the etch stop semiconductor material layer is laterally offset from a vertical axis passing through a geometric center of the memory opening filling structure further than the interface between the memory opening filling structure and a bottommost second insulating layer in the second insulating layer is laterally offset from the vertical axis.

33. A method of forming a memory device, the method comprising: forming a first layer alternating stack of first insulating layers and first spacer material layers over the substrate, wherein the first spacer material layers are formed as or subsequently replaced with the first conductive layer; forming a first layer memory opening through the first layer alternating stack; forming a sacrificial first-layer memory opening filling structure within the first-layer memory opening; forming an etch stop semiconductor material layer over the first layer alternating stack and the sacrificial first layer memory opening fill structure; forming an alternating stack of a second insulating layer and a second spacer material layer over the etch stop semiconductor material layer, wherein the second spacer material layer is formed as a second conductive layer or is subsequently replaced with a second conductive layer; forming a second layer memory opening through the second layer alternating stack and through the etch stop semiconductor material layer; forming a semiconductor plug on a cylindrical sidewall of the etch stop semiconductor material layer above the sacrificial first level memory opening filling structure; laterally expanding the second-level memory opening when the semiconductor plug covers the sacrificial first-level memory opening filling structure; forming an inter-layer memory opening by removing the semiconductor plug and the sacrificial first-layer memory opening filling structure; as well as A memory opening filling structure is formed in the inter-level memory opening, wherein the memory opening filling structure includes a vertical semiconductor channel and a vertical stack of memory elements.

34. The method of claim 33, further comprising forming a patterned etch mask layer over the second layer alternating stack, wherein the second layer memory openings are formed below openings in the patterned etch mask layer.

35. The method of claim 34, wherein: The patterned etch mask layer comprises a carbon-based material comprising greater than 50 atomic percent carbon; and The patterned etching mask layer is removed by performing an ashing process.

36. The method of claim 34, wherein the patterned etch mask layer is removed when the semiconductor plug covers the sacrificial first level memory opening filling structure.

37. The method of claim 36, wherein: The sacrificial first level memory opening fill structure includes a carbon-based first level fill material portion including greater than 50 atomic percent carbon; and The carbon-based first layer filling material portion is removed by performing an ashing process after removing the semiconductor plug.

38. A method according to claim 33, wherein the semiconductor plug is formed by performing a selective semiconductor material deposition process, which grows semiconductor material from the cylindrical sidewalls of the etch stop semiconductor material layer while inhibiting the growth of the semiconductor material from the physically exposed surface of the second layer alternating stack.

39. The method of claim 33, further comprising laterally recessing a proximal portion of the etch stop semiconductor material layer around a bottom portion of the second level memory opening after removing the semiconductor plug.

40. The method of claim 33, further comprising forming an etch stop conductive material layer over the etch stop semiconductor material layer, wherein: The second layers are alternately stacked and formed above the etching stop conductive material layer; and The second level memory opening is formed through the etch stop conductive material layer.

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