Intelligent separation microsystem preparation method

Abstract

The application provides a micro-system preparation method of intelligent separation, which injects ions or irradiates laser to form a damage layer at different depths of a wafer of a transfer board in advance, and then separates the wafer at the damage layer by annealing or chemical method after the transfer board process is completed. The application can separate one wafer into three pieces for use, improves the utilization efficiency of the wafer, and reduces the production cost; since the wafer is finally divided into three pieces, the substrate need not be thinned to realize the miniaturization of the overall package, and the process flow is simplified. Meanwhile, the process procedures such as cavity digging of the transfer board and TSV all use thick wafers, and the wafers can provide process mechanical support without temporary bonding, so that the process difficulty and complexity are reduced; since two transfer boards are processed on one side, processes such as TSV etching, passivation layer deposition and via metal filling can be combined together through reasonable design. Compared with the single-piece separate processing mode, the process flow is simplified, and the process uniformity is improved.

Description

Technical Field

[0001] This invention relates to the field of electrical component technology, and more specifically to a method for preparing an intelligently separated microsystem. Background Technology

[0002] With the rapid development of technologies such as the Internet, cloud computing, and artificial intelligence, electronic systems face challenges from massive and diverse data volumes and increasingly complex transmission environments. Size and power consumption have become significant bottlenecks restricting the development of electronic systems. Therefore, it is urgent to change the traditional discrete, stand-alone model of electronic systems and achieve high-performance, small-size, intelligent, and multifunctional integrated electronic systems. Three-dimensional heterogeneous integrated microsystems utilize silicon-based microelectromechanical systems (MEMS) and through-silicon via (TSV) technologies to integrate chips of different materials and functions in a three-dimensional space, thereby forming multifunctional, miniaturized, and low-power electronic systems.

[0003] Currently, 3D heterogeneous integrated microsystems mainly employ a multi-layer silicon interposer board stacking method. The fabrication process involves processing each silicon interposer board individually, then embedding or surface-mounting functional chips within the interposer boards, and finally achieving 3D stacking through wafer-level bonding or module bonding. This current fabrication method has the following problems:

[0004] (1) In order to ensure the overall package size and reduce power consumption, each silicon interposer layer needs to be thinned to 100-200μm during processing. The thickness of a complete silicon wafer is 500-800μm, and most of the silicon is removed after polishing, which reduces the utilization efficiency of the wafer;

[0005] (2) In order to provide mechanical support for the thinned wafer, it is usually necessary to develop an ultra-thin wafer holding technology solution. Currently, the most common method is to temporarily bond the wafer to the carrier. The temporary bonding of the wafer to the carrier and the cleaning of the wafer surface after separation increase the difficulty and complexity of the process;

[0006] (3) The processing of each adapter board is separate. For example, the processes such as TSV etching, passivation layer deposition and through-hole metal filling cannot be combined, which increases the process steps and production costs. Summary of the Invention

[0007] This invention addresses the issues of low wafer utilization and complex fabrication processes in microsystems by providing an intelligent separation method for microsystem fabrication. The method involves pre-forming damage layers by implanting ions or irradiating with a laser at different depths on a transition plate wafer. Then, processes such as cavity removal and TSV (Transient Vapor Deposition) are performed on the entire transition plate wafer. After completing the transition plate process, annealing or chemical methods are used to separate the wafer at the damage layer. This method divides the wafer into multiple parts, and some processes can be completed in one step, thus overcoming the drawbacks of low wafer utilization, complex processes, and high costs in traditional microsystem fabrication.

[0008] This invention provides a method for preparing an intelligent separation microsystem, comprising the following steps:

[0009] S1. A first damage layer and a second damage layer are formed in a double-sided polished silicon wafer by ion implantation or laser irradiation. The first damage layer is located above the second damage layer. The first damage layer and the second damage layer divide the silicon wafer into a transition plate A, a transition plate B and a transition plate C from top to bottom.

[0010] S2. With one side of the interposer plate A in the silicon wafer facing upward, a first TSV via, a first cavity, and a second TSV via located below the first cavity and between the first damage layer are prepared in the interposer plate A.

[0011] S3. With one side of the interposer plate C in the silicon wafer facing upward, a second cavity is prepared in the interposer plate C. The number of second cavities is at least two. A third cavity is prepared on the surface of the interposer plate B through a portion of the second cavity. A third TSV via is prepared in the interposer plate B through another portion of the second cavity. Then, a fourth TSV via is prepared in the interposer plate C.

[0012] S4. Annealing or wet etching a silicon wafer to generate bubbles or micro / nano structures in the first and second damaged layers to obtain independent adapter plates A, B, and C, with the second cavity being a through-hole; embedding a chip in the first cavity and interconnecting the chip with adapter plate A to obtain adapter plate A assembly; surface-mounting a chip on the surface of adapter plate B and interconnecting it with external signals via gold wire to obtain adapter plate B assembly; then performing wafer-level bonding, slicing, bonding with capping layer, and interconnection with PCB to obtain a microsystem, thus completing a method for fabricating an intelligently separated microsystem.

[0013] In the preferred embodiment of the intelligent separation microsystem fabrication method described in this invention, the thickness of the silicon wafer in step S1 is 500 μm to 800 μm.

[0014] The distance from the first damage layer to the upper surface of the silicon wafer is 100μm to 200μm, the distance from the second damage layer to the upper surface of the silicon wafer is 200μm to 300μm, and the thickness of both the first and second damage layers is 20μm to 30μm.

[0015] The method for preparing a smart separation microsystem according to the present invention, in a preferred embodiment, includes step S2 as follows:

[0016] S21. With one side of the interposer plate A in the silicon wafer facing upward, perform photolithography and etching on the interposer plate A to obtain a through hole, deposit a passivation layer on the sidewall of the through hole, fill the through hole with metal, and expose the metal by chemical mechanical polishing or metal etching to obtain the first TSV through hole.

[0017] S22. A first cavity is obtained by photolithography and etching on the surface of the adapter plate A. The depth of the first cavity is less than the thickness of the adapter plate A. After removing the photoresist and cleaning, a passivation layer is deposited on the sidewall and bottom of the first cavity.

[0018] S23. Photolithography is performed on the surface of the adapter plate A to etch a through hole at the bottom of the first cavity and deposit a passivation layer on the sidewall of the through hole. The through hole is filled with metal, and the metal at the bottom of the first cavity is exposed by metal etching to obtain the second TSV through hole.

[0019] In the preferred embodiment of the intelligent separation microsystem fabrication method described in this invention, the etching methods in steps S21 and S23 include: reactive ion etching and inductively coupled plasma etching; both the first TSV via and the second TSV via are filled with Cu metal, and the etching depth reaches the first damage layer.

[0020] In step S22, the method for etching to obtain the first cavity is any one of the following: RIE, ICP, or wet etching, and the etching depth is half of the adapter plate A.

[0021] The method for preparing an intelligent separation microsystem according to the present invention, in a preferred embodiment, includes the following steps in step S3:

[0022] S31. With one side of the silicon wafer's adapter plate C facing upwards, photolithography and etching are performed in the adapter plate C to obtain a second cavity. The etching is stopped at the interface between the second damage layer and the adapter plate B. The number of second cavities is at least two. After removing the photoresist, the wafer is cleaned.

[0023] S32. Photolithography is performed on the surface of the adapter plate C. A third cavity is obtained by etching on the surface of the adapter plate B through a window left in part of the second cavity. The depth of the third cavity is less than the thickness of the adapter plate B. The photoresist is removed, and after cleaning, a passivation layer is deposited on the sidewalls and bottom of the third cavity and the sidewalls of the second cavity.

[0024] S33. Photolithography is performed on the surface of the adapter plate C. Through the window reserved in another part of the second cavity, a through hole is etched in the adapter plate B. The etching stops at the first damage layer. After removing the photoresist and cleaning, a passivation layer is deposited on the sidewall of the through hole, metal is filled in the through hole, and the metal at the bottom of the second cavity is exposed to obtain the third TSV through hole.

[0025] S34. Photolithography is performed on the surface of the adapter plate C, and through holes that stop at the second damage layer are etched in the adapter plate C. The photoresist is removed, and a passivation layer is deposited on the sidewall of the through hole. The through hole is filled with metal, and the bottom metal Cu of the cavity is exposed to obtain the fourth TSV through hole.

[0026] In a preferred embodiment of the intelligent separation microsystem fabrication method described in this invention, when the thickness of the adapter plate C and the thickness of the adapter plate B are the same, steps S33 and S34 can be combined to simultaneously fabricate a third TSV through-hole and a fourth TSV through-hole. The third TSV through-hole and the fourth TSV through-hole can be identical TSVs. After filling with metal, the metal is exposed using a metal etching method.

[0027] In the preferred embodiment of the intelligent separation microsystem fabrication method described in this invention, in steps S31 and S32, the etching methods for the second cavity and the third cavity are RIE, ICP, or wet etching, and the depth of the third cavity is one-third of the thickness of the adapter plate B.

[0028] In steps S33 and S34, the etching method for the through holes is either RIE or ICP; both are filled with Cu metal. In step S33, the Cu metal at the bottom of the cavity is exposed using a metal etching method, and in step S34, the Cu metal at the bottom of the cavity is exposed using a CMP or metal etching method.

[0029] The method for preparing an intelligent separation microsystem according to the present invention, in a preferred embodiment, includes the following steps in step S4:

[0030] S41. Annealing or wet etching the silicon wafer to generate bubbles or micro / nano structures in the first and second damage layers to obtain independent adapter plates A, B and C, with the second cavity being a through hole.

[0031] S42. A chip is embedded in the first cavity of the adapter board A, and the chip and the surface of the adapter board A are interconnected by RDL to obtain the adapter board A assembly; a chip is surface-mounted on the surface of the adapter board B and interconnected with the outside world by gold wire to obtain the adapter board B assembly; the adapter board A assembly, the adapter board B assembly and the adapter board C are wafer-level bonded to perform heterogeneous integration and signal interconnection to obtain a hybrid module;

[0032] S43. The hybrid module is cut into bare chips. The adapter board C in the bare chip is bonded to the capping layer. Balls are implanted at the bottom of the adapter board A component in the bare chip to obtain a BGA. The microsystem is obtained by interconnecting the BGA with the PCB. A method for preparing an intelligently separated microsystem is completed.

[0033] In a preferred embodiment of the intelligent separation microsystem preparation method of the present invention, when the first damaged layer and the second damaged layer are obtained by ion implantation in step S1, the independent adapter plate A, adapter plate B and adapter plate C are obtained by annealing at a temperature between 300°C and 600°C in step S41 to generate bubbles in the first damaged layer and the second damaged layer.

[0034] When the first and second damage layers are obtained by laser irradiation in step S1, in step S41, micro-nano structures are obtained by wet etching chemical method to generate micro-nano structures in the first and second damage layers to obtain independent adapter plates A, B and C. The etching solution for wet etching includes: potassium hydroxide solution, tetramethylammonium hydroxide solution, hydrofluoric acid solution, and a mixed solution of hydrofluoric acid and concentrated nitric acid.

[0035] In a preferred embodiment of the intelligent separation microsystem fabrication method of the present invention, in step S42, the number of first cavities is at least two, and chips C1 and C2 are embedded in the first cavities, such that the surface of the adapter plate B without the third cavity faces upward and chip C3 is surface-mounted.

[0036] During wafer-level bonding, the adapter plate A assembly is located at the bottom with the surface of the first cavity facing upwards, the adapter plate B assembly is bonded to the upper part of the adapter plate A assembly with the first cavity communicating with the third cavity, and the adapter plate C is bonded to the upper part of the adapter plate B assembly.

[0037] This invention proposes a microsystem fabrication process based on intelligent separation technology. By pre-implanting ions or irradiating with lasers at different depths of the interposer wafer to form a damage layer, and then using annealing or chemical methods to separate the wafer at the damage layer after the interposer process is completed, the wafer can be separated at the damage layer, thereby improving wafer utilization efficiency, simplifying the process and reducing production costs.

[0038] The present invention has the following advantages:

[0039] (1) The present invention can separate one wafer into three wafers for use, thereby improving the utilization efficiency of the wafer and reducing the production cost;

[0040] (2) Since the wafer is ultimately divided into three parts, miniaturization of the overall package can be achieved without substrate thinning, simplifying the process flow. At the same time, processes such as interposer cavity cutting and TSV use thick wafers, which can provide process mechanical support for the wafer without temporary bonding, thus reducing the process difficulty and complexity;

[0041] (3) Since the two adapter boards are processed on one side, processes such as TSV etching, passivation layer deposition, and through-hole metal filling can be combined into one process through reasonable design. Compared with the method of processing each board separately, the process flow is simplified and the process uniformity is improved. Attached Figure Description

[0042] Figure 1 This is a schematic diagram of step S1, ion implantation or laser irradiation, in a method for preparing a smart separation microsystem.

[0043] Figure 2 This is a schematic diagram of step S21 in a method for preparing an intelligent separation microsystem.

[0044] Figure 3 This is a schematic diagram of step S22 in a method for preparing an intelligent separation microsystem.

[0045] Figure 4 This is a schematic diagram of step S23 in a method for preparing an intelligent separation microsystem.

[0046] Figure 5 This is a schematic diagram of step S31 in a method for preparing an intelligent separation microsystem.

[0047] Figure 6 This is a schematic diagram of step S32 in a method for preparing an intelligent separation microsystem.

[0048] Figure 7 This is a schematic diagram of step S33 in a method for preparing an intelligent separation microsystem.

[0049] Figure 8 This is a schematic diagram of step S34 in a method for preparing an intelligent separation microsystem.

[0050] Figure 9 This is a schematic diagram of step S41 in a method for preparing an intelligent separation microsystem.

[0051] Figure 10 This is a schematic diagram of step S42 in a method for preparing an intelligent separation microsystem.

[0052] Figure 11 This is a schematic diagram of step S43 in a method for preparing an intelligent separation microsystem.

[0053] Figure label:

[0054] 1. Silicon wafer; 21. First damaged layer; 22. Second damaged layer; 31. First TSV via; 32. Second TSV via; 33. Third TSV via; 41. First cavity; 42. Second cavity; 43. Third cavity; 5. RDL; 6. Gold wire; 7. Capping layer; 8. BGA. Detailed Implementation

[0055] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0056] Example 1

[0057] like Figures 1-11 As shown, a method for preparing an intelligent separation microsystem includes the following steps:

[0058] (1) A first damage layer 21 and a second damage layer 22 are formed in a double-sided polished silicon wafer 1 with a thickness of 500μm to 800μm by implanting H ions, He ions, or H / He ions co-implanting. The two damage layers divide the silicon wafer into three parts: a transition plate A, a transition plate B, and a transition plate C. The implantation depth is controllable by changing parameters such as ion implantation dose and current density. The surface is tilted at 5° to 10° during implantation to reduce the channel effect. The implantation depth is 200μm to 300μm and 100μm to 200μm from the upper surface of the wafer, respectively. The width of the first damage layer 21 and the second damage layer 22 is between 20μm and 30μm.

[0059] (2) Fabrication of adapter plate A:

[0060] (21) With the A side of the adapter plate facing upwards, photolithography is performed. Reactive ion etching (RIE) or inductively coupled plasma etching (ICP) is used to etch through-holes in the adapter plate A, with the etching depth being the same as the first damaged layer 21. The photoresist is removed, the plate is cleaned, and then a passivation layer (TSV liner) is deposited on the sidewall of the through-hole. The through-hole is filled with metal, and finally, chemical mechanical polishing (CMP) or metal etching is used to expose the Cu metal, forming the first TSV through-hole 31.

[0061] (22) Photolithography is performed on the surface of the adapter plate A processed in step (21). The first cavity 41 is etched using RIE, ICP, or wet etching, with an etching depth of half that of the adapter plate A. The photoresist is removed, the surface is cleaned, and a passivation layer is deposited on the sidewalls and bottom of the cavity.

[0062] (23) Photolithography is performed on the surface of the adapter plate A processed in step (22). A through hole is etched at the bottom of the first cavity 41 of the adapter plate A using RIE or ICP, and the etching stops at the first damage layer 21. The photoresist is removed, the surface is cleaned, and then a passivation layer is deposited on the sidewall of the through hole. The through hole is filled with metal, and finally the metal Cu at the bottom of the cavity is exposed by metal etching to form the second TSV through hole 32.

[0063] (3) Fabrication of adapter plate B and adapter plate C:

[0064] (31) With the C-side of the wafer adapter plate processed in step (2) facing upwards, perform photolithography and etch the second cavity 42 using RIE, ICP, or wet etching, stopping at the interface between the second damaged layer 22 and the adapter plate B. Remove the photoresist and clean.

[0065] (32) Photolithography is performed on the surface of the adapter plate C processed in step (31). A third cavity 43 is etched into the surface of the adapter plate B through the window left in the second cavity 42 in the adapter plate C using RIE, ICP, or wet etching. The etching depth is approximately one-third of the adapter plate's depth. The photoresist is removed, the surface is cleaned, and a passivation layer is deposited on the sidewalls and bottom of the third cavity 43 and on the sidewalls of the second cavity 42.

[0066] (33) Photolithography is performed on the surface of the adapter plate C processed in step (32). RIE or ICP is used to etch a through hole in the adapter plate B through the window reserved in the second cavity 42 in the adapter plate C, and the etching stops at the first damage layer 21. The photoresist is removed and the plate is cleaned. Then, a passivation layer is deposited on the sidewall of the through hole, the through hole is filled with metal, and finally, the bottom metal Cu of the cavity is exposed by metal etching to form the third TSV through hole 33.

[0067] (34) Photolithography is performed on the surface of the adapter plate C processed in step (33). Through holes are etched in the adapter plate C using RIE or ICP, and the etching stops at the second damage layer 22. The photoresist is removed and the plate is cleaned. Then, a passivation layer is deposited on the sidewall of the through hole, and the through hole is filled with metal. Finally, the bottom metal Cu of the cavity is exposed by CMP or metal etching to form the fourth TSV through hole 34.

[0068] Preferably, if the thickness of the adapter plate C and the adapter plate B is the same, steps (7) and (8) can be combined into one step, that is, TSV through hole 33 and TSV through hole 34 are etched at the same time; through holes 33 and 34 can be completely identical TSVs, and finally, metal etching is used together to expose Cu, so as to simplify the process and reduce costs.

[0069] (4) Intelligent separation and stacking:

[0070] (41) Anneal the wafer processed in step (3) at a temperature between 300°C and 600°C. The implanted ions diffuse under heat and generate bubbles in the first damage layer 21 and the second damage layer 22, thereby separating the three parts of the wafer to form independent adapter plate A, adapter plate B and adapter plate C.

[0071] (42) Chips C1 and C2 are embedded in the first cavity 41 of adapter board A, and the chips and the surface RDL 5 of adapter board A are interconnected for signals. Chip C3 is surface-mounted on the surface of adapter board B, and gold wire 6 is used to interconnect the chip with the external signal. Adapter board A, adapter board B and adapter board C are wafer-level bonded to realize heterogeneous chip integration and signal interconnection.

[0072] (43) The hybrid module processed in step (42) is cut into single dies and bonded to the capping layer 7. Bottom ball 8 is used to realize the interconnection between the module and the PCB, thereby realizing a four-layer three-dimensional heterogeneous integrated microsystem.

[0073] Example 2

[0074] like Figures 1-11 As shown, a method for preparing an intelligent separation microsystem includes the following steps:

[0075] (1) A first damage layer 21 and a second damage layer 22 are formed in a double-sided polished silicon wafer 1 with a thickness of 500μm to 800μm by laser irradiation. The two damage layers divide the silicon wafer into three parts: a transition plate A, a transition plate B, and a transition plate C. By changing parameters such as laser frequency and irradiation time, the thickness and depth of the damage layers can be controlled. The depths of the two damage layers from the upper surface of the wafer are 200μm to 300μm and 100μm to 200μm, respectively, and the widths of the first damage layer 21 and the second damage layer 22 are between 20μm and 30μm.

[0076] (2) Fabrication of adapter plate A:

[0077] (21) With the A side of the adapter plate facing upwards, photolithography is performed. Reactive ion etching (RIE) or inductively coupled plasma etching (ICP) is used to etch through-holes in the adapter plate A, with the etching depth being the same as the first damaged layer 21. The photoresist is removed, the plate is cleaned, and then a passivation layer (TSV liner) is deposited on the sidewall of the through-hole. The through-hole is filled with metal, and finally, chemical mechanical polishing (CMP) or metal etching is used to expose the Cu metal, forming the first TSV through-hole 31.

[0078] (22) Photolithography is performed on the surface of the adapter plate A processed in step (21). The first cavity 41 is etched using RIE, ICP, or wet etching, with an etching depth of half that of the adapter plate A. The photoresist is removed, the surface is cleaned, and a passivation layer is deposited on the sidewalls and bottom of the cavity.

[0079] (23) Photolithography is performed on the surface of the adapter plate A processed in step (22). A through hole is etched at the bottom of the first cavity 41 of the adapter plate A using RIE or ICP, and the etching stops at the first damage layer 21. The photoresist is removed, the surface is cleaned, and then a passivation layer is deposited on the sidewall of the through hole. The through hole is filled with metal, and finally the metal Cu at the bottom of the cavity is exposed by metal etching to form the second TSV through hole 32.

[0080] (3) Fabrication of adapter plate B and adapter plate C:

[0081] (31) With the C-side of the wafer adapter plate processed in step (2) facing upwards, perform photolithography and etch the second cavity 42 using RIE, ICP, or wet etching, stopping at the interface between the second damaged layer 22 and the adapter plate B. Remove the photoresist and clean.

[0082] (32) Photolithography is performed on the surface of the adapter plate C processed in step (31). A third cavity 43 is etched into the surface of the adapter plate B through the window left in the second cavity 42 in the adapter plate C using RIE, ICP, or wet etching. The etching depth is approximately one-third of the adapter plate's depth. The photoresist is removed, the surface is cleaned, and a passivation layer is deposited on the sidewalls and bottom of the third cavity 43 and on the sidewalls of the second cavity 42.

[0083] (33) Photolithography is performed on the surface of the adapter plate C processed in step (32). RIE or ICP is used to etch a through hole in the adapter plate B through the window reserved in the second cavity 42 in the adapter plate C, and the etching stops at the first damage layer 21. The photoresist is removed and the plate is cleaned. Then, a passivation layer is deposited on the sidewall of the through hole, the through hole is filled with metal, and finally, the bottom metal Cu of the cavity is exposed by metal etching to form the third TSV through hole 33.

[0084] (34) Photolithography is performed on the surface of the adapter plate C processed in step (33). Through holes are etched in the adapter plate C using RIE or ICP, and the etching stops at the second damage layer 22. The photoresist is removed and the plate is cleaned. Then, a passivation layer is deposited on the sidewall of the through hole, and the through hole is filled with metal. Finally, the bottom metal Cu of the cavity is exposed by CMP or metal etching to form the fourth TSV through hole 34.

[0085] Preferably, if the thickness of the adapter plate C and the adapter plate B is the same, steps (7) and (8) can be combined into one step, that is, TSV through hole 33 and TSV through hole 34 are etched at the same time; through holes 33 and 34 can be completely identical TSVs, and finally, metal etching is used together to expose Cu, so as to simplify the process and reduce costs.

[0086] (4) Intelligent separation and stacking:

[0087] (41) The modified region (i.e., the first damage layer 21 and the second damage layer 22) of the wafer processed in step (3) is selectively removed by the corresponding chemical method, thereby separating the three parts of the wafer to form independent transition plate A, transition plate B and transition plate C. The chemical method is wet etching, which uses a solution to react and remove the exposed part of the silicon surface to obtain the micro-nano structure. The etching solution includes: potassium hydroxide solution, tetramethylammonium hydroxide solution, hydrofluoric acid solution and a mixed solution of hydrofluoric acid and concentrated nitric acid.

[0088] (42) Chips C1 and C2 are embedded in the first cavity 41 of adapter board A, and the chips and the surface RDL 5 of adapter board A are interconnected for signals. Chip C3 is surface-mounted on the surface of adapter board B, and gold wire 6 is used to interconnect the chip with the external signal. Adapter board A, adapter board B and adapter board C are wafer-level bonded to realize heterogeneous chip integration and signal interconnection.

[0089] (43) The hybrid module processed in step (42) is cut into single dies and bonded to the capping layer 7. Bottom ball 8 is used to realize the interconnection between the module and the PCB, thereby realizing a four-layer three-dimensional heterogeneous integrated microsystem.

[0090] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A method for preparing an intelligent separation microsystem, characterized in that: Includes the following steps: S1. A first damage layer (21) and a second damage layer (22) are formed in a double-sided polished silicon wafer (1) by ion implantation or laser irradiation. The first damage layer (21) is located above the second damage layer (22). The first damage layer (21) and the second damage layer (22) divide the silicon wafer (1) into a transition plate A, a transition plate B and a transition plate C from top to bottom. S2. With the adapter plate A side of the silicon wafer (1) facing upward, a first TSV via (31), a first cavity (41), and a second TSV via (32) located below the first cavity (41) and between the first damage layer (21) are prepared in the adapter plate A. S3. With one side of the adapter plate C in the silicon wafer (1) facing upward, a second cavity (42) is prepared in the adapter plate C. The number of the second cavities (42) is at least two. A third cavity (43) is prepared on the surface of the adapter plate B through a portion of the second cavity (42). A third TSV through-hole (33) is prepared in the adapter plate B through another portion of the second cavity (42). Then, a fourth TSV through-hole (34) is prepared in the adapter plate C. S4. Annealing or wet etching the silicon wafer (1) to generate bubbles or micro / nano structures in the first damaged layer (21) and the second damaged layer (22) to obtain independent adapter plates A, B and C. The second cavity (42) is a through hole. A chip is embedded in the first cavity (41) and interconnected with the adapter plate A to obtain the adapter plate A assembly. A chip is surface-mounted on the surface of the adapter plate B and interconnected with external signals through gold wire to obtain the adapter plate B assembly. Then, the adapter plate A assembly, the adapter plate B assembly and the adapter plate C are wafer-level bonded, sliced, bonded with the capping layer (7) and interconnected with the PCB to obtain the microsystem. A method for preparing an intelligently separated microsystem is completed.

2. The method for preparing an intelligent separation microsystem according to claim 1, characterized in that: In step S1, the thickness of the silicon wafer (1) is 500μm to 800μm, the distance from the first damage layer (21) to the upper surface of the silicon wafer (1) is 100μm to 200μm, the distance from the second damage layer (22) to the upper surface of the silicon wafer (1) is 200μm to 300μm, and the thickness of both the first damage layer (21) and the second damage layer (22) is 20μm to 30μm.

3. The method for preparing an intelligent separation microsystem according to claim 1, characterized in that: Step S2 includes: S21. With the adapter plate A in the silicon wafer (1) facing upward, perform photolithography and etching on the adapter plate A to obtain a through hole, deposit a passivation layer on the sidewall of the through hole, fill the through hole with metal, and expose the metal by chemical mechanical polishing or metal etching to obtain the first TSV through hole (31). S22. The first cavity (41) is obtained by photolithography and etching on the surface of the adapter plate A. The depth of the first cavity (41) is less than the thickness of the adapter plate A. After removing the photoresist and cleaning, a passivation layer is deposited on the sidewall and bottom of the first cavity (41). S23. Photolithography is performed on the surface of the adapter plate A to etch a through hole at the bottom of the first cavity (41) and deposit a passivation layer on the sidewall of the through hole. The through hole is filled with metal, and the metal at the bottom of the first cavity (41) is exposed by metal etching to obtain the second TSV through hole (32).

4. The method for preparing an intelligent separation microsystem according to claim 3, characterized in that: In steps S21 and S23, the etching methods include reactive ion etching and inductively coupled plasma etching; the first TSV via (31) and the second TSV via (32) are filled with Cu metal and the etching depth reaches the first damage layer (21). In step S22, the method for etching the first cavity (41) is any one of the following: RIE, ICP or wet etching, and the etching depth is half of the adapter plate A.

5. The method for preparing an intelligent separation microsystem according to claim 1, characterized in that: Step S3 includes the following steps: S31. With the adapter plate C side of the silicon wafer (1) facing upward, the second cavity (42) is obtained by photolithography and etching in the adapter plate C. The etching is stopped at the interface between the second damage layer (22) and the adapter plate B. The number of the second cavity (42) is at least two. After removing the photoresist, the wafer is cleaned. S32. Photolithography is performed on the surface of the adapter plate C. The third cavity (43) is obtained by etching through a window left in a portion of the second cavity (42) on the surface of the adapter plate B. The depth of the third cavity (43) is less than the thickness of the adapter plate B. The photoresist is removed and cleaned. After cleaning, a passivation layer is deposited on the sidewall and bottom of the third cavity (43) and the sidewall of the second cavity (42). S33. Photolithography is performed on the surface of the adapter plate C. Through the window reserved in another part of the second cavity (42), a through hole is etched in the adapter plate B. The etching stops at the first damage layer (21). After removing the photoresist and cleaning, a passivation layer is deposited on the sidewall of the through hole, metal is filled in the through hole, and the metal at the bottom of the second cavity (42) is exposed to obtain the third TSV through hole (33). S34. Photolithography is performed on the surface of the adapter plate C, and a through hole is etched in the adapter plate C to the second damage layer (22). The photoresist is removed, and a passivation layer is deposited on the sidewall of the through hole. The through hole is filled with metal, and the bottom metal Cu of the cavity is exposed to obtain the fourth TSV through hole (34).

6. The method for preparing an intelligent separation microsystem according to claim 5, characterized in that: When the thickness of the adapter plate C is the same as the thickness of the adapter plate B, steps S33 and S34 can be combined together to simultaneously prepare the third TSV through hole (33) and the fourth TSV through hole (34); the third TSV through hole (33) and the fourth TSV through hole (34) can be completely identical TSVs, and after filling with metal, the metal is exposed by metal etching.

7. The method for preparing an intelligent separation microsystem according to claim 5, characterized in that: In steps S31 and S32, the etching methods for the second cavity (42) and the third cavity (43) are RIE, ICP or wet etching, and the depth of the third cavity (43) is one-third of the thickness of the adapter plate B. In steps S33 and S34, the etching method for the through holes is either RIE or ICP; both are filled with Cu metal. In step S33, the Cu metal at the bottom of the cavity is exposed using a metal etching method, and in step S34, the Cu metal at the bottom of the cavity is exposed using a CMP or metal etching method.

8. The method for preparing an intelligent separation microsystem according to claim 1, characterized in that: Step S4 includes the following steps: S41. Annealing or wet etching the silicon wafer (1) to generate bubbles or micro / nano structures in the first damage layer (21) and the second damage layer (22) to obtain independent adapter plates A, B and C, wherein the second cavity (42) is a through hole. S42. A chip is embedded in the first cavity (41) in the adapter plate A, and the chip and the surface of the adapter plate A are interconnected by RDL (5) to obtain the adapter plate A assembly; a chip is surface-mounted on the surface of the adapter plate B and interconnected with the outside signal by gold wire (6) to obtain the adapter plate B assembly; the adapter plate A assembly, the adapter plate B assembly and the adapter plate C are wafer-level bonded to perform heterogeneous integration and signal interconnection to obtain a hybrid module; S43. The hybrid module is cut into bare chips. The adapter board C in the bare chip is bonded to the cover layer (7). The bottom of the adapter board A component in the bare chip is planted with balls to obtain BGA (8). The microsystem is obtained by interconnecting the BGA (8) with the PCB. A method for preparing an intelligently separated microsystem is completed.

9. The method for preparing an intelligent separation microsystem according to claim 8, characterized in that: When the first damaged layer (21) and the second damaged layer (22) are obtained by ion implantation in step S1, in step S41, bubbles are generated in the first damaged layer (21) and the second damaged layer (22) by annealing at a temperature between 300°C and 600°C to obtain independent adapter plates A, B and C. When the first damaged layer (21) and the second damaged layer (22) are obtained by laser irradiation in step S1, in step S41, micro-nano structures are obtained by wet etching chemical method to generate micro-nano structures in the first damaged layer (21) and the second damaged layer (22) to obtain independent adapter plates A, B and C. The etching solution for wet etching includes: potassium hydroxide solution, tetramethylammonium hydroxide solution, hydrofluoric acid solution, and a mixed solution of hydrofluoric acid and concentrated nitric acid.

10. The method for preparing an intelligent separation microsystem according to claim 8, characterized in that: In step S42, the number of the first cavity (41) is at least two, and chips C1 and C2 are embedded in the first cavity (41), so that the surface of the adapter board B without the third cavity (43) faces upward and chip C3 is surface-mounted. During wafer-level bonding, the adapter plate A assembly is located at the bottom with the surface of the first cavity (41) facing upwards, the adapter plate B assembly is bonded to the upper part of the adapter plate A assembly and the first cavity (41) communicates with the third cavity (43), and the adapter plate C is bonded to the upper part of the adapter plate B assembly.

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