A full-silicon vertical leadless package structure and a preparation method thereof

Abstract

A full-silicon vertical leadless packaging structure and a preparation method thereof, comprising a sensor chip, the sensor chip is connected to a ceramic substrate through a high-doped silicon vertical conductive structure, a conductive pin is connected to the ceramic substrate, the conductive pin is electrically connected to the doped silicon vertical conductive structure, and an alloy shell is connected to the outside of the sensor chip, the high-doped silicon vertical conductive structure and the ceramic substrate; the sensor chip adopts an SOI silicon wafer, and the high-doped silicon vertical conductive structure adopts a P-type high-doped low-resistivity silicon wafer; the full-silicon packaging structure without metal or conductive solder can be realized, the packaging structure is suitable for application in an ultrahigh-temperature environment, has the advantages of simple manufacturing process, stable electrical connection, low cost and the like, and is easy to mass produce.

Description

Technical Field

[0001] The present invention belongs to the technical field of sensor packaging, and in particular relates to an all-silicon vertical leadless packaging structure and a preparation method thereof. Background Art

[0002] In the field of high-temperature pressure measurement, the packaging structure has a significant impact on sensor performance, stability, and service life. Currently, two packaging structures are mostly used in high-temperature environments, both domestically and internationally: oil-filled packaging to protect gold wire leads, and leadless packaging with conductive solder added to through-glass vias after silicon-glass bonding. Because silicone oil has a certain thermal expansion coefficient, the oil-filled packaging method with gold wire leads will experience significant volume expansion in temperatures exceeding 200°C, leading to liquid leakage, damage to the packaging structure, failure of the sensor's electrical connections, and reduced sensor service life. Furthermore, the oil-filled packaging process is complex and has high production costs, limiting its mass production.

[0003] The traditional leadless packaging structure ([1] Li Junlong, Zhu Ping, Design of leadless packaged SOI piezoresistive pressure sensor [J]. Instrument Technology and Sensor, 2017(12):20-24; [2] Xu Jiao, Zhao Chenxi, Yang Jian, et al., Research on leadless packaging of high-temperature pressure sensor [J]. Telemetry and Remote Control, 2023, 44(6):126-131; [3] Dong Zhichao, Lei Cheng, Liang Ting, et al., Research on leadless flip-chip packaging of SOI high-temperature pressure sensor [J]. Sensors and Microsystems, 2021, 40(11):65-68.) uses a method of bonding silicon wafer to glass substrate. The airtightness of the package is achieved by a through-hole in the glass substrate, which is filled with conductive solder for electrical connection. However, due to the inconsistent thermal expansion coefficients of the silicon wafer and glass over a wide temperature range, when the ambient temperature changes from high to low, residual thermal stress will be generated at the bonding interface. Over time, cracks will form on the interface, destroying the cavity structure and seriously affecting the service life of the sensor. At the same time, the filling of the conductive solder is directly related to the effectiveness and stability of the sensor's electrical connection. Therefore, when filling the conductive solder into the through-hole in the glass, the material, quality and uniformity of the conductive solder must be strictly selected, which increases the complexity of the package. Therefore, simplifying the packaging process while ensuring the stability of the electrical connection at ultra-high temperatures is a key technical difficulty that needs to be overcome in the high-temperature sensor packaging structure. Summary of the Invention

[0004] In order to overcome the shortcomings of the above-mentioned prior art, the purpose of the present invention is to provide an all-silicon vertical leadless packaging structure and a preparation method thereof, which can realize a fully siliconized packaging structure without the participation of metal or conductive solder, is suitable for application in ultra-high temperature environments, has the advantages of simple manufacturing process, stable electrical connection, low cost, and is easy to mass produce.

[0005] In order to achieve the above object, the technical solution of the present invention is as follows:

[0006] An all-silicon vertical leadless packaging structure includes a sensor chip 1, which is connected to a ceramic substrate 3 via a highly doped silicon vertical conductive structure 2. The ceramic substrate 3 is connected to a conductive pin 4, which is electrically connected to the doped silicon vertical conductive structure 2. An alloy shell 5 is connected to the outside of the sensor chip 1, the highly doped silicon vertical conductive structure 2, and the ceramic substrate 3.

[0007] The sensor chip 1 includes, from top to bottom, a device layer, an insulating layer, and a support layer; the device layer includes four P-type doped piezoresistive strips 1-1 and five P-type highly doped silicon leads 1-2, the four P-type doped piezoresistive strips 1-1 are sequentially connected through the five P-type highly doped silicon leads 1-2 to form a Wheatstone bridge; adjacent P-type highly doped silicon leads 1-2 are separated by fine gaps; the support layer is provided with a square mass block 1-4 and a support frame 1-5, the area between the square mass block 1-4 and the support frame 1-5 is a stress concentration area, and the P-type doped piezoresistive strip 1-1 is arranged in the stress concentration area; the insulating layer 1-3 is located between the device layer and the support layer, and the material is SiO2, which realizes electrical insulation between the device layer and the support layer.

[0008] The sensor chip 1 is made of SOI silicon wafer.

[0009] The device layer is single crystal silicon with a (100) crystal plane, and the four P-type doped piezoresistive strips 1-1 have the same crystal orientation, all along the

[011] crystal orientation.

[0010] The highly doped silicon vertical conductive structure 2 is made of a P-type highly doped low resistivity silicon wafer, and is connected to the P-type highly doped silicon lead 1-2 by anodic bonding. The highly doped silicon vertical conductive structure 2 includes five highly doped silicon vertical wires 2-2 corresponding to the five P-type highly doped silicon leads 1-2, and the five highly doped silicon vertical wires 2-2 form a cavity 2-1. Adjacent highly doped silicon vertical wires 2-2 are separated by dividing line segments 2-3, and the dividing line segments 2-3 are filled with SiO2 to achieve insulation between the highly doped silicon vertical wires 2-2. At the same time, after bonding, the surface of the highly doped silicon vertical conductive structure 2 is electroplated with point electrodes 2-4.

[0011] The conductive pin 4 is fixedly connected to the ceramic substrate 3 through a through-hole by glass welding. An electrode pad is provided at the contact point between the top of the conductive pin 4 and the ceramic substrate 3. A layer of flux is coated on the electrode pad. The electrode pad is aligned and fitted with the point electrodes 2-4 on the surface of the highly doped silicon vertical conductive structure 2, and then the two are welded together by reflow soldering to achieve electrical connection from the sensor to the external device.

[0012] 所述的陶瓷基底3通过玻璃胶烧结与高掺杂硅立式导电结构2固连。

[0013] The alloy shell 5 is bonded to the ceramic substrate 3 by high-temperature epoxy adhesive.

[0014] The method for preparing the all-silicon vertical leadless package structure comprises the following steps:

[0015] (1) Cleaning the highly doped silicon vertical conductive structure 2 with a standard RCA to remove impurities attached to the surface;

[0016] (2) Wet etching the highly doped silicon vertical conductive structure 2 to form a cavity 2-1 for the sensor chip 1 to move;

[0017] (3) using ICP technology to carve a dividing line segment 2 - 3 on the side of the highly doped silicon vertical conductive structure 2 containing the cavity 2 - 1 ;

[0018] (4) The sensor chip 1 is made of an SOI silicon wafer, and the P-type highly doped silicon lead 1-2 of the sensor chip 1 is aligned with one side of the cavity 2-1 of the highly doped silicon vertical conductive structure 2 by using anodic bonding technology and then bonded;

[0019] (5) Thinning the highly doped silicon vertical conductive structure 2 until the previously etched segment 2-3 is exposed. The segment 2-3 divides the highly doped silicon vertical conductive structure 2 into five highly doped silicon vertical wires 2-2. The highly doped silicon vertical wires 2-2 correspond to the P-type highly doped silicon leads 1-2 of the device layer respectively.

[0020] (6) using PECVD technology to fill SiO2 in the dividing line segments 2-3 between the highly doped silicon vertical conductive structures 2 to achieve insulation between the highly doped silicon vertical wires 2-2;

[0021] (7) using ICP to etch part of the SiO2 on the surface of the highly doped silicon vertical conductive structure 2 to expose the area in contact with the electrode pad;

[0022] (8) electroplating metal on the surface of the highly doped silicon vertical conductive structure 2 by electroplating technology, and obtaining point electrodes 2-4 after wet etching;

[0023] (9) Apply glass glue to the surface of the highly doped silicon vertical conductive structure 2 except for the point electrodes 2-4, and bond the ceramic substrate 3 to the surface of the highly doped silicon vertical conductive structure 2. After bonding, align the conductive pins 4 with the point electrodes 2-4 and weld them together by reflow soldering.

[0024] The shape of the dividing line segment 2-3 in step (3) is the same as the dividing slits between the five P-type highly doped silicon leads 1-2 on the device layer.

[0025] The step (8) is to electroplate metal materials in turn as Ti / Pt / Au three-layer metal.

[0026] Compared with the prior art, the application has the following beneficial effects:

[0027] The vertical conductive structure 2 is anodically bonded with the sensor chip 1, so as to realize the electrical connection in the vertical direction and the air tightness of the packaging structure. In the traditional leadless packaging structure, the glass substrate with a cavity is bonded with the sensor chip, so as to realize the air tightness of the packaging structure. Since the thermal expansion coefficients of glass and silicon are different in a wide temperature range, thermal stress is generated at the bonding interface under thermal cycling, which has an adverse effect on the sensor packaging structure. In the application, the device layer of the vertical conductive structure 2 and the sensor chip 1 are both made of silicon material, so the thermal expansion coefficients of the same material are the same, and no thermal stress is generated at the silicon-silicon bonding interface, thereby avoiding the packaging failure caused by thermal cycling. Compared with the traditional leadless packaging structure, the electrical connection is realized by sintering the conductive paste and the conductive lead, which is complex and high in cost. In the application, the vertical lead is realized by the vertical conductive structure 2, and the electrical connection is realized by welding the metal sputtering electrode and the electrode pad, so as to greatly simplify the process steps, reduce the packaging cost, and improve the stability and reliability of the electrical transmission.

[0028] The SOI silicon wafer is used as the material of the sensor chip 1, so as to avoid the problem that the PN junction of the traditional silicon wafer is broken down at more than 150 DEG C, thereby improving the working temperature of the sensor.

[0029] The device layer of the sensor chip is replaced by the P-type high-doped silicon lead 1-2 instead of the metal sputtering lead, so as to avoid the problem that the metal sputtering lead is subjected to metallization reaction at high temperature to generate intermetallic compounds, thereby increasing the circuit resistance and reducing the sensor output. Meanwhile, the preparation process of the sensor chip is greatly simplified, and the sensor chip is very suitable for mass production.

[0030] Compared with the prior art, the packaging structure of the application is designed in a full-silicon type by using the vertical conductive structure of high-doped silicon and the sensor chip, so as to avoid the sensor failure caused by metallization reaction at ultra-high temperature. The packaging structure has the characteristics of high temperature resistance, corrosion resistance, high precision, high linearity, high stability, low cost, and is suitable for mass production. BRIEF DESCRIPTION OF DRAWINGS

[0031] Figure 1 It is a partial cross-sectional axonometric schematic view of the packaging structure of the application.

[0032] Figure 2 It is an axonometric schematic view of the structure after the vertical conductive structure of high-doped silicon and the chip of the sensor are bonded.

[0033] Figure 3This is a schematic diagram of the front axonometric view of the sensor chip of the present invention.

[0034] Figure 4 This is a schematic diagram of the back side axonometric view of the sensor chip of the present invention.

[0035] Figure 5 This is a schematic cross-sectional isometric view of the back side of the highly doped silicon vertical conductive structure of the present invention.

[0036] Figure 6 This is a front axonometric schematic diagram of the highly doped silicon vertical conductive structure of the present invention.

[0037] Figure 7 Schematic diagram of the method for preparing the packaging structure of the present invention: Figure (a) is a schematic diagram of the P-type highly doped, low-resistivity silicon wafer used in the preparation method; Figure (b) is a schematic diagram of the wet etching cavity; Figure (c) is a schematic diagram of the dry etching dividing line segment; Figure (d) is a schematic diagram of bonding; Figure (e) is a schematic diagram of thinning the P-type highly doped, low-resistivity silicon wafer; Figure (f) is a schematic diagram of depositing silicon dioxide; Figure (g) is a schematic diagram of etching local silicon dioxide; Figure (h) is a schematic diagram of the sputtering point electrode; Figure (i) is a schematic diagram of sintering and welding fixation. DETAILED DESCRIPTION

[0038] The present invention is described in detail below with reference to the accompanying drawings and embodiments.

[0039] Reference Figure 1 、 Figure 2 A full-silicon vertical leadless packaging structure includes a sensor chip 1, a highly doped silicon vertical conductive structure 2, a ceramic substrate 3, a conductive pin 4 and an alloy shell 5. The sensor chip 1 is connected to the ceramic substrate 3 via the highly doped silicon vertical conductive structure 2. The ceramic substrate 3 is connected to the conductive pin 4. The conductive pin 4 is electrically connected to the doped silicon vertical conductive structure 2. The alloy shell 5 is connected to the outside of the sensor chip 1, the highly doped silicon vertical conductive structure 2 and the ceramic substrate 3.

[0040] Reference Figure 3 、 Figure 4The sensor chip 1 includes a device layer, an insulating layer, and a support layer from top to bottom; wherein the device layer includes four P-type doped piezoresistive strips 1-1 and five P-type highly doped silicon leads 1-2, the P-type doped piezoresistive strips 1-1 are respectively along the crystal direction with the largest piezoresistive coefficient of the (100) crystal plane, the four P-type doped piezoresistive strips 1-1 have the same crystal direction, all along the

[011] crystal direction, the four P-type doped piezoresistive strips 1-1 are sequentially connected through the five P-type highly doped silicon leads 1-2 to form a Wheatstone bridge, the P-type doped piezoresistive strips 1-1 and the P-type highly doped silicon leads 1-2 are respectively along the crystal direction with the largest piezoresistive coefficient of the (100) crystal plane, the four P-type doped piezoresistive strips 1-1 have the same crystal direction, all along the

[011] crystal direction, the four P-type doped piezoresistive strips 1-1 are sequentially connected through the five P-type highly doped silicon leads 1-2 to form a Wheatstone bridge, the P-type doped piezoresistive strips 1-1 and the P-type highly doped silicon leads 1- 2 constitutes the sensitive circuit of the sensor chip 1; adjacent P-type highly doped silicon leads 1-2 are separated by a dividing gap of about 30μm to prevent direct connection between the P-type highly doped silicon leads 1-2 and causing a short circuit; the support layer is provided with a square mass block 1-4 and a support frame 1-5. The area between the square mass block 1-4 and the support frame 1-5 is a stress concentration area, and the P-type doped piezoresistive strip 1-1 is arranged in the stress concentration area; the insulating layer 1-3 is located between the device layer and the support layer, and the material is SiO2, which realizes electrical insulation between the device layer and the support layer.

[0041] Reference Figure 5 、 Figure 6 The highly doped silicon vertical conductive structure 2 uses a P-type highly doped low-resistivity silicon wafer. The highly doped silicon vertical conductive structure 2 is connected to the P-type highly doped silicon lead 1-2 through anodic bonding. To achieve alignment and ensure the stability of circuit conduction in the vertical direction, the highly doped silicon vertical conductive structure 2 includes five highly doped silicon vertical wires 2-2 corresponding to the five P-type highly doped silicon leads 1-2. The five highly doped silicon vertical wires 2-2 enclose a cavity 2-1. Adjacent highly doped silicon vertical wires 2-2 are separated by a dividing line segment 2-3 of approximately 60 μm. The dividing line segment 2-3 is filled with SiO2 to achieve insulation between the highly doped silicon vertical wires 2-2 and prevent the highly doped silicon vertical wires 2-2 from interconnecting and causing a short circuit. At the same time, after bonding, the surface of the highly doped silicon vertical conductive structure 2 is electroplated with a dot electrode 2-4.

[0042] The conductive pin 4 is fixedly connected to the ceramic substrate 3 through a through-hole by glass welding. An electrode pad is provided at the contact point between the top of the conductive pin 4 and the ceramic substrate 3. A layer of flux is coated on the electrode pad. The electrode pad is aligned and fitted with the point electrodes 2-4 on the surface of the highly doped silicon vertical conductive structure 2, and then the two are welded together by reflow soldering to achieve electrical connection from the sensor to the external device.

[0043] The ceramic substrate 3 is fixedly connected to the highly doped silicon vertical conductive structure 2 by sintering with glass glue, thereby achieving a compact internal structure.

[0044] The alloy shell 5 is bonded to the ceramic substrate 3 by high-temperature epoxy adhesive to complete the packaging.

[0045] Reference Figure 7The method for preparing the all-silicon vertical leadless package structure comprises the following steps:

[0046] (1)Reference Figure 7 In (a), the highly doped silicon vertical conductive structure 2 is cleaned using a standard RCA to remove impurities attached to the surface;

[0047] (2)Reference Figure 7 In (b), the highly doped silicon vertical conductive structure 2 is wet-etched to form a cavity 2-1 for the sensor chip 1 to move;

[0048] (3)Reference Figure 7 In (c), ICP technology is used to etch a dividing line segment 2-3 on the side of the highly doped silicon vertical conductive structure 2 containing the cavity 2-1. The etching depth is about 2 / 3 of the silicon wafer thickness. The shape of the dividing line segment 2-3 is the same as the dividing slits between the five P-type highly doped silicon leads 1-2 on the device layer.

[0049] (4)Reference Figure 7 In (d), the sensor chip 1 uses an SOI silicon wafer, and the P-type highly doped silicon lead 1-2 of the sensor chip 1 is aligned with one side of the cavity 2-1 of the highly doped silicon vertical conductive structure 2 by anodic bonding technology and then bonded;

[0050] (5)Reference Figure 7 In step (e), the highly doped silicon vertical conductive structure 2 is thinned until the previously etched segment 2-3 is exposed. The segment 2-3 divides the highly doped silicon vertical conductive structure 2 into five highly doped silicon vertical conductors 2-2. The highly doped silicon vertical conductors 2-2 respectively correspond to the P-type highly doped silicon leads 1-2 of the device layer and serve as vertical conductors.

[0051] (6)Reference Figure 7 In (f), SiO2 is filled in the dividing line segments 2-3 between the highly doped silicon vertical conductive structures 2 using PECVD technology to achieve insulation between the highly doped silicon vertical conductive wires 2-2;

[0052] (7)Reference Figure 7 In (g), ICP is used to etch part of SiO2 on the surface of the highly doped silicon vertical conductive structure 2 to expose the area in contact with the electrode pad;

[0053] (8)Reference Figure 7 In (h), metal is electroplated on the surface of the highly doped silicon vertical conductive structure 2 by electroplating technology, and point electrodes 2-4 are obtained after wet etching; the electroplated metal materials are three layers of Ti / Pt / Au metal in sequence;

[0054] (9)Reference Figure 7In (i), glass glue is applied to the surface of the highly doped silicon vertical conductive structure 2 except for the point electrodes 2-4, and the ceramic substrate 3 is bonded to the surface of the highly doped silicon vertical conductive structure 2. After bonding, the conductive pins 4 are aligned with the point electrodes 2-4 and the two are welded and fixed together by reflow soldering.

[0055] The present invention proposes, for the first time, the use of a highly doped silicon vertical conductive structure 2 and a sensor chip 1, anodic bonding, to achieve vertical electrical connection and airtightness of the package structure. Traditional leadless packaging structures achieve airtightness by bonding a glass substrate containing a cavity 2-1 to the sensor chip 1. However, because the thermal expansion coefficients of glass and silicon differ over a wide temperature range, thermal stress is generated at the bonding interface during thermal cycling, adversely affecting the sensor package structure. However, the present invention utilizes both the highly doped silicon vertical conductive structure 2 and the device layer of the sensor chip 1 made of silicon, which has the same thermal expansion coefficient between materials of the same type. Therefore, thermal stress is eliminated at the silicon-silicon bonding interface, thus avoiding package failure due to thermal cycling. Furthermore, compared to traditional leadless packaging, which utilizes a complex and costly process of sintering conductive paste and conductive leads to achieve electrical connection, the present invention utilizes a highly doped silicon vertical conductive structure 2 as a vertical lead and completes the electrical connection by reflow soldering electroplated point electrodes 2-4 to electrode pads. This significantly simplifies the process steps, reduces packaging costs, and improves the stability and reliability of electrical transmission.

[0056] The present invention uses SOI silicon wafer as the material of the sensor chip 1, which avoids the problem of current leakage caused by PN junction breakdown of traditional silicon wafers when the temperature exceeds 150° C., and improves the operating temperature of the sensor.

[0057] The device layer of the sensor chip of the present invention adopts a method of replacing metal sputtering leads with highly doped silicon leads, thereby avoiding the problem that the metal sputtering leads undergo metallization reaction at high temperature to produce intermetallic compounds, which increases the circuit resistance and reduces the sensor output; at the same time, it greatly simplifies the preparation process of the sensor chip, making it very suitable for mass production.

[0058] The above is only one embodiment of the present invention, not all or the only embodiment. Any equivalent transformation of the technical solution of the present invention made by ordinary technicians in this field after reading the specification of the present invention is covered by the claims of the present invention.

Claims

1. An all-silicon vertical leadless package structure, comprising a sensor chip (1), characterized in that: The sensor chip (1) is connected to the ceramic substrate (3) via the highly doped silicon vertical conductive structure (2); the ceramic substrate (3) is connected to a conductive pin (4); the conductive pin (4) and the highly doped silicon vertical conductive structure (2) are electrically connected; and the sensor chip (1), the highly doped silicon vertical conductive structure (2), and the ceramic substrate (3) are connected to an alloy housing (5) on their outer sides; The sensor chip (1) comprises, from top to bottom, a device layer, an insulating layer, and a support layer; wherein the device layer comprises four P-type doped piezoresistive strips (1-1) and five P-type highly doped silicon leads (1-2); the four P-type doped piezoresistive strips (1-1) are sequentially connected via the five P-type highly doped silicon leads (1-2) to form a Wheatstone bridge; adjacent P-type highly doped silicon leads (1-2) are separated by a dividing slit; the support layer is provided with a square mass block (1-4) and a support frame (1-5); the area between the square mass block (1-4) and the support frame (1-5) is a stress concentration area, and the P-type doped piezoresistive strip (1-1) is arranged in the stress concentration area; the insulating layer (1-3) is located between the device layer and the support layer, and the material is SiO2, so as to achieve electrical insulation between the device layer and the support layer; The highly doped silicon vertical conductive structure (2) uses a P-type highly doped low resistivity silicon wafer, and the highly doped silicon vertical conductive structure (2) is connected to the P-type highly doped silicon lead (1-2) through anodic bonding; the highly doped silicon vertical conductive structure (2) includes five highly doped silicon vertical wires (2-2) corresponding to the five P-type highly doped silicon leads (1-2), and the five highly doped silicon vertical wires (2-2) enclose a cavity (2-1); adjacent highly doped silicon vertical wires (2-2) are separated by a dividing line segment (2-3), and the dividing line segment (2-3) is filled with SiO2 to achieve insulation between the highly doped silicon vertical wires (2-2); at the same time, after bonding, the surface of the highly doped silicon vertical conductive structure (2) is electroplated with a point electrode (2-4).

2. The all-silicon vertical leadless package structure according to claim 1, characterized in that: The sensor chip (1) adopts an SOI silicon wafer.

3. The all-silicon vertical leadless package structure according to claim 1, characterized in that: The device layer is single crystal silicon with a (100) crystal plane, and the four P-type doped piezoresistive strips (1-1) have the same crystal orientation, all along the [011] crystal orientation.

4. The all-silicon vertical leadless package structure according to claim 1, characterized in that: The conductive pin (4) is fixedly connected to the ceramic substrate (3) through a through hole by glass welding. An electrode pad is provided at the contact point between the top of the conductive pin (4) and the ceramic substrate (3). A layer of flux is coated on the electrode pad. The electrode pad is aligned and fitted with the point electrode (2-4) on the surface of the highly doped silicon vertical conductive structure (2). The two are then welded together by reflow soldering to achieve electrical connection from the sensor to the external device.

5. The all-silicon vertical leadless package structure according to claim 1, characterized in that: The ceramic substrate (3) is fixedly connected to the highly doped silicon vertical conductive structure (2) by sintering with glass glue.

6. The all-silicon vertical leadless package structure according to claim 1, characterized in that: The alloy shell (5) is bonded to the ceramic base (3) via high-temperature epoxy adhesive.

7. The method for preparing the all-silicon vertical leadless package structure according to any one of claims 1 to 6, characterized in that: The following steps are involved: 1) Clean the highly doped silicon vertical conductive structure (2) using standard RCA to remove impurities attached to the surface; 2) wet-etching the highly doped silicon vertical conductive structure (2) to etch out a cavity (2-1) for the sensor chip (1) to generate displacement; 3) using ICP technology to carve a dividing line segment (2-3) on the side of the highly doped silicon vertical conductive structure (2) containing the cavity (2-1); 4) The sensor chip (1) uses an SOI silicon wafer, and uses an anodic bonding technique to align the P-type highly doped silicon lead (1-2) of the sensor chip (1) with one side of the cavity (2-1) of the highly doped silicon vertical conductive structure (2) and then bond them together; 5) thinning the highly doped silicon vertical conductive structure (2) until the previously etched dividing line segment (2-3) is exposed, the dividing line segment (2-3) dividing the highly doped silicon vertical conductive structure (2) into five highly doped silicon vertical wires (2-2), the highly doped silicon vertical wires (2-2) respectively corresponding to the P-type highly doped silicon leads (1-2) of the device layer; 6) using PECVD technology to fill SiO2 in the dividing line segments (2-3) between the highly doped silicon vertical conductive structures (2) to achieve insulation between the highly doped silicon vertical conductors (2-2); 7) Using ICP to etch part of the SiO2 on the surface of the highly doped silicon vertical conductive structure (2) to expose the area in contact with the electrode pad; 8) Electroplating metal on the surface of the highly doped silicon vertical conductive structure (2) using electroplating technology, and obtaining point electrodes (2-4) after wet etching; 9) Applying glass glue to the surface of the highly doped silicon vertical conductive structure (2) except for the point electrodes (2-4), bonding the ceramic substrate (3) to the surface of the highly doped silicon vertical conductive structure (2), aligning the conductive pins (4) with the point electrodes (2-4) after bonding, and soldering the two together by reflow soldering.

8. The preparation method according to claim 7, characterized in that: In step 3), the shape of the dividing line segment (2-3) is the same as the dividing slits between the five P-type highly doped silicon leads (1-2) on the device layer; in step 8), the electroplated metal materials are three layers of Ti / Pt / Au metal in sequence.

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