Test circuit and test method based on test circuit
By designing a test circuit that integrates the combined logic and timing logic test modules, the problem of inaccurate test results in the prior art is solved, and systematic measurement of target units in the standard unit library is achieved, and the accuracy of test results is improved.
Patent Information
- Application Number
- CN202411474104.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-22
- Publication Date
- 2024-12-31
AI Technical Summary
When verifying units in the standard unit library, existing test circuits mainly conduct timing verification based on combination logic, and the test results are inaccurate.
A test circuit including input module, combined logic test module, timing logic test module and output module was designed. Through the integration of combined logic test module and timing logic test module, timing measurement of combined logic and timing logic is realized, and testing is improved. Accuracy of the results.
This test circuit can not only realize timing measurement of combined logic, but also realize timing measurement of timing logic. Through integrated testing, the accuracy of test results is improved, and mutual interference between test circuits is reduced through Gray code encoding.
Smart Images
Figure CN119224540A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of testing technology, and in particular, to a testing circuit and a testing method based on the testing circuit. Background Art
[0002] According to some customized requirements in the current chip design field, some standardized units required in chip design have been designed. During the application process, dedicated test circuits need to be designed to test the standardized units, so the design of test circuits has also become a research hotspot.
[0003] Existing test circuits can be used to verify the functional accuracy of standardized cells. However, when verifying cells in a standard cell library, most of the existing test circuits only perform timing verification based on combinational logic, and the test results are inaccurate. Summary of the invention
[0004] The purpose of this application is to provide a test circuit and a test method based on the test circuit to address the deficiencies in the above-mentioned prior art, so as to solve the above-mentioned technical problems existing in the related art.
[0005] To achieve the above purpose, the technical solution adopted in the embodiment of the present application is as follows:
[0006] In a first aspect, an embodiment of the present application provides a test circuit, including: an input module, a combinational logic test module, a sequential logic test module, and an output module;
[0007] The output end of the input module is connected to the input end of the combinational logic test module and the input end of the sequential logic test module respectively, so as to output the first test signal and the second test signal to the input end of the combinational logic test module and the input end of the sequential logic test module respectively according to the target test signal, wherein the input end of the input module is used to input the target test signal;
[0008] The output end of the combinational logic test module is connected to the input end of the output module to output a first result signal to the input end of the output module according to the first test signal; the output end of the sequential logic test module is connected to the input end of the output module to output a second result signal to the input end of the output module according to the second test signal;
[0009] The output module is used to output the test result through the output end of the output module according to the first result signal and the second result signal.
[0010] Optionally, the input module includes: an encoding module and a first sequential logic unit to be tested;
[0011] The output end of the encoding module is connected to the input end of the first sequential logic unit to be tested, the input end of the encoding module is used to input the combinational logic selection signal or the sequential logic selection signal in the test signal, and the output end of the encoding module is used to output the encoded combinational logic selection signal or the encoded sequential logic selection signal to the input end of the first sequential logic unit to be tested;
[0012] The input end of the first sequential logic unit to be tested is also used to input the first enable signal and the test selection signal in the test signal, and the first sequential logic unit to be tested is used to output the second enable signal to the input end of the combinational logic test module and the input end of the sequential logic test module respectively;
[0013] The first test signal and the second test signal both include the second enable signal.
[0014] Optionally, the second test signal further includes: a clock signal, a reset signal, a set signal, a clear signal and an input signal.
[0015] Optionally, the combinational logic test module includes: a judgment unit and at least one ring oscillator;
[0016] The input end of the judgment unit is the input end of the combinational logic test module, the output end of the judgment unit is connected to the input end of each ring oscillator, and the output end of each ring oscillator is the output end of the combinational logic test module.
[0017] Optionally, the judgment unit includes: a judgment module, a first NOT gate circuit and an AND gate circuit; the input end of the judgment unit includes: an input end of the judgment module, an input end of the first NOT gate circuit, and a first input end of the AND gate circuit;
[0018] The output end of the judgment module is connected to the second input end of the AND gate circuit, the output end of the first NOT gate circuit is connected to the third input end of the AND gate circuit, and the output end of the AND gate circuit is the output end of the judgment unit.
[0019] Optionally, the ring oscillator comprises: a NAND gate circuit and a plurality of NAND gate units connected in sequence, wherein the input end of the ring oscillator is the first input end of the NAND gate circuit, and the output end of a previous NAND gate unit among the plurality of NAND gate units is connected to the input end of a subsequent NAND gate unit;
[0020] The output end of the NAND gate circuit is connected to the input end of the first NAND gate unit among the multiple NAND gate units, the output end of the last NAND gate unit among the multiple NAND gate units is connected to the second input end of the NAND gate circuit, and the output end of the ring oscillator is the output end of the last NAND gate unit.
[0021] Optionally, the NOT gate unit includes: a second NOT gate circuit and a third NOT gate circuit;
[0022] The input end of the NOT gate unit includes: the input end of the second NOT gate circuit and the input end of the third NOT gate circuit, and the output end of the second NOT gate circuit is the output end of the NOT gate unit.
[0023] Optionally, the sequential logic test module includes: a first multiplexer, a second multiplexer, a first buffer, a second buffer, and a plurality of delay modules connected in sequence; the input end of the sequential logic test module includes: an input end of the first multiplexer, an input end of the second multiplexer; a first output end and a second output end of a previous delay module among the plurality of delay modules are respectively connected to a first input end and a second input end of a subsequent delay module;
[0024] The output end of the first multiplexer is connected to the input end of the first buffer, and the output end of the first buffer is connected to the first input end of the first delay module among the plurality of delay modules;
[0025] The output end of the second multiplexer is connected to the input end of the second buffer, and the output end of the second buffer is connected to the second input end of the first delay module;
[0026] The third output ends of the plurality of delay modules are output ends of the sequential logic test module.
[0027] Optionally, the delay module includes: a data delay unit, a clock delay unit and a second sequential logic unit to be tested; the data delay unit includes: a plurality of first combinational logic units connected in series, and the clock delay unit includes: a plurality of second combinational logic units connected in series;
[0028] The input end of the first first combinational logic unit among the plurality of the first combinational logic units is the first input end of the delay module, and the input end of the first second combinational logic unit among the plurality of the second combinational logic units is the second input end of the delay module;
[0029] The output end of the last of the first combinational logic units among the plurality of the second combinational logic units is the first output end of the delay module, and the output end of the last of the second combinational logic units among the plurality of the second combinational logic units is the second output end of the delay module;
[0030] The output end of the last one of the first combinational logic units and the output end of the last one of the second combinational logic units are respectively connected to the data input end and the clock input end of the second sequential logic unit to be tested, and the output end of the second sequential logic unit to be tested is the third output end of the delay module.
[0031] Optionally, the output module includes: a combinational logic output module and a sequential logic output module;
[0032] The output end of the combinational logic test module is connected to the input end of the combinational logic output module to output the first result signal to the input end of the combinational logic output module according to the first test signal, and the output end of the combinational logic output module is used to output the first test result according to the first result signal;
[0033] The output end of the sequential logic test module is connected to the input end of the sequential logic output module to output the second result signal to the input end of the sequential logic output module according to the second test signal, and the output end of the combinational logic output module is used to output the second test result according to the second result signal;
[0034] The test results include: the first test result and the second test result.
[0035] Optionally, the combinational logic output module includes: a third multiplexer; the input end of the third multiplexer is the input end of the combinational logic output module, the output end of the third multiplexer is the output end of the combinational logic output module, and the third multiplexer is used to determine the first test result from a plurality of the first result signals according to the first test signal;
[0036] The sequential logic output module includes: a fourth multiplexer; an input end of the fourth multiplexer is an input end of the sequential logic output module, an output end of the fourth multiplexer is an output end of the sequential logic output module, and the fourth multiplexer is used to determine the second test result from a plurality of second result signals according to the second test signal.
[0037] In a second aspect, an embodiment of the present application further provides a test method based on a test circuit applied to the test circuit described in any one of the first aspects above, the method comprising:
[0038] Obtaining post-silicon test results of a physical circuit built based on the test circuit;
[0039] Obtaining simulator test results of the test circuit and timing results of back-annotation analysis;
[0040] According to the post-silicon test results, the simulator test results and the timing results of the back-label analysis, determine whether the timing of the target unit in the standard cell library is accurate, wherein the combinational logic test module and the sequential logic test module include the target unit, and the target unit in the standard cell library includes: a combinational logic unit and / or a sequential logic unit.
[0041] Optionally, obtaining a post-silicon test result of a physical circuit built based on the test circuit includes:
[0042] Generate a test chain index according to the preset measurement method;
[0043] According to the test chain index, the combinational logic test module and the sequential logic test module in the physical circuit are tested to obtain the post-silicon test result.
[0044] The beneficial effects of the present application are as follows: the present application embodiment provides a test circuit, including: an input module, a combinational logic test module, a sequential logic test module and an output module; the output end of the input module is respectively connected to the input end of the combinational logic test module and the input end of the sequential logic test module, so as to output a first test signal and a second test signal to the input end of the combinational logic test module and the input end of the sequential logic test module according to a target test signal, wherein the input end of the input module is used to input a target test signal; the output end of the combinational logic test module is connected to the input end of the output module, so as to output a first result signal to the input end of the output module according to the first test signal; the output end of the sequential logic test module is connected to the input end of the output module, so as to output a second result signal to the input end of the output module according to the second test signal; the output module is used to output a test result through the output end of the output module according to the first result signal and the second result signal. The test circuit is provided with a combinational logic test module and a sequential logic test module, which can not only realize the sequential measurement of the combinational logic, but also realize the sequential measurement of the sequential logic, and integrate the sequential measurement of the combinational logic and the sequential logic to carry out systematic measurement, which can improve the accuracy of the test result. BRIEF DESCRIPTION OF THE DRAWINGS
[0045] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.
[0046] Figure 1 A schematic diagram of a test circuit provided in an embodiment of the present application Figure 1 ;
[0047] Figure 2 A schematic diagram of the structure of an input module provided in an embodiment of the present application;
[0048] Figure 3 A schematic diagram of the structure of a combinational logic test module provided in an embodiment of the present application;
[0049] Figure 4 A schematic diagram of the structure of a judgment unit provided in an embodiment of the present application;
[0050] Figure 5 A schematic diagram of the structure of a ring oscillator provided in an embodiment of the present application;
[0051] Figure 6 A schematic diagram of the structure of a sequential logic test module provided in an embodiment of the present application;
[0052] Figure 7 A schematic diagram of a test circuit provided in an embodiment of the present application Figure 2 ;
[0053] Figure 8 A schematic diagram of the structure of a third multiplexer provided in an embodiment of the present application;
[0054] Fig. 9 A schematic diagram of the structure of a fourth multiplexer provided in an embodiment of the present application;
[0055] Fig.10 A flow chart of a test method based on a test circuit provided in an embodiment of the present application. DETAILED DESCRIPTION
[0056] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments.
[0057] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.
[0058] In addition, the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.
[0059] It should be noted that, in the absence of conflict, the features in the embodiments of the present application may be combined with each other.
[0060] A test circuit provided in an embodiment of the present application is explained below.
[0061] Figure 1 A schematic diagram of a test circuit provided in an embodiment of the present application Figure 1 ;like Figure 1 As shown, the test circuit includes: an input module 10 , a combinational logic test module 11 , a sequential logic test module 12 and an output module 13 .
[0062] The output end of the input module 10 is connected to the input end of the combinational logic test module 11 and the input end of the sequential logic test module 12, respectively, so as to output the first test signal and the second test signal to the input end of the combinational logic test module 11 and the input end of the sequential logic test module 12 according to the target test signal, wherein the input end of the input module 10 is used to input the target test signal;
[0063] In addition, the output end of the combinational logic test module 11 is connected to the input end of the output module 13 to output a first result signal to the input end of the output module 13 according to the first test signal; the output end of the sequential logic test module 12 is connected to the input end of the output module 13 to output a second result signal to the input end of the output module 13 according to the second test signal; the output module 13 is used to output the test result through the output end of the output module 13 according to the first result signal and the second result signal.
[0064] In the embodiment of the present application, the combinational logic test module 11 is a test circuit for measuring the timing delay of the combinational logic; the sequential logic test module 12 is a circuit for measuring the setup time and hold time of the sequential logic unit. That is, the timing measurement of the combinational logic and the sequential logic can be realized. Specifically, the combinational logic test module 11 and the sequential logic test module 12 include target cells in the standard cell library, and the target cells in the standard cell library include: combinational logic cells and / or sequential logic cells. The embodiment of the present application can realize the timing measurement of the combinational logic and sequential logic of the target cells in the standard cell library.
[0065] In some embodiments, the target test signal may include: a clock signal (Clk), a reset signal (RST), an automatic test signal (Auto_Test), a first enable signal (Enable), a test selection signal (Test_sel), and a combinational / sequential logic selection signal (Tset_idx). The target test signal may also include: a set signal, a clear signal, and an input signal. The set signal includes: a low effective set signal, a synchronous set signal (SN), a low effective set signal, and an asynchronous set signal (SDN); the clear signal includes: a high effective clear signal, a synchronous reset signal (C), a high effective clear signal, and an asynchronous reset signal (CD); the input signal includes: a scan chain (Scan Chain) input signal (SI), and a scan chain (Scan Chain) enable signal (SE). For specific information of each signal in the target test signal, please refer to Table 1 below.
[0066] It should be noted that the number of input terminals and output terminals of the input module 10 can be multiple, and each signal in the target test signal can be input to the input module 10 using different input terminals of the input module 10. Similarly, the first test signal and the second test signal can also be output from the input module 10 through different output terminals of the input module 10. Similarly, the combinational logic test module 11, the sequential logic test module 12 and the output module 13 can all be provided with at least one input terminal and at least one output terminal according to actual needs.
[0067] In summary, the embodiment of the present application provides a test circuit, including: an input module 10, a combinational logic test module 11, a sequential logic test module 12, and an output module 13. The output end of the input module 10 is connected to the input end of the combinational logic test module 11 and the input end of the sequential logic test module 12, respectively, so as to output a first test signal and a second test signal to the input end of the combinational logic test module 11 and the input end of the sequential logic test module 12 according to a target test signal, wherein the input end of the input module 10 is used to input a target test signal; the output end of the combinational logic test module 11 is connected to the input end of the output module 13, so as to output a first result signal to the input end of the output module 13 according to the first test signal; the output end of the sequential logic test module 12 is connected to the input end of the output module 13, so as to output a second result signal to the input end of the output module 13 according to the second test signal; the output module 13 is used to output a test result through the output end of the output module 13 according to the first result signal and the second result signal. The test circuit is provided with a combinational logic test module 11 and a sequential logic test module 12, which can realize not only the timing measurement of the combinational logic, but also the timing measurement of the sequential logic. The timing measurement of the combinational logic and the sequential logic is integrated to carry out systematic measurement, which can improve the accuracy of the test results.
[0068] Optionally, Figure 2 A schematic diagram of the structure of an input module provided in an embodiment of the present application; Figure 2 As shown, the input module 10 includes: an encoding module 101 and a first sequential logic unit to be tested 102 .
[0069] The output end of the encoding module 101 is connected to the input end of the first sequential logic unit to be tested 102. The input end of the encoding module 101 is used to input the combinational logic selection signal or the sequential logic selection signal in the test signal. The output end of the encoding module 101 is used to output the encoded combinational logic selection signal or the encoded sequential logic selection signal to the input end of the first sequential logic unit to be tested 102; the input end of the first sequential logic unit to be tested 102 is also used to input the first enable signal and the test selection signal in the test signal. The first sequential logic unit to be tested 102 is used to output the second enable signal to the input end of the combinational logic test module 11 and the input end of the sequential logic test module 12 respectively; the first test signal and the second test signal both include the second enable signal.
[0070] The combinational logic selection signal or the sequential logic selection signal may be the Tset_idx signal mentioned above. The first enable signal may be the Enable signal mentioned above, and the test selection signal may be the Test_sel signal mentioned above. The second enable signal may be the Idx_enable signal. For specific information of the Idx_enable signal, please refer to Table 1.
[0071] In some embodiments, the first sequential logic unit 102 to be tested may be a DFF (D-type flip-flop), and the encoding module 101 may be a BIN2GREY (usually referring to a binary to Gray code conversion process or module), wherein the Gray code is a binary number encoding method, and two consecutive values in the Gray code differ by only one bit.
[0072] It should be noted that the output module 13 can determine the test content and the target unit of the test according to the Tset_idx signal and the Test_sel signal, and transmit the Idx_enable signal to the combinational logic test module 11 and the sequential logic test module 12 for testing the target unit. The circuits in the combinational logic test module 11 and the sequential logic test module 12 are encoded with Gray code to ensure that the change of the index during each measurement will not affect other unit test circuits.
[0073] Optionally, the second test signal further includes: a clock signal, a reset signal, a set signal, a clear signal and an input signal.
[0074] Among them, the set signal includes: a low effective set signal, a synchronous set signal (SN), a low effective set signal, and an asynchronous set signal (SDN); the clear signal includes: a high effective clear signal, a synchronous reset signal (C), a high effective clear signal, and an asynchronous reset signal (CD); the input signal includes: a scan chain input signal (SI) and a scan chain enable signal (SE). For specific information of each signal in the second test signal, please refer to Table 1.
[0075] Table 1
[0076]
[0077]
[0078] Among them, I represents input and O represents output.
[0079] Optionally, Figure 3 A schematic diagram of the structure of a combinational logic test module provided in an embodiment of the present application; Figure 3 As shown, the combinational logic test module 11 includes: a judgment unit 110 and at least one ring oscillator 111;
[0080] The input end of the judgment unit 110 is the input end of the combinational logic test module 11 , the output end of the judgment unit 110 is connected to the input end of each ring oscillator 111 , and the output end of each ring oscillator 111 is the output end of the combinational logic test module 11 .
[0081] In the embodiment of the present application, the judgment unit 110 is used to compare the index to determine whether to start the oscillation. The ring oscillator 111 is used to test the delay time of the combinational logic. Based on the different data points in the standard cell library timing model library, the ring oscillation circuit has multiple structures to obtain the cell delay under different loads.
[0082] In addition, a ring oscillator 111 may be referred to as a measurement ring. In the embodiment of the present application, typical data points are sampled from a standard cell library timing model library to establish a measurement ring of a combinational logic.
[0083] Optionally, Figure 4 A structural diagram of a judgment unit provided in an embodiment of the present application; Figure 4 As shown, the judgment unit 110 includes: a judgment module 1101, a first NOT gate circuit 1102 and an AND gate circuit 1103; the input end of the judgment unit 110 includes: an input end of the judgment module, an input end of the first NOT gate circuit, and a first input end of the AND gate circuit;
[0084] The output end of the judgment module 1101 is connected to the second input end of the AND gate circuit 1103 , the output end of the first NOT gate circuit 1102 is connected to the third input end of the AND gate circuit 1103 , and the output end of the AND gate circuit 1103 is the output end of the judgment unit 110 .
[0085] In some embodiments, a second enable signal is input to the input end of the judgment module 1101, and an output end of the judgment module 1101 outputs a first signal to a second input end of the AND gate circuit 1103 according to the second enable signal; a second enable signal is input to a first input end of the AND gate circuit 1103; a second enable signal is input to an input end of the first NOT gate circuit 1102, and an output end of the first NOT gate circuit 1102 outputs a second signal to a third input end of the AND gate circuit 1103 according to the second enable signal; an output end of the AND gate circuit 1103 outputs a third enable signal according to the first signal, the second enable signal and the second signal, and the third enable signal may be Enable.
[0086] Optionally, Figure 5 A schematic diagram of the structure of a ring oscillator provided in an embodiment of the present application; Figure 5 As shown, the ring oscillator 111 includes: a NAND gate circuit 1110, and a plurality of NAND gate units 1111 connected in sequence, wherein the input end of the ring oscillator 111 is the first input end of the NAND gate circuit 1110, and the output end of the previous NAND gate unit 1111 among the plurality of NAND gate units 1111 is connected to the input end of the next NAND gate unit 1111;
[0087] The output end of the NAND gate circuit 1110 is connected to the input end of the first NAND gate unit 1111 among the multiple NAND gate units 1111, the output end of the last NAND gate unit 1111 among the multiple NAND gate units 1111 is connected to the second input end of the NAND gate circuit 1110, and the output end of the ring oscillator 111 is the output end of the last NAND gate unit 1111.
[0088] Each NOT gate unit 1111 includes at least one second NOT gate circuit.
[0089] It should be noted that the output end of the AND gate circuit 1103 outputs the third enable signal to the first input end of the NAND gate circuit 1110, and the NAND gate circuit 1110 can receive the third enable signal. There can be multiple ring oscillators 111, and the third enable signal is input to the first input end of the NAND gate circuit 1110 of each ring oscillator 111. The third enable signal can be used to control whether each ring oscillator 111 starts oscillation.
[0090] In the embodiment of the present application, the measurement ring formed by the ring oscillator 111 can measure the target unit in the sequential logic test module 12. Optionally, the target unit in the sequential logic test module 12 may include a combinational logic unit. At the same time, the measurement ring also measures other combinational logic units.
[0091] Alternatively, if Figure 5 As shown, the NOT gate unit 1111 includes: a second NOT gate circuit 1111a and a third NOT gate circuit 1111b;
[0092] The input end of the NOT gate unit 1111 includes: the input end of the second NOT gate circuit 1111 a and the input end of the third NOT gate circuit 1111 b , and the output end of the second NOT gate circuit 1111 a is the output end of the NOT gate unit 1111 .
[0093] It is worth noting that the input end of the second NOT gate circuit 1111a and the input end of the third NOT gate circuit 1111b in the first NOT gate unit 1111 among the multiple NOT gate units 1111 are connected to the output end of the NAND gate circuit 1110. The output end of the second NOT gate circuit 1111a in the first NOT gate unit 1111 is connected to the input end of the second NOT gate circuit 1111a and the input end of the third NOT gate circuit 1111b in the next NOT gate unit 1111.
[0094] In addition, the output end of the second NOT gate unit 1111 in the previous NOT gate unit 1111 in the multiple NOT gate units 1111 is connected to the input end of the second NOT gate circuit 1111a and the input end of the third NOT gate circuit 1111b in the next NOT gate unit 1111; the output end of the second NOT gate circuit 1111a in the last NOT gate unit 1111 is connected to the second input end of the NAND gate circuit 1110.
[0095] In practical applications, each ring oscillator 111 in at least one ring oscillator 111 can output a first result signal. The signal output by at least one ring oscillator 111 is a collection of at least one first result signal, which can be expressed as a Ro_Out signal. For specific information of the Ro_Out signal, please refer to Table 2 below.
[0096] Optionally, Figure 6 A schematic diagram of the structure of a sequential logic test module 12 provided in an embodiment of the present application; Figure 6 As shown, the sequential logic test module 12 includes: a first multiplexer 120, a second multiplexer 121, a first buffer 122, a second buffer 123, and a plurality of delay modules 124 connected in sequence; the input end of the sequential logic test module 12 includes: an input end of the first multiplexer 120, an input end of the second multiplexer 121; a first output end and a second output end of a previous delay module 124 among the plurality of delay modules 124 are connected to a first input end and a second input end of a subsequent delay module 124, respectively;
[0097] The output terminal of the first multiplexer 120 is connected to the input terminal of the first buffer 122 , and the output terminal of the first buffer 122 is connected to the first input terminal of the first delay module 124 among the plurality of delay modules 124 ;
[0098] The output end of the second multiplexer 121 is connected to the input end of the second buffer 123 , and the output end of the second buffer 123 is connected to the second input end of the first delay module 124 ;
[0099] The third output terminals of the plurality of delay modules 124 are output terminals of the sequential logic test module 12 .
[0100] The sequential logic test module 12 can also be called a sequential logic unit setup time and hold time measurement circuit. A plurality of delay modules 124 in the sequential logic test module 12 are connected in series to form a delay chain, and the delay chain can be customized to adjust the measurement accuracy.
[0101] In the embodiment of the present application, the output end of the sequential logic test module 12 includes the third output ends of the plurality of delay modules 124, and a second result signal can be output through the third output end of each delay module 124, and a second result signal is a binary code, and a plurality of second result signals can form a plurality of binary codes, and a plurality of second result signals can be represented as a meas_out signal, and the meas_out signal can be represented as a string of binary code outputs of Q0 to Qn. For specific information of the meas_out signal, please refer to Table 2 below.
[0102] Alternatively, if Figure 6 As shown, the delay module 124 includes: a data delay unit 1241, a clock delay unit 1242 and a second sequential logic unit to be tested 1243; the data delay unit 1241 includes: a plurality of first combination logic units 1241a connected in series, and the clock delay unit 1242 includes: a plurality of second combination logic units 1242a connected in series;
[0103] An input terminal of a first first combinational logic unit 1241a among the plurality of first combinational logic units 1241a is a first input terminal of the delay module 124, and an input terminal of a first second combinational logic unit 1242a among the plurality of second combinational logic units 1242a is a second input terminal of the delay module 124;
[0104] The output end of the last first combinational logic unit 1241a among the plurality of second combinational logic units 1242a is the first output end of the delay module 124, and the output end of the last second combinational logic unit 1242a among the plurality of second combinational logic units 1242a is the second output end of the delay module 124;
[0105] The output end of the last first combinational logic unit 1241a and the output end of the last second combinational logic unit 1242a are respectively connected to the data input end and the clock input end of the second sequential logic unit 1243 to be tested. The output end of the second sequential logic unit 1243 to be tested is the third output end of the delay module 124.
[0106] The output end of the last first combinational logic unit 1241a outputs a data signal to the data input end of the second sequential logic unit to be tested 1243, and the output end of the last second combinational logic unit 1242a inputs a clock signal to the clock input end of the second sequential logic unit to be tested 1243. The output end of the second sequential logic unit to be tested 1243 outputs a fourth signal.
[0107] It should be noted that the multiple first combinational logic units 1241a connected in series in the multiple delay modules 124 form a delay chain, namely a data delay chain, and the multiple second combinational logic units 1242a connected in series in the multiple delay modules 124 form another delay chain, namely a clock delay chain. The sequential logic test module 12 measures the setup time and the hold time based on the two delay chains and the multiple second sequential logic units to be tested 1243 connected in series, and the number of the second sequential logic units to be tested 1243 connected in series can adjust the measurement range. The sequential logic test module 12 applies the combinational logic unit to the time constraint measurement of the sequential logic.
[0108] In some embodiments, a reset signal is input to the first multiplexer 120 and the second multiplexer 121. The reset signal may include an initialization reset signal and a further reset signal. The initialization reset signal may be an RST signal. The further reset signal may include: a C signal, a CD signal, an SN signal, an SDN signal, an SE signal, and an SI signal. A second enable signal is input to the second multiplexer. The second enable signal may control whether the sequential logic test module 12 is turned on. The second enable signal transmits a high potential to the data input terminal and the clock input terminal of the second sequential logic unit 1243 to be tested through two different delay chains.
[0109] Among them, the sequential logic test module 12 and the combinational logic test module 11 are both input to the test module. The test unit is a small unit in the test module. The RST signal is used as a reset signal to reset the second sequential logic unit 1243 to be tested. Taking into account that some test units in the test unit do not have a reset / set function, the Rst reset signal is used to initialize the test unit. When the Rst signal is reset at a low level, the data end will select the same input Rst low level through the first multiplexer 120 to reset the test unit to 0; when Rst is at a high level, the second enable signal is selected through the second multiplexer 121 to perform normal testing. The second enable signal is also selected using a multiplexer to ensure the consistency of the input signal when entering the system test.
[0110] It should be noted that the sequential logic test module 12 contains two independent delay chains, and the delay units on the delay chains can be customized. By adjusting different delay units, measurements under different process angles and voltage and temperature conditions can be achieved, and higher accuracy can be achieved.
[0111] Optionally, Figure 7 A schematic diagram of a test circuit provided in an embodiment of the present application Figure 2 ;like Figure 7 As shown, the output module 13 includes: a combinational logic output module 131 and a sequential logic output module 132;
[0112] The output end of the combinational logic test module 11 is connected to the input end of the combinational logic output module 131 to output a first result signal to the input end of the combinational logic output module 131 according to the first test signal, and the output end of the combinational logic output module 131 is used to output a first test result according to the first result signal;
[0113] The output end of the sequential logic test module 12 is connected to the input end of the sequential logic output module 132 to output a second result signal to the input end of the sequential logic output module 132 according to the second test signal, and the output end of the combinational logic output module 131 is used to output a second test result according to the second result signal;
[0114] The test results include: a first test result and a second test result.
[0115] It should be noted that the combinational logic test module 11 and the sequential logic test module 12 respectively process the first result signal and the second result signal to output the first test result signal and the second test result signal.
[0116] In some embodiments, the output end of the combinational logic test module 11 outputs a Ro_out signal to the input end of the combinational logic output module 131, and the combinational logic output module 131 outputs a Comb_valid signal and a Comb_out signal through the output end of the combinational logic output module 131 according to the Ro_out signal, wherein the Comb_valid signal is obtained by selecting the Ro_out signal by the combinational logic output module 131, and the Comb_valid signal is judged by the first enable signal in the combinational logic output module 131.
[0117] In addition, the output end of the sequential logic test module 12 outputs the Meas_out signal to the input end of the sequential logic output module 132, and the sequential logic test module 12 outputs the Seq_out signal and the Seq_valid signal through the output end of the sequential logic test module 12 according to the Meas_out signal, wherein the Seq_out signal is obtained by selecting the Meas_out signal by the sequential logic output module 132, and the Seq_valid signal is judged by the first enable signal in the sequential logic output module 132.
[0118] For specific information of the Comb_valid signal, the Comb_out signal, the Seq_out signal, and the Seq_valid signal, please refer to Table 2 below.
[0119] Table 2
[0120] signal name Bit width I / O describe Ro_out 1*N I Output results of several ring oscillators 111 Meas_out 20*M I Output results of several delay units Comb_valid 1 O Combination logic outputs valid signal; high flag output signal is valid Comb_out 1 O Combinational logic output signal Seq_out 20 O Sequential logic output signal Seq_valid 1 O Sequential logic output valid signal; high flag output signal is valid
[0121] Optionally, the combinational logic output module 131 includes: a third multiplexer; an input end of the third multiplexer is an input end of the combinational logic output module 131, an output end of the third multiplexer is an output end of the combinational logic output module 131, and the third multiplexer is used to determine the first test result from the plurality of first result signals according to the first test signal;
[0122] The sequential logic output module 132 includes: a fourth multiplexer; the input end of the fourth multiplexer is the input end of the sequential logic output module 132, the output end of the fourth multiplexer is the output end of the sequential logic output module 132, and the fourth multiplexer is used to determine the second test result from multiple second result signals according to the second test signal.
[0123] Figure 8 A schematic diagram of the structure of a third multiplexer provided in an embodiment of the present application; Figure 8 As shown, the third multiplexer determines the Comb_out signal from multiple first result signals, namely the Ro_out signal, according to the second enable signal Idx_Enable in the first test signal. The output end of the third multiplexer can output the Comb_out signal. The first test result includes: the Comb_out signal. The first test result can also include: the Comb_valid signal. Fig. 9 A schematic diagram of the structure of a fourth multiplexer provided in an embodiment of the present application; Fig. 9 As shown, the fourth multiplexer determines the Seq_out signal from multiple second result signals, namely the Meas_out signal, according to the second enable signal Idx_Enable in the second test signal. The output end of the third multiplexer can output the Seq_out signal. The second test result includes: the Seq_out signal. The second test result can also include: the Seq_valid signal.
[0124] In the embodiment of the present application, when measuring the setup time of the sequential logic, it is required that the first-level delay of the clock delay chain is greater than the first-level delay of the data delay chain to ensure that the initial setup time is met and no timing violation occurs; then, the delay of the data delay unit 1241 is required to be greater than the clock delay unit 1242, so that the data end can "catch up" with the clock end, thereby achieving the purpose of measuring the setup time. By observing the output of the sequential logic, it can be known which level of sequential logic unit has a setup time violation. The setup time of the sequential logic unit to be tested can be calculated using the following formula: T setup time = T initial delay - n * (T data delay unit delay - T clock delay unit delay)
[0125] Wherein, T initial delay is the initial delay time, which is obtained by simulating the data delay chain and the clock delay chain, that is, the difference between the first level of the clock delay chain and the data delay chain; n represents the observed violation of the nth second sequential logic unit 1243 to be tested, and n can be carried in the meas_out signal; T data delay unit 1241 delay and T clock delay unit 1242 delay are the delay time of the data end delay unit and the delay time of the clock end delay unit respectively. Wherein, the data end delay unit is a plurality of first combinational logic units 1241a connected in series, and the clock end delay unit is a plurality of second combinational logic units 1242a connected in series.
[0126] It is worth noting that the delay of the T data delay unit 1241 and the delay of the T clock delay unit 1242 can be measured by the ring oscillator 111 in the combinational logic test module 11, thereby reducing the error caused by the external environment.
[0127] In summary, the embodiment of the present application provides a test circuit, in which a combinational logic test module 11 and a sequential logic test module 12 are provided, which can not only realize the timing measurement of the combinational logic, but also realize the timing measurement of the sequential logic. The timing measurement of the combinational logic and the sequential logic are integrated to carry out systematic measurement, which can improve the accuracy of the test results. Moreover, the sequential logic test module 12 is designed, and the combinational logic timing measurement of the ring oscillator 111 is integrated at the same time, so that the test items of the entire test circuit cover the entire standard cell library. At the same time, Gray code encoding technology is also used to reduce mutual interference between test circuits.
[0128] When a wafer fab has a new process and needs to design a new set of standard cell libraries, or when some special cells are customized based on the existing process, it is generally necessary to design a dedicated test circuit to test these cells. The role of post-silicon timing verification consistency is to verify the accuracy of the standard cell library model. When the error between the post-silicon timing and the standard cell library model is large, it means that the standard cell library model is inaccurate, and the design of the model needs to be confirmed and calibrated; when there is an acceptable error between the post-silicon timing and the standard cell library model, the standard cell library model can also be calibrated to achieve more accurate timing information. At the same time, it can guide the next tape-out of the same process, and the timing margin can be adjusted during circuit design. Therefore, post-silicon verification is very necessary.
[0129] The embodiment of the present application also provides a test method based on a test circuit, which integrates the timing measurement of combinational logic and sequential logic to carry out systematic measurement, and compares the post-silicon measurement results with the data in the standard cell library to verify the consistency, so as to achieve a guiding role in the next tape-out with the same process.
[0130] The following is an explanation of a test method based on a test circuit provided in the embodiment of the present application. The method is applied to the above-mentioned test circuit, and the method can be run on an electronic device, which can be a terminal device, a server or a test device; the terminal device can include but is not limited to: a computer device, a laptop computer, a smart phone or a tablet computer; for example, the test device can be an oscilloscope.
[0131] Fig.10 A flow chart of a test method based on a test circuit provided in an embodiment of the present application; Fig.10 As shown, the method includes:
[0132] S101. Obtain post-silicon test results of a physical circuit built based on the test circuit.
[0133] In the embodiment of the present application, the test items are determined, that is, the sequential logic unit and the combinational logic unit, as well as the target unit to be tested. The test circuit design is performed, which includes selecting the test points, determining the measurement accuracy and the range, that is, obtaining the above-mentioned test circuit, and building a physical circuit based on the test circuit. Post-silicon testing is performed based on the physical circuit, and the post-silicon test results are collected through electronic equipment.
[0134] S102, obtaining simulator test results of the test circuit and timing results of back-labeling analysis.
[0135] In some implementations, a test circuit is built, a pre-test circuit simulation is performed, the test circuit is integrated into a chip, a back-end physical implementation of the test circuit is performed, a post-test circuit simulation is performed, and a software simulation of the test circuit is completed. Based on the software simulation, the simulator test results of the test circuit and the timing results of the back-label analysis are obtained.
[0136] Among them, the simulator test result refers to the hspice (a circuit module program) simulation measurement result of the simulation circuit built before tape-out, that is, the result of the simulation before the test circuit, which occurs before the back-end physical implementation. The timing result of the back-label analysis refers to the timing result analyzed by the EDA (Electronic Design Automation) tool after the back-end physical implementation of the test circuit.
[0137] S103 , determining whether the timing of the target cell in the standard cell library is accurate according to the post-silicon test results, the simulator test results, and the timing results of the back-annotation analysis.
[0138] The combinational logic test module and the sequential logic test module include target cells, and the target cells in the standard cell library include: combinational logic cells and / or sequential logic cells.
[0139] Optionally, the target unit in the combinational logic test module includes: a first sequential logic unit to be tested, and the target unit in the sequential logic test module includes: a first combinational logic unit, a second combinational logic unit, and a second sequential logic unit to be tested.
[0140] In the embodiment of the present application, the three groups of results, namely, the post-silicon test results, the simulator test results, and the timing results of the back-annotation analysis, are compared in pairs to calculate the error, thereby obtaining the accuracy of the standard cell library model.
[0141] It should be noted that the timing results of the back-annotation analysis actually refer to the timing results of the back-annotation analysis performed by the EDA tool through the standard cell library model.
[0142] It is worth noting that when the error between the post-silicon test results and the simulator test results and the timing results of the back-labeling analysis is large, it means that the standard cell library model is inaccurate, that is, the timing of the target cell in the standard cell library is inaccurate, and the design of the model needs to be confirmed and calibrated; when there is an acceptable error between the post-silicon timing and the simulator test results and the timing results of the back-labeling analysis, the standard cell library model can also be calibrated, that is, the timing of the target cell in the standard cell library can be calibrated to achieve more accurate timing information, and at the same time it can serve as a guide for the next tape-out with the same process.
[0143] In summary, an embodiment of the present application provides a test method based on a test circuit, the method comprising: obtaining post-silicon test results of a physical circuit built based on the test circuit; obtaining simulator test results of the test circuit, and timing results of back-label analysis; determining whether the timing of the target unit in the standard cell library is accurate based on the post-silicon test results, the simulator test results, and the timing results of the back-label analysis, wherein the combinational logic test module and the sequential logic test module include the target unit, and the target unit in the standard cell library includes: a combinational logic unit and / or a sequential logic unit. By comparing the post-silicon test results, the simulator test results, and the timing results of the back-label analysis, it is verified whether the timing of the standard cell library is consistent with the post-silicon data, so that the timing accuracy of the target unit in the standard cell library can be accurately determined.
[0144] Moreover, this method can improve the accuracy of the standard cell library under the same process, and can also provide guidance for the timing sign-off strategy before tape-out.
[0145] Optionally, the process of obtaining the post-silicon test results of the physical circuit built based on the test circuit in the above S101 may include: generating a test chain index according to a preset measurement method; testing the combinational logic test module and the sequential logic test module in the physical circuit according to the test chain index to obtain the post-silicon test results.
[0146] Among them, the physical circuit can also become a test circuit for the hardware.
[0147] In an embodiment of the present application, when performing post-silicon testing, the measurement items can be determined first according to the needs. There are two modes for the test circuit, automatic test and manual test. When automatic test is selected, Auto_Test will be set to a high potential, and the input module root Test_sel and Enabl signals will automatically generate test vectors for the items to be tested, and then each test circuit chain of the design will be tested. At this time, an external device is required to collect and collect the results. When all test vectors are tested, the automatic test process ends. Among them, the items to be tested include: combinational logic delay, sequential logic setup time, and sequential logic hold time. The test vector is a series of input stimuli for testing the combinational logic test module and the sequential logic test module, specifically including the stimulus for control test, which is composed of binary code.
[0148] In addition, when the manual test mode is selected, Auto_Test will be set to a low level, and Idx_enable will control which module to test and whether to start the test. Idx_enable actually concatenates the input signals Enable, Test_sel, and Test_idx. The first bit is the enable signal of the test module, and a high level indicates that the module starts testing; the second and third bits are Test_sel, which tests the combinational logic circuit when it is low and the sequential logic circuit when it is high; the remaining 16 bits serve as the index of the test module to mark different test modules. When the test vector is manually entered, the index value corresponding to the test circuit chain will select the test chain for testing and collect data through external equipment according to the input test chain index to complete a single manual test.
[0149] It should be noted that the test method based on the test circuit provided in the embodiment of the present application not only meets the test requirements of both automatic test and manual test modes, but also can realize the timing measurement under different process angles, voltages and temperatures. Moreover, the embodiment of the present application covers the timing measurement of combinational logic and sequential logic, based on which it is verified whether the timing of the standard cell library is consistent with the post-silicon data, and the timing accuracy of the target cell in the standard cell library can be accurately verified.
[0150] The above are only preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims
1. A test circuit, characterized in that: include: Input module, combinational logic test module, sequential logic test module and output module; The output end of the input module is connected to the input end of the combinational logic test module and the input end of the sequential logic test module respectively, so as to output the first test signal and the second test signal to the input end of the combinational logic test module and the input end of the sequential logic test module respectively according to the target test signal, wherein the input end of the input module is used to input the target test signal; The output end of the combinational logic test module is connected to the input end of the output module to output a first result signal to the input end of the output module according to the first test signal; the output end of the sequential logic test module is connected to the input end of the output module to output a second result signal to the input end of the output module according to the second test signal; The output module is used to output the test result through the output end of the output module according to the first result signal and the second result signal.
2. The test circuit according to claim 1, characterized in that: The input module includes: an encoding module and a first sequential logic unit to be tested; The output end of the encoding module is connected to the input end of the first sequential logic unit to be tested, the input end of the encoding module is used to input the combinational logic selection signal or the sequential logic selection signal in the test signal, and the output end of the encoding module is used to output the encoded combinational logic selection signal or the encoded sequential logic selection signal to the input end of the first sequential logic unit to be tested; The input end of the first sequential logic unit to be tested is also used to input the first enable signal and the test selection signal in the test signal, and the first sequential logic unit to be tested is used to output the second enable signal to the input end of the combinational logic test module and the input end of the sequential logic test module respectively; The first test signal and the second test signal both include the second enable signal.
3. The test circuit according to claim 2, characterized in that: The second test signal also includes: a clock signal, a reset signal, a set signal, a clear signal and an input signal.
4. The test circuit according to claim 1, characterized in that: The combinational logic test module includes: a judgment unit and at least one ring oscillator; The input end of the judgment unit is the input end of the combinational logic test module, the output end of the judgment unit is connected to the input end of each ring oscillator, and the output end of each ring oscillator is the output end of the combinational logic test module.
5. The test circuit according to claim 4, characterized in that: The judgment unit includes: a judgment module, a first NOT gate circuit and an AND gate circuit; the input end of the judgment unit includes: an input end of the judgment module, an input end of the first NOT gate circuit, and a first input end of the AND gate circuit; The output end of the judgment module is connected to the second input end of the AND gate circuit, the output end of the first NOT gate circuit is connected to the third input end of the AND gate circuit, and the output end of the AND gate circuit is the output end of the judgment unit.
6. The test circuit according to claim 4, characterized in that: The ring oscillator comprises: a NAND gate circuit and a plurality of NAND gate units connected in sequence, wherein the input end of the ring oscillator is the first input end of the NAND gate circuit, and the output end of the first NAND gate unit among the plurality of NAND gate units is connected to the input end of the second NAND gate unit; The output end of the NAND gate circuit is connected to the input end of the first NAND gate unit among the multiple NAND gate units, the output end of the last NAND gate unit among the multiple NAND gate units is connected to the second input end of the NAND gate circuit, and the output end of the ring oscillator is the output end of the last NAND gate unit.
7. The test circuit according to claim 6, characterized in that: The NOT gate unit comprises: a second NOT gate circuit and a third NOT gate circuit; The input end of the NOT gate unit includes: the input end of the second NOT gate circuit and the input end of the third NOT gate circuit, and the output end of the second NOT gate circuit is the output end of the NOT gate unit.
8. The test circuit according to claim 1, characterized in that: The sequential logic test module comprises: a first multiplexer, a second multiplexer, a first buffer, a second buffer, and a plurality of delay modules connected in sequence; the input end of the sequential logic test module comprises: an input end of the first multiplexer and an input end of the second multiplexer; a first output end and a second output end of a previous delay module among the plurality of delay modules are respectively connected to a first input end and a second input end of a subsequent delay module; The output end of the first multiplexer is connected to the input end of the first buffer, and the output end of the first buffer is connected to the first input end of the first delay module among the plurality of delay modules; The output end of the second multiplexer is connected to the input end of the second buffer, and the output end of the second buffer is connected to the second input end of the first delay module; The third output ends of the plurality of delay modules are output ends of the sequential logic test module.
9. The test circuit according to claim 8, characterized in that: The delay module includes: a data delay unit, a clock delay unit and a second sequential logic unit to be tested; the data delay unit includes: a plurality of first combinational logic units connected in series, and the clock delay unit includes: a plurality of second combinational logic units connected in series; The input end of the first first combinational logic unit among the plurality of the first combinational logic units is the first input end of the delay module, and the input end of the first second combinational logic unit among the plurality of the second combinational logic units is the second input end of the delay module; The output end of the last of the first combinational logic units among the plurality of the second combinational logic units is the first output end of the delay module, and the output end of the last of the second combinational logic units among the plurality of the second combinational logic units is the second output end of the delay module; The output end of the last one of the first combinational logic units and the output end of the last one of the second combinational logic units are respectively connected to the data input end and the clock input end of the second sequential logic unit to be tested, and the output end of the second sequential logic unit to be tested is the third output end of the delay module.
10. The test circuit according to claim 1, characterized in that: The output module includes: a combinational logic output module and a sequential logic output module; The output end of the combinational logic test module is connected to the input end of the combinational logic output module to output the first result signal to the input end of the combinational logic output module according to the first test signal, and the output end of the combinational logic output module is used to output the first test result according to the first result signal; The output end of the sequential logic test module is connected to the input end of the sequential logic output module to output the second result signal to the input end of the sequential logic output module according to the second test signal, and the output end of the combinational logic output module is used to output the second test result according to the second result signal; The test results include: the first test result and the second test result.
11. The test circuit according to claim 10, characterized in that: The combinational logic output module comprises: a third multiplexer; an input end of the third multiplexer is an input end of the combinational logic output module, an output end of the third multiplexer is an output end of the combinational logic output module, and the third multiplexer is used to determine the first test result from a plurality of the first result signals according to the first test signal; The sequential logic output module includes: a fourth multiplexer; an input end of the fourth multiplexer is an input end of the sequential logic output module, an output end of the fourth multiplexer is an output end of the sequential logic output module, and the fourth multiplexer is used to determine the second test result from a plurality of second result signals according to the second test signal.
12. A test method based on a test circuit, characterized in that: Applied to the test circuit according to any one of claims 1 to 11 above, the method comprises: Obtaining post-silicon test results of a physical circuit built based on the test circuit; Obtaining simulator test results of the test circuit and timing results of back-annotation analysis; According to the post-silicon test results, the simulator test results and the timing results of the back-label analysis, determine whether the timing of the target unit in the standard cell library is accurate, wherein the combinational logic test module and the sequential logic test module include the target unit, and the target unit in the standard cell library includes: a combinational logic unit and / or a sequential logic unit.
13. The method according to claim 12, characterized in that The obtaining of a post-silicon test result of a physical circuit constructed based on the test circuit comprises: Generate a test chain index according to the preset measurement method; According to the test chain index, the combinational logic test module and the sequential logic test module in the physical circuit are tested to obtain the post-silicon test result.