Digital auxiliary analog off-chip capacitor-free low dropout linear regulator

Abstract

The invention belongs to the field of power management in analog integrated circuits, and particularly relates to a digital auxiliary analog low dropout regulator without an off-chip capacitor. Comprising a control module, a band-gap reference circuit, a transient enhancement circuit, a transient enhancement power tube group, an analog loop and a digital loop, in a load steady state, an analog LDO is adopted as a main control scheme, a high-gain amplifier can obtain accurate output voltage, and limit cyclic oscillation does not occur. A digital LDO is called as a main control scheme only when a load transient occurs, so that the speed is increased, the quiescent current is reduced, and the switching noise is suppressed. On-chip integration, high-precision output voltage, wide load current range, fast transient response speed, high-efficiency power tube area utilization rate and low output ripple can be realized. The circuit is suitable for SoC modular power management and digital IP load.

Description

Technical Field

[0001] The invention belongs to the field of power management in analog integrated circuits, and in particular relates to a digital-assisted analog low-voltage difference linear regulator without external capacitors. Background Art

[0002] As the integration of electronic systems becomes higher and higher, modern system-on-chip (SOC) power supply systems present a multi-voltage domain design, and the corresponding power management chip types are also increasing. Among them, the traditional low-dropout linear regulator (LDO) is a common step-down chip, which is widely used in various small circuits and as an on-chip regulator. Among them, the traditional analog LDO is the most widely used, which can provide good noise performance, good power supply rejection ratio, and a small layout area.

[0003] However, traditional analog circuits cannot benefit from advanced CMOS processes and are incompatible with standard digital design processes. Under advanced processes, the error amplifier of analog LDO is affected by low power supply voltage and has disadvantages such as small intrinsic gain of MOS tube and small output swing. In order to solve the defects of traditional analog LDO, digital LDO was proposed. Unlike traditional analog LDO, it can operate under low threshold voltage or subthreshold conditions, and digital LDO can be designed according to standard digital design processes and can be integrated with other digital modules. Digital LDO has the characteristics of low power consumption and scalability, but the ripple suppression effect of power supply is poor and the output accuracy is low.

[0004] The digital-analog hybrid LDO combines the technical features of the analog LDO and the digital LDO to achieve higher performance and more flexible voltage stable output. For example, Chinese patent CN117631735A proposes an analog-digital dual-loop LDO circuit, which adopts the form of a digital loop and an analog loop, and divides the power tube into an analog power tube and a digital power tube, solving the loop stability problem of the existing LDO circuit without external capacitors, and making corresponding improvements in large load current, stability and transient response. For example, Chinese patent CN118399966A proposes an analog-digital hybrid LDO circuit based on a switched capacitor integral loop and its working method. This scheme realizes a large load under ultra-low voltage through a digital loop in a stable working state, and replaces the locked digital loop with an analog loop in a stable working state to obtain a lower output ripple. However, these solutions cannot better solve the fast transient response, and have disadvantages such as slow transient recovery time. Summary of the invention

[0005] The present invention discloses a digital-assisted analog low-voltage dropout linear regulator without external capacitors. The low-voltage dropout linear regulator adopts a dual-loop structure hybrid solution to take into account the advantages of both digital LDO and analog LDO, make up for the relative shortcomings, and does not require large external capacitors. It can achieve on-chip integration, high-precision output voltage, wide load current range, fast transient response, high-efficiency power tube area utilization, and low output ripple. In view of the various defects of traditional analog LDO circuits and digital LDO circuits, the present invention proposes a digital-assisted analog low-voltage dropout linear regulator without external capacitors. The digital-analog hybrid LDO circuit can be applied to SoC modular power management and digital IP loads.

[0006] The objective of the present invention is achieved through the following technical solutions:

[0007] A digitally assisted analog low-voltage dropout linear regulator without external capacitors comprises a control module, a bandgap reference circuit, a transient enhancement circuit, a transient enhancement power tube group, an analog loop and a digital loop;

[0008] The bandgap reference circuit outputs four reference voltages VREF, VREFH, VREFL, VRFB and an enable signal EN;

[0009] The control module inputs three reference voltages VREF, VREFH, VREFL, two enable signals EN, EN3 and a clock signal CLK, and outputs four control signals VOH, VOL, COMP_OUT, RSTN and one enable signal;

[0010] The digital loop inputs four control signals VOH, VOL, COMP_OUT, and RSTN, and outputs a voltage signal VOUT;

[0011] The analog loop inputs a reference voltage VRFB and outputs a voltage signal VOUT;

[0012] The transient enhancement circuit inputs a voltage signal VOUT and an enable signal EN2, and outputs an enable signal EN3 and a control signal S;

[0013] The transient enhancement power tube group inputs a control signal S and outputs a voltage signal VOUT.

[0014] Furthermore, the analog loop includes an error amplifier EA, a PMOS tube, load resistors R1, R2 and a load capacitor CL; the non-inverting input end of the error amplifier EA is connected to the resistor R1 and one end of the resistor R2, the inverting input end of the error amplifier EA is connected to the reference voltage VRFB, the output end of the error amplifier EA is connected to the gate of the PMOS tube, the source of the PMOS tube is connected to the power supply voltage VDD, the drain of the PMOS tube is connected to the other end of the resistor R1 and one end of the capacitor CL, and the other end of the resistor R2 and the other end of the capacitor CL are grounded GND.

[0015] Furthermore, the digital loop includes a coarse adjustment logic circuit and a corresponding coarse adjustment power tube group, and a fine adjustment logic circuit and a corresponding fine adjustment power tube group; the coarse adjustment logic circuit inputs four control signals VOH, VOL, COMP_OUT, and RSTN, and outputs an enable signal EN1 and a coarse adjustment control signal C; the coarse adjustment power tube group inputs the coarse adjustment control signal C to control the number of coarse adjustment power tube groups that are turned on, thereby outputting a voltage signal VOUT; the fine adjustment logic circuit inputs four control signals VOH, VOL, COMP_OUT, RSTN and an enable signal EN1, and outputs a control signal X; the fine adjustment power tube group inputs the control signal X to control the number of fine adjustment power tube groups that are turned on, thereby outputting a voltage signal VOUT.

[0016] Further, the coarse adjustment power tube group includes: taking the minimum width-to-length ratio power tube as a basic unit, according to the binary and multi-unit arrangement and combination, the number ratio of the first N power tube groups is in accordance with the binary ratio 2 0 ,2 1 ,…,2 N-1 Increase in sequence; the ratio of the number of power tube groups in the middle K position is in accordance with the binary ratio 2 N Remain unchanged; the ratio of the number of power tube groups in the last N digits is in accordance with the binary ratio 2 N-1 ,…,2 1 ,2 0 Decrease successively; K≥2, N≥2.

[0017] Furthermore, the fine-tuning logic circuit is a multi-bit shift register, and the fine-tuning power tube group is a power tube with a corresponding number of bits.

[0018] Further, the control module includes three comparators COMP1, COMP2, and COMP3. Comparator COMP1 compares the magnitude of the output voltage VOUT with the expected value VREF. When VOUT > VREF, COMP_OUT outputs a high level; when VOUT < VREF, COMP_OUT outputs a low level. The comparators COMP2, COMP3, and an exclusive-OR gate form a dead zone controller. When VREFH > VOUT > VREFL, VOH outputs a low level, VOL outputs a high level, and RSTN outputs a high level. When VOUT > VREFH > VREFL, VOH outputs a high level, VOL outputs a high level, and RSTN outputs a low level. When VREFH > VREFL > VOUT, VOH outputs a low level, VOL outputs a low level, and RSTN outputs a low level. When the signal EN3 is pulled from a high level to a low level, RSTN outputs a low level.

[0019] Further, the transient enhancement circuit includes resistors R11, R12, RC, capacitor Cc, NAND gate AND, power transistor M1, and power transistor M2. One end of resistor R12 is connected to the power supply voltage VDD, the other end of resistor R12 is connected to one end of RC and one end of R11, the other end of R11 is grounded to GND, the other end of resistor RC is connected to capacitor Cc and one input terminal of NAND gate AND, and the other end of capacitor Cc outputs a voltage signal VOUT. The other input terminal of the NAND gate is connected to the EN2 enable signal, the output terminal of the NAND gate is connected to the bases of power transistor M1 and power transistor M2, and the gates of power transistor M1 and power transistor M2 output a control signal S. The source of power transistor M1 is connected to the power supply voltage VDD, and the source of power transistor M2 is grounded to GND.

[0020] Further, the operation processes of the digital loop and the analog loop include:

[0021] When RSTN is pulled from a high level to a low level, the coarse-tuning logic circuit and the fine-tuning logic circuit are initialized simultaneously, and all power transistors are not conducting. The coarse-tuning logic circuit uses a successive approximation search algorithm to achieve the conduction of the coarse-tuning power transistor group by increasing the search step size smoothly in binary.

[0022] When VOUT > VREFL, the coarse-tuning logic circuit stops increasing the search step size.

[0023] When VOUT > VREFH and EN3 is at a low level, a transient event is triggered, and the coarse-tuning logic circuit starts searching from the highest step size for the search step size.

[0024] When VREF>VOUT>VREFL, the coarse adjustment logic circuit will stop the conduction of the new coarse adjustment power tube group and keep the turned-on coarse adjustment power tube group. At this time, the fine adjustment logic circuit starts to work. At each rising edge of the clock, a unary shift register is used to search and turn on a fine adjustment power tube to provide fine adjustment current.

[0025] When VOUT>VREF, the fine-tuning logic circuit turns off the fine-tuning power tube that was turned on by the rising edge of the clock just before. The fine-tuning logic circuit will maintain the current state and will not turn on the subsequent power tubes again. The turned-on fine-tuning power tube group will be kept on. Finally, the analog loop will be enabled, which will provide compensation current to suppress ripple.

[0026] Beneficial effects of the present invention:

[0027] The present invention proposes a novel dual-loop digital-analog hybrid LDO circuit without off-chip capacitors, which adopts a dual-loop structure hybrid solution. Under load steady state, an analog LDO is used as the main control solution, and the analog loop provides fine-tuning current. The high-gain amplifier can obtain accurate output voltage, and no limit cycle oscillation occurs. The digital LDO is called as the main control solution only when the load transient occurs. The digital loop provides coarse-tuning current, and a hybrid algorithm based on successive approximation search and unary shift register search is adopted to quickly open or close the power tube in a short time to match the transient change of the load current; the hybrid algorithm can increase the speed, reduce the quiescent current and suppress the switching noise. On-chip integration, high-precision output voltage, wide load current range, fast transient response speed, high-efficiency power tube area utilization, and low output ripple can be achieved. The circuit can be applied to SoC modular power management and digital IP loads. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 This is an overall framework diagram of a digitally assisted analog low voltage drop linear regulator without external capacitors according to an embodiment of the present invention;

[0029] Figure 2 is a schematic diagram of the internal structure of a control module according to an embodiment of the present invention;

[0030] Figure 3 is a schematic diagram of the structure of a transient enhancement circuit according to an embodiment of the present invention;

[0031] Figure 4 is a coarse adjustment state transition diagram of an embodiment of the present invention;

[0032] Figure 5 is a schematic diagram of the working output state of each load in an embodiment of the present invention;

[0033] Figure 6 3 is a transient process comparison diagram of an embodiment of the present invention. DETAILED DESCRIPTION

[0034] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0035] It should be noted that, since the embodiments of the present invention focus on the current or voltage of the signal, the current or voltage input / output of each module / unit / device is used for description herein, and it should be understood by those skilled in the art that, in fact, the input / output of each module / unit / device is a signal. In order to make the technical means and creative features of the present invention easy to understand, the present invention is further described in conjunction with the accompanying drawings.

[0036] like Figure 1 As shown, a digital-assisted analog low-voltage dropout linear regulator without external capacitors includes a control module, a bandgap reference circuit, a transient enhancement circuit, a transient enhancement power tube group, an analog loop and a digital loop; the reference bandgap circuit generates four reference voltages, which are respectively used to control the operation of the digital loop and the analog loop; the transient enhancement circuit detects the output voltage of the digital loop and the analog loop, outputs a signal to turn on the transient enhancement power tube group completely or partially, and outputs a signal to operate the control module; the control module combines the reference voltage with the clock signal and the enable signal to turn on the coarse adjustment power tube group and / or the fine adjustment power tube group completely or partially; the analog loop provides a compensation current to the output voltage of the digital loop and the analog loop.

[0037] In the embodiment of the present invention, VDD (1.2V) is the power supply of the circuit, and VOUT (0.9V) is the stable output voltage of the digital-analog hybrid LDO.

[0038] In an embodiment of the present invention, the bandgap reference circuit outputs four reference voltages VREF, VREFH, VREFL, VRFB and an enable signal EN; the input signal of the bandgap reference circuit may be a power supply voltage VDD, which can drive the bandgap reference circuit to start, and is used to wake up the bandgap reference circuit from a sleep state and start normal operation; of course, the input signal of the bandgap reference circuit may be a control signal, and these control signals may come from an external circuit, such as a digital circuit or an analog circuit, and are used to adjust the output voltage of the bandgap reference circuit according to specific needs; the input signal of the bandgap reference circuit may also be a temperature sensing signal, which is used to monitor changes in ambient temperature in real time, and compensate for the influence of temperature on the output reference voltage by adjusting the internal circuit.

[0039] In some embodiments of the present invention, the bandgap reference module generates four reference voltages VRFB (800 mV), VREFL (870 mV), VREF (900 mV), and VREFH (930 mV). VRFB is output to the error amplifier of the analog loop as the reference voltage of the analog loop, and VREFL, VREFH, and VREF are output to the control module as the reference voltages of the digital loop. The power supply voltage of the entire bandgap reference is VDD (1.2V). Only when the VDD voltage is successfully powered up to a certain voltage can these four reference voltages be generated normally. When the power supply voltage VDD reaches 1.2V, the bandgap reference module outputs a signal EN, which is pulled from low level to high level, indicating that the power-on is completed.

[0040] In an embodiment of the present invention, the control module inputs three reference voltages VREF, VREFH, VREFL, two enable signals EN, EN3, and a clock signal CLK, and outputs four control signals VOH, VOL, COMP_OUT, RSTN, and one enable signal; the CLK clock of the control module is 50 MHz, and the control module can work normally only when EN is valid.

[0041] In some embodiments of the present invention, the internal structure of the control module is as Figure 2 shown. The comparator COMP1 compares the magnitude of the output voltage VOUT with the expected value VREF. When VOUT > VREF, COMP_OUT outputs a high level; when VOUT < VREF, COMP_OUT outputs a low level. The comparator COMP2, COMP3, and an exclusive-OR gate form a dead zone controller to effectively suppress the limit cycle oscillation. When VREFH > VOUT > VREFL, VOH outputs a low level, VOL outputs a high level, and RSTN outputs a high level; when VOUT > VREFH > VREFL, VOH outputs a high level, VOL outputs a high level, and RSTN outputs a low level; when VREFH > VREFL > VOUT, VOH outputs a low level, VOL outputs a low level, and RSTN outputs a low level. In addition, when the signal EN3 is pulled from high level to low level, RSTN outputs a low level.

[0042] In some embodiments of the present invention, as Figure 3As shown, the transient enhancement circuit includes resistors R11, R12, RC, capacitor Cc, NAND gate AND, power tube M1 and power tube M2; wherein, one end of the resistor R12 is connected to the power supply voltage VDD, the other end of the resistor R12 is connected to one end of RC and one end of R11, the other end of R11 is grounded GND, the other end of the resistor RC is connected to the capacitor Cc and an input end of the NAND gate AND, and the other end of the capacitor Cc outputs a voltage signal VOUT; the other input end of the NAND gate is connected to the EN2 enable signal, the output end of the NAND gate is connected to the base of the power tube M1 and the power tube M2, and the gate of the power tube M1 and the power tube M2 outputs a control signal S; the source of the power tube M1 is connected to the power supply voltage VDD, and the source of the power tube M2 is grounded GND.

[0043] It should be noted that the transient enhancement circuit mainly provides an asynchronous undershoot detection signal to enhance the transient response. When the load jumps and causes the output voltage to undershoot, the voltage at the FB point drops below the set threshold, causing the NAND gate output to be pulled high, causing M2 to be turned on, and the corresponding S signal is converted from a high level state to a low level state, and asynchronously triggers the transient enhancement power tube group to be asynchronously turned on to suppress the change in the output voltage. EN2 is an enable signal, and a high level is valid.

[0044] In an embodiment of the present invention, the digital loop inputs four control signals VOH, VOL, COMP_OUT, and RSTN, and outputs a voltage signal VOUT; the digital loop includes a coarse adjustment logic circuit and a corresponding coarse adjustment power tube group, and a fine adjustment logic circuit and a corresponding fine adjustment power tube group; the coarse adjustment logic circuit inputs four control signals VOH, VOL, COMP_OUT, and RSTN, and outputs an enable signal EN1 and a coarse adjustment control signal C; the coarse adjustment power tube group inputs the coarse adjustment control signal C to control the number of coarse adjustment power tube groups turned on, thereby outputting a voltage signal VOUT; the fine adjustment logic circuit inputs four control signals VOH, VOL, COMP_OUT, and RSTN and an enable signal EN1, and outputs a control signal X; the fine adjustment power tube group inputs the control signal X to control the number of fine adjustment power tube groups turned on, thereby outputting a voltage signal VOUT.

[0045] In the embodiment of the present invention, the coarse adjustment power tube group is arranged and combined according to binary and multiple unary, and the number ratio of the first N power tube groups is arranged according to the binary ratio 2 0 ,2 1 ,…,2 N-1 Increase in sequence; the ratio of the number of power tube groups in the middle K position is in accordance with the binary ratio 2 N Remain unchanged; the ratio of the number of power tube groups in the last N digits is in accordance with the binary ratio 2 N-1 ,…,2 1 ,2 0 Decrease successively. K≥2, N≥2.

[0046] It can be understood that the present invention arranges the coarse-tuning power tube group in binary and multi-unary combinations. This method can flexibly meet the output requirements of different power levels by adjusting the number, arrangement and control strategy of the power tubes; utilizes a hybrid algorithm based on successive approximation search and unary shift register search to quickly open or close the power tube in a short time to match the transient changes of the load current; and solves the problems of fast transient response and slow transient recovery time.

[0047] In some embodiments of the present invention, the minimum size of the power transistor is 0.8 / 0.06, both in μm, and the coarse adjustment power tube group arrangement scheme is arranged in binary and multiple unary combinations. For example, if N=5, the ratio of the number of power tube groups in the first five digits and the last five digits is 1:2:4:8:16, and the ratio of the number of power tube groups in the middle digits is 32. In an embodiment of the present invention, the digital loop adopts a hybrid algorithm of successive approximation search and unary shift register search to achieve an optimal trade-off between voltage accuracy and stabilization time. The current that the minimum size digital power tube can provide is I LSB , the current provided by the analog loop is I A , for any given load current I L , there is always I L =I A +aI LSB +bI LSB , where aI LSB To fine-tune the current provided by the power tube group, bI LSB The current provided by the coarse adjustment power tube group, I A The current provided to the analog loop, I A Always greater than I LSB , parameter a represents the number of bits of the fine-tuning power tube group that are turned on, and parameter b represents the number of power tubes with the minimum aspect ratio that are turned on in the coarse-tuning power tube group.

[0048] Among them, successive approximation search and univariate shift register search are two different optimization algorithms. The global search capability of successive approximation search and the local search capability of univariate shift register search are combined. Such a hybrid algorithm can use the successive approximation method in the search space to roughly determine the corresponding power tube, and then use the univariate shift register method to more finely determine the corresponding power tube, which is easier to compensate the loop current. In an embodiment of the present invention, the control module and the digital loop are composed of a digital logic control unit, and the digital logic control unit is synthesized, automatically laid out and wired according to the standard digital design process.

[0049] In the embodiment of the present invention, the coarse adjustment module includes a coarse adjustment logic circuit and a corresponding coarse adjustment power tube group, the fine adjustment module includes a fine adjustment logic circuit and a corresponding fine adjustment power tube group, and the state transition of the coarse adjustment module (SAR logic) is as follows: Figure 4 As shown in the figure, when RSTN is pulled from high level to low level, the coarse adjustment module and the fine adjustment module are initialized at the same time, and all power tubes are not turned on. The black arrow line indicates that the coarse adjustment module performs a normal successive approximation search algorithm state, with a smooth binary increase in search step. Only when VOUT>VREFL will the search step increase stop; the sparse dotted arrow indicates that the transient event triggers the conversion. Only when VOUT>VREFH and EN3 is low level, the transient event will be triggered, and the search step will start from the highest step; the dense dotted arrow indicates the state transition from the coarse adjustment module to the fine adjustment module. Only when VREF>VOUT>VREFL, the coarse adjustment state will turn to the fine adjustment state.

[0050] In some embodiments, the fine-tuning module is composed of a 24-bit shift register, and the 24-bit signal controls 24 small-sized power tubes. When the loop state enters the fine-tuning mode, each rising edge of the clock will turn on a fine-tuning power tube. When VOUT>VREF, the fine-tuning power tube turned on by the previous clock will be turned off. The fine-tuning module will maintain the current state and will no longer turn on the subsequent power tube. The analog loop will compensate for the subsequent current to achieve the purpose of precise output voltage, thereby effectively reducing the output ripple.

[0051] In some embodiments of the present invention, taking the minimum aspect ratio power tube as 1 basic unit of quantity, the number of power tube groups for each bit of fine-tuning power tube group is M, the number of power tube groups for the analog power tube group (transient enhancement power tube group) is N (the load capacity must be greater than the load capacity of the minimum aspect ratio power tube), and the number of power tube groups for the transient enhancement power tube group is K.

[0052] In some embodiments, the minimum size of the power transistor is 0.8 / 0.06, both in μm, the number of power tube groups per bit of the 24-bit fine-tuning power tube group is 24 minimum-size power tubes, the number of power tube groups of the analog power tube group is 40 minimum-size power tubes, and the number of power tube groups of the transient enhancement power tube group is 40 minimum-size power tubes.

[0053] It should be noted that in the embodiment of the present invention, the power tube controlled by the digital loop is referred to as the digital power tube, and the power tube driven by the analog loop or the error amplifier is referred to as the analog power tube; there is no essential difference between these analog power tubes and digital power tubes, they are all power tubes, but their number is different; by dynamically adjusting the number of power tubes turned on or off to match the transient changes of the load current, the speed is improved, the quiescent current is reduced and the switching noise is suppressed.

[0054] In some embodiments of the present invention, the analog loop is similar to a traditional analog LDO, and may also include an error amplifier EA, a PMOS tube, load resistors R1, R2, and a load capacitor CL; the non-inverting input of the error amplifier EA is connected to the resistor R1 and one end of the resistor R2, the inverting input of the error amplifier EA is connected to the reference voltage VRFB, the output of the error amplifier EA is connected to the gate of the PMOS tube, the source of the PMOS tube is connected to the power supply voltage VDD, the drain of the PMOS tube is connected to the other end of the resistor R1 and one end of the capacitor CL, and the other end of the resistor R2 and the other end of the capacitor CL are grounded GND. The analog loop automatically detects the output voltage VOUT through the resistor divider formed by the resistor R1 and the resistor R2, and the error amplifier EA continuously adjusts the current source I L In order to maintain the output voltage VOUT stable at the rated voltage, the present invention further adds a control module, a bandgap reference circuit, a transient enhancement circuit, a transient enhancement power tube group and a digital loop structure on top of the traditional analog LDO circuit. The analog LDO is used as the main control scheme under load steady state, and the high-gain amplifier can obtain an accurate output voltage without limit cycle oscillation. The digital LDO is called as the main control scheme only when the load transient occurs to increase the speed, reduce the quiescent current and suppress the switching noise.

[0055] like Figure 5 As shown in the figure, the working state of the entire dual-loop digital-analog hybrid LDO circuit under different current load conditions is illustrated. At the beginning of power-on, the entire digital loop does not work, and only the analog loop provides a small amount of current. When power-on is completed, the digital loop starts to work and enters the coarse adjustment mode for a fast search. The output voltage fluctuates greatly. When entering the fine adjustment mode, it can be seen that the difference between the output voltage and the expected value is already very small, and it only takes a few clock cycles to complete. Finally, it enters the fine adjustment mode, and the analog loop compensates the current. The entire working time is <2μs, and the output ripple is <2mv.

[0056] like Figure 6 As shown, the transient response process under different mechanisms is illustrated. The comparison shows that the transient enhancement circuit can significantly suppress the undershoot voltage, and the transient event triggering mechanism can improve the system stability and effectively suppress the overshoot and undershoot voltage. The above shows that the proposed dual-loop non-external capacitor digital-analog hybrid LDO circuit has been effectively verified.

[0057] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A digitally assisted analog low voltage drop linear regulator without external capacitor, characterized in that: It includes a control module, a bandgap reference circuit, a transient enhancement circuit, a transient enhancement power tube group, an analog loop and a digital loop; The bandgap reference circuit outputs four reference voltages VREF, VREFH, VREFL, VRFB and an enable signal EN; The control module inputs three reference voltages VREF, VREFH, VREFL, two enable signals EN, EN3 and a clock signal CLK, and outputs four control signals VOH, VOL, COMP_OUT, RSTN and one enable signal; The digital loop inputs four control signals VOH, VOL, COMP_OUT, and RSTN, and outputs a voltage signal VOUT; The analog loop inputs a reference voltage VRFB and outputs a voltage signal VOUT; The transient enhancement circuit inputs a voltage signal VOUT and an enable signal EN2, and outputs an enable signal EN3 and a control signal S; The transient enhancement power tube group inputs a control signal S and outputs a voltage signal VOUT.

2. The digitally assisted analog low voltage dropout linear regulator without external capacitor according to claim 1, characterized in that: The analog loop includes an error amplifier EA, a PMOS tube, load resistors R1, R2 and a load capacitor CL; the non-inverting input end of the error amplifier EA is connected to the resistor R1 and one end of the resistor R2, the inverting input end of the error amplifier EA is connected to the reference voltage VRFB, the output end of the error amplifier EA is connected to the gate of the PMOS tube, the source of the PMOS tube is connected to the power supply voltage VDD, the drain of the PMOS tube is connected to the other end of the resistor R1 and one end of the capacitor CL, and the other end of the resistor R2 and the other end of the capacitor CL are grounded GND.

3. The digitally assisted analog low voltage dropout linear regulator without external capacitor according to claim 1, characterized in that: The digital loop includes a coarse adjustment logic circuit and a corresponding coarse adjustment power tube group, and a fine adjustment logic circuit and a corresponding fine adjustment power tube group; the coarse adjustment logic circuit inputs four control signals VOH, VOL, COMP_OUT, and RSTN, and outputs an enable signal EN1 and a coarse adjustment control signal C; the coarse adjustment power tube group inputs the coarse adjustment control signal C to control the number of coarse adjustment power tube groups that are turned on, thereby outputting a voltage signal VOUT; the fine adjustment logic circuit inputs four control signals VOH, VOL, COMP_OUT, RSTN and an enable signal EN1, and outputs a control signal X; the fine adjustment power tube group inputs the control signal X to control the number of fine adjustment power tube groups that are turned on, thereby outputting a voltage signal VOUT.

4. The digitally assisted analog low voltage dropout linear regulator without external capacitor according to claim 3, characterized in that: The coarse adjustment power tube group includes: taking the minimum width-to-length ratio power tube as a basic unit, according to binary and multi-unit arrangement and combination, the number ratio of the first N power tube groups is in accordance with the binary ratio 2 0 ,2 1 ,…,2 N-1 Increase in sequence; the ratio of the number of power tube groups in the middle K position is in accordance with the binary ratio 2 N Remain unchanged; the ratio of the number of power tube groups in the last N digits is in accordance with the binary ratio 2 N -1 ,…,2 1 ,2 0 Decrease successively; K≥2, N≥2.

5. The digitally assisted analog low voltage dropout linear regulator without external capacitor according to claim 3, characterized in that: The fine-tuning logic circuit is a multi-bit shift register, and the fine-tuning power tube group is a power tube with a corresponding number of bits.

6. The digitally assisted analog low voltage dropout linear regulator without external capacitor according to claim 1, characterized in that: The control module includes three comparators COMP1, COMP2, and COMP3. Comparator COMP1 compares the magnitude of the output voltage VOUT and the expected value VREF. When VOUT > VREF, COMP_OUT outputs a high level; when VOUT < VREF, COMP_OUT outputs a low level. The comparators COMP2, COMP3, and an exclusive-OR gate form a dead zone controller. When VREFH > VOUT > VREFL, VOH outputs a low level, VOL outputs a high level, and RSTN outputs a high level. When VOUT > VREFH > VREFL, VOH outputs a high level, VOL outputs a high level, and RSTN outputs a low level. When VREFH > VREFL > VOUT, VOH outputs a low level, VOL outputs a low level, and RSTN outputs a low level. When the signal EN3 is pulled from a high level to a low level, RSTN outputs a low level.

7. The digitally assisted analog low voltage dropout linear regulator without external capacitor according to claim 1, characterized in that: The transient enhancement circuit includes resistors R11, R12, RC, capacitor Cc, NAND gate AND, power transistor M1, and power transistor M2. One end of resistor R12 is connected to the power supply voltage VDD, the other end of resistor R12 is connected to one end of RC and one end of R11, the other end of R11 is grounded to GND, the other end of resistor RC is connected to capacitor Cc and one input terminal of NAND gate AND, and the other end of capacitor Cc outputs a voltage signal VOUT. The other input terminal of the NAND gate is connected to the EN2 enable signal, the output terminal of the NAND gate is connected to the bases of power transistor M1 and power transistor M2, and the gates of power transistor M1 and power transistor M2 output a control signal S. The source of power transistor M1 is connected to the power supply voltage VDD, and the source of power transistor M2 is grounded to GND.

8. A digitally assisted analog low voltage dropout linear regulator without external capacitor according to any one of claims 1 to 7, characterized in that: The operation processes of the digital loop and the analog loop include: When RSTN is pulled from a high level to a low level, the coarse adjustment logic circuit and the fine adjustment logic circuit are initialized simultaneously, and all power transistors are not conducting. The coarse adjustment logic circuit uses a successive approximation search algorithm to achieve the conduction of the coarse adjustment power transistor group according to a smooth binary increasing search step. When VOUT > VREFL, the coarse adjustment logic circuit stops increasing the search step. When VOUT > VREFH and EN3 is at a low level, a transient event is triggered, and the coarse adjustment logic circuit starts searching from the highest search step. When VREF > VOUT > VREFL, the coarse adjustment logic circuit stops the conduction of the new coarse adjustment power transistor group and maintains the conduction state of the already opened coarse adjustment power transistor group. At this time, the fine adjustment logic circuit starts to work. At each rising edge of the clock, a unary shift register search is used to turn on a fine adjustment power transistor to provide a fine adjustment current. When VOUT > VREF, the fine adjustment logic circuit turns off the fine adjustment power transistor opened at the previous rising edge of the clock. The fine adjustment logic circuit will maintain the current state and will not turn on the subsequent power transistors, maintaining the conduction state of the already opened fine adjustment power transistor group. Finally, the analog loop is enabled, and the analog loop will provide a compensation current to suppress the ripple.

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