Low dropout regulator with low power consumption and high performance

Abstract

The invention discloses a low dropout linear regulator with low power consumption and high performance. The low dropout linear regulator comprises a reference source circuit, a buffer circuit, a control circuit, a load circuit and an output control loop, the reference source circuit is connected to the buffer circuit, the buffer circuit outputs target voltage to the control circuit and feeds back the target voltage to the input end of the buffer circuit, and the control circuit generates control voltage to the output control loop and then outputs the control voltage to the load circuit; an output feedback stage sub-circuit in the output control loop is respectively connected with the control circuit and the output circuit and feeds back an output voltage to an amplification stage sub-circuit, and after the output voltage is amplified and gained by the amplification stage sub-circuit and a current buffer stage sub-circuit, the output voltage is close to a target voltage and is stably output. According to the technical scheme, the buffer circuit and the output circuit are completely separated through the output control loop, large stray capacitance at the input end of the buffer circuit and high output impedance at the output end of the buffer circuit are prevented from being introduced into the loop, and therefore the output bandwidth is increased, and the dynamic response is enhanced.

Description

Technical Field

[0001] The invention relates to the field of integrated circuits, and in particular to a low-power consumption and high-performance low voltage difference linear regulator. Background Art

[0002] Low dropout linear regulator (LDO) is very popular in portable devices, RF components, etc. due to its advantages such as low power consumption, low noise, fast dynamic response, simple circuit structure and low cost. However, the increasingly complex load environment makes the design of LDO more difficult. How to ensure that the circuit can have fast dynamic response while maintaining low power consumption is the key point of current circuit design.

[0003] In order to improve the dynamic response, the commonly used method is to add a FVF (Flipped voltage follower) structure to the LDO. This structure allows the change of the output voltage to be quickly transmitted to the output power tube gate, thereby regulating the output voltage and greatly improving the transient response. However, due to the small loop gain of the FVF structure, the accuracy of the output voltage is small, so it is often necessary to add a gain-enhancing circuit to the FVF loop. However, in reality, the introduction of the gain-enhancing circuit will limit the transient response of the LDO, and a more complex frequency compensation network is required to ensure the stability of the circuit. This increases the complexity of the circuit and the difficulty of design.

[0004] In some prior art, a source follower is inserted between the gain stage and the output power tube gate to isolate the high output impedance of the gain stage from the large capacitance of the power tube gate. The source follower has a small input capacitance and low output impedance, which can split a low-frequency pole into two higher-frequency poles, increase the bandwidth upper limit of the LDO, and enhance the dynamic response. However, the source follower will require the minimum input power supply voltage to be two MOS tubes Vgs. The wider the load current variation range, the greater the Vgs, resulting in a limited minimum input power supply voltage of the LDO. Summary of the invention

[0005] The main purpose of the present invention is to provide a low-power and high-performance low-dropout linear regulator, aiming to enhance the dynamic response of the LDO.

[0006] To achieve the above-mentioned purpose, the present invention provides a low-power consumption and high-performance low-voltage difference linear regulator, comprising a reference source circuit, a buffer circuit, a control circuit, a load circuit, and an output control loop connected to the load circuit; the reference source circuit is connected to the buffer circuit, the buffer circuit receives the reference voltage and performs buffer amplification, then outputs the target voltage to the control circuit and feeds back to the input end of the buffer circuit at the same time, the control circuit generates a stable control voltage to the output control loop, performs feedback amplification, and then outputs the voltage to the load circuit, so as to output the voltage to the subsequent circuit; The output control loop includes an amplifier stage subcircuit, a current buffer stage subcircuit and an output feedback stage subcircuit; the output feedback stage subcircuit is respectively connected to the control circuit and the output circuit to amplify the control voltage and output it to the load circuit. At the same time, the output voltage is fed back to the amplifier stage subcircuit. After amplification and gain improvement by the amplifier stage subcircuit and the current buffer stage subcircuit, the output voltage is close to the target voltage and maintains a stable output.

[0007] Preferably, the output feedback stage subcircuit is connected to the control circuit and the load circuit, and includes a first field effect transistor, a second field effect transistor and a first capacitor, the source of the first field effect transistor is connected to the input power supply, and the drain is connected to the source of the second field effect transistor and the output circuit; the gate of the second field effect transistor is connected to the control circuit, one end of the first capacitor is connected to the output circuit and the drain of the first field effect transistor and the source of the second field effect transistor, and the other end is connected to the drain of the second field effect transistor and the amplifier stage subcircuit.

[0008] Preferably, the amplifier stage subcircuit includes a first NMOS tube, the drain of the first NMOS tube is connected to the first bias current source and the current buffer stage subcircuit, the gate is connected to the second bias voltage, and the source is connected to the drain of the second field effect tube in the output feedback stage subcircuit and the third bias current source.

[0009] Preferably, the current buffer stage subcircuit comprises a first PMOS tube, a second PMOS tube, a second NMOS tube, a third NMOS tube, and a fourth NMOS tube; the gate of the first PMOS tube is connected to the drain of the first NMOS tube, the source is connected to the input power supply, and the drain is connected to the third bias current source and the gate of the second NMOS tube in the amplifier stage subcircuit; the source of the second PMOS tube is connected to the input power supply, the drain is connected to the drain of the third NMOS tube and the gates of the third NMOS tube and the fourth NMOS tube, and the gate is connected to the gate of the first field effect tube; the drain of the second NMOS tube is connected to the gate of the second PMOS tube and the gate of the first field effect tube in the output feedback stage subcircuit, the source is grounded, and the gate is connected to the drain of the first PMOS tube in the amplifier stage subcircuit; the gate and the drain of the third NMOS tube are connected to each other and to the gate of the fourth NMOS tube, and the source is grounded; the source of the fourth NMOS tube is grounded.

[0010] Preferably, the current buffer stage subcircuit also includes a group of PMOS field effect transistors, the sources of which are connected to the input power supply, the gates are respectively connected to the gates of the second PMOS tube and the gates of the first field effect tube, and the drains are respectively connected to the gates thereof and the drains of the second NMOS tube.

[0011] Preferably, the second PMOS tube and the PMOS field effect tube group form a current mirror, and the number ratio thereof is 1:K, where K is a positive integer, and its preferred range is 2-5.

[0012] Preferably, the second PMOS transistor and any field effect transistor in the PMOS field effect transistor group have the same size.

[0013] The technical solution of the present invention completely separates the buffer circuit and the output circuit through an output control loop. This structure avoids introducing large parasitic capacitance at the input end of the buffer circuit and high output impedance at the output end into the loop, so that the pole of the loop can be at a higher frequency, thereby increasing the output bandwidth and enhancing the dynamic response. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a schematic diagram of the principle of a low-power, high-performance low-dropout linear regulator according to an embodiment of the present invention; Figure 2 A schematic diagram of the circuit structure of an output control loop and a load circuit in a low-power, high-performance low-dropout linear regulator according to an embodiment of the present invention; Figure 3 This is a schematic diagram of a common FC FVF structure in the prior art.

[0015] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0016] It should be understood that the specific embodiments described herein are only used to explain the present invention, and are not used to limit the present invention.

[0017] The present invention is further described below in conjunction with the accompanying drawings.

[0018] The embodiment of the present invention provides a low-power and high-performance low-dropout linear regulator, such as Figure 1 As shown, it includes a reference source circuit, a buffer circuit, a control circuit, a load circuit, and an output control loop connected to the load circuit; the reference source circuit is connected to the buffer circuit, the buffer circuit receives the reference voltage and performs buffer amplification, then outputs the target voltage to the control circuit and feeds back to the input end of the buffer circuit at the same time, the control circuit generates a stable control voltage to the output control loop, which performs feedback amplification and then outputs to the load circuit, so as to output the voltage to the subsequent circuit; The output control loop includes an amplifier stage subcircuit, a current buffer stage subcircuit and an output feedback stage subcircuit; the output feedback stage subcircuit is respectively connected to the control circuit and the output circuit to amplify the control voltage and output it to the load circuit. At the same time, the output voltage is fed back to the amplifier stage subcircuit. After amplification and gain improvement by the amplifier stage subcircuit and the current buffer stage subcircuit, the output voltage is close to the target voltage and maintains a stable output.

[0019] The working principle of the embodiment of the present invention is as follows: the reference voltage is passed through the buffer circuit to obtain the target voltage, the target voltage generates a stable control voltage Vctrl through the control circuit, and is fed back to the input end of the buffer circuit; the control voltage Vctrl is input to the load circuit via the output control loop, and at the same time, the difference between the output voltage of the load circuit and the target voltage is amplified by the output control loop, reducing the difference between the output voltage Vout and the target voltage, so that the output voltage Vout approaches the target value and remains stable.

[0020] Specifically, the buffer circuit in the embodiment of the present invention feeds back the target voltage of its output to its input end to form the first loop of the present invention, the buffer loop; the output control loop constitutes the second loop of the present invention. This embodiment completely separates the buffer circuit and the output circuit through the output control loop to form two control loops; wherein, the buffer loop of the front stage adjusts the target voltage size according to demand during the actual working process; the output control loop of the rear stage reduces the difference between the output voltage Vout and the target voltage, so that the output voltage Vout approaches the target value and remains stable. This structure avoids the introduction of large parasitic capacitance at the input end of the buffer circuit and high output impedance at the output end in the output control loop, so that the pole of the output control loop can be at a higher frequency, thereby increasing the output bandwidth and enhancing the dynamic response.

[0021] In some embodiments, Figure 2 As shown, the output feedback stage subcircuit is connected to the control circuit and the load circuit, including a first field effect transistor M1, a second field effect transistor M2 and a first capacitor Cc, the source of the first field effect transistor M1 is connected to the input power supply, and the drain is connected to the source of the second field effect transistor M2 and the output circuit; the gate of the second field effect transistor M2 is connected to the control circuit, one end of the first capacitor Cc is connected to the output circuit and the drain of the first field effect transistor M1, the source of the second field effect transistor M2, and the other end is connected to the drain of the second field effect transistor M2 and the amplifier stage subcircuit. Specifically, the load circuit includes a resistor RL and a capacitor CL, one end of the resistor RL and the capacitor CL are commonly connected to the source of the second field effect transistor M2, and the other end is grounded.

[0022] The embodiment of the present invention can improve the output voltage accuracy, linearity adjustment, load adjustment, power supply rejection ratio and other performances through the structure of the output feedback stage sub-circuit. The first capacitor Cc is a compensation capacitor of the circuit, which is used to improve the circuit stability.

[0023] In a specific embodiment, the first field effect transistor M1 and the second field effect transistor M2 are PMOS field effect transistors, wherein the first field effect transistor M1 is a power transistor.

[0024] The output feedback stage subcircuit can be implemented in other embodiments by using the FC FVF structure commonly used in the prior art, such as Figure 3 .

[0025] In some embodiments, Figure 2 As shown, the amplifier stage subcircuit includes a first NMOS tube MN1, the drain of the first NMOS tube MN1 is connected to the first bias current source VBC1 and the gate of the first PMOS tube MP1 in the current buffer stage subcircuit, the gate is connected to the second bias voltage VBC2, and the source is connected to the drain of the second field effect tube M2 in the output feedback stage subcircuit and the third bias current source VBC3. The first bias current source VBC1, the second bias voltage VBC2 and the third bias current source VBC3 are used to ensure the normal operation of the first NMOS tube MN1, and can be mirrored to the amplifier stage subcircuit through the preamble circuit.

[0026] In some embodiments, Figure 2 As shown, the current buffer stage subcircuit includes a first PMOS tube MP1, a second PMOS tube MP2, a second NMOS tube MN2, a third NMOS tube MN3, and a fourth NMOS tube MN4; the gate of the first PMOS tube MP1 is connected to the drain of the first NMOS tube MN1, the source is connected to the input power supply, and the drain is connected to the third bias current source in the amplifier stage subcircuit and the gate of the second NMOS tube MN2; the source of the second PMOS tube MP2 is connected to the input power supply, and the drain is connected to the drain of the third NMOS tube MN3 and the fourth NMOS tube MN4. The gates of the third NMOS tube MN3 and the fourth NMOS tube MN4 are connected to the gate of the first field effect tube M1; the drain of the second NMOS tube MN2 is connected to the gate of the second PMOS tube MP2 and the gate of the first field effect tube M1 in the output feedback stage sub-circuit, the source is grounded, and the gate is connected to the drain of the first PMOS tube MP1 in the amplifier stage sub-circuit; the gate of the third NMOS tube MN3 and its drain are connected to each other and to the gate of the fourth NMOS tube MN4, and the source is grounded; the source of the fourth NMOS tube MN4 is grounded; The current buffer stage subcircuit also includes a group of PMOS field effect transistors MPS0-MPSk, the source of which is connected to the input power supply, the gate is respectively connected to the gate of the second PMOS transistor MP2 and the gate of the first field effect transistor M1, and the drain is respectively connected to the gate thereof and the drain of the second NMOS transistor MN2. Figure 2 As shown, the figure of the embodiment of the present invention only lists the graph when the number of the PMOS field effect tube in the group is 1.

[0027] Specifically, the second PMOS tube MP2 and the PMOS field effect tube group MPS0-MPSk form a current mirror, the number ratio of which is 1:K, and the second PMOS tube MP2 and each field effect tube in the PMOS field effect tube group MPS0-MPSk have the same size. The current mirror with the same size and the number ratio of 1:K formed by the second PMOS tube MP2 and the PMOS field effect tube group MPS0-MPSk is used to reduce the no-load power consumption, and overcome the problem of insufficient input power supply voltage caused by components such as source followers in the buffer circuit, and improve the adaptability of the power supply. At the same time, mos tubes of the same size can achieve better matching. In addition, in order to better match the first field effect tube M1 in the output feedback stage sub-circuit, the number ratio of the second PMOS tube MP2, the PMOS field effect tube group MPS0-MPSk and the first field effect tube M1 is 1:K:N, and each mos tube in the first field effect tube M1 is also the same size as each field effect tube in the PMOS field effect tube group.

[0028] In the embodiment of the present invention, the second PMOS tube MP2, the PMOS field effect tube group MPS0-MPSk, the second NMOS tube MN2, the third NMOS tube MN3 and the fourth NMOS tube MN4 in the current buffer stage subcircuit constitute the third loop in the present invention, the negative feedback loop. Specifically, the voltage after the inversion amplification of the first PMOS tube MP1 reaches point D, and is converted into current by the second NMOS tube MN2, and is mirrored to the second PMOS tube MP2 by the PMOS field effect tube group, and the mirror ratio is K:1; the current of the second PMOS tube MP2 flows through the third NMOS tube MN3, and the third NMOS tube MN3 and the fourth NMOS tube MN4 form a 1:1 current mirror, that is, the current flows through the fourth NMOS tube MN4 back to point D, forming a loop. The negative feedback loop is used to reduce the gain of the circuit and improve the stability of the LDO.

[0029] In a specific embodiment, K is a positive integer, and its value range is 2 to 5. The value of K is determined by the maximum load current of the LDO and the stability of the negative feedback loop; the larger the load current, the larger the current passing through the PMOS field effect tube group, and when overloaded, the power consumption of the circuit will increase with the increase of the value of K; the gain of the negative feedback loop increases with the increase of the value of K, but the stability will decrease accordingly; in the embodiment of the present invention, the value of K is more preferably 3 or 4. When the value of K is 4, that is, the second PMOS tube MP2 and the field effect tube group form a 1:4 current mirror, so that the power consumption of the circuit will not be too high, and the gain of the negative feedback loop in the current buffer stage subcircuit is not large, and the stability is better.

[0030] In addition, since the gate of the first PMOS tube MP1 is connected to the first bias current source VBC1, when the circuit is in no-load state, the voltage negative feedback loop in the current buffer stage sub-circuit has almost zero power consumption, and the current of the first PMOS tube MP1 is determined by the first bias current source VBC1, thereby avoiding the problem of uncertain current in the amplifier stage where the first PMOS tube MP1 is located, and achieving low power consumption under no-load state.

[0031] At the same time, the output control loop of the embodiment of the present invention is provided with a current buffer stage subcircuit, and the negative output control loop nested in the current buffer stage subcircuit can increase the stability of the output control loop and improve the accuracy of the LDO output voltage Vout; in the current buffer stage subcircuit, the feedback voltage fed back by the second field effect tube M2 in the output feedback stage subcircuit and amplified by the first NMOS tube MN1 is received by the first PMOS tube MP1, and is synchronized to the second NMOS tube MN2, and the current mirror composed of the second PMOS tube MP2 and the PMOS field effect tube group, and then the second PMOS tube MP2 is mirrored to the first field effect tube M1 to adjust the output voltage Vout.

[0032] The working principle of the embodiment of the present invention is: like Figure 2 As shown, when the output voltage Vout of the low voltage difference linear regulator increases, the current flowing through the second field effect transistor M2 increases. Since the current of the third bias current source VBC3 remains unchanged, the current flowing into point A through the first NMOS transistor MN1 becomes smaller. At the same time, since the current flowing into point B from the first bias current source VBC1 remains unchanged, the voltage at point B increases. After the first field effect transistor M1 inverts and amplifies, the voltage at point D decreases, the Vgs of the second NMOS transistor MN2 decreases, and the current decreases. Then, the voltage at point C increases, the Vsg of the first field effect transistor M1 decreases, and the current decreases, thereby reducing the output voltage Vout of the LDO, thereby stabilizing the output voltage Vout.

[0033] like Figure 2 As shown, when the output voltage Vout of the low voltage difference linear regulator decreases, the current flowing through the second field effect transistor M2 decreases. Since the current of the third bias current source VBC3 remains unchanged, the current flowing into point A through the first NMOS transistor MN1 increases. At the same time, since the current flowing into point B from the first bias current source VBC1 remains unchanged, the voltage at point B decreases. After the first field effect transistor M1 inverts and amplifies, the voltage at point D increases, the Vgs of the second NMOS transistor MN2 increases, and the current increases. Then, the voltage at point C decreases, the Vsg of the first field effect transistor M1 increases, and the current increases, thereby increasing the output voltage Vout of the LDO, thereby stabilizing the output voltage Vout.

[0034] The embodiment of the present invention achieves high precision, low power consumption, high power supply rejection ratio, fast dynamic response, and a large load current range through three loops, wherein the first loop is a buffer circuit connected with negative feedback; the second loop is an output feedback stage subcircuit, an amplifier stage subcircuit, and a current buffer stage subcircuit controlled by a single tube; and the third loop is a voltage negative feedback loop nested in the current buffer stage subcircuit.

[0035] In the second loop, the small signal of the output voltage Vout The second field effect transistor M2 converts the current into a current flowing from point A into the amplifier sub-circuit. , the small signal voltage at point B is The output impedance at point B The product of, assuming the gain of the current buffer stage subcircuit is A1, then the small signal voltage at point C is , the first field effect tube M1 amplifies it to: , where R L is the resistance value in the load circuit, g m1 is the transconductance of the first field effect transistor M1, r Om1 is the output impedance of the first field effect tube M1, g m2 is the transconductance of the second field effect tube M2; o Equal to the transconductance g of the second field effect tube m2 Multiply the output voltage small signal v o , then the loop gain of the second loop is: ; It can be seen that when the A1 value is reasonably designed, the gain of the second loop of the LDO is equivalent to the gain of the secondary amplifier, and it will not provide too high a gain to cause insufficient loop stability.

[0036] In the third loop, the small signal voltage v generated at point D i , which is converted into current g by the second NMOS tube MN2 mn2 *v i , which is converted into current by the second PMOS tube MP2, the PMOS field effect tube group, the third NMOS tube MN3, and the fourth NMOS tube MN4 Flows through point D, and the output impedance at point D is , then the loop gain of the third loop is: , where k is the value of K in the 1:K current mirror formed by the second PMOS tube MP2 and the PMOS field effect tube group, g mn2 is the transconductance of the second NMOS tube MN2; the equivalent output impedance of the voltage negative feedback is the output impedance at this point divided by the loop gain, then the equivalent output impedance at point C is: , where g mps0 is the total transconductance of all FETs in the PMOS FET group; the gain from point B to point C is: ; It can be seen from this that the small signal model of the current buffer stage subcircuit with the third loop in the embodiment of the present invention is consistent with the small signal model of the ordinary current buffer circuit, that is, the third loop does not significantly increase the gain while reducing power consumption, and its gain increase factor is the ratio k of the current mirror.

[0037] Substituting the above formula into the loop gain expression of the second loop, we can get: ; because , then the above formula can be transformed to obtain the final loop gain of the second loop: ; When the LDO load is light, the load resistance The output impedance of the first field effect transistor M1M1 Much greater than , the output impedance of the LDO is given by Dominant, the loop gain can be simplified to: ; Where N is the value of the number of first field effect tube M1 units. In low power applications, The value of N is relatively large, considering the power consumption under heavy load. In a wide load range, the value is usually several thousand to tens of thousands. Therefore, the gain under light load can easily reach 90dB, or even more than 100dB. If the light load stability is improved by reducing the gain, any item in the formula can be reduced, but the value of N is limited by the power consumption under heavy load; reduce The current flowing through the first PMOS tube MP1 can be reduced and its width-to-length ratio can be reduced. However, the current reduction is limited by the DC operating point of the third loop under light load, and the width-to-length ratio is limited by the DC operating point of the third loop under heavy load, and both cannot be too small. Therefore, the most direct and effective method is to reduce the output impedance of point B. .

[0038] When the LDO load is heavy, the load resistance Dominant, the loop gain can be simplified to:

[0039] Similarly, the gain under heavy load can be reduced by reducing the output impedance r at point B. oB and the transconductance g of the second field effect transistor M2 m2 .

[0040] It should be understood that the above are only preferred embodiments of the present invention, and the patent scope of the present invention cannot be limited thereto. Any equivalent structure or equivalent process transformation made using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A low-power, high-performance low-dropout linear regulator, comprising a reference source circuit, a buffer circuit, a control circuit, and a load circuit, characterized in that: It also includes an output control loop connected to a load circuit; a reference source circuit is connected to a buffer circuit, the buffer circuit receives a reference voltage and performs buffer amplification, then outputs a target voltage to the control circuit and simultaneously feeds back to an input end of the buffer circuit, the control circuit generates a stable control voltage to the output control loop, performs feedback amplification, and then outputs the voltage to the load circuit, so as to output the voltage to a subsequent circuit; The output control loop includes an amplifier stage subcircuit, a current buffer stage subcircuit and an output feedback stage subcircuit; the output feedback stage subcircuit is respectively connected to the control circuit and the output circuit to amplify the control voltage and output it to the load circuit. At the same time, the output voltage is fed back to the amplifier stage subcircuit. After amplification and gain improvement by the amplifier stage subcircuit and the current buffer stage subcircuit, the output voltage is close to the target voltage and maintains a stable output.

2. The low-power, high-performance low-dropout linear regulator according to claim 1, characterized in that: The output feedback stage subcircuit is connected to the control circuit and the load circuit, and includes a first field effect transistor, a second field effect transistor and a first capacitor. The source of the first field effect transistor is connected to the input power supply, and the drain is connected to the source of the second field effect transistor and the output circuit; the gate of the second field effect transistor is connected to the control circuit, one end of the first capacitor is connected to the output circuit and the drain of the first field effect transistor and the source of the second field effect transistor, and the other end is connected to the drain of the second field effect transistor and the amplifier stage subcircuit.

3. The low-power, high-performance low-dropout linear regulator according to claim 2, characterized in that: The amplifier stage subcircuit includes a first NMOS tube, the drain of the first NMOS tube is connected to the first bias current source and the current buffer stage subcircuit, the gate is connected to the second bias voltage, and the source is connected to the drain of the second field effect tube in the output feedback stage subcircuit and the third bias current source.

4. The low-power, high-performance low-dropout linear regulator according to claim 2, characterized in that: The current buffer stage subcircuit includes a first PMOS tube, a second PMOS tube, a second NMOS tube, a third NMOS tube, and a fourth NMOS tube; the gate of the first PMOS tube is connected to the drain of the first NMOS tube, the source is connected to the input power supply, and the drain is connected to the third bias current source in the amplifier stage subcircuit and the gate of the second NMOS tube; the source of the second PMOS tube is connected to the input power supply, the drain is connected to the drain of the third NMOS tube and the gates of the third NMOS tube and the fourth NMOS tube, and the gate is connected to the gate of the first field effect tube; The drain of the second NMOS tube is connected to the gate of the second PMOS tube and the gate of the first field effect tube, the source is grounded, and the gate is connected to the amplifier stage sub-circuit to receive the signal amplified by the amplifier stage sub-circuit; the gate and drain of the third NMOS tube are connected to each other and to the gate of the fourth NMOS tube, and the source is grounded; the source of the fourth NMOS tube is grounded.

5. The low-power, high-performance low-dropout linear regulator according to claim 4, characterized in that: The current buffer stage subcircuit also includes a group of PMOS field effect transistors, the sources of which are connected to the input power supply, the gates are respectively connected to the gates of the second PMOS tube and the first field effect tube, and the drains are respectively connected to the gates thereof and the drain of the second NMOS tube.

6. The low-power, high-performance low-dropout linear regulator according to claim 5, characterized in that: The second PMOS tube and the PMOS field effect tube group form a current mirror, and the number ratio thereof is 1:K, where K is a positive integer, and its preferred range is 2-5.

7. The low-power, high-performance low-dropout linear regulator according to claim 6, characterized in that: The second PMOS transistor and any field effect transistor in the PMOS field effect transistor group have the same size.

8. The low-power, high-performance low-dropout linear regulator according to claim 2, characterized in that: The first field effect tube is a power tube.

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