High-reliability high-stability high-voltage reference source

Abstract

The invention discloses a high-reliability high-stability high-voltage reference source, and belongs to the field of power supply circuits. The Is1 is formed by VBE of a triode Q3 and a resistor R3, the current flowing through a high-voltage NMOS tube hnmos1 is VBE3 / R3, the current is irrelevant to a high-voltage power supply VDD, along with the small change of the process and the temperature, the Is2 copying the current of the Is1 is used as the starting current, and the power supply can be stably and reliably started no matter how the power supply changes; through a high-voltage tube hnmos2 / hnmos3, triodes Q1 and Q2 can meet the requirement of generating IPTAT current in many processes without a high-voltage triode; similarly, an Ictat current is formed by a triode Q1, a low-voltage tube pmos9 / pmos10 / nmos1 / nmos2, a high-voltage tube hnmos4 and a resistor R5, the implementation is convenient, and no special device is needed. The reference source is wide in applicable voltage range, stable and reliable in starting, free of special devices and capable of meeting the current source of any temperature characteristic.

Description

Technical Field

[0001] The invention relates to the technical field of power supply circuits, and in particular to a high-reliability and high-stability high-voltage reference source. Background Art

[0002] As the domestic high-voltage process technology matures and improves, high-voltage analog circuits are developing towards large-scale and high-integration. However, the most basic startup circuit of the high-voltage circuit is indeed a difficult point. Since the high voltage is over 60 or 70 volts, and the gate voltage withstand voltage of the high-voltage MOS tube is relatively low, the startup circuit design of the high-voltage reference source is more complicated. In addition, the startup circuit of the high-voltage reference source has the problem of unstable startup current, and will be greatly affected by changes in process and power supply. Summary of the invention

[0003] The object of the present invention is to provide a high-reliability and high-stability high-voltage reference source to solve the problems in the background technology.

[0004] In order to solve the above technical problems, the present invention provides a high-reliability and high-stability high-voltage reference source, including high-voltage PMOS tubes hpmos1~hpmos8, high-voltage NMOS tubes hnmos1~hnmos4, PMOS tubes pmos1~pmos10, NMOS tubes nmos1~nmos2, transistors Q1~Q3, and resistors R1~R6; The source terminals of the PMOS tubes pmos1 to pmos8 are all connected to the power supply voltage Vdd, and the drain terminals of the PMOS tubes pmos1 to pmos8 are respectively connected to the source terminals of the high-voltage PMOS tubes hpmos1 to hpmos8; the gate terminal of the PMOS tube pmos1 is simultaneously connected to its own drain terminal and the gate terminal of the PMOS tube pmos2, and the gate terminal of the PMOS tube pmos7 is simultaneously connected to its own drain terminal and the gate terminal of the PMOS tube pmos8; the gate terminals of the PMOS tubes pmos3 to pmos6 are interconnected; The drain end of the high-voltage PMOS tube hpmos1 is connected to the drain end of the high-voltage NMOS tube hnmos1, the drain end of the high-voltage PMOS tube hpmos2 and the drain end of the high-voltage PMOS tube hpmos3 are both connected to the drain end of the high-voltage NMOS tube hnmos2, and the drain end of the high-voltage PMOS tube hpmos4 is connected to the drain end of the high-voltage NMOS tube hnmos3 through the resistor R6; the gate end of the high-voltage PMOS tube hpmos1 is simultaneously connected to its own drain end and the gate end of the high-voltage PMOS tube hpmos2, the gate ends of the high-voltage PMOS tubes hpmos3~hpmos6 are interconnected, and the gate end of the high-voltage PMOS tube hpmos4 is connected to the drain end of the high-voltage NMOS tube hnmos3. The drain end is connected to the gate end of the PMOS tube pmos3 and the gate end of the PMOS tube pmos4 at the same time, the drain end of the high-voltage NMOS tube hnmos3 is connected to the gate end of the high-voltage PMOS tube hpmos3 and the gate end of the high-voltage PMOS tube hpmos4 at the same time, the drain end of the high-voltage PMOS tube hpmos5 is connected to the source end of the PMOS tube pmos9 and the source end of the PMOS tube pmos10 at the same time; the drain end current of the high-voltage PMOS tube hpmos6 and the drain end current of the high-voltage PMOS tube hpmos8 are added; the drain end of the high-voltage PMOS tube hpmos7 is connected to the drain end of the high-voltage NMOS tube hnmos4; The first end of the resistor R1 is connected to the power supply voltage Vdd, and the second end of the resistor R1 is connected to the first end of the resistor R2; the second end of the resistor R2 is connected to the gate end of the high-voltage NMOS tube hnmos1 and the collector of the transistor Q3; the base of the transistor Q3 is connected to the source end of the high-voltage NMOS tube hnmos1 and the first end of the resistor R3, and the emitter of the transistor Q3 and the second end of the resistor R3 are grounded Vss at the same time; the drain end of the high-voltage NMOS tube hnmos2 is connected to its own gate end and the gate end of the high-voltage NMOS tube hnmos3, the source end of the high-voltage NMOS tube hnmos2 is connected to the collector of the transistor Q1 and the gate end of the PMOS tube pmos9, the base of the transistor Q1 is connected to its own collector and the base of the transistor Q2 at the same time; the source end of the high-voltage NMOS tube hnmos3 is connected to the gate end of the transistor Q 2, the emitter of the transistor Q2 is connected to the first end of the resistor R4, and the emitter of the transistor Q1 and the second end of the resistor R4 are both grounded to Vss; the drain terminal of the PMOS tube pmos9 is connected to the drain terminal of the NMOS tube nmos1, and the drain terminal of the NMOS tube nmos1 is connected to its own gate terminal and the gate terminal of the NMOS tube nmos2; the gate terminal of the PMOS tube pmos10 is connected to the first end of the resistor R5, the drain terminal of the PMOS tube pmos10 is connected to the drain terminal of the NMOS tube nmos2, and the second end of the resistor R5, the source terminal of the NMOS tube nmos1 and the source terminal of the NMOS tube nmos2 are all grounded to Vss; the gate terminal of the high-voltage NMOS tube hnmos4 is connected to the drain terminal of the PMOS tube pmos10, and the source terminal of the high-voltage NMOS tube hnmos4 is connected to the first end of the resistor R5.

[0005] The invention provides a high-reliability and high-stability high-voltage reference source, which is easy to implement and does not require special devices. The reference source is applicable to a current source with a wide voltage range, stable and reliable startup, no special devices, and any temperature characteristics. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 It is a structural schematic diagram of a high-reliability and high-stability high-voltage reference source provided by the present invention. DETAILED DESCRIPTION

[0007] The following is a further detailed description of a high reliability and high stability high voltage reference source proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0008] The invention provides a high-reliability and high-stability high-voltage reference source, comprising high-voltage PMOS tubes hpmos1-hpmos8, high-voltage NMOS tubes hnmos1-hnmos4, PMOS tubes pmos1-pmos10, NMOS tubes nmos1-nmos2, triodes Q1-Q3, and resistors R1-R6; source ends of the PMOS tubes pmos1-pmos8 are all connected to a power supply voltage Vdd, drain ends of the PMOS tubes pmos1-pmos8 are respectively connected to source ends of the high-voltage PMOS tubes hpmos1-hpmos8; a gate end of the PMOS tube pmos1 is simultaneously connected to its own drain end and a gate end of the PMOS tube pmos2, a gate end of the PMOS tube pmos7 is simultaneously connected to its own drain end and a gate end of the PMOS tube pmos8; and gate ends of the PMOS tubes pmos3-pmos6 are interconnected.

[0009] The drain end of the high-voltage PMOS tube hpmos1 is connected to the drain end of the high-voltage NMOS tube hnmos1, the drain end of the high-voltage PMOS tube hpmos2 and the drain end of the high-voltage PMOS tube hpmos3 are both connected to the drain end of the high-voltage NMOS tube hnmos2, and the drain end of the high-voltage PMOS tube hpmos4 is connected to the drain end of the high-voltage NMOS tube hnmos3 through the resistor R6. The gate end of the high-voltage PMOS tube hpmos1 is connected to its own drain end and the gate end of the high-voltage PMOS tube hpmos2 at the same time, the gate ends of the high-voltage PMOS tubes hpmos3 to hpmos6 are interconnected, the drain end of the high-voltage PMOS tube hpmos4 is connected to the gate end of the PMOS tube pmos3 and the gate end of the PMOS tube pmos4 at the same time, the drain end of the high-voltage NMOS tube hnmos3 is connected to the gate end of the high-voltage PMOS tube hpmos3 and the gate end of the high-voltage PMOS tube hpmos4 at the same time, the drain end of the high-voltage PMOS tube hpmos5 is connected to the source end of the PMOS tube pmos9 and the source end of the PMOS tube pmos10 at the same time; the drain end current of the high-voltage PMOS tube hpmos6 and the drain end current of the high-voltage PMOS tube hpmos8 are added; the drain end of the high-voltage PMOS tube hpmos7 is connected to the drain end of the high-voltage NMOS tube hnmos4.

[0010] The first end of the resistor R1 is connected to the power supply voltage Vdd, and the second end of the resistor R1 is connected to the first end of the resistor R2; the second end of the resistor R2 is connected to the gate end of the high-voltage NMOS tube hnmos1 and the collector of the transistor Q3; the base of the transistor Q3 is connected to the source end of the high-voltage NMOS tube hnmos1 and the first end of the resistor R3, and the emitter of the transistor Q3 and the second end of the resistor R3 are connected to the ground Vss. The drain end of the high-voltage NMOS tube hnmos2 is connected to its own gate end and the gate end of the high-voltage NMOS tube hnmos3, the source end of the high-voltage NMOS tube hnmos2 is connected to the collector of the transistor Q1 and the gate end of the PMOS tube pmos9, and the base of the transistor Q1 is connected to its own collector and the base of the transistor Q2; the source end of the high-voltage NMOS tube hnmos3 is connected to the collector of the transistor Q2, the emitter of the transistor Q2 is connected to the first end of the resistor R4, and the emitter of the transistor Q1 and the second end of the resistor R4 are both connected to the ground Vss. The drain terminal of the PMOS tube pmos9 is connected to the drain terminal of the NMOS tube nmos1, and the drain terminal of the NMOS tube nmos1 is connected to its own gate terminal and the gate terminal of the NMOS tube nmos2; the gate terminal of the PMOS tube pmos10 is connected to the first end of the resistor R5, and the drain terminal of the PMOS tube pmos10 is connected to the drain terminal of the NMOS tube nmos2, and the second end of the resistor R5, the source terminal of the NMOS tube nmos1 and the source terminal of the NMOS tube nmos2 are all grounded to Vss. The gate terminal of the high-voltage NMOS tube hnmos4 is connected to the drain terminal of the PMOS tube pmos10, and the source terminal of the high-voltage NMOS tube hnmos4 is connected to the first end of the resistor R5.

[0011] Please continue reading Figure 1 The startup circuit is composed of resistor R1, resistor R2, transistor Q3, resistor R3, PMOS tube pmos1, PMOS tube pmos2, high-voltage PMOS tube hpmos1, and high-voltage PMOS tube hpmos2. The startup current Is2 copies Is1, and the current of Is1 is VBE3 / R3; The positive temperature characteristic current (PTAT) is composed of PMOS tube pmos3, PMOS tube pmos4, high-voltage PMOS tube hpmos3, high-voltage PMOS tube hpmos4, resistor R6, high-voltage NMOS tube hnmos2, high-voltage NMOS tube hnmos3, transistor Q1, transistor Q2, and resistor R4. IPTAT=VTln(m*IC2 / IC1) / R4; The negative temperature characteristic current (CTAT) is composed of transistor Q1, PMOS tube pmos9, PMOS tube pmos10, NMOS tube nmos1, NMOS tube nmos2, resistor R5, and high-voltage NMOS tube hnmos4, ICTAT=VBE1 / R5; The current of PMOS tube pmos6 / high-voltage PMOS tube hpmos6 copies the current of PMOS tube pmos4 / high-voltage PMOS tube hpmos4, and the current of PMOS tube pmos8 / high-voltage PMOS tube hpmos8 copies the current of PMOS tube pmos7 / high-voltage PMOS tube hpmos7; The reference current IREF is composed of the PTAT current of the PMOS tube pmos6 / high-voltage PMOS tube hpmos6 and the CTAT current of the PMOS tube pmos8 / high-voltage PMOS tube hpmos8; In the present invention, Is1 is formed by the VBE of transistor Q3 and resistor R3, and the current flowing through the high-voltage NMOS tube hnmos1 is VBE3 / R3, which is independent of the high-voltage power supply VDD. With the process and temperature changes, Is2, which copies the current of Is1, is used as the startup current, so that the startup can be stable and reliable regardless of the power supply changes; through the high-voltage tube hnmos2 / hnmos3, the transistors Q1 and Q2 do not need high-voltage transistors, so that many processes can meet the requirements of generating IPTAT current; similarly, the Ictat current is formed by the transistor Q1 and the low-voltage tube pmos9 / pmos10 / nmos1 / nmos2 and the high-voltage tube hnmos4 and resistor R5, which is convenient to implement and does not require special devices. The reference source is applicable to a current source with a wide voltage range, stable and reliable startup, no special devices, and any temperature characteristics.

[0012] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A high reliability and high stability high voltage reference source, characterized in that: Including high-voltage PMOS tubes hpmos1~hpmos8, high-voltage NMOS tubes hnmos1~hnmos4, PMOS tubes pmos1~pmos10, NMOS tubes nmos1~nmos2, transistors Q1~Q3, and resistors R1~R6; The source terminals of the PMOS tubes pmos1 to pmos8 are all connected to the power supply voltage Vdd, and the drain terminals of the PMOS tubes pmos1 to pmos8 are respectively connected to the source terminals of the high-voltage PMOS tubes hpmos1 to hpmos8; the gate terminal of the PMOS tube pmos1 is simultaneously connected to its own drain terminal and the gate terminal of the PMOS tube pmos2, and the gate terminal of the PMOS tube pmos7 is simultaneously connected to its own drain terminal and the gate terminal of the PMOS tube pmos8; the gate terminals of the PMOS tubes pmos3 to pmos6 are interconnected; The drain end of the high-voltage PMOS tube hpmos1 is connected to the drain end of the high-voltage NMOS tube hnmos1, the drain end of the high-voltage PMOS tube hpmos2 and the drain end of the high-voltage PMOS tube hpmos3 are both connected to the drain end of the high-voltage NMOS tube hnmos2, and the drain end of the high-voltage PMOS tube hpmos4 is connected to the drain end of the high-voltage NMOS tube hnmos3 through the resistor R6; the gate end of the high-voltage PMOS tube hpmos1 is simultaneously connected to its own drain end and the gate end of the high-voltage PMOS tube hpmos2, the gate ends of the high-voltage PMOS tubes hpmos3~hpmos6 are interconnected, and the gate end of the high-voltage PMOS tube hpmos4 is connected to the drain end of the high-voltage NMOS tube hnmos3. The drain end is connected to the gate end of the PMOS tube pmos3 and the gate end of the PMOS tube pmos4 at the same time, the drain end of the high-voltage NMOS tube hnmos3 is connected to the gate end of the high-voltage PMOS tube hpmos3 and the gate end of the high-voltage PMOS tube hpmos4 at the same time, the drain end of the high-voltage PMOS tube hpmos5 is connected to the source end of the PMOS tube pmos9 and the source end of the PMOS tube pmos10 at the same time; the drain end current of the high-voltage PMOS tube hpmos6 and the drain end current of the high-voltage PMOS tube hpmos8 are added; the drain end of the high-voltage PMOS tube hpmos7 is connected to the drain end of the high-voltage NMOS tube hnmos4; The first end of the resistor R1 is connected to the power supply voltage Vdd, and the second end of the resistor R1 is connected to the first end of the resistor R2; the second end of the resistor R2 is connected to the gate end of the high-voltage NMOS tube hnmos1 and the collector of the transistor Q3; the base of the transistor Q3 is connected to the source end of the high-voltage NMOS tube hnmos1 and the first end of the resistor R3, and the emitter of the transistor Q3 and the second end of the resistor R3 are grounded Vss at the same time; the drain end of the high-voltage NMOS tube hnmos2 is connected to its own gate end and the gate end of the high-voltage NMOS tube hnmos3, the source end of the high-voltage NMOS tube hnmos2 is connected to the collector of the transistor Q1 and the gate end of the PMOS tube pmos9, the base of the transistor Q1 is connected to its own collector and the base of the transistor Q2 at the same time; the source end of the high-voltage NMOS tube hnmos3 is connected to the gate end of the transistor Q 2, the emitter of the transistor Q2 is connected to the first end of the resistor R4, and the emitter of the transistor Q1 and the second end of the resistor R4 are both grounded to Vss; the drain terminal of the PMOS tube pmos9 is connected to the drain terminal of the NMOS tube nmos1, and the drain terminal of the NMOS tube nmos1 is connected to its own gate terminal and the gate terminal of the NMOS tube nmos2; the gate terminal of the PMOS tube pmos10 is connected to the first end of the resistor R5, the drain terminal of the PMOS tube pmos10 is connected to the drain terminal of the NMOS tube nmos2, and the second end of the resistor R5, the source terminal of the NMOS tube nmos1 and the source terminal of the NMOS tube nmos2 are all grounded to Vss; the gate terminal of the high-voltage NMOS tube hnmos4 is connected to the drain terminal of the PMOS tube pmos10, and the source terminal of the high-voltage NMOS tube hnmos4 is connected to the first end of the resistor R5.

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