High-precision high-power-supply-rejection-ratio band-gap reference circuit integrated with digital trimming module

Abstract

The invention discloses a high-precision high-power-supply-rejection-ratio band-gap reference circuit integrated with a digital trimming module. The high-precision high-power-supply-rejection-ratio band-gap reference circuit comprises a first-stage band-gap reference circuit, a second-stage band-gap reference circuit, a zero-temperature-coefficient current source circuit and the digital trimming module. The two-stage band-gap reference circuit is adopted, the power supply rejection ratio of output reference voltage is increased, zero-temperature-coefficient current is obtained through the current summing circuit, a digital trimming mode is adopted, an I2C module and a level conversion module are integrated, high-precision and repeatable trimming of the output reference voltage can be achieved, a traditional resistance trimming mode is improved, and the power supply rejection ratio of the output reference voltage is increased. And the precision of the output reference voltage is improved.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit design, and more specifically, to a high-precision high power supply rejection ratio bandgap reference circuit integrated with an I2C digital trimming module. Background Art

[0002] The bandgap reference circuit is a basic module in the field of analog integrated circuit design. Its function is to provide a reference voltage for the overall circuit that varies little with external factors. The voltage should have good temperature stability and a high power supply rejection ratio, that is, it varies little with temperature and power supply voltage. Therefore, the performance of the bandgap reference circuit has a crucial impact on the performance and accuracy of the circuit system.

[0003] Some existing bandgap reference circuits are affected by process corners and mismatches and will add a single resistor trimming circuit. Trimming is a technology that adjusts the characteristics of a circuit (such as a high-precision integrated circuit) to make it closer to the target, generally trimming the resistor or capacitor. The function of this single resistor trimming circuit is not perfect and the trimming steps are relatively complicated. Usually, after the chip is manufactured, the resistor is cut off by laser etching or high-current fusing. This method is often one-time and irreversible. At the same time, the high temperature of laser etching may damage the performance of other devices in the circuit, and its impact needs to be fully considered during the layout process.

[0004] Therefore, based on the existing bandgap reference with trimming circuit, how to modify the circuit structure so that the output voltage can be trimmed at low cost and high convenience has become a problem that technicians in this field need to solve. Summary of the invention

[0005] The technical problem to be solved by the present invention is: in a bandgap reference circuit structure with a trimming circuit, how to improve the trimming circuit structure so that the output voltage can be adjusted at a lower cost, and how to improve the trimming method to achieve high-precision and repeatable trimming.

[0006] To solve the above problems, the present invention proposes a high-precision, high-power supply rejection ratio bandgap reference circuit integrated with a digital trimming module, comprising a first-stage bandgap reference circuit, a second-stage bandgap reference circuit, a zero temperature coefficient current source circuit, and a digital trimming module. The first-stage bandgap reference circuit generates a first-stage reference voltage, which provides a power supply voltage for the second-stage bandgap reference circuit and the zero temperature coefficient current source circuit. The second-stage bandgap reference circuit generates a reference voltage with a low temperature coefficient, high precision, and high power supply rejection ratio, and simultaneously forms a PTAT current that is proportional to the absolute temperature. The zero temperature coefficient current source circuit can generate a zero temperature coefficient current. The digital trimming module can control the on and off of the internal switch MOS tube through the I2C signal of the external host, thereby trimming the reference voltage.

[0007] Furthermore, the digital trimming module includes a trimming resistor circuit, an I2C module, and a level conversion module; the size of the resistance in the trimming resistor circuit can be controlled by a switch MOS tube, thereby changing the resistance voltage division and further trimming the output voltage value; the I2C module can output a level signal to control the conduction and closing of the switch MOS tube in the trimming resistor, thereby changing the resistance value of the trimming resistor; the level conversion module is used to match the level signal of its input and output ports. The voltage value of the host IO port is different from the internal power supply voltage of the chip. The level conversion module can achieve matching between the voltage of the host IO port and the internal power supply voltage of the chip.

[0008] The first-stage bandgap reference circuit includes PMOS transistors MP1, MP2, MP3, transistors Q1, Q2, and resistors R1, R2, R3, R4, R5, R6, and R7. The gates of MP1 and MP2 are connected to the drain of MP1 and the collector of Q1, the source of MP1 is connected to the first port of resistor R3, the source of MP2 is connected to the first port of resistor R4, the drain of MP2 is connected to the gate of MP3 and the collector of Q2, the gate of MP3 is connected to the second port of resistor R5, the drain of MP3 is connected to the first port of resistor R6 and the power supply voltage VDD2, the first ports of resistors R3, R4, and R5 are connected to the power supply VDD1, the first port of resistor R1 is connected to the emitter of Q2, the second port of resistor R1 is connected to the emitter of Q1 and the first port of R2, the second port of R2 is grounded, the bases of transistors Q1 and Q2 are connected to the second port of R6 and the first port of R7, and the second port of R7 is grounded.

[0009] The second-stage bandgap reference circuit includes PMOS transistors MP4, MP5, MP6, transistors Q3, Q4, and resistors R8, R9, R10, R11, and R1. The gates of MP4 and MP5 are connected to the drain of MP4 and the collector of Q3, the source of MP4 is connected to the first port of resistor R8, the source of MP5 is connected to the first port of resistor R9, the drain of MP5 is connected to the gate of MP6 and the collector of Q4, the source of MP6 is connected to the second port of resistor R12, the first ports of resistors R8, R9, and R12 are connected to the power supply VDD2, the first port of resistor R10 is connected to the emitter of Q4, the second port of resistor R10 is connected to the emitter of Q3 and the first port of R11, the second port of R11 is grounded, and the bases of transistors Q3 and Q4 are connected to the drain of MP6 and the digital trimming module.

[0010] The first-stage bandgap reference circuit and the second-stage bandgap reference circuit have similar principles for generating reference circuits. The current mirror structure is used to make the collector currents of the transistors Q1 and Q2 equal, and the collector currents of the transistors Q3 and Q4 equal. The base voltage of the transistor is the sum of a voltage proportional to the absolute temperature and another voltage inversely proportional to the absolute temperature, which is the required reference voltage. The drain current of the PMOS tube in the current mirror structure is a current IPTAT proportional to the absolute temperature, which can be used in a zero temperature coefficient current source circuit.

[0011] The zero temperature coefficient current source circuit includes PMOS tubes MP7, MP8, MP9, MP10, MP11, MP12, NMOS tubes MN1, MN2, MN3, MN4, triode Q5, resistors R13, R14, R15. The gates of MP7 and MP8 are connected to the gate and drain of MP4 in the second-level voltage reference, and the current IPTAT is copied through the current mirror. The source of MP7 is connected to the second port of the resistor R13, the source of MP8 is connected to the second port of the resistor R14, the first ports of the resistors R13 and R14 are connected to the power supply VDD2, the gates of the NMOS tubes MN1, MN2, MN3, MN4 are connected to the drain of MN3 and the drain of MP7, the drain of MN1 is connected to the source of MN3, the drain of MN2 is connected to the source of MN4, and MN1, MN2, MN3, MN4 form a common source and common gate current mirror. The drain of MP8 is connected to the gate of MN5 and the collector of transistor Q5, the base of Q5 is connected to the source of MN5 and the first port of R15, and the emitter of Q5 is grounded, and the second port of R15 is grounded. This circuit can form a current ICTAT that is inversely proportional to the absolute temperature. The drains of MN4 and MN5 are connected to the gates of MP9, MP10, MP11, MP12 and the drain of MP10. MN2, MN4, MN5, MP9, MP10, Q5, and R15 form a current summing circuit, which sums the current IPTAT with the current ICTAT to obtain a zero temperature coefficient current, and copies the current through the current mirrors of MP9, MP10, MP11, and MP12 to obtain the current IB.

[0012] The digital trimming module includes a trimming resistor circuit, an I2C module, and a level conversion module. The trimming resistor circuit includes a first port PA, a second port PB, ports P0-P7, an output port P OUT The first port PA is connected to the base of transistors Q3 and Q4 in the second-stage bandgap reference circuit and the drain of PMOS tube MP6, the second port PB is grounded, and the output port P OUTThe I2C module includes a data input port SDA, a clock input port SCL, an output port Y0-Y7, a power port VDD, and a ground port GND, wherein the SDA port is connected to the level conversion module port B1, the SCL port is connected to the level conversion module port B0, the output ports Y0-Y7 are connected to the corresponding ports P0-P7 of the trimming resistor circuit, the power port is connected to VDD1, and the ground port is grounded; the level conversion module includes a first power port VCCA, a second power port VCCB, input ports A0 and A1, output ports B0 and B1, and a ground port, wherein the first power port is connected to the host end power supply voltage VDDA, the second power port is connected to VDD1, A1 is externally connected to the data signal of the host end, A0 is externally connected to the clock signal of the host end, and the ground port is grounded.

[0013] The trimming resistor circuit is composed of NMOS tubes M0, M1, M2, M3, M4, M5, M6, M7, and resistors R00, R01, R02, R03, R04, R05, R06, R07, R08, and R09, wherein NMOS is connected in series in sequence as a switch MOS tube, and resistors R00-R09 are also connected in series as shown in the figure, and the source of each MOS tube is connected to the first port of a resistor, and the drain is connected to the second port of the corresponding resistor, that is, connected in parallel. The trimming resistor circuit can be realized, when the gate of the MOS tube is connected to a high level, it is turned on, and when it is connected to a low level, it is turned off. When a certain MOS tube is turned on, the resistor in parallel with it is short-circuited, changing the equivalent resistance of the total branch, thereby changing the voltage division of the output port, and then realizing the trimming of the output voltage.

[0014] The present invention proposes a high-precision, high-power supply rejection ratio bandgap reference circuit with a digital trimming function, and its technical effects are: a two-stage bandgap reference voltage circuit is adopted to improve the power supply rejection ratio of the output voltage; the reference voltage is output by a digital trimming method (voltage accuracy trimming), and the output can be kept within the ±3mV error range; at the same time, I2C control is adopted, and a level conversion module is integrated, so that multiple high-precision trimming can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 The schematic diagram of the high-precision high power supply rejection ratio bandgap reference circuit with integrated digital trimming module proposed by the present invention;

[0016] Figure 2 To adjust the resistor circuit schematic;

[0017] Figure 3 The simulation result of the reference voltage Vref of the high-precision and high-power supply rejection ratio bandgap reference circuit with integrated digital trimming module proposed by the present invention;

[0018] Figure 4The zero temperature coefficient current simulation result of the high-precision high power supply rejection ratio bandgap reference circuit with integrated digital trimming module proposed by the present invention;

[0019] Figure 5 The power supply rejection ratio simulation result of the high-precision high power supply rejection ratio bandgap reference circuit with integrated digital trimming module proposed in the present invention;

[0020] Figure 6 The output reference voltage when different control words are written into the I2C register; DETAILED DESCRIPTION

[0021] The present invention is further described in detail below in conjunction with the accompanying drawings and embodiments.

[0022] The high-precision high power supply rejection ratio bandgap reference circuit with digital trimming function proposed by the present invention is as follows Figure 1 As shown, it includes a first-stage bandgap reference circuit, a second-stage bandgap reference circuit, a zero temperature coefficient current source circuit, a digital adjustment module, and a startup and shutdown circuit, which does not involve the technical innovation of the present invention.

[0023] like Figure 1 As shown, the first-stage bandgap reference circuit includes PMOS transistors MP1, MP2, MP3, transistors Q1, Q2, and resistors R1, R2, R3, R4, R5, R6, and R7. The gates of MP1 and MP2 are connected to the drain of MP1 and the collector of Q1, the source of MP1 is connected to the first port of the resistor R3, the source of MP2 is connected to the first port of the resistor R4, the drain of MP2 is connected to the gate of MP3 and the collector of Q2, the gate of MP3 is connected to the second port of the resistor R5, the drain of MP3 is connected to the first port of the resistor R6 and the power supply voltage VDD2, the first ports of the resistors R3, R4, and R5 are connected to the power supply VDD1, the first port of the resistor R1 is connected to the emitter of Q2, the second port of the resistor R1 is connected to the emitter of Q1 and the first port of R2, the second port of R2 is grounded, the bases of the transistors Q1 and Q2 are connected to the second port of R6 and the first port of R7, and the second port of R7 is grounded.

[0024] The second-stage bandgap reference circuit includes PMOS tubes MP4, MP5, MP6, transistors Q3, Q4, and resistors R8, R9, R10, R11, and R1. The gates of MP4 and MP5 are connected to the drain of MP4 and the collector of Q3, the source of MP4 is connected to the first port of resistor R8, the source of MP5 is connected to the first port of resistor R9, the drain of MP5 is connected to the gate of MP6 and the collector of Q4, the source of MP6 is connected to the second port of resistor R12, the first ports of resistors R8, R9, and R12 are connected to the power supply VDD2, the first port of resistor R10 is connected to the emitter of Q4, the second port of resistor R10 is connected to the emitter of Q3 and the first port of R11, the second port of R11 is grounded, and the bases of transistors Q3 and Q4 are connected to the drain of MP6 and the digital trimming module.

[0025] The first-stage bandgap reference circuit and the second-stage bandgap reference circuit are both current mirror structure bandgap reference circuits without operational amplifiers, which can generate a first-order zero temperature coefficient voltage. The two-stage bandgap reference circuit reduces the influence of the power supply voltage on the output voltage and improves the power supply rejection ratio. The first-stage bandgap reference circuit can generate a bandgap reference voltage VBG1, and then boost it through a resistor to obtain a stable power supply voltage VDD2 to provide power for the second-stage bandgap reference circuit and the zero temperature coefficient current circuit.

[0026] The principle of the first-stage bandgap reference circuit is described below. The principle of the second-stage bandgap reference circuit is similar. Figure 1 As shown, the first-stage bandgap reference circuit is composed of PMOS transistors MP1, MP2, triodes Q1, Q2, resistors R1, R2, R3, R4, R5, R6, and R7, which generates a reference voltage VDD1 with load capacity to provide power for the second-stage bandgap reference circuit.

[0027] In the first-stage bandgap reference circuit, the PMOS tubes MP1 and MP2 form a current mirror, which ensures that the collector currents of the transistors Q1 and Q2 are basically equal. In addition, the circuit uses transistors with a higher β coefficient, whose base currents can be ignored, and the currents flowing through the emitters are also approximately equal. Therefore, by summing the currents, I2=2I1 can be obtained.

[0028] The voltage drop across resistor R1 is the base-emitter voltage V of transistor Q1. BE1 The base-emitter voltage V BE2 The voltage difference is:

[0029] ΔV BE1 =V BE1 -V BE2 =I1×R1.

[0030] Where, ΔV BE1 Yes VBE1 With V BE2 voltage difference.

[0031] Then, the bandgap reference voltage output by the first-stage bandgap reference circuit is:

[0032]

[0033] Where: ΔV BE1 =V T ×ln(M1),V T =KT / q, V T is the thermal voltage of the transistor, which changes positively with temperature, K is the Boltzmann constant, T is the absolute temperature, q is the electron charge, and M1 is the ratio of the areas of transistors Q2 and Q1.

[0034] V BE1 Negatively correlated with temperature, by adjusting the appropriate values ​​of R1 and R2, a bandgap reference voltage V that is independent of temperature can be achieved. BG1 .

[0035] Similarly, the bandgap reference voltage V of the second-stage bandgap reference circuit BG2 for:

[0036]

[0037] Where, ΔV BE2 Yes V BE3 With V BE4 The voltage difference, V BE3 is the base-emitter voltage of transistor Q3, V BE4 is the base-emitter voltage of transistor Q4.

[0038] In the first-level voltage reference, Q2, MP3, R6, and R7 form a negative feedback loop to maintain the stability of the reference voltage. At the same time, the voltage is boosted through resistors R6 and R7 to obtain the second-level reference voltage power supply VDD2, that is:

[0039]

[0040] like Figure 1As shown, the zero temperature coefficient current source circuit includes PMOS tubes MP7, MP8, MP9, MP10, MP11, MP12, NMOS tubes MN1, MN2, MN3, MN4, transistor Q5, and resistors R13, R14, and R15. The gates of MP7 and MP8 are connected to the gate and drain of MP4 in the second-level voltage reference, and the current IPTAT is copied through the current mirror. The source of MP7 is connected to the second port of the resistor R13, the source of MP8 is connected to the second port of the resistor R14, and the first ports of the resistors R13 and R14 are connected to the power supply VDD2. The gates of the NMOS tubes MN1, MN2, MN3, and MN4 are connected to the drain of MN3 and the drain of MP7, the drain of MN1 is connected to the source of MN3, and the drain of MN2 is connected to the source of MN4. MN1, MN2, MN3, and MN4 form a common source and common gate current mirror. The drain of MP8 is connected to the gate of MN5 and the collector of transistor Q5, the base of Q5 is connected to the source of MN5 and the first port of R15, and the emitter of Q5 is grounded, and the second port of R15 is grounded. This circuit can form a current ICTAT that is inversely proportional to the absolute temperature. The drains of MN4 and MN5 are connected to the gates of MP9, MP10, MP11, MP12 and the drain of MP10. MN2, MN4, MN5, MP9, MP10, Q5, and R15 form a current summing circuit, which sums the current IPTAT with the current ICTAT to obtain a zero temperature coefficient current, and copies the current through the current mirrors of MP9, MP10, MP11, and MP12 to obtain the current IB.

[0041] The following explains the principle of zero temperature coefficient current circuit. Figure 1 As shown, the zero temperature coefficient current circuit is composed of PMOS tubes MP7, MP8, MP9, MP10, MP11, MP12, NMOS tubes MN1, MN2, MN3, MN4, transistor Q5, and resistors R13, R14, R15, which generates a positive temperature coefficient current IPTAT and a negative temperature coefficient ICTAT, and adds the two currents through a current summing circuit to obtain a current with a zero temperature coefficient, and copies it through a current mirror and uses it as a current source for other circuits.

[0042] As described above, the PMOS transistors MP4 and MP5 in the second-stage bandgap reference circuit have the same size, the MP7 and MP8 in the zero temperature coefficient current circuit have the same size, and the size of MP4 and MP5 is K1 times the size of MP7 and MP8, that is:

[0043]

[0044] PMOS tubes MP4, MP5, MP7, and MP8 are connected in the form of current mirrors to copy the drain current in proportion. As mentioned above, the drain currents of MP4 and MP5 are equal. Considering that the beta coefficient of the transistor is very large, the current is approximately:

[0045]

[0046] Where, ΔV BE2 Yes V BE3 With V BE4 The voltage difference, V BE3 is the base-emitter voltage of transistor Q3, V BE4 is the base-emitter voltage of transistor Q4, and ΔV BE2 =V T ×ln(M2),V T =KT / q, V T is the thermal voltage of the transistor, which changes positively with temperature, K is the Boltzmann constant, T is the absolute temperature, q is the electron charge, and M2 is the ratio of the areas of transistors Q3 and Q4. It is obtained that the current I3 is proportional to the absolute temperature, that is, the current IPTAT.

[0047] After the current mirror, the current I3 is copied in proportion to the size of the transistor, and the drain current I5 of the PMOS tube MP7 is:

[0048] The current I5 is copied into the current I6 through the common source and common gate current mirror composed of NMOS tubes MN1, MN2, MN3, and MN4, and: I5 = I6

[0049] The drain current of MP8 is equal to I5, the transistor Q5 and the NMOS tube MN5 are turned on, and the drain current I7 of the MN5 tube is:

[0050] Since V BE5 is the base-emitter voltage of transistor Q5, which is inversely proportional to the absolute temperature, and I7 is the current ICTAT which is inversely proportional to the absolute temperature.

[0051] The PMOS tubes MP9 and MP10 are connected in a common source and common gate form, and together with MP11 and MP12 form a current mirror structure to replicate the current.

[0052] The drain current I8 flowing through MP9 and MP10 is the sum of the currents I6 and I7, that is:

[0053] Where ΔV BE2 Proportional to absolute temperature, V BE5It is inversely proportional to the absolute temperature. By adjusting the values ​​of K1 and R15, a reference current of appropriate size and independent of temperature can be obtained, which can be used as a current source for other circuits.

[0054] The digital trimming module includes a trimming resistor circuit, an I2C module, and a level conversion module. Figure 2 As shown in the schematic diagram of the trimming resistor circuit, the circuit is composed of a series of resistors in series. An NMOS tube is connected in parallel between each series resistor as a switch, and its conduction or closure is controlled by the I2C signal. When the NMOS tube is turned off, the total resistance and the voltage divider resistance remain unchanged, and the output voltage remains unchanged. When the MOS tube is turned on, current flows through the MOS tube, which is equivalent to the parallel resistor being short-circuited, the total resistance and the voltage divider resistance are reduced, and the output voltage changes, thereby achieving the purpose of voltage trimming.

[0055] In the resistor adjustment circuit, the switch MOS tube works, and the ports PA and P OUT The equivalent resistance between is Req1, P OUT The equivalent resistance between PB and Vref is Req2, then Vref is:

[0056]

[0057] The I2C module controls an 8-bit signal through two control lines SDA (data line) and SCL (clock line), thereby controlling the on and off of the switch MOS tube in the above-mentioned trimming resistor circuit. The resistance value in the trimming resistor circuit can be controlled by the difference in the high and low levels of each output signal, thereby achieving precise trimming of the output voltage.

[0058] The IO voltage used by the host Master is usually lower than the power supply voltage of the normal operation of the reference power supply. When the host needs to communicate with the I2C module integrated in the reference source chip, the communication interface voltage will not match. At this time, the communication interface needs to be level-converted. The above-mentioned level conversion module is to match the host interface voltage with the internal power supply voltage of the chip. Its input port A0 is connected to the I2C control clock signal SCL sent by the host Master, the input port A1 is connected to the I2C control data signal SDA sent by the host Master, the output end B0 is connected to the SCL interface corresponding to the internal I2C module of the chip, and the output end B1 is connected to the SDA interface corresponding to the internal I2C module of the chip. The level converter includes two power ports, the power port VCCA is connected to the host power supply voltage VDDA, and the power port VCCB is connected to the bandgap reference circuit working power supply voltage VDD1. Through the level converter, the high and low levels of the input signal under the power supply VDDA can be converted to the high and low levels of the signal under the power supply VDD1, thereby achieving voltage matching between the communication interface of the host and the internal I2C module of the bandgap reference circuit.

[0059] In some specific embodiments, the I2C register uses an 8-bit register, in which the default values ​​of the upper 4 bits are 0000 and the default values ​​of the lower 4 bits are 0000. By writing different control words to the register through the I2C data line, high-precision adjustment of the output can be achieved. Figure 6 When different control words are written into the register, the output reference voltage is adjusted to a value with an output trimming range of ±40mV.

[0060] Figure 3 The simulation results of the temperature characteristic curves of the reference voltage Vref of the high-precision and high-PSR bandgap reference circuit with integrated digital trimming module proposed in the present invention under different process angles.

[0061] Figure 4 The simulation results of the zero temperature coefficient current of the high-precision and high power supply rejection ratio bandgap reference circuit with integrated digital trimming module proposed in the present invention under different process angles.

[0062] Figure 5 The simulation results of the power supply rejection ratio of the high-precision and high-power supply rejection ratio bandgap reference circuit with integrated digital trimming module proposed in the present invention at different process angles.

[0063] A high-precision, high-power supply rejection ratio bandgap reference circuit with a digital adjustment function in the above-mentioned embodiment of the present invention adopts a two-stage bandgap reference voltage circuit to improve the power supply rejection ratio of the output voltage. Preliminary simulation shows that it can reach -140dB at low frequency; the reference voltage is output by a digital adjustment method (voltage accuracy adjustment), and the output voltage adjustment in the range of ±40mV can be achieved, and the adjustment accuracy reaches 3mV each time. At the same time, the adjustment module adopts I2C control and integrates a level conversion module, which can achieve multiple high-precision adjustments.

[0064] The technical features of the above embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0065] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims. The contents not described in detail in the present invention are all conventional technical contents.

Claims

1. A high-precision, high-power-supply-rejection-ratio bandgap reference circuit with an integrated digital trimming module, comprising a first-stage bandgap reference circuit, a second-stage bandgap reference circuit, a zero-temperature-coefficient current source circuit, and a digital trimming module. The first-stage bandgap reference circuit generates a first-stage reference voltage, which provides a power supply voltage for the second-stage bandgap reference circuit and the zero-temperature-coefficient current source circuit. The second-stage bandgap reference circuit generates a reference voltage with a low temperature coefficient, high precision, and a high power-supply-rejection-ratio, and simultaneously forms a PTAT current that is proportional to the absolute temperature. The zero-temperature-coefficient current source circuit can generate a zero-temperature-coefficient current. The digital trimming module can control the on and off of an internal switch MOS tube through an I2C signal from an external host, thereby trimming the reference voltage.

2. The high-precision high power supply rejection ratio bandgap reference circuit with integrated digital trimming module according to claim 1, characterized in that: The first-stage bandgap reference circuit includes PMOS tubes MP1, MP2, MP3, transistors Q1, Q2, and resistors R1, R2, R3, R4, R5, R6, and R7. Among them, the gates of MP1 and MP2 are connected to the drain of MP1 and the collector of Q1, the source of MP1 is connected to the first port of resistor R3, the source of MP2 is connected to the first port of resistor R4, the drain of MP2 is connected to the gate of MP3 and the collector of Q2, the gate of MP3 is connected to the second port of resistor R5, and the drain of MP3 is connected to the first port of resistor R6 and the power supply voltage VDD2. The first ports of resistors R3, R4, and R5 are all connected to the power supply VDD1, the first port of resistor R1 is connected to the emitter of Q2, the second port of resistor R1 is connected to the emitter of Q1 and the first port of R2, the second port of R2 is grounded, the bases of transistors Q1 and Q2 are connected to the second port of R6 and the first port of R7, and the second port of R7 is grounded.

3. The high-precision high power supply rejection ratio bandgap reference circuit with integrated digital trimming module according to claim 1, characterized in that: The second-stage bandgap reference circuit includes PMOS tubes MP4, MP5, MP6, transistors Q3, Q4, and resistors R8, R9, R10, R11, and R1. Among them, the gates of MP4 and MP5 are connected to the drain of MP4 and the collector of Q3, the source of MP4 is connected to one end of the resistor R8, the source of MP5 is connected to the first port of the resistor R9, the drain of MP5 is connected to the gate of MP6 and the collector of Q4, and the source of MP6 is connected to the second port of the resistor R12. The first ports of the resistors R8, R9, and R12 are connected to the power supply VDD2, the first port of the resistor R10 is connected to the emitter of Q4, the second port of the resistor R10 is connected to the emitter of Q3 and the first port of R11, the second port of R11 is grounded, and the bases of the transistors Q3 and Q4 are connected to the drain of MP6 and the digital trimming module.

4. The high-precision high power supply rejection ratio bandgap reference circuit with integrated digital trimming module according to claim 1, characterized in that: The zero temperature coefficient current source circuit includes PMOS tubes MP7, MP8, MP9, MP10, MP11, MP12, NMOS tubes MN1, MN2, MN3, MN4, transistor Q5, and resistors R13, R14, and R15. Among them, the gates of MP7 and MP8 are connected to the gate and drain of MP4 in the second-level voltage reference, and the current IPTAT is copied through the current mirror. The source of MP7 is connected to the second port of the resistor R13, the source of MP8 is connected to the second port of the resistor R14, and the first ports of the resistors R13 and R14 are connected to the power supply VDD2. The gates of NMOS tubes MN1, MN2, MN3, and MN4 are connected to the drain of MN3 and the drain of MP7, the drain of MN1 is connected to the source of MN3, and the drain of MN2 is connected to the source of MN4. MN1, MN2, MN3, and MN4 form a common source and common gate current mirror, and the drain of MP8 is connected to the gate of MN5 and the transistor Q5. The collector of Q5 is connected to the source of MN5 and the first port of R15, and the emitter of Q5 is grounded, and the second port of R15 is grounded. This circuit can form a current ICTAT which is inversely proportional to the absolute temperature. The drains of MN4 and MN5 are connected to the gates of MP9, MP10, MP11, MP12 and the drain of MP10. MN2, MN4, MN5, MP9, MP10, Q5, and R15 form a current summing circuit, which sums the current IPTAT with the current ICTAT to obtain a zero temperature coefficient current, and copies the current through the current mirrors of MP9, MP10, MP11, and MP12 to obtain a current IB.

5. The high-precision high power supply rejection ratio bandgap reference circuit with integrated digital trimming module according to claim 1, characterized in that: The digital trimming module includes a trimming resistor circuit, an I2C module, and a level conversion module. The trimming resistor circuit includes a first port PA, a second port PB, ports P0-P7, an output port P OUT The first port PA is connected to the base of transistors Q3 and Q4 in the second-stage bandgap reference circuit and the drain of PMOS tube MP6, the second port PB is grounded, and the output port P OUT The I2C module includes a data input port SDA, a clock input port SCL, an output port Y0-Y7, a power port VDD, and a ground port GND, wherein the SDA port is connected to the level conversion module port B1, the SCL port is connected to the level conversion module port B0, the output ports Y0-Y7 are connected to the corresponding ports P0-P7 of the trimming resistor circuit, the power port is connected to VDD1, and the ground port is grounded; the level conversion module includes a first power port VCCA, a second power port VCCB, input ports A0 and A1, output ports B0 and B1, and a ground port, wherein the first power port is connected to the host end power supply voltage VDDA, the second power port is connected to VDD1, A1 is externally connected to the data signal of the host end, A0 is externally connected to the clock signal of the host end, and the ground port is grounded.

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