Low-cost optical fiber IMU voltage acquisition circuit

Abstract

A low-cost optical fiber IMU voltage acquisition circuit comprises an isolation voltage acquisition circuit and a non-isolation voltage acquisition circuit. In the isolation voltage acquisition circuit, a DC / DC isolation power supply module T1 generates an isolation power supply + 5VGIS; the divider resistor R1 and the divider resistor R2 reduce the isolation voltage to be collected to the input range of the K1. The operational amplifier T2 forms a voltage follower circuit and buffers an isolation voltage signal to be collected; the K1 converts analog voltage into digital quantity; the digital isolator K2 performs level conversion on the digital voltage signal, and the converted voltage value is output to the FPGA in the form of an I2C bus; in the non-isolated voltage acquisition circuit, divider resistors R7-R14 divide non-isolated voltage to be acquired into an input range of a four-channel analog / digital converter K3; the operational amplifiers T3-T11 form a voltage follower circuit and are used for buffering to-be-collected isolation voltage signals; and the K3 converts the analog voltage into a digital quantity and outputs the digital quantity to the FPGA in the form of an I2C bus. The method is used for accurately collecting five paths of voltage values of gyroscope and accelerometer channels in an optical fiber IMU (Inertial Measurement Unit).

Description

Technical Field

[0001] The invention relates to a low-cost optical fiber IMU voltage acquisition circuit, belonging to the technical field of analog-to-digital conversion of inertial devices. Background Art

[0002] The fiber optic inertial measurement unit (fiber optic IMU) consists of a fiber optic gyroscope, a quartz flexible accelerometer, and an I / F conversion circuit. Among them, the power supply voltage of the fiber optic gyroscope is DC +5V_G (light source), DC +5V (digital processing), and DC -5V, and the power supply voltage of the I / F conversion circuit and the accelerometer is DC +5V, DC +15V_J, and DC -15V_J. Since the light source of the fiber optic gyroscope has high requirements on the quality of power supply, it is generally necessary to isolate the DC +5V_G (light source) from other power supplies, and +5V, -5V, +15V_J, and -15V_J can be grounded at a single point in the fiber optic IMU. The power supply voltage directly determines whether the fiber optic IMU can work normally, so it is necessary to digitally collect and monitor the 5-way power supply voltage of the fiber optic IMU. There are currently two commonly used isolation voltage acquisition methods. One is to use the transformer winding to isolate the voltage of the primary and secondary sides, and the other is to use an isolation operational amplifier to isolate the input voltage and output voltage of the op amp. Since transformer windings are generally used to isolate strong electricity from weak electricity, isolation operational amplifiers are large in size and high in cost, and the fiber-optic IMU has four non-isolated voltages and no need for isolated acquisition, these two solutions are not the best fiber-optic IMU voltage acquisition solutions. Summary of the invention

[0003] The technical problem solved by the present invention is: to overcome the shortcomings of the prior art and provide a low-cost fiber optic IMU voltage acquisition circuit for accurately acquiring 5 voltage values ​​of the gyroscope and accelerometer channels in the fiber optic IMU, to realize the monitoring of the fiber optic IMU voltage signal, and to provide a basis for locating and troubleshooting the faults of the fiber optic IMU.

[0004] The technical solution of the present invention is:

[0005] A low-cost optical fiber IMU voltage acquisition circuit, comprising: an isolated voltage acquisition circuit and a non-isolated voltage acquisition circuit;

[0006] The isolation voltage acquisition circuit acquires the isolation voltage signal +5V_G and outputs I 2 C data line signal 5VG_SDA to FPGA; the non-isolated voltage acquisition circuit collects non-isolated voltage signals +15V_J, -15V_J, +5V, -5V, and outputs I 2 C data line signal FP_SDA_IPV to FPGA;

[0007] The isolated voltage acquisition circuit includes a DC / DC isolated power supply module T1, voltage divider resistors R1 and R2, an operational amplifier T2, a single-channel analog / digital converter K1, and a digital isolator K2;

[0008] The non-isolated voltage acquisition circuit includes voltage divider resistors R7 to R14, operational amplifiers T3 to T11, and a four-channel analog / digital converter K3;

[0009] In the isolated voltage acquisition circuit, the DC / DC isolated power supply module T1 generates an isolated power supply +5V_GIS; the voltage divider resistors R1 and R2 reduce the isolated voltage to be collected to the input range of the single-channel analog / digital converter K1; the operational amplifier T2 constitutes a voltage follower circuit to buffer the isolated voltage signal to be collected; the single-channel analog / digital converter K1 converts the analog voltage into a digital quantity; the digital isolator K2 performs level conversion on the digital voltage signal, and the converted voltage value is expressed as I 2 Output to FPGA in the form of C bus;

[0010] In the non-isolated voltage acquisition circuit, the voltage-dividing resistors R7 to R14 divide the non-isolated voltage to be collected into the input range of the four-channel analog / digital converter K3; the operational amplifiers T3 to T11 form a voltage follower circuit to buffer the isolated voltage signal to be collected; the four-channel analog / digital converter K3 converts the analog voltage into a digital quantity, and outputs the digital signal as I 2 C bus to the FPGA.

[0011] Furthermore, the input pin Vin of the DC / DC isolated power supply module T1 is connected to the non-isolated voltage +5V, the GND pin is connected to the non-isolated +5V power ground AGND, and the filter capacitor C1 is connected between +5V and AGND; the output pin +Vo generates an isolated voltage +5V_GIS, the 0V pin is connected to the isolated ground GND_02 corresponding to +5V_G, and the filter capacitor C2 is connected between +5V_GIS and GND_02.

[0012] Furthermore, one end of the voltage-dividing resistor R1 is connected to +5V_G, and the other end is connected to the positive input terminal IN+ pin of the operational amplifier T2; one end of the voltage-dividing resistor R2 is connected to GND_02, and the other end is connected to the positive input terminal IN+ pin of the operational amplifier T2.

[0013] Furthermore, the negative input IN- pin of the operational amplifier T2 is short-circuited with the output OUT pin and connected to the positive input Vin+ pin of the single-channel analog / digital converter K1; the positive power supply Vs+ pin is connected to +5V_GIS and is connected to the ground GND_02 through the capacitor C3; the negative power supply Vs- pin is connected to the ground GND_02.

[0014] Furthermore, the negative input terminal Vin- pin of the single-channel analog / digital converter K1 is connected to the ground GND_02, the positive power supply terminal Vdd pin is connected to +5V_GIS, and the negative power supply terminal GND pin is connected to GND_02; a filter capacitor C4 is connected between +5V_GIS and GND_02; 2 The SCL pin of the C clock terminal is connected to the I 2 C clock 1 end SCL1 pin, I 2 The SDA pin of the C data terminal is connected to the I 2 C data 1 end SDA1 pin.

[0015] Furthermore, the first power positive terminal Vcc1 pin of the digital isolator K2 is connected to +5V_GIS, the first power negative terminal GND1 pin is connected to GND_02, the second power positive terminal Vcc2 pin is connected to +3.3V power supply signal, the second power negative terminal GND2 pin is connected to AGND, and the second I 2 C clock end SCL2 pin is connected to the FPGA output I 2 C clock signal FP_5VG_SCL, the second I 2 C data terminal SDA2 pin outputs the isolated I 2 C data signal FP_5VG_SDA; first I 2 C clock end SCL1 pin, the first I 2 The SDA1 pin of the C data terminal is connected to +5V_GIS through pull-up resistors R3 and R4 respectively. 2 C clock end SCL2 pin, the second I 2 The C data terminal SDA2 pin is connected to +3.3V through pull-up resistors R5 and R6 respectively to improve signal transmission capability.

[0016] Furthermore, one end of the voltage divider resistor R7 in the non-isolated voltage acquisition circuit is connected to +5V, and the other end is connected to the positive input terminal IN+ pin of the operational amplifier T3; one end of the voltage divider resistor R8 is connected to AGND, and the other end is connected to the positive input terminal IN+ pin of the operational amplifier T3;

[0017] The negative input terminal IN- pin of the operational amplifier T3 is short-circuited with the output terminal OUT pin, and the output terminal OUT pin outputs the signal Vin_P5; the positive power supply terminal Vs+ pin is connected to +5V and is connected to AGND through the filter capacitor C7, and the negative power supply terminal Vs- pin is connected to AGND.

[0018] Furthermore, one end of the voltage-dividing resistor R10 is connected to -5V, and the other end is connected to the positive input terminal of the operational amplifier T4; one end of the voltage-dividing resistor R9 is connected to AGND, and the other end is connected to the positive input terminal of the operational amplifier T4;

[0019] The negative input terminal IN- pin of the operational amplifier T4 is short-circuited with the output terminal OUT pin, and the output terminal OUT pin is connected to the negative input terminal IN- pin of the operational amplifier T5 through a resistor R15; the positive terminal Vs+ pin of the power supply is connected to +5V and connected to AGND through a filter capacitor C8; the negative terminal Vs- pin of the power supply is connected to -5V and connected to AGND through a filter capacitor C9;

[0020] The positive input terminal IN+ pin of the operational amplifier T5 is connected to AGND through a resistor R17, the negative input terminal IN- pin and the output terminal OUT pin are connected through a resistor R16, the positive terminal Vs+ pin of the power supply is connected to +5V and connected to AGND through a filter capacitor C11; the negative terminal Vs- pin of the power supply is connected to -5V and connected to AGND through a filter capacitor C10; the output terminal OUT pin outputs the signal Vin_N5.

[0021] Furthermore, one end of the voltage divider resistor R11 in the non-isolated voltage acquisition circuit is connected to +15V_J, and the other end is connected to the positive input terminal IN+ pin of the operational amplifier T6; one end of the voltage divider resistor R12 is connected to AGND, and the other end is connected to the positive input terminal IN+ pin of the operational amplifier T6;

[0022] The negative input terminal IN- pin of the operational amplifier T6 is short-circuited with the output terminal OUT pin, and the output terminal OUT pin outputs the signal Vin_P15J; the positive power supply terminal Vs+ pin is connected to +5V and is connected to AGND through the filter capacitor C12, and the negative power supply terminal Vs- pin is connected to AGND.

[0023] Furthermore, one end of the voltage-dividing resistor R13 is connected to -15V_J, and the other end is connected to the positive input terminal of the operational amplifier T7; one end of the voltage-dividing resistor R14 is connected to AGND, and the other end is connected to the positive input terminal of the operational amplifier T7;

[0024] The negative input terminal IN- pin of the operational amplifier T7 is short-circuited with the output terminal OUT pin, and the output terminal OUT pin is connected to the negative input terminal IN- pin of the operational amplifier T8 through a resistor R18; the positive terminal Vs+ pin of the power supply is connected to +5V and is connected to AGND through a filter capacitor C14; the negative terminal Vs- pin of the power supply is connected to -5V and is connected to AGND through a filter capacitor C13;

[0025] The positive input terminal IN+ pin of the operational amplifier T8 is connected to AGND through a resistor R20, the negative input terminal IN- pin and the output terminal OUT pin are connected through a resistor R19, the positive terminal Vs+ pin of the power supply is connected to +5V and connected to AGND through a filter capacitor C16; the negative terminal Vs- pin of the power supply is connected to -5V and connected to AGND through a filter capacitor C15; the output terminal OUT pin outputs the signal Vin_N15J.

[0026] Furthermore, the positive power supply Vdd pin of the four-channel analog / digital converter K3 is connected to +3.3V, the negative power supply GND pin is connected to AGND, and the input pins AIN0 to AIN3 are connected to Vin_P5, Vin_N5, Vin_P15J, Vin_N15J, respectively. 2 The SCL pin at the C clock end is connected to the FP_SCL_IPV signal output by the FPGA, and the I 2 The SDA pin of the C data end outputs the FP_SDA_IPV signal; the SCL pin and SDA pin are connected to +3.3V through pull-up resistors R21 and R22 respectively to improve the signal transmission capability.

[0027] Furthermore, the FPGA has a built-in digital processing program to control the working timing of the analog / digital converters K1 and K3, and output 5 voltage digital quantities for the MCU to read.

[0028] The beneficial effects of the present invention compared with the prior art are:

[0029] The present invention uses a DC / DC isolated power supply module to generate an isolated power supply to sample the isolated voltage of the optical fiber IMU; and uses a non-isolated analog / digital conversion chip to sample the non-isolated voltage of the optical fiber IMU. Without affecting the isolation of the voltage of each channel, the complexity and cost of the circuit are reduced, and the invention can be widely used in the field of voltage acquisition of the optical fiber IMU. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 It is a circuit signal block diagram of the present invention;

[0031] Figure 2 The isolated voltage acquisition circuit of the present invention;

[0032] Figure 3 This is the non-isolated voltage acquisition circuit of the present invention. DETAILED DESCRIPTION

[0033] The specific embodiments of the present invention are further described in detail below with reference to the accompanying drawings.

[0034] The specific implementation of the present invention is described below with reference to the accompanying drawings.

[0035] like Figure 1 As shown in the figure, the optical fiber IMU voltage acquisition circuit proposed by the present invention includes an isolated voltage acquisition circuit and a non-isolated voltage acquisition circuit. The isolated voltage acquisition circuit acquires the isolated voltage signal +5V_G and outputs I 2 C data line signal 5VG_SDA is sent to FPGA; the non-isolated voltage acquisition circuit collects non-isolated voltage signals +15V_J, -15V_J, +5V, -5V, and outputs I 2C data line signal FP_SDA_IPV to FPGA.

[0036] The isolated voltage acquisition circuit includes a DC / DC isolated power supply module T1, voltage divider resistors R1 and R2, an operational amplifier T2, a single-channel analog / digital converter K1, and a digital isolator K2;

[0037] The non-isolated voltage acquisition circuit includes voltage divider resistors R7 to R14, operational amplifiers T3 to T11, and a four-channel analog / digital converter K3;

[0038] In the isolated voltage acquisition circuit, the DC / DC isolated power supply module T1 generates an isolated power supply +5V_GIS; the voltage divider resistors R1 and R2 reduce the isolated voltage to be collected to the input range of the single-channel analog / digital converter K1; the operational amplifier T2 constitutes a voltage follower circuit to buffer the isolated voltage signal to be collected; the single-channel analog / digital converter K1 converts the analog voltage into a digital quantity; the digital isolator K2 performs level conversion on the digital voltage signal, and the converted voltage value is expressed as I 2 Output to FPGA in the form of C bus;

[0039] In the non-isolated voltage acquisition circuit, the voltage-dividing resistors R7 to R14 divide the non-isolated voltage to be collected into the input range of the four-channel analog / digital converter K3; the operational amplifiers T3 to T11 form a voltage follower circuit to buffer the isolated voltage signal to be collected; the four-channel analog / digital converter K3 converts the analog voltage into a digital quantity, and outputs the digital signal as I 2 C bus to the FPGA.

[0040] The input pin Vin of the DC / DC isolated power supply module T1 is connected to the non-isolated voltage +5V, the GND pin is connected to the non-isolated +5V power ground AGND, and the filter capacitor C1 is connected between +5V and AGND; the output pin +Vo generates an isolated voltage +5V_GIS, the 0V pin is connected to the isolated ground GND_02 corresponding to +5V_G, and the filter capacitor C2 is connected between +5V_GIS and GND_02.

[0041] One end of the voltage-dividing resistor R1 is connected to +5V_G, and the other end is connected to the positive input terminal IN+ pin of the operational amplifier T2; one end of the voltage-dividing resistor R2 is connected to GND_02, and the other end is connected to the positive input terminal IN+ pin of the operational amplifier T2.

[0042] The negative input terminal IN- pin of the operational amplifier T2 is short-circuited with the output terminal OUT pin and connected to the positive input terminal Vin+ pin of the single-channel analog / digital converter K1; the positive power supply terminal Vs+ pin is connected to +5V_GIS and is connected to the ground GND_02 through the capacitor C3; the negative power supply terminal Vs- pin is connected to the ground GND_02.

[0043] The negative input terminal Vin- pin of the single-channel analog / digital converter K1 is connected to the ground GND_02, the positive power supply terminal Vdd pin is connected to +5V_GIS, and the negative power supply terminal GND pin is connected to GND_02; a filter capacitor C4 is connected between +5V_GIS and GND_02; I 2 The SCL pin of the C clock terminal is connected to the I 2 C clock 1 end SCL1 pin, I 2 The SDA pin of the C data terminal is connected to the I 2 C data 1 end SDA1 pin.

[0044] The first power positive terminal Vcc1 pin of the digital isolator K2 is connected to +5V_GIS, the first power negative terminal GND1 pin is connected to GND_02, the second power positive terminal Vcc2 pin is connected to +3.3V power supply signal, the second power negative terminal GND2 pin is connected to AGND, and the second I 2 C clock end SCL2 pin is connected to the FPGA input I 2 C clock signal FP_5VG_SCL, the second I 2 C data terminal SDA2 pin outputs the isolated I 2 C data signal FP_5VG_SDA; first I 2 C clock end SCL1 pin, the first I 2 The SDA1 pin of the C data terminal is connected to +5V_GIS through pull-up resistors R3 and R4 respectively. 2 C clock end SCL2 pin, the second I 2 The C data terminal SDA2 pin is connected to +3.3V through pull-up resistors R5 and R6 respectively to improve signal transmission capability.

[0045] One end of the voltage divider resistor R7 in the non-isolated voltage acquisition circuit is connected to +5V, and the other end is connected to the positive input terminal IN+ pin of the operational amplifier T3; one end of the voltage divider resistor R8 is connected to AGND, and the other end is connected to the positive input terminal IN+ pin of the operational amplifier T3;

[0046] The negative input terminal IN- pin of the operational amplifier T3 is short-circuited with the output terminal OUT pin, and the output terminal OUT pin outputs the signal Vin_P5; the positive power supply terminal Vs+ pin is connected to +5V and is connected to AGND through the filter capacitor C7, and the negative power supply terminal Vs- pin is connected to AGND.

[0047] One end of the voltage-dividing resistor R10 is connected to -5V, and the other end is connected to the positive input terminal of the operational amplifier T4; one end of the voltage-dividing resistor R9 is connected to AGND, and the other end is connected to the positive input terminal of the operational amplifier T4;

[0048] The negative input terminal IN- pin of the operational amplifier T4 is short-circuited with the output terminal OUT pin, and the output terminal OUT pin is connected to the negative input terminal IN- pin of the operational amplifier T5 through a resistor R15; the positive terminal Vs+ pin of the power supply is connected to +5V and connected to AGND through a filter capacitor C8; the negative terminal Vs- pin of the power supply is connected to -5V and connected to AGND through a filter capacitor C9;

[0049] The positive input terminal IN+ pin of the operational amplifier T5 is connected to AGND through a resistor R17, the negative input terminal IN- pin and the output terminal OUT pin are connected through a resistor R16, the positive terminal Vs+ pin of the power supply is connected to +5V and connected to AGND through a filter capacitor C11; the negative terminal Vs- pin of the power supply is connected to -5V and connected to AGND through a filter capacitor C10; the output terminal OUT pin outputs the signal Vin_N5.

[0050] One end of the voltage divider resistor R11 in the non-isolated voltage acquisition circuit is connected to +15_J, and the other end is connected to the positive input terminal IN+ pin of the operational amplifier T6; one end of the voltage divider resistor R12 is connected to AGND, and the other end is connected to the positive input terminal IN+ pin of the operational amplifier T6;

[0051] The negative input terminal IN- pin of the operational amplifier T6 is short-circuited with the output terminal OUT pin, and the output terminal OUT pin outputs the signal Vin_P15J; the positive power supply terminal Vs+ pin is connected to +5V and is connected to AGND through the filter capacitor C12, and the negative power supply terminal Vs- pin is connected to AGND.

[0052] One end of the voltage-dividing resistor R13 is connected to -15_J, and the other end is connected to the positive input terminal of the operational amplifier T7; one end of the voltage-dividing resistor R14 is connected to AGND, and the other end is connected to the positive input terminal of the operational amplifier T7;

[0053] The negative input terminal IN- pin of the operational amplifier T7 is short-circuited with the output terminal OUT pin, and the output terminal OUT pin is connected to the negative input terminal IN- pin of the operational amplifier T8 through a resistor R18; the positive terminal Vs+ pin of the power supply is connected to +5V and is connected to AGND through a filter capacitor C14; the negative terminal Vs- pin of the power supply is connected to -5V and is connected to AGND through a filter capacitor C13;

[0054] The positive input terminal IN+ pin of the operational amplifier T8 is connected to AGND through a resistor R20, the negative input terminal IN- pin and the output terminal OUT pin are connected through a resistor R19, the positive terminal Vs+ pin of the power supply is connected to +5V and connected to AGND through a filter capacitor C16; the negative terminal Vs- pin of the power supply is connected to -5V and connected to AGND through a filter capacitor C15; the output terminal OUT pin outputs the signal Vin_N15J.

[0055] The positive power supply Vdd pin of the four-channel analog / digital converter K3 is connected to +3.3V, the negative power supply GND pin is connected to AGND, and the input pins AIN0 to AIN3 are connected to Vin_P5, Vin_N5, Vin_P15J, Vin_N15J, respectively. 2 The SCL pin at the C clock end is connected to the FP_SCL_IPV signal output by the FPGA, and the I 2 The SDA pin of the C data end outputs the FP_SDA_IPV signal; the SCL pin and SDA pin are connected to +3.3V through pull-up resistors R21 and R22 respectively to improve the signal transmission capability.

[0056] The FPGA has a built-in digital processing program to control the working timing of the analog / digital converters K1 and K3, and output 5 voltage digital quantities for the MCU to read.

[0057] Example:

[0058] like Figure 2 As shown, the isolated voltage acquisition circuit includes a DC / DC isolated power supply module T1, voltage divider resistors R1 and R2, an operational amplifier T2, a single-channel analog / digital converter K1, a digital isolator K2, capacitors C1 to C6, and resistors R1 to R6.

[0059] Among them, the input pin Vin of the DC / DC isolated power supply module T1 is connected to the non-isolated voltage +5V, the GND pin is connected to the +5V power ground AGND, and a 4.7uF filter capacitor C1 is connected between +5V and AGND; the output pin +Vo generates an isolated power supply +5V_GIS, and the 0V pin is connected to the isolated power ground GND_02 corresponding to +5V_G.

[0060] Connect a 10uF filter capacitor C2 between +5V_GIS and GND_02;

[0061] One end of the voltage divider resistor R1 is connected to +5V_G, and the other end is connected to the positive input terminal IN+ of the operational amplifier T2; one end of the voltage divider resistor R2 is connected to GND_02, and the other end is connected to the positive input terminal IN+ of the operational amplifier T2;

[0062] The negative input terminal IN- of the operational amplifier T2 is short-circuited with the output terminal OUT, and connected to the positive input terminal Vin+ of the single-channel analog / digital converter K1; the power supply Vs+ pin is connected to +5V_GIS, and is connected to GND_02 through a 0.1uF filter capacitor C3; the power supply ground Vs- pin is connected to GND_02;

[0063] The negative input terminal Vin- pin and the power ground GND pin of the single-channel analog / digital converter K1 are both connected to GND_02, the power supply Vdd pin is connected to +5V_GIS, and a 0.1uF filter capacitor C4 is connected between GND_02 and +5V_GIS; I2 The SCL pin of the C clock terminal is connected to the I 2 C clock 1 end SCL1 pin, I 2 The SDA pin of the C data terminal is connected to the I 2 C data 1 end SDA1 pin;

[0064] The Vcc1 pin of the digital isolator K2 is connected to +5V_GIS and connected to GND_02 through a 0.1uF capacitor C5; the GND1 pin is connected to GND_02; the Vcc2 pin is connected to the power supply signal +3.3V and connected to AGND through a 0.1uF capacitor C6; the GND2 pin is connected to AGND; the SDA2 pin outputs the isolated I 2 C data line signal FP_5VG_SDA, SCL2 pin is connected to FPGA input I 2 C clock signal FP_5VG_SCL; SCL1 pin and SDA1 pin are connected to +5V_GIS through 10KΩ pull-up resistors R3 and R4 respectively, and SCL2 pin and SDA2 pin are connected to +3.3V through 10KΩ pull-up resistors R5 and R6 respectively;

[0065] The digital isolator K2 outputs the data line signal FP_5VG_SDA into the FPGA, and the FPGA controls the conversion timing of the single-channel analog / digital converter K1 and converts I 2 C's serial data is processed into parallel data and placed into the FPGA register for reading by the MCU.

[0066] like Figure 3 As shown, the non-isolated voltage acquisition circuit includes: voltage divider resistors R7-R12, resistors R15-R22, operational amplifiers T3-T8, four-channel analog / digital converter K3, and capacitors C7-C18. The non-isolated voltage acquisition circuit collects non-isolated voltage signals +15V_J, -15V_J, +5V, -5V, and outputs I 2 C data line signal FP_SDA_IPV to FPGA.

[0067] Among them, one end of the voltage divider resistor R7 is connected to +5V, and the other end is connected to the positive input terminal IN+ of the operational amplifier T3; one end of the voltage divider resistor R8 is connected to AGND, and the other end is connected to the positive input terminal IN+ of the operational amplifier T3;

[0068] The negative input terminal IN- of the operational amplifier T3 is short-circuited with the output terminal OUT, and the signal Vin_P5 is output; the power supply Vs+ pin is connected to +5V and connected to AGND through a 0.1uF capacitor C7; the power supply ground Vs- pin is connected to AGND;

[0069] One end of the voltage-dividing resistor R10 is connected to -5V, and the other end is connected to the positive input terminal IN+ of the operational amplifier T4; one end of the voltage-dividing resistor R9 is connected to AGND, and the other end is connected to the positive input terminal IN+ of the operational amplifier T4;

[0070] The negative input terminal IN- of the operational amplifier T4 is short-circuited with the output terminal OUT, the power supply Vs+ pin is connected to +5V and connected to AGND through a 0.1uF capacitor C8; the power ground Vs- pin is connected to -5V and connected to AGND through a 0.1uF capacitor C9; the output pin OUT is connected to the negative input terminal IN- of the operational amplifier T5 through a resistor R15;

[0071] The positive input terminal IN+ of the operational amplifier T5 is connected to AGND through a resistor R17, and the negative input terminal IN- is connected to the output terminal OUT through a resistor R16; the power supply Vs+ pin is connected to +5V and connected to AGND through a capacitor C11; the Vs- pin is connected to -5V and connected to AGND through a 0.1uF capacitor C10; the output terminal OUT outputs the signal Vin_N5;

[0072] The circuit connection method of the voltage-dividing resistors R11, R12, operational amplifier T6, and capacitor C12 is the same as that of the voltage-dividing resistors R7, R8, operational amplifier T3, and capacitor C7. Only the input end of the circuit is changed from +5V to +15V_J, and the circuit outputs the Vin_P15J signal.

[0073] The circuit connection method of the voltage-dividing resistors R13 and R14, operational amplifiers T7 and T8, capacitors C13 to C16, and resistors R18 to R20 is the same as that of the voltage-dividing resistors R10 and R9, operational amplifiers T4 and T5, capacitors C8 to C11, and resistors R15 to R17. Only the input terminal of the circuit is changed from -5V to -15V_J, and the circuit outputs Vin_N15J signal;

[0074] The Vdd pin of the four-channel analog / digital converter K3 is connected to the power supply +3.3V, and is connected to AGND through the capacitors C17 and C18 connected in parallel; the GND pin is connected to AGND, the AIN0~AIN3 pins are connected to Vin_P5, Vin_N5, Vin_P15J, and Vin_N15J respectively, the SCL pin is connected to the FP_SCL_IPV signal output by the FPGA, and the SDA pin outputs the FP_SDA_IPV signal; the SDA pin and the SCL pin are connected to +3.3V through 4.7KΩ pull-up resistors R22 and R21 respectively to improve the signal transmission capability; the ALT / RDY pin is connected to +3.3V through a 10KΩ pull-up resistor R23 to ensure that the chip is in a ready state.

[0075] The four-channel analog / digital converter K3 outputs I 2C data line signal FP_SDA_IPV enters the FPGA, and the FPGA controls the conversion timing of the four-channel analog / digital converter K3 and converts I 2 C's serial data is processed into parallel data and placed into the FPGA register for reading by the MCU.

[0076] The above is only the best implementation scheme of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by technicians familiar with the technical field within the technical scope disclosed in the present invention should be covered within the protection scope of the present invention.

[0077] Parts of the present invention that are not described in detail belong to common knowledge among those skilled in the art.

Claims

1. A low-cost optical fiber IMU voltage acquisition circuit, characterized in that include: Isolated voltage acquisition circuit and non-isolated voltage acquisition circuit; The isolation voltage acquisition circuit acquires the isolation voltage signal +5V_G and outputs I 2 C data line signal 5VG_SDA to FPGA; the non-isolated voltage acquisition circuit collects non-isolated voltage signals +15V_J, -15V_J, +5V, -5V, and outputs I 2 C data line signal FP_SDA_IPV to FPGA; The isolated voltage acquisition circuit includes a DC / DC isolated power supply module T1, voltage divider resistors R1 and R2, an operational amplifier T2, a single-channel analog / digital converter K1, and a digital isolator K2; The non-isolated voltage acquisition circuit includes voltage divider resistors R7 to R14, operational amplifiers T3 to T11, and a four-channel analog / digital converter K3; In the isolated voltage acquisition circuit, the DC / DC isolated power supply module T1 generates an isolated power supply +5V_GIS; the voltage divider resistors R1 and R2 reduce the isolated voltage to be collected to the input range of the single-channel analog / digital converter K1; the operational amplifier T2 forms a voltage follower circuit to buffer the isolated voltage signal to be collected; The single-channel analog / digital converter K1 converts the analog voltage into a digital value; the digital isolator K2 performs level conversion on the digital voltage signal, and the converted voltage value is expressed as I 2 Output to FPGA in the form of C bus; In the non-isolated voltage acquisition circuit, the voltage-dividing resistors R7 to R14 divide the non-isolated voltage to be collected into the input range of the four-channel analog / digital converter K3; the operational amplifiers T3 to T11 form a voltage follower circuit to buffer the isolated voltage signal to be collected; the four-channel analog / digital converter K3 converts the analog voltage into a digital quantity, and outputs the digital signal as I 2 C bus to the FPGA.

2. A low-cost optical fiber IMU voltage acquisition circuit according to claim 1, characterized in that: The input pin Vin of the DC / DC isolated power supply module T1 is connected to the non-isolated voltage +5V, the GND pin is connected to the non-isolated +5V power ground AGND, and the filter capacitor C1 is connected between +5V and AGND; the output pin +Vo generates an isolated voltage +5V_GIS, the 0V pin is connected to the isolated ground GND_02 corresponding to +5V_G, and the filter capacitor C2 is connected between +5V_GIS and GND_02.

3. A low-cost optical fiber IMU voltage acquisition circuit according to claim 1, characterized in that: One end of the voltage-dividing resistor R1 is connected to +5V_G, and the other end is connected to the positive input terminal IN+ pin of the operational amplifier T2; one end of the voltage-dividing resistor R2 is connected to GND_02, and the other end is connected to the positive input terminal IN+ pin of the operational amplifier T2.

4. A low-cost optical fiber IMU voltage acquisition circuit according to claim 1, characterized in that: The negative input terminal IN- pin of the operational amplifier T2 is short-circuited with the output terminal OUT pin and connected to the positive input terminal Vin+ pin of the single-channel analog / digital converter K1; the positive power supply terminal Vs+ pin is connected to +5V_GIS and is connected to the ground GND_02 through the capacitor C3; the negative power supply terminal Vs- pin is connected to the ground GND_02.

5. A low-cost optical fiber IMU voltage acquisition circuit according to claim 1, characterized in that: The negative input terminal Vin- pin of the single-channel analog / digital converter K1 is connected to the ground GND_02, the positive power supply terminal Vdd pin is connected to +5V_GIS, and the negative power supply terminal GND pin is connected to GND_02; a filter capacitor C4 is connected between +5V_GIS and GND_02; I 2 The SCL pin of the C clock terminal is connected to the I 2 C clock 1 end SCL1 pin, I 2 The SDA pin of the C data terminal is connected to the I 2 C data 1 end SDA1 pin.

6. A low-cost optical fiber IMU voltage acquisition circuit according to claim 5, characterized in that: The first power positive terminal Vcc1 pin of the digital isolator K2 is connected to +5V_GIS, the first power negative terminal GND1 pin is connected to GND_02, the second power positive terminal Vcc2 pin is connected to +3.3V power supply signal, the second power negative terminal GND2 pin is connected to AGND, and the second I 2 C clock end SCL2 pin is connected to the FPGA output I 2 C clock signal FP_5VG_SCL, the second I 2 C data terminal SDA2 pin outputs the isolated I 2 C data signal FP_5VG_SDA; first I 2 C clock end SCL1 pin, the first I 2 C data end SDA1 pin is connected to +5V_GIS through pull-up resistors R3 and R4 respectively, and the second I 2 C clock end SCL2 pin, the second I 2 The C data terminal SDA2 pin is connected to +3.3V through pull-up resistors R5 and R6 respectively to improve signal transmission capability.

7. A low-cost optical fiber IMU voltage acquisition circuit according to any one of claims 1-6, characterized in that: One end of the voltage divider resistor R7 in the non-isolated voltage acquisition circuit is connected to +5V, and the other end is connected to the positive input terminal IN+ pin of the operational amplifier T3; one end of the voltage divider resistor R8 is connected to AGND, and the other end is connected to the positive input terminal IN+ pin of the operational amplifier T3; The negative input terminal IN- pin of the operational amplifier T3 is short-circuited with the output terminal OUT pin, and the output terminal OUT pin outputs the signal Vin_P5; the positive power supply terminal Vs+ pin is connected to +5V and is connected to AGND through the filter capacitor C7, and the negative power supply terminal Vs- pin is connected to AGND.

8. A low-cost optical fiber IMU voltage acquisition circuit according to claim 7, characterized in that: One end of the voltage-dividing resistor R10 is connected to -5V, and the other end is connected to the positive input terminal of the operational amplifier T4; one end of the voltage-dividing resistor R9 is connected to AGND, and the other end is connected to the positive input terminal of the operational amplifier T4; The negative input terminal IN- pin of the operational amplifier T4 is short-circuited with the output terminal OUT pin, and the output terminal OUT pin is connected to the negative input terminal IN- pin of the operational amplifier T5 through a resistor R15; the positive terminal Vs+ pin of the power supply is connected to +5V and connected to AGND through a filter capacitor C8; the negative terminal Vs- pin of the power supply is connected to -5V and connected to AGND through a filter capacitor C9; The positive input terminal IN+ pin of the operational amplifier T5 is connected to AGND through a resistor R17, the negative input terminal IN- pin and the output terminal OUT pin are connected through a resistor R16, the positive terminal Vs+ pin of the power supply is connected to +5V and connected to AGND through a filter capacitor C11; the negative terminal Vs- pin of the power supply is connected to -5V and connected to AGND through a filter capacitor C10; the output terminal OUT pin outputs the signal Vin_N5.

9. A low-cost optical fiber IMU voltage acquisition circuit according to claim 7, characterized in that: One end of the voltage divider resistor R11 in the non-isolated voltage acquisition circuit is connected to +5V, and the other end is connected to the positive input terminal IN+ pin of the operational amplifier T6; one end of the voltage divider resistor R12 is connected to AGND, and the other end is connected to the positive input terminal IN+ pin of the operational amplifier T6; The negative input terminal IN- pin of the operational amplifier T6 is short-circuited with the output terminal OUT pin, and the output terminal OUT pin outputs the signal Vin_P15J; the positive power supply terminal Vs+ pin is connected to +5V and is connected to AGND through the filter capacitor C12, and the negative power supply terminal Vs- pin is connected to AGND.

10. A low-cost optical fiber IMU voltage acquisition circuit according to claim 7, characterized in that: One end of the voltage-dividing resistor R13 is connected to -5V, and the other end is connected to the positive input terminal of the operational amplifier T7; one end of the voltage-dividing resistor R14 is connected to AGND, and the other end is connected to the positive input terminal of the operational amplifier T7; The negative input terminal IN- pin of the operational amplifier T7 is short-circuited with the output terminal OUT pin, and the output terminal OUT pin is connected to the negative input terminal IN- pin of the operational amplifier T8 through a resistor R18; the positive terminal Vs+ pin of the power supply is connected to +5V and is connected to AGND through a filter capacitor C14; the negative terminal Vs- pin of the power supply is connected to -5V and is connected to AGND through a filter capacitor C13; The positive input terminal IN+ pin of the operational amplifier T8 is connected to AGND through a resistor R20, the negative input terminal IN- pin and the output terminal OUT pin are connected through a resistor R19, the positive terminal Vs+ pin of the power supply is connected to +5V and connected to AGND through a filter capacitor C16; the negative terminal Vs- pin of the power supply is connected to -5V and connected to AGND through a filter capacitor C15; the output terminal OUT pin outputs the signal Vin_N15J.

11. A low-cost optical fiber IMU voltage acquisition circuit according to claim 7, characterized in that: The positive power supply Vdd pin of the four-channel analog / digital converter K3 is connected to +3.3V, the negative power supply GND pin is connected to AGND, and the input pins AIN0 to AIN3 are connected to Vin_P5, Vin_N5, Vin_P15J, Vin_N15J, respectively. 2 The SCL pin at the C clock end is connected to the FP_SCL_IPV signal output by the FPGA, and the I 2 The SDA pin of the C data end outputs the FP_SDA_IPV signal; the SCL pin and SDA pin are connected to +3.3V through pull-up resistors R20 and R21 respectively to improve the signal transmission capability.

12. A low-cost optical fiber IMU voltage acquisition circuit according to claim 7, characterized in that: The FPGA has a built-in digital processing program to control the working timing of the analog / digital converters K1 and K3, and output 5 voltage digital quantities for the MCU to read.

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