Level shift circuit with wide input range and low power consumption

Abstract

The invention discloses a wide-input-range low-power-consumption level shift circuit, which relates to the technical field of electronic equipment and comprises a current mirror branch and a logic error diagnosis circuit. The current mirror branch is connected with the logic error diagnosis circuit; the current mirror branch at least comprises a first phase inverter and a second phase inverter; the first phase inverter and the second phase inverter are used for ensuring that the static power consumption is about zero and reducing the transient power consumption of the circuit; the logic error diagnosis circuit is used for ensuring that the input level is consistent with the output level. The level shift circuit is constructed by adopting the current mirror, so that the competitive relationship between an NMOS (N-channel Metal Oxide Semiconductor) and a PMOS (P-channel Metal Oxide Semiconductor) is avoided, and a wide input voltage range can be A phase inverter is inserted into a current mirror branch to reduce power consumption. The logic error diagnosis circuit avoids a logic error caused by inconsistent input and output levels of the shifter; level conversion in a wide input voltage range is achieved, low static power consumption and dynamic power consumption are achieved, and rail-to-rail output swing can be achieved.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic equipment, and in particular to a low-power level shift circuit with a wide input range. Background Art

[0002] A level shift circuit is a circuit used to transfer signals between different voltage domains. Its main function is to change the input signal from one voltage domain to the target voltage domain. Level shift circuits are crucial in modern integrated circuit design, especially in low-power, high-integration, and multi-voltage domain SoCs. In a multi-voltage domain system, signals need to be transmitted between different voltage domains. This transmission may cause voltage mismatch problems, which may cause the circuit to not work properly. Level shift circuits ensure that signals can be correctly transmitted and processed by adapting to different voltage requirements. They are often used in communications between processors and peripherals, analog and digital circuit interfaces, and asynchronous communication circuits.

[0003] Therefore, there is an urgent need to provide a reliable, wide input range, low power consumption level shifting circuit. Summary of the invention

[0004] The object of the present invention is to provide a low-power level shift circuit with a wide input range, which is used to achieve level conversion in a wide input voltage range while ensuring low static power consumption and dynamic power consumption.

[0005] In order to achieve the above object, the present invention provides the following technical solutions:

[0006] In a first aspect, the present invention provides a wide input range low power consumption level shifting circuit, comprising:

[0007] Current mirror branch and logic error diagnosis circuit;

[0008] The current mirror branch is connected to the logic error diagnosis circuit;

[0009] The current mirror branch includes at least a first inverter and a second inverter; the first inverter and the second inverter are used to ensure that the static power consumption is approximately zero; the logic error diagnosis circuit is used to ensure that the input level is consistent with the output level.

[0010] Optionally, the current mirror branch includes a first PMOS tube, a second PMOS tube, a first NMOS tube, a first inverter and a second inverter;

[0011] The first inverter includes a fifth PMOS tube and a fifth NMOS tube; the second inverter includes a sixth PMOS tube and a second NMOS tube.

[0012] Optionally, the logic error diagnosis circuit at least includes:

[0013] a third PMOS tube, a fourth PMOS tube, a seventh PMOS tube, a third NMOS tube, a fourth NMOS tube and a sixth NMOS tube.

[0014] Optionally, the source of the first PMOS tube is connected to the source of the second PMOS tube, the drain of the first PMOS tube is connected to the source of the fifth PMOS tube, the gate of the first PMOS tube is connected to the gate of the second PMOS tube, the drain of the fifth PMOS tube and the drain of the fifth NMOS tube; the source of the fifth NMOS tube is connected to the drain of the first NMOS tube, and the source of the first NMOS tube is grounded;

[0015] The drain of the second PMOS tube is connected to the source of the sixth PMOS tube, the gate of the sixth PMOS tube is connected to the gate of the second NMOS tube, and the source of the second NMOS tube is grounded.

[0016] Optionally, the drain of the third PMOS tube is connected to the source of the seventh PMOS tube, and the drain of the seventh PMOS tube is connected to the drain of the third NMOS tube; the source of the third NMOS tube is grounded, and the gate of the third PMOS tube is connected to the gate of the fourth PMOS tube; the drain of the fourth PMOS tube is connected to the drain of the sixth NMOS tube, the source of the sixth NMOS tube is connected to the drain of the fourth NMOS tube, and the source of the fourth NMOS tube is grounded.

[0017] Optionally, when the input changes from a low level to a high level, the initial value of the output is a high level, the first NMOS tube is turned on, the fifth PMOS tube is turned on, the second PMOS tube is turned on, and the sixth PMOS tube is turned on, and the output is a high level.

[0018] Optionally, when the input changes from a high level to a low level, the initial value of the output is a high level, the fourth NMOS tube, the sixth NMOS tube, the third PMOS tube and the fourth PMOS tube are turned on, the seventh PMOS tube is turned on, and the output is a high level.

[0019] Optionally, when the input changes from a high level to a low level, the initial value of the output is a high level, the fourth NMOS tube and the sixth NMOS tube are turned on, current flows through the third PMOS tube and the fourth PMOS tube, and the output voltage becomes a low level, which is consistent with the input voltage potential.

[0020] Optionally, when the voltage difference between VDDL and VDDH is large, the PMOS with the gate and drain shorted directly realizes the conversion from VDDL to VDDH.

[0021] Compared with the prior art, the present invention provides a low-power level shift circuit with a wide input range. It includes a current mirror branch and a logic error diagnosis circuit; the current mirror branch is connected to the logic error diagnosis circuit; the current mirror branch includes at least a first inverter and a second inverter; the first inverter and the second inverter are used to ensure that the static power consumption is approximately zero and reduce the transient power consumption of the circuit; the logic error diagnosis circuit is used to ensure that the input level is consistent with the output level. The present invention adopts a current mirror architecture level shift circuit to avoid the competition between NMOS and PMOS, and can achieve a wide input voltage range; inserting an inverter in the current mirror branch reduces power consumption. The logic error diagnosis circuit avoids the logic error of inconsistent input and output levels of the shifter; realizes level conversion in a wide input voltage range, has low static power consumption and dynamic power consumption, and can achieve rail-to-rail output swing. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0023] Figure 1 It is a structural schematic diagram of a level shifter based on a cross-coupling structure in the prior art 1;

[0024] Figure 2 It is a structural schematic diagram of a level shifter based on current mirror technology in the second prior art;

[0025] Figure 3 A schematic diagram of the structure of a wide input range and low power consumption level shift circuit provided by the present invention;

[0026] FIG4(a) is a diagram showing power consumption simulation results of level shift circuits with different structures when the input changes from low to high, and a diagram showing simulation results of the level function verification of the structure of the present invention;

[0027] FIG4( b ) is a diagram showing power consumption simulation results of level shift circuits with different structures when the input changes from high to low, and a diagram showing simulation results of the structure level function verification of the present invention.

[0028] Reference numerals:

[0029] 1-current mirror branch, 2-logic error diagnosis circuit, 11-first inverter, 12-second inverter, MP1-first PMOS tube, MP2-second PMOS tube, MP3-third PMOS tube, MP4-fourth PMOS tube, MP5-fifth PMOS tube, MP6-sixth PMOS tube, MP7-seventh PMOS tube, MN1-first NMOS tube, MN2-second NMOS tube, MN3-third NMOS tube, MN4-fourth NMOS tube, MN5-fifth NMOS tube, MN6-sixth NMOS tube. DETAILED DESCRIPTION

[0030] In order to clearly describe the technical solutions of the embodiments of the present invention, in the embodiments of the present invention, words such as "first" and "second" are used to distinguish the same items or similar items with basically the same functions and effects. For example, the first threshold and the second threshold are only used to distinguish different thresholds, and their order is not limited. Those skilled in the art can understand that words such as "first" and "second" do not limit the quantity and execution order, and words such as "first" and "second" do not necessarily limit them to be different.

[0031] It should be noted that, in the present invention, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the present invention should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0032] In the present invention, "at least one" means one or more, and "plurality" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the associated objects before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can mean: a, b, c, the combination of a and b, the combination of a and c, the combination of b and c, or the combination of a, b and c, where a, b, c can be single or multiple.

[0033] First, some abbreviations, English and key term definitions used in the embodiments of this specification are explained:

[0034] NMOS tube (N-type metal-oxide-semiconductor field-effect transistor).

[0035] PMOS tube (P-type metal-oxide-semiconductor field-effect transistor).

[0036] SoC (System on Chip).

[0037] In the prior art, there are two commonly used level shift circuit technologies. The level shift circuit based on the cross-coupling structure has competition between NMOS and PMOS. When the voltage difference between the high-voltage domain and the low-voltage domain is large, a large-sized NMOS tube is required, which occupies a large area. The level shift circuit based on the current mirror architecture has the problem of large static power consumption. The two structures are as follows: Figure 1 and Figure 2 Next, two common solutions in the prior art are described respectively:

[0038] Prior art 1. Figure 1 As shown in the figure, the level shift circuit based on the cross-coupling structure consists of an inverter, two NMOS and two PMOS. When IN changes from low to high, MN1 turns on, the X node is low, and then MP2 turns on, and OUT is high. Conversely, when IN changes from high to low, MN2 turns on, and OUT is low. If the voltage difference between VDDH and VDDDL is large, MP2 and MN2 will compete with each other, and the OUT potential will be unstable, which is not suitable for wide input voltage applications.

[0039] Prior art II. Figure 2 As shown in the figure, the level shift circuit based on current mirror technology consists of a set of current mirrors, two NMOS and an inverter. When IN changes from low to high, MN1 is turned on, the gates of MP1 and MP2 are low, and then MP2 is turned on, and OUT is high. Conversely, when IN changes from high to low, MN2 is turned on, and OUT is low. Figure 2 The circuit in this circuit has a large static current and consumes a lot of power, so it is not suitable for low-power applications.

[0040] In view of the defects in the prior art, the present invention provides a low-power level shift circuit with a wide input range. Next, the scheme provided by the embodiments of this specification is described in conjunction with the accompanying drawings:

[0041] like Figure 3 As shown, the present invention provides a wide input range low power consumption level shift circuit which may include the following structure:

[0042] A current mirror branch 1 and a logic error diagnosis circuit 2;

[0043] The current mirror branch 1 is connected to the logic error diagnosis circuit 2;

[0044] The current mirror branch 1 at least includes a first inverter 11 and a second inverter 12; the first inverter 11 and the second inverter 12 are used to ensure that the static power consumption is approximately zero; the logic error diagnosis circuit 2 is used to ensure that the input level is consistent with the output level.

[0045] In the above circuit structure, there are many current sources in the actual circuit. Usually, the device matching method is applied, and only one "reference current source" is used as the input to provide bias voltage for multiple current sources, or directly provide multiple constant currents. The structure composed of these matching devices is called a current mirror, which is a special case of a constant current source circuit. Its controlled current is equal to the input reference current, that is, the input-output current transfer ratio is equal to 1.

[0046] The inverter can reverse the phase of the input signal by 180 degrees. This circuit is used in analog circuits, such as audio amplifiers, clock oscillators, etc. Inverters are often used in electronic circuit design. The CMOS inverter circuit consists of two enhancement MOS field effect transistors. The typical TTL NAND gate circuit consists of an input stage, an intermediate stage, and an output stage.

[0047] Figure 3 The circuit in the embodiment avoids the competition between NMOS and PMOS by adopting the current mirror architecture level shift circuit, and can achieve a wide input voltage range; inserting an inverter in the current mirror branch 1 reduces power consumption. The logic error diagnosis circuit 2 avoids the logic error of inconsistent input and output levels of the shifter; realizes level conversion in a wide input voltage range, has low static power consumption and dynamic power consumption, and can achieve rail-to-rail output swing.

[0048] based on Figure 3 The present specification also provides some specific implementations of the circuit, which will be described below.

[0049] for Figure 3 The specific structure of the current mirror branch 1 in FIG. 1 is described as follows:

[0050] exist Figure 3 In the embodiment, the current mirror branch 1 may include two branches, and the first inverter 11 and the second inverter 12 are added to the two branches respectively. Specifically, the current mirror branch 1 may include a first PMOS transistor MP1, a second PMOS transistor MP2, a first NMOS transistor MN1, a first inverter 11 and a second inverter 12;

[0051] The first inverter 11 may include a fifth PMOS transistor MP5 and a fifth NMOS transistor MN5 ; the second inverter 12 may include a sixth PMOS transistor MP6 and a second NMOS transistor MN2 .

[0052] The connection relationship of the above structure is: the source of the first PMOS tube MP1 is connected to the source of the second PMOS tube MP2, the drain of the first PMOS tube MP1 is connected to the source of the fifth PMOS tube MP5, the gate of the first PMOS tube MP1 is connected to the gate of the second PMOS tube MP2, the drain of the fifth PMOS tube MP5 and the drain of the fifth NMOS tube MN5; the source of the fifth NMOS tube MN5 is connected to the drain of the first NMOS tube MN1, and the source of the first NMOS tube MN1 is grounded;

[0053] The drain of the second PMOS transistor MP2 is connected to the source of the sixth PMOS transistor MP6 , the gate of the sixth PMOS transistor MP6 is connected to the gate of the second NMOS transistor MN2 , and the source of the second NMOS transistor MN2 is grounded.

[0054] When the input changes from low level to high level, the initial value of the output is high level, the first NMOS tube MN1 is turned on, the fifth PMOS tube MP5 is turned on, the second PMOS tube MP2 is turned on, and the sixth PMOS tube MP6 is turned on, and the output is high level.

[0055] When the input changes from high level to low level, the initial value of the output is high level, the fourth NMOS tube MN4, the sixth NMOS tube MN6, the third PMOS tube MP3 and the fourth PMOS tube MP4 are turned on, the seventh PMOS tube MP7 is turned on, and the output is high level.

[0056] The above-mentioned current mirror branch 1 structure is set up. First, the current mirror architecture is adopted to avoid the competition between NMOS and PMOS. When the voltage difference between VDDL and VDDH is large, the PMOS with gate-drain short circuit can directly realize the conversion from VDDL to VDDH, avoiding the use of large-size NMOS, saving area, and having better voltage compatibility.

[0057] Secondly, an inverter is added to the current mirror branch 1. The two inverters are composed of MN5 and MP5, MN2 and MP6 respectively. When the input changes from low to high, the initial value of OUT is high, and MN1 is turned on. MP5 is turned on, the X node is pulled low, MP2 is turned on, and MP6 is turned on at the same time, and OUT is high. When the input changes from high to low, the initial value of OUT is high, INB is high, MN4 and MN6 are turned on, the Y node becomes low potential, MP4 and MP3 are turned on, and then MP7 is turned on, the Z node is high, and OUT is high. The introduction of two inverters makes the static power consumption approximately 0, thereby reducing the power consumption of the level shifting circuit.

[0058] for Figure 3The specific structure of the logic error diagnosis circuit 2 is described as follows:

[0059] The logic error diagnosis circuit 2 may at least include:

[0060] The third PMOS transistor MP3, the fourth PMOS transistor MP4, the seventh PMOS transistor MP7, the third NMOS transistor MN3, the fourth NMOS transistor MN4 and the sixth NMOS transistor MN6 are connected in the following manner:

[0061] The drain of the third PMOS tube MP3 is connected to the source of the seventh PMOS tube MP7, and the drain of the seventh PMOS tube MP7 is connected to the drain of the third NMOS tube MN3; the source of the third NMOS tube MN3 is grounded, and the gate of the third PMOS tube MP3 is connected to the gate of the fourth PMOS tube MP4; the drain of the fourth PMOS tube MP4 is connected to the drain of the sixth NMOS tube MN6, the source of the sixth NMOS tube MN6 is connected to the drain of the fourth NMOS tube MN4, and the source of the fourth NMOS tube MN4 is grounded.

[0062] When the input changes from high level to low level, the initial value of the output is high level, the fourth NMOS tube MN4 and the sixth NMOS tube MN6 are turned on, the third PMOS tube MP3 and the fourth PMOS tube MP4 flow current, and the output voltage changes to low level, which is consistent with the input voltage potential. Figure 3 When the input IN changes from high to low, INB changes from low to high, the initial state of OUT is high, the MN4 and MN6 tubes are turned on, the MP3 and MP4 currents flow through, the Z node voltage becomes high, and the OUT voltage becomes low, which is consistent with the input voltage potential.

[0063] The above-mentioned structure of the logic error diagnosis circuit 2 can avoid inconsistency between input and output levels.

[0064] Next, in combination with FIG. 4(a) and FIG. 4(b), based on the simulation results of the conventional level shift circuit and the wide input range low power consumption level shift circuit proposed by the present invention, the beneficial effects of the wide input range low power consumption level shift circuit provided by the present invention are described:

[0065] Figure 4(a) shows the power consumption simulation results of different structure level shift circuits when the input changes from low to high, and the simulation results of the structure level function verification of the present invention. The green curve in Figure 4(a) is the power consumption simulation result of the conventional current mirror architecture level shift circuit in the prior art; the red curve is the simulation result corresponding to a wide input range low power consumption level shift circuit provided by the present invention; the yellow curve is Figure 3 The simulation results of removing MN5 from the provided structure; the blue curve and purple curve are input and output function verification.

[0066] It can be seen from the green curve of Figure 4(a) that the conventional current mirror architecture of the prior art has large static power consumption; it can be seen from the red and yellow curves of Figure 4(a) that the introduction of the inverter reduces power consumption; and it can be seen from the input-output function verification of the blue and purple curves of Figure 4(a) that when the input changes from low to high, a wide input range low power consumption level shift circuit provided by the present invention can achieve a wide range rail-to-rail output.

[0067] Figure 4(b) is a diagram showing the power consumption simulation results of different level shifting circuit structures when the input changes from high to low, and the simulation results of the level function verification of the structure of the present invention. The green curve in Figure 4(b) is the power consumption simulation result of the conventional current mirror architecture level shifting circuit in the prior art; the red curve is the simulation result corresponding to a wide input range low power level shifting circuit provided by the present invention; the yellow curve is Figure 3 The simulation results of removing MN5 from the provided structure; the blue curve and purple curve are input and output function verification.

[0068] It can be seen from the green curve of Figure 4(b) that there is a large static power consumption. The red and yellow curves of Figure 4(b) show that the introduction of the inverter reduces the power consumption. The blue and purple curves of Figure 4(b) verify the input and output functions. It can be seen that when the input changes from high to low, a wide input range low power consumption level shift circuit provided by the present invention can achieve a wide range rail-to-rail output.

[0069] Therefore, through the description of the above embodiments and the comparison of simulation results, it can be determined that the present invention realizes level conversion in a wide input voltage range, has low static power consumption and dynamic power consumption, and can achieve rail-to-rail output swing. The current mirror architecture level shift circuit avoids the competition between NMOS and PMOS, and can achieve a wide input voltage range; inserting an inverter in the current mirror branch 1 reduces power consumption. The logic error diagnosis circuit 2 avoids the logic error of inconsistent input and output levels of the shifter.

[0070] Although the present invention is described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art may understand and implement other variations of the disclosed embodiments by viewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "one" or "an" does not exclude multiple situations. A single processor or other unit may implement several functions listed in the claims. Certain measures are recorded in different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

[0071] Although the present invention has been described in conjunction with specific features and embodiments thereof, it is apparent that various modifications and combinations may be made thereto without departing from the spirit and scope of the present invention. Accordingly, this specification and the accompanying drawings are merely exemplary illustrations of the present invention as defined by the appended claims and are deemed to cover any and all modifications, variations, combinations or equivalents within the scope of the present invention. Obviously, those skilled in the art may make various modifications and variations to the present invention without departing from the spirit and scope of the present invention. Thus, the present invention is intended to include such modifications and variations if they fall within the scope of the claims of the present invention and their equivalents.

Claims

1. A wide input range low power consumption level shift circuit, characterized in that: include: Current mirror branch and logic error diagnosis circuit; The current mirror branch is connected to the logic error diagnosis circuit; The current mirror branch includes at least a first inverter and a second inverter; the first inverter and the second inverter are used to ensure that the static power consumption is approximately zero; the logic error diagnosis circuit is used to ensure that the input level is consistent with the output level.

2. A wide input range low power consumption level shift circuit according to claim 1, characterized in that: The current mirror branch includes a first PMOS tube, a second PMOS tube, a first NMOS tube, a first inverter and a second inverter; The first inverter includes a fifth PMOS tube and a fifth NMOS tube; the second inverter includes a sixth PMOS tube and a second NMOS tube.

3. The wide input range low power consumption level shift circuit according to claim 1, characterized in that: The logic error diagnosis circuit at least comprises: a third PMOS tube, a fourth PMOS tube, a seventh PMOS tube, a third NMOS tube, a fourth NMOS tube and a sixth NMOS tube.

4. The wide input range low power consumption level shift circuit according to claim 2, characterized in that: The source of the first PMOS tube is connected to the source of the second PMOS tube, the drain of the first PMOS tube is connected to the source of the fifth PMOS tube, the gate of the first PMOS tube is connected to the gate of the second PMOS tube, the drain of the fifth PMOS tube and the drain of the fifth NMOS tube; the source of the fifth NMOS tube is connected to the drain of the first NMOS tube, and the source of the first NMOS tube is grounded; The drain of the second PMOS tube is connected to the source of the sixth PMOS tube, the gate of the sixth PMOS tube is connected to the gate of the second NMOS tube, and the source of the second NMOS tube is grounded.

5. The wide input range low power consumption level shift circuit according to claim 3, characterized in that: The drain of the third PMOS tube is connected to the source of the seventh PMOS tube, and the drain of the seventh PMOS tube is connected to the drain of the third NMOS tube; the source of the third NMOS tube is grounded, and the gate of the third PMOS tube is connected to the gate of the fourth PMOS tube; the drain of the fourth PMOS tube is connected to the drain of the sixth NMOS tube, the source of the sixth NMOS tube is connected to the drain of the fourth NMOS tube, and the source of the fourth NMOS tube is grounded.

6. A wide input range low power consumption level shift circuit according to claim 4, characterized in that: When the input changes from low level to high level, the initial value of the output is high level, the first NMOS tube is turned on, the fifth PMOS tube is turned on, the second PMOS tube is turned on, and the sixth PMOS tube is turned on, and the output is high level.

7. The wide input range low power consumption level shift circuit according to claim 3, characterized in that: When the input changes from high level to low level, the initial value of the output is high level, the fourth NMOS tube, the sixth NMOS tube, the third PMOS tube and the fourth PMOS tube are turned on, the seventh PMOS tube is turned on, and the output is high level.

8. The wide input range low power consumption level shift circuit according to claim 5, characterized in that: When the input changes from a high level to a low level, the initial value of the output is a high level, the fourth NMOS tube and the sixth NMOS tube are turned on, current flows through the third PMOS tube and the fourth PMOS tube, and the output voltage becomes a low level, which is consistent with the input voltage potential.

9. The wide input range low power consumption level shift circuit according to claim 1, characterized in that: When the voltage difference between VDDL and VDDH is large, the PMOS with gate and drain shorted directly realizes the conversion from VDDL to VDDH.

Images