Grid voltage bootstrapped switch circuit
By introducing a level converter circuit module into the gate voltage bootstrap switch circuit, keeping the gate source voltage of the sampling switch constant, the problem that traditional circuits cannot collect signals higher than the power supply voltage is solved, and the signal higher than the power supply voltage is realized Effective sampling and improvement of linearity.
Patent Information
- Application Number
- CN202411378515.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-30
- Publication Date
- 2025-02-07
AI Technical Summary
Traditional gate voltage bootstrap switching circuits cannot effectively collect input signals higher than the power supply voltage, resulting in nonlinear problems and leakage paths.
A gate voltage bootstrap switching circuit including a sampling switch, a capacitor C0 and a level converter circuit module is designed, and the input high level VDD is converted into the source level output of the PMOS tube through the level converter circuit module. The gate voltage and source voltage of the PMOS tube are both greater than the drain voltage, so as to keep the gate and source voltage of the sampling switch constant.
The sampling of input signals larger than the power supply voltage is realized, the generation of leakage paths is avoided, and the linearity of the sampling is improved.
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Figure CN119401994A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of integrated circuit design, and in particular to a gate voltage bootstrap switch circuit. Background Art
[0002] The switched capacitor circuit is a discrete time circuit consisting of a MOS switch and a capacitor. It mainly uses a clock-controlled MOS switch to realize the charge transfer between the input signal and the capacitor. It is widely used in various products such as filters, analog-to-digital / digital-to-analog converters, comparators, telecommunications, etc.
[0003] As one of the most commonly used analog-to-digital converters, the successive approximation analog-to-digital converter, namely SAR ADC, the sampling switch is an important component of the sample-and-hold circuit. Its performance directly determines the performance of the sample-and-hold circuit, and further determines the performance of the SAR ADC.
[0004] The function of the sample-and-hold circuit is to convert the input continuous voltage signal into a discrete voltage on the sampling capacitor through the sampling clock control. When the sampling switch is turned on, the input signal charges the sampling capacitor, and the amount of charge is determined by the input voltage at the end of the sampling. After the sampling clock is flipped, the sampling switch is disconnected, and the circuit works in the hold state to maintain the input voltage value at the end of the sampling for subsequent comparison and quantization processes.
[0005] The on-resistance of the MOS switch used for sampling is a function of the gate-source voltage. The input signal is transmitted from the source to the drain of the MOS switch. Therefore, if the gate voltage has only two levels, high and low, then when it is turned on, the gate-source voltage will also change for different input signals, causing the on-resistance of the sampling switch to change with the input signal, thus introducing nonlinearity.
[0006] In addition, reference Figure 1 As shown in the schematic diagram of the existing gate voltage bootstrap switch circuit, it can be seen through analysis that in the sampling stage CLK is a high level VDD. When the input signal VIN is greater than the power supply voltage VDD, NM3 is turned on, so the drain voltage of PM4 is VIN, and the gate and source voltages of PM4 are both VDD. VIN is greater than VDD, so a leakage path from the drain of PM4 to the source is generated, and the circuit cannot work normally, that is, the traditional gate voltage bootstrap circuit cannot collect input signals higher than the power supply voltage. Summary of the invention
[0007] In order to solve the above technical problems, the present invention provides a gate voltage bootstrap switch circuit, which is applied to a scenario with sampling linearity requirements and an input signal VIN higher than a power supply voltage VDD. The circuit includes a sampling switch, a capacitor C0 and a level converter circuit module; wherein:
[0008] The on-off of the sampling switch is controlled by the sampling clock signal CLK, so that the circuit is in the charging stage or the sampling stage; when the CLK is a high level VDD, the circuit is in the sampling stage:
[0009] The source of the sampling switch is connected to the input signal VIN, and the lower plate of the capacitor C0 is connected to the input signal VIN; then the source voltage of the sampling switch is VIN;
[0010] The gate of the sampling switch is connected to the upper plate of the capacitor C0, and the upper plate of the capacitor C0 generates a bootstrap voltage of VDD+VIN, so the gate voltage of the sampling switch is VDD+VIN, that is, the gate-source voltage of the sampling switch is constant at VDD;
[0011] The level converter circuit module includes a plurality of PMOS tubes, an NMOS tube and an inverter INV3. The source of the PMOS tube is connected to the upper plate of the capacitor C0, and the source of the NMOS tube is connected to the lower plate of the capacitor C0. The level converter circuit module can convert the input high level VDD into the source level output of the PMOS tube, so that the gate voltage and the source voltage of the PMOS tube are greater than the drain voltage.
[0012] Furthermore, the level converter circuit module includes an NMOS tube NM4, an NMOS tube NM5, a PMOS tube PM3, a PMOS tube PM4 and an inverter INV3, wherein:
[0013] The gate of the NMOS tube NM4 is connected to the input end of the inverter INV3;
[0014] The gate of the NMOS tube NM5 is connected to the output end of the inverter INV3;
[0015] The input end of the level converter circuit module is the gate of the NMOS tube NM4, and the output end of the level converter circuit module is the drain of the NMOS tube NM4. The level converter circuit module can convert the input high level VDD into the source level output of the PMOS tube PM4.
[0016] Furthermore, the circuit further includes an NMOS tube NM6, an NMOS tube NM7, an NMOS tube NM8, an inverter INV1, an inverter INV2, an inverter INV4 and an inverter INV5, wherein:
[0017] The gate of the NMOS tube NM6 is connected to the output end of the inverter INV5, and the source of the NMOS tube NM6 is connected to the ground;
[0018] The source of the NMOS tube NM7 is connected to the drain of the NMOS tube NM8, the gate of the NMOS tube NM8 is connected to the output end of the inverter INV1, the input end of the inverter INV2 and the input end of the inverter INV4, and the source of the NMOS tube NM8 is connected to the ground;
[0019] The drain of the inverter INV5 is connected to the gate of the PMOS transistor PM4;
[0020] The output end of the inverter INV4 is connected to the input end of the inverter INV5;
[0021] An input terminal of the inverter INV1 is connected to the sampling clock signal CLK.
[0022] Furthermore, when the CLK is at a low level of 0, the circuit is in a charging stage:
[0023] The NMOS transistors NM5 , NMOS transistors NM6 , NMOS transistors NM7 , NMOS transistors NM8 and PMOS transistor PM4 are turned on, so that the upper plate of the capacitor C0 is connected to the power supply voltage VDD, and the lower plate of the capacitor C0 is connected to the ground.
[0024] Furthermore, the circuit further includes an NMOS transistor NM1, an NMOS transistor NM2, an NMOS transistor NM3 and a PMOS transistor PM1, wherein:
[0025] The source or input end of the NMOS tube NM1 is connected to the drain of the NMOS tube NM2, the drain of the NMOS tube NM1 is connected to the output end, and the gate of the NMOS tube NM1 is connected to the gate of the NMOS tube NM2, the gate of the NMOS tube NM3, the drain of the NMOS tube NM7 and the source of the PMOS tube PM1;
[0026] The source of the NMOS tube NM2 is connected to the source of the NMOS tube NM3, the source of the NMOS tube NM4, the source of the NMOS tube NM5, the drain of the NMOS tube NM6 and the lower plate of the capacitor C0;
[0027] The drain of the NMOS transistor NM3 is connected to the drain of the NMOS transistor NM4, the gate of the PMOS transistor PM1, the gate of the PMOS transistor PM3, and the drain of the PMOS transistor PM4.
[0028] Furthermore, when the CLK is at a high level VDD, the circuit is in a sampling phase:
[0029] The NMOS tubes NM1, NMOS tubes NM2, NMOS tubes NM3 and PMOS tube PM1 are turned on, so that the upper plate of the capacitor C0 is connected to the gate of the NMOS tube NM1, and the lower plate of the capacitor C0 is connected to the source of the NMOS tube NM1 and the input signal VIN.
[0030] Furthermore, when the circuit is in the sampling stage and the input signal VIN is greater than the power supply voltage VDD:
[0031] The NMOS transistor NM3 is turned on to transmit the input signal VIN to the drain of the PMOS transistor PM4 , and the source of the PMOS transistor PM4 is bootstrapped to VDD+VIN by the capacitor C0 .
[0032] Furthermore, the NMOS tube NM1 is the sampling switch, and during sampling, the input signal VIN is transmitted to the drain output end of the NMOS tube NM1 through the source of the NMOS tube NM1.
[0033] Furthermore, the circuit further includes a PMOS tube PM2, an inverter INV2 and a resistor R0, wherein:
[0034] The gate of the PMOS tube PM2 is connected to the gate of the NMOS tube NM1;
[0035] The output end of the inverter INV2 is connected to the gate of the NMOS tube NM4;
[0036] The drain of the PMOS transistor PM2 is connected to the drain of the PMOS transistor PM1, and the source of the PMOS transistor PM2 is connected to the power supply voltage VDD;
[0037] Two ends of the resistor R0 are connected to the power supply voltage VDD and the gate of the NMOS transistor NM7 respectively.
[0038] Compared with the prior art, the present invention has the following beneficial effects:
[0039] The gate voltage bootstrap switch circuit provided by the present invention can keep the gate-source voltage of the sampling switch constant during sampling, thereby improving the linearity of sampling; at the same time, the leakage path when the input signal is greater than the power supply voltage is avoided through the level converter circuit module, thereby realizing the sampling of the input signal greater than the power supply voltage. BRIEF DESCRIPTION OF THE DRAWINGS
[0040] Figure 1 This is a conventional gate voltage bootstrap switch circuit diagram;
[0041] Figure 2 The gate voltage bootstrap switch circuit diagram disclosed in the present invention;
[0042] Figure 3 It is a schematic diagram of a framework of the gate voltage bootstrap switch circuit disclosed in the present invention applied to a SAR ADC;
[0043] Figure 4 It is a simulation diagram of the gate-source voltage Vgs of the gate voltage bootstrap switch circuit disclosed in the present invention being applied to a SAR ADC and the change of the input signal;
[0044] Figure 5 This is a simulation diagram of the fast Fourier transform of the gate voltage bootstrap switch circuit disclosed in the present invention applied to a SAR ADC. DETAILED DESCRIPTION
[0045] In order to make the technical scheme and technical effect of the present invention clearer, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments.
[0046] The present invention aims to provide a gate voltage bootstrap switch circuit, which is applied to scenarios with high sampling linearity requirements and where the input signal VIN is higher than the power supply voltage VDD, and is used to solve the nonlinear problem caused by the switch on-resistance. The design idea is to make the gate of the sampling switch follow the input voltage change through a bootstrap circuit, thereby keeping the gate-source voltage of the sampling switch constant to improve the sampling linearity.
[0047] The gate voltage bootstrap switch circuit mainly includes a sampling switch, a capacitor C0 and a level converter circuit module.
[0048] The on and off of the sampling switch is controlled by the sampling clock signal CLK, so that the circuit is in the charging stage or the sampling stage. When CLK is a high level VDD, the circuit is in the sampling stage; when CLK is a low level 0, the circuit is in the charging stage.
[0049] When the circuit is in the sampling stage, the source of the sampling switch is connected to the input signal VIN, and the lower plate of the capacitor C0 is connected to the input signal VIN; the source voltage of the sampling switch is VIN; the gate of the sampling switch is connected to the upper plate of the capacitor C0, and the upper plate of the capacitor C0 generates a bootstrap voltage of VDD+VIN, then the gate voltage of the sampling switch is VDD+VIN, that is, the gate-source voltage of the sampling switch is constant at VDD.
[0050] The level converter circuit module includes several PMOS tubes, NMOS tubes and an inverter INV3. The source of the PMOS tube is connected to the upper plate of the capacitor C0, and the source of the NMOS tube is connected to the lower plate of the capacitor C0. The level converter circuit module can convert the input high level VDD into the source level output of the PMOS tube, so that the gate voltage and source voltage of the PMOS tube are greater than the drain voltage.
[0051] See also Figure 2 The gate voltage bootstrap switch circuit disclosed in the present invention includes NMOS tube NM1, NMOS tube NM2, NMOS tube NM3, NMOS tube NM4, NMOS tube NM5, NMOS tube NM6, NMOS tube NM7, NMOS tube NM8, PMOS tube PM1, PMOS tube PM2, PMOS tube PM3, PMOS tube PM4, inverter INV1, inverter INV2, inverter INV3, inverter INV4, inverter INV5, capacitor C0 and resistor R0; wherein:
[0052] The source or input end of the NMOS tube NM1 is connected to the drain of the NMOS tube NM2, the drain of the NMOS tube NM1 is connected to the output end, and the gate of the NMOS tube NM1 is connected to the gate of the NMOS tube NM2, the gate of the NMOS tube NM3, the drain of the NMOS tube NM7, the source of the PMOS tube PM1 and the gate of the PMOS tube PM2.
[0053] The source of the NMOS transistor NM2 is connected to the source of the NMOS transistor NM3 , the source of the NMOS transistor NM4 , the source of the NMOS transistor NM5 , the drain of the NMOS transistor NM6 , and the lower plate of the capacitor C0 .
[0054] The drain of the NMOS transistor NM3 is connected to the drain of the NMOS transistor NM4, the gate of the PMOS transistor PM1, the gate of the PMOS transistor PM3, and the drain of the PMOS transistor PM4.
[0055] The gate of the NMOS tube NM4 is connected to the output end of the inverter INV2 and the input end of the inverter INV3.
[0056] The gate of the NMOS tube NM5 is connected to the output end of the inverter INV3; the drain of the inverter INV5 is connected to the gate of the PMOS tube PM4.
[0057] The gate of the NMOS transistor NM6 is connected to the output end of the inverter INV5 , and the source of the NMOS transistor NM6 is connected to the ground.
[0058] The source of the NMOS tube NM7 is connected to the drain of the NMOS tube NM8, the gate of the NMOS tube NM8 is connected to the output end of the inverter INV1, the input end of the inverter INV2 and the input end of the inverter INV4, and the source of the NMOS tube NM8 is connected to the ground.
[0059] The drain of the PMOS transistor PM1 is connected to the drain of the PMOS transistor PM2 , the source of the PMOS transistor PM3 , the source of the PMOS transistor PM4 , and the upper plate of the capacitor C0 .
[0060] The source of the PMOS transistor PM2 is connected to the power supply voltage VDD.
[0061] An input terminal of the inverter INV1 is connected to the sampling clock signal CLK.
[0062] The output terminal of the inverter INV4 is connected to the input terminal of the inverter INV5.
[0063] Two ends of the resistor R0 are connected to the power supply voltage VDD and the gate of the NMOS transistor NM7 respectively.
[0064] Further:
[0065] The NMOS tube NM1 is a sampling switch. During sampling, the input signal VIN is transmitted to the drain output terminal of the NMOS tube NM1 through the source of the NMOS tube NM1.
[0066] The level converter circuit module includes NMOS tube NM4, NMOS tube NM5, PMOS tube PM3, PMOS tube PM4 and inverter INV3. Among them, the gate of NMOS tube NM4 is connected to the input end of inverter INV3; the gate of NMOS tube NM5 is connected to the output end of inverter INV3. The input end of the level converter circuit module is the gate of NMOS tube NM4, and the output end of the level converter circuit module is the drain of NMOS tube NM4. The level converter circuit module can convert the input high level VDD into the source level output of PMOS tube PM4.
[0067] When the sampling clock signal CLK is at low level 0, the circuit is in the charging stage:
[0068] NMOS transistors NM5, NMOS transistors NM6, NMOS transistors NM7, NMOS transistors NM8 and PMOS transistor PM4 are turned on, so that the upper plate of capacitor C0 is connected to the power supply voltage VDD, and the lower plate of capacitor C0 is connected to the ground, and the upper plate of capacitor C0 is charged to the power supply voltage VDD.
[0069] When the sampling clock signal CLK is at a high level VDD, the circuit is in the sampling stage:
[0070] NMOS tubes NM1, NMOS tubes NM2, NMOS tubes NM3 and PMOS tube PM1 are turned on, so that the upper plate of capacitor C0 is connected to the gate of NMOS tube NM1, and the gate voltage of NMOS tube NM1, i.e., the sampling switch, is VDD+VIN; the lower plate of capacitor C0 is connected to the source of NMOS tube NM1 and the input signal VIN, and the source voltage of NMOS tube NM1, i.e., the sampling switch, is VIN. Therefore, it can be concluded that no matter how the input signal changes, the gate-source voltage Vgs of the sampling switch can keep VDD constant, so it has better linearity.
[0071] In addition to having good sampling linearity, the gate voltage bootstrap switch circuit can also sample input signals exceeding the power supply voltage.
[0072] When the input signal VIN is greater than the power supply voltage VDD:
[0073] NMOS tube NM3 is turned on, so the drain voltage of PMOS tube PM4 and the gate voltage of PMOS tube PM3 are VIN, and the source of PMOS tube PM3 and PMOS tube PM4 are connected to the upper plate of capacitor C0, and their voltage is VDD+VIN. At this time, PMOS tube PM3 is turned on to pull the gate voltage of PMOS tube PM4 to VDD+VIN, that is, the source of PMOS tube PM4 is bootstrapped to VDD+VIN by capacitor C0, so that the gate voltage and source voltage of PMOS tube PM4 are greater than the drain voltage, thereby avoiding the generation of leakage path. Therefore, compared with Figure 1 , the present invention can realize sampling of input signals higher than the power supply voltage.
[0074] like Figure 3 The schematic diagram of the framework of the gate voltage bootstrap switch circuit provided by the present invention applied to a SAR ADC is shown. When the sampling clock signal CLK is at a high level, the gate voltage bootstrap switch circuit provided by the present invention collects the input signal onto the bottom plate of the DAC capacitor. At this time, the output of the SAR logic is in a high impedance state. After the sampling is completed, the sampling clock signal CLK is at a low level, and the output of the gate voltage bootstrap switch circuit provided by the present invention is in a high impedance state. The SAR ADC enters the conversion stage, and the input signal collected by the DAC capacitor is approximated successively by the comparator and the SAR logic, and the result of each approximation is stored in the output register. Finally, the codeword obtained by the output register is quantized, and the analog input signal with a certain accuracy can be restored by using the digital codeword.
[0075] It can be seen that the gate voltage bootstrap switch circuit used as a sampling switch is an important component of the SAR ADC, and its performance directly determines the linearity of the sampling signal, and further determines the performance of the SAR ADC. In the application of this SAR ADC, the voltage amplitude of the input signal is 0-5V, and the power supply voltage is 2.5V, so the gate voltage bootstrap switch circuit provided by the present invention is required to realize the sampling of the input signal higher than the power supply voltage.
[0076] like Figure 4 The gate voltage bootstrap switch circuit provided by the present invention is applied to a simulation diagram of the gate-source voltage Vgs in a SAR ADC changing with the input signal VIN. The input signal frequency is 100KHz and the sampling frequency is 2MSPS. It can be concluded that as the input signal VIN changes from 0 to 5V, the gate-source voltage Vgs of the sampling switch is basically maintained at VDD=2.5V.
[0077] It should be noted that due to the presence of parasitic capacitance in the circuit, the gate-source voltage Vgs of the sampling switch cannot be perfectly constant at 2.5V. The larger the capacitance used for gate voltage bootstrap in the gate voltage bootstrap switch circuit, the smaller the influence of the parasitic capacitance, and the closer the gate-source voltage Vgs of the sampling switch is to 2.5V; but a large gate voltage bootstrap capacitance will bring about problems with area and charging and discharging speed, which requires a compromise between gate-source voltage, speed and area.
[0078] like Figure 5 The FFT simulation diagram of the gate voltage bootstrap switch circuit provided by the present invention applied to a SAR ADC is shown. The FFT result is obtained by analyzing the output of the gate voltage bootstrap switch circuit at the end of sampling. It can be concluded that: its signal-to-noise ratio (SNR) reaches 132.4dB, and the spurious-free dynamic range (SFDR) reaches 133.3dB, with high sampling linearity.
[0079] It can be seen that the gate voltage bootstrap switch circuit provided by the present invention has a simple circuit structure and a high linearity. In addition, the gate voltage bootstrap switch structure can sample input signals higher than the power supply voltage, and has a broad application prospect in circuit structures that need to sample input signals higher than the power supply voltage.
[0080] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.
Claims
1. A gate voltage bootstrap switch circuit, applied to a scenario with sampling linearity requirements and an input signal VIN higher than a power supply voltage VDD, characterized in that: The circuit includes a sampling switch, a capacitor C0 and a level converter circuit module; wherein: The on-off of the sampling switch is controlled by the sampling clock signal CLK, so that the circuit is in the charging stage or the sampling stage; when the CLK is a high level VDD, the circuit is in the sampling stage: The source of the sampling switch is connected to the input signal VIN, and the lower plate of the capacitor C0 is connected to the input signal VIN; then the source voltage of the sampling switch is VIN; The gate of the sampling switch is connected to the upper plate of the capacitor C0, and the upper plate of the capacitor C0 generates a bootstrap voltage of VDD+VIN, so the gate voltage of the sampling switch is VDD+VIN, that is, the gate-source voltage of the sampling switch is constant at VDD; The level converter circuit module includes a plurality of PMOS tubes, an NMOS tube and an inverter INV3. The source of the PMOS tube is connected to the upper plate of the capacitor C0, and the source of the NMOS tube is connected to the lower plate of the capacitor C0. The level converter circuit module can convert the input high level VDD into the source level output of the PMOS tube, so that the gate voltage and the source voltage of the PMOS tube are greater than the drain voltage.
2. The gate voltage bootstrap switch circuit according to claim 1, characterized in that: The level converter circuit module includes an NMOS tube NM4, an NMOS tube NM5, a PMOS tube PM3, a PMOS tube PM4 and an inverter INV3, wherein: The gate of the NMOS tube NM4 is connected to the input end of the inverter INV3; The gate of the NMOS tube NM5 is connected to the output end of the inverter INV3; The input end of the level converter circuit module is the gate of the NMOS tube NM4, and the output end of the level converter circuit module is the drain of the NMOS tube NM4. The level converter circuit module can convert the input high level VDD into the source level output of the PMOS tube PM4.
3. The gate voltage bootstrap switch circuit according to claim 2, characterized in that: The circuit further includes NMOS tube NM6, NMOS tube NM7, NMOS tube NM8, inverter INV1, inverter INV2, inverter INV4 and inverter INV5, wherein: The gate of the NMOS tube NM6 is connected to the output end of the inverter INV5, and the source of the NMOS tube NM6 is connected to the ground; The source of the NMOS tube NM7 is connected to the drain of the NMOS tube NM8, the gate of the NMOS tube NM8 is connected to the output end of the inverter INV1, the input end of the inverter INV2 and the input end of the inverter INV4, and the source of the NMOS tube NM8 is connected to the ground; The drain of the inverter INV5 is connected to the gate of the PMOS transistor PM4; The output end of the inverter INV4 is connected to the input end of the inverter INV5; An input terminal of the inverter INV1 is connected to the sampling clock signal CLK.
4. The gate voltage bootstrap switch circuit according to claim 3, characterized in that: When the CLK is at a low level of 0, the circuit is in the charging stage: The NMOS transistors NM5 , NMOS transistors NM6 , NMOS transistors NM7 , NMOS transistors NM8 and PMOS transistor PM4 are turned on, so that the upper plate of the capacitor C0 is connected to the power supply voltage VDD, and the lower plate of the capacitor C0 is connected to the ground.
5. The gate voltage bootstrap switch circuit according to claim 3, characterized in that: The circuit further includes an NMOS tube NM1, an NMOS tube NM2, an NMOS tube NM3 and a PMOS tube PM1, wherein: The source or input end of the NMOS tube NM1 is connected to the drain of the NMOS tube NM2, the drain of the NMOS tube NM1 is connected to the output end, and the gate of the NMOS tube NM1 is connected to the gate of the NMOS tube NM2, the gate of the NMOS tube NM3, the drain of the NMOS tube NM7 and the source of the PMOS tube PM1; The source of the NMOS tube NM2 is connected to the source of the NMOS tube NM3, the source of the NMOS tube NM4, the source of the NMOS tube NM5, the drain of the NMOS tube NM6 and the lower plate of the capacitor C0; The drain of the NMOS transistor NM3 is connected to the drain of the NMOS transistor NM4, the gate of the PMOS transistor PM1, the gate of the PMOS transistor PM3, and the drain of the PMOS transistor PM4.
6. The gate voltage bootstrap switch circuit according to claim 5, characterized in that: When the CLK is at a high level VDD, the circuit is in the sampling phase: The NMOS tubes NM1, NMOS tubes NM2, NMOS tubes NM3 and PMOS tube PM1 are turned on, so that the upper plate of the capacitor C0 is connected to the gate of the NMOS tube NM1, and the lower plate of the capacitor C0 is connected to the source of the NMOS tube NM1 and the input signal VIN.
7. The gate voltage bootstrap switch circuit according to claim 5, characterized in that: When the circuit is in the sampling phase and the input signal VIN is greater than the power supply voltage VDD: The NMOS transistor NM3 is turned on to transmit the input signal VIN to the drain of the PMOS transistor PM4 , and the source of the PMOS transistor PM4 is bootstrapped to VDD+VIN by the capacitor C0 .
8. The gate voltage bootstrap switch circuit according to claim 5, characterized in that: The NMOS transistor NM1 is the sampling switch. During sampling, the input signal VIN is transmitted to the drain output terminal of the NMOS transistor NM1 through the source of the NMOS transistor NM1.
9. The gate voltage bootstrap switch circuit according to claim 5, characterized in that: The circuit further includes a PMOS tube PM2, an inverter INV2 and a resistor R0, wherein: The gate of the PMOS tube PM2 is connected to the gate of the NMOS tube NM1; The output end of the inverter INV2 is connected to the gate of the NMOS tube NM4; The drain of the PMOS tube PM2 is connected to the drain of the PMOS tube PM1, and the source of the PMOS tube PM2 is connected to the power supply voltage VDD; Two ends of the resistor R0 are connected to the power supply voltage VDD and the gate of the NMOS transistor NM7 respectively.
Citation Information
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