Devices, methods, and systems for providing limited power state modes to manage processor operations

Abstract

Apparatuses, methods, and systems are described for providing limited power state modes to manage processor operations. Techniques and mechanisms for determining a mode in which a processor is transitioned between power states. In one embodiment, circuitry selectively transitions power management of a processor to or transitions from a limited power state (LPS) mode that makes a relatively limited number of power states of two or more power states available to the processor as compared to an alternative power management mode. The transition to or from the LPS mode is performed based on a thermal condition, such as a thermal condition based on a surface temperature of the housing structure in which the processor is disposed. In another embodiment, during LPS mode, transitions between two or more power states are performed based on pending of a software process or based on completion of such software workloads.

Description

background 1. Technical Field

[0001] The present disclosure relates generally to processor operation and, more particularly, but not exclusively, to determination of processor power states. 2. Background technology

[0002] Smart phones, notebook computers, board or pod devices, tablets, and other types of information and media terminals have gained widespread popularity and continue to evolve in terms of performance, size, and functionality. The main advantage of some modern architectures with large processor components (such as quad-core processors or octa-core processors) is the ability to quickly and on-demand increase processor and system performance. Such "turbo burst" capabilities allow the CPU and / or graphics processor unit (GPU) to be increased to very high power, thereby achieving a responsive system with an enhanced user experience. However, generation after generation of devices (whether mobile or stationary) are expected to meet increasingly stringent power and performance requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Embodiments of the invention are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which:

[0004] Figure 1 A functional block diagram illustrating features of a system for determining a mode for managing a power state of a processor according to an embodiment is shown.

[0005] Figure 2 A functional block diagram illustrating features of a system for providing a limited power state mode according to an embodiment is shown.

[0006] Figure 3 A functional block diagram illustrating features of a system for managing power consumption caused by a processor according to an embodiment is shown.

[0007] Figure 4A , Figure 4B Flowcharts are shown that each illustrate respective features of a method for operating power management logic according to a corresponding embodiment.

[0008] Figure 5 A functional block diagram illustrating features of a system for configuring a limited power state mode according to an embodiment is shown.

[0009] Figure 6 A diagram illustrating operations for transitioning a processor between power states, according to an embodiment, is shown.

[0010] Figure 7A functional block diagram illustrating features of a computing device for providing power management for a processor according to an embodiment is shown.

[0011] Figure 8 An exemplary system is shown.

[0012] Fig. 9 A block diagram illustrating an example processor that may have more than one core and may have an integrated memory controller.

[0013] Fig. 10A is a block diagram illustrating both an exemplary in-order pipeline and an exemplary register renaming, out-of-order issue / execution pipeline according to examples.

[0014] Fig. 10B is a block diagram illustrating both an exemplary example of an in-order architecture core and an exemplary register renaming, out-of-order issue / execution architecture core to be included in a processor according to an example.

[0015] Fig.11 An example of execution unit(s) circuitry is shown.

[0016] Fig.12 is a block diagram of a register architecture according to some examples.

[0017] Fig.13 An example of the instruction format is shown.

[0018] Fig.14 Figure 1 shows an example of an addressing field.

[0019] Fig.15 An example of the first prefix is ​​illustrated.

[0020] Figures 16A-16D How to use the diagram Fig.15 Example of the R, X, and B fields of the first prefix in .

[0021] Figure 17A-17B An example of the second prefix is ​​shown in the figure.

[0022] Fig.18 An example of the third prefix is ​​shown in FIG.

[0023] Fig.19 is a block diagram illustrating converting binary instructions in a source instruction set architecture to binary instructions in a target instruction set architecture using a software instruction converter according to an example. DETAILED DESCRIPTION

[0024] The embodiments discussed herein provide in various ways techniques and mechanisms for determining an operating mode through which a processor is to transition between power states. In various embodiments, circuits and / or other logic provide functionality to selectively transition the power management of a processor to or from an operating mode, referred to herein as a "limited power state mode" (i.e., "LPS mode"), which reduces the total number of power states available to the processor to two or more. Based on the thermal condition of a system including the processor, power management logic (e.g., including any combination of hardware, firmware, executive software, and / or various suitable combinations thereof) configures such an LPS mode so that one or more power states that would otherwise be available when the processor is not in the LPS mode are unavailable. However, during the LPS mode, a plurality of other power states remain available to the processor.

[0025] In contrast, many existing thermal management techniques lock the processor into one and only one power state (e.g., to only one operating frequency) when the surface temperature (e.g.) is above a certain threshold level. In providing an LPS mode that makes two or more states available, some embodiments achieve an improved balance between thermal regulation and system responsiveness (e.g., user experience) in various ways.

[0026] In some embodiments, the processor is configured to be operated at various times in any of a plurality of power states, each of which corresponds to a different respective amount of power consumption caused by the processor. For example, some or all of such power states each include or otherwise correspond to a different respective processor frequency—for example, where the frequency of a clock signal is changed to facilitate the change of the processor between two such power states. Additionally or alternatively, some or all of such power states each include or otherwise correspond to a different respective combination of one or more functional blocks of the processor, each in a respective active state, and one or more other functional blocks of the processor, each in a respective inactive state. In various embodiments, some or all of such power states are (for example) changed from power states used in any of a variety of existing processor architectures. However, some embodiments are not limited with respect to a particular plurality of power states available during non-LPS mode, and / or are not limited with respect to a particular plurality of power states available during LPS mode.

[0027] Certain features of various embodiments are described herein with reference to a system that includes a processor that is transitioned to an LPS mode based on a thermal condition that includes, is based on, or otherwise corresponds to a temperature of a frame, chassis, or other suitable housing structure in which the processor (e.g., along with one or more other components of the system) is disposed (referred to herein as a "surface temperature"). By way of illustration and not limitation, such thermal condition includes or is otherwise based on one or more of: a current surface temperature of the housing structure, an average value of the surface temperature (e.g., a moving window average), an integral of the surface temperature over time, a rate of change of the surface temperature (e.g., a first order rate, a second order rate, etc.), etc. However, in some embodiments, the thermal condition is additionally or alternatively based on any suitable temperature of a variety of other suitable temperatures of the system.

[0028] In an embodiment, the power management logic is configured to receive, generate, or otherwise identify information at least in part indicative of thermal conditions for use in determining whether the LPS mode is to be configured. For example, the power management logic includes, is coupled to, or otherwise operates based on one or more sensors that provide functionality for sensing environmental characteristics indicative of such thermal conditions (e.g., a "surface" temperature of a housing structure).

[0029] By way of illustration and not limitation, the power management logic receives or otherwise detects sensor information identifying a current surface temperature. The power management logic determines whether the LPS mode is to be configured based on whether the current surface temperature value (or another value based on the current surface temperature value) is above (e.g., at or above) a certain threshold maximum value. In one such embodiment, the power management logic (or other suitable logic) performs any of an averaging operation, an integration operation, and / or various other suitable calculations based on the surface temperature to generate a value that is then compared to (or otherwise evaluated based on) a corresponding threshold value.

[0030] Alternatively or additionally, the power management logic receives or otherwise detects sensor information identifying corresponding current temperature levels of one or more components disposed in the housing structure. In one such embodiment, the power management logic includes reference information specifying a relationship of each of a plurality of surface temperature levels to a different corresponding set of one or more component temperature levels, or otherwise has access to the reference information. For example, the reference information includes any of a lookup table, a function, and / or various other suitable types of information identifying the correspondence of each of the surface temperature levels to a different corresponding set of one or more component temperature levels. The power management logic (or other suitable logic) performs any of a variety of lookups, calculations, or other suitable operations based on the reference information and the identified one or more component temperature levels to determine an estimated (or actual) surface temperature level.

[0031] Alternatively or additionally, the power management logic is configured to generate, receive, or otherwise identify one or more performance metrics indicative of a thermal condition (such as, a surface temperature). In one such embodiment, the power management logic includes reference information specifying a relationship of a plurality of surface temperature levels to a different corresponding set of one or more performance metric values, or otherwise has access to the reference information. For example, the reference information includes any of a lookup table, a function, and / or various other suitable types of information identifying the correspondence of each of the surface temperature levels to a different corresponding set of one or more component performance metric values. The power management logic (or other suitable logic) performs any of a variety of lookups, calculations, or other suitable operations based on the reference information and the identified one or more performance metric values ​​to determine an estimated (or actual) surface temperature level.

[0032] In various embodiments, the power management logic evaluates the detected thermal condition based on test criteria (e.g., including a threshold surface temperature level) to determine whether power management of the processor is to be performed according to the LPS mode. By way of illustration and not limitation, at one time during the baseline (non-LPS) mode, power management of the processor is performed using a first state machine according to which the processor transitions between any of a first plurality of power states in various ways. In contrast, at another time during the LPS mode, power management of the processor is instead performed using a second state machine according to which the processor transitions between any of a second plurality of power states in various ways. In one such embodiment, the total number of the first plurality of power states is greater than the total number of the second plurality of power states—e.g., where the second plurality of power states is a subset of the first plurality of power states.

[0033] As used herein, the term "relatively higher power state" refers to a power state whose corresponding power consumption level is higher than the power consumption level corresponding to some other (reference) power state. In contrast, the term "relatively lower power state" refers to a power state that corresponds to a power consumption level lower than the power consumption level corresponding to some other (reference) power state. For example, the term "power increase transition" refers herein to a transition from a relatively lower power state to a relatively higher power state. In addition, the term "power reduction transition" refers herein to a transition from a relatively higher power state to a relatively lower power state.

[0034] In some embodiments, whether a test criterion is to be used to enable a transition to LPS mode (or, alternatively, a transition from LPS mode) is specified or otherwise indicated by an operating system (OS) prompt. For example, a programmer, administrator, or other suitable user provides such an OS prompt to specify whether one or more particular types of workloads (e.g., workloads that tend to be relatively bursty) will be able to utilize the LPS mode functionality. Alternatively or additionally, a determination as to whether a test criterion is to be used for a transition to LPS mode (or a transition from LPS mode) is made based on monitoring of core interrupts and / or wakeups from very low power states (such as, for example, a CC6 sleep state). In one such embodiment, a relatively high rate of core wakeup events indicates that selective use of the LPS mode functionality is to be enabled.

[0035] The techniques described herein may be implemented in one or more electronic devices. Non-limiting examples of electronic devices that may utilize the techniques described herein include any type of mobile and / or fixed device, such as a camera, a cellular telephone, a computer terminal, a desktop computer, an e-reader, a fax machine, a kiosk, a laptop computer, a netbook computer, a notebook computer, an Internet appliance, a payment terminal, a personal digital assistant, a media player and / or recorder, a server (e.g., a blade server, a rack-mounted server, a combination thereof, etc.), a set-top box, a smart phone, a tablet personal computer, an ultra-mobile personal computer, a wired telephone, a combination of the above, and the like. More generally, the techniques described herein may be employed in any of a variety of electronic devices that include circuitry to support providing power management functionality.

[0036] Figure 1Features of a system 100 for determining a processor operating mode based on detected thermal conditions according to an embodiment are shown. System 100 illustrates one example of an embodiment that provides an operating mode that limits the number of available power states of a processor based on thermal conditions - referred to herein as a limited power state (LPS) mode. In various embodiments, system 100 provides functionality to perform any of a variety of general purpose computing, graphics processing functions, functionality to perform wireless communications, electronic imaging, and / or other such operations.

[0037] like Figure 1 As shown in , the system 100 includes a housing 102 having various additional components disposed therein or thereon, such as one or more processors. In the illustrated example embodiment, the system 100 includes a central processing unit (CPU) 104, a graphics processing unit (GPU) 106, a cache 108, an input / output (I / O) controller 110, a memory controller 112, a power control unit 114, a display engine 116, an I / O device 118, a memory 120, a platform sensor 122, a platform temperature control component 124, a digital display 126, a radio component 128, and a chipset 130. The radio component is a wireless communication chip, and the chipset is a chip that communicates with the CPU and / or GPU to perform various known control functions and / or input / output functions. The specific combination of components in the housing 102 is merely illustrative, and in other embodiments, the system 100 includes any of various one or more additional components and / or one or more alternative embodiments.

[0038] During operation, one or more of the components housed in the system 100 generates heat sufficient to cause the temperature of the housing 102 (i.e., the "surface temperature" of the system 100) to approach or reach a surface temperature limit (i.e., a threshold maximum surface temperature) designed for the system 100. For example, such a surface temperature limit is specified as a value that does not cause undue discomfort to a user of the system 100 who intermittently or continuously contacts the housing 102. In some embodiments, the platform temperature control unit 124 monitors and adjusts the operation of one or more components in the system 100 (e.g., the operation of at least one processor) based on one or more temperature measurements, including, for example, a measurement of the temperature of the housing 102. In one such embodiment, such adjustments are performed in such a manner that the steady-state temperature of some or all of the one or more components does not exceed a value established to ensure that the surface temperature limit of the system 100 is not exceeded.

[0039] The platform temperature control component 124 includes various hardware elements, software elements, or a combination of the two. Examples of hardware elements include devices, components, processors, microprocessors, circuits, circuit elements (e.g., transistors, resistors, capacitors, inductors, etc.), integrated circuits, application specific integrated circuits (ASICs), programmable logic devices (PLDs), digital signal processors (DSPs), field programmable gate arrays (FPGAs), memory cells, logic gates, registers, semiconductor devices, chips, microchips, chipsets, etc. Examples of software elements include software components, programs, applications, computer programs, applications, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, processes, software interfaces, application program interfaces (APIs), instruction sets, computing codes, computer codes, code segments, computer code segments, words, values, symbols, or any combination thereof. Whether hardware elements and / or software elements are used to implement an embodiment is based on, for example, any number of implementation-specific factors, such as required computing rates, power levels, thermal tolerances, processing cycle budgets, input data rates, output data rates, memory resources, data bus speeds, and other design or performance constraints as desired for a given implementation.

[0040] In certain embodiments, the platform temperature control component 124 includes logic at least partially implemented in hardware and included in a controller or processor. For example, the logic is included in a processor circuit that is linked to other components of the system 100. In one specific example, the logic forms part of a processor (such as CPU 104) and is communicatively linked to other components of the system 100. In other embodiments, the logic of the platform temperature control component 124 is located in a controller such as a power management or power control unit 114. In further embodiments, the platform temperature control component 124 is distributed across multiple platform components (including cache and / or memory components).

[0041] System 100 illustrates an example of an embodiment that transitions one or more components to an operating mode (referred to herein as a "limited power state mode" (or "LPS mode")) that includes or otherwise enables one or more continuous alternations of a processor between a first (relatively higher power consumption) power state and a second (relatively lower power consumption) power state, as described in detail herein. In an embodiment, the LPS mode is configured based on detection of a thermal condition, such as, for example, a surface temperature of the housing 102 reaching or exceeding a threshold maximum surface temperature. In one such embodiment, the one or more continuous alternations are to be performed according to a predetermined schedule. For example, the platform temperature control component 124 includes hardware, firmware, and / or executive software that specifies or otherwise indicates, for each of two or more power states, a respective length of time that the power state is to be provided during the LPS mode, before transitioning to (or after transitioning from) another of the two or more power states during the LPS mode, coupled to the hardware, firmware, and / or executive software, or otherwise configured to operate with the hardware, firmware, and / or executive software.

[0042] Accordingly, some embodiments implement constrained utilization of turbo mode (or other relatively high performance power state) in various ways when the system 100 is at or near a critical condition (such as a surface temperature limit). In one such embodiment, power consumption is budgeted for improved responsiveness—e.g., where the budget is subsequently released when, for example, the surface temperature is reduced below the surface temperature limit or some other threshold temperature level. Some embodiments provide or otherwise utilize a dynamic platform and thermal framework (DPTF) (such as Dynamic Tuning Technology (DTT) of Intel Corporation of Santa Clara, California) in various ways to implement LPS mode functionality (e.g., by managing alternating power states and their respective durations during a given instance of LPS mode).

[0043] In an illustrative scenario according to one embodiment, the platform sensor 122 includes a thermal sensor configured to measure a surface temperature of the housing 102. The thermal sensor provides an indication of the measured surface temperature to the platform temperature control component 124. In an embodiment, the platform temperature control component 124 performs an evaluation based on the indication and a test criterion (such as a threshold maximum surface temperature limit) to detect whether a test condition has been satisfied by a thermal condition of the system 100. By way of illustration and not limitation, the platform temperature control component 124 evaluates whether a current level of the surface temperature (e.g., a moving average of the surface temperature) is above a threshold maximum surface temperature. In an embodiment, the platform temperature control component 124 evaluates whether an integral of the surface temperature over time is above a threshold maximum level.

[0044] In the event that the evaluation determines that the test condition has been met, the platform temperature control component 124 generates a signal for causing one or more components of the system 100 to transition to the LPS mode. By way of illustration and not limitation, the platform temperature control component 124 signals the power control unit 114 (and / or other suitable circuitry of the system 100) to transition the power management of the CPU 104 and / or the GPU 106 from a first mode that enables relatively more power states to be available to an LPS mode that enables relatively fewer power states to be available. In some embodiments, the platform temperature control component 124 signals the circuitry of the CPU 104 and / or the GPU 106 to at least partially implement or otherwise adapt to the LPS mode.

[0045] In various embodiments, the LPS mode makes two or more power states available to the processor and blocks one or more other power states that would otherwise be available to the processor during a non-LPS mode of power management. In one such embodiment, the CPU 104 (e.g., or the GPU 106) is subject to transitions between two or more power states during the LPS mode. By way of illustration and not limitation, the power control unit 114, the CPU 104, and / or other suitable logic of the system 100 provide functionality for monitoring software processes being executed using the CPU 104—e.g., where such monitoring is used to detect whether a workload of the process is to be executed using the CPU 104. In an illustrative scenario according to one embodiment, such monitoring is used to detect whether a mouse click, keyboard stroke, or other interaction with a user interface has caused (or is expected to cause) a need to execute the workload of the software process.

[0046] In the event that the monitoring detects a workload, the CPU 104 is subjected to a power increase transition from a relatively lower power state of two or more power states to a relatively higher power state of the two or more power states. In an illustrative scenario according to one embodiment, the detection of the workload includes detecting the start of a software task, a user keystroke or mouse click, the start of a phase of an application, and the like. In one such embodiment, after the CPU 104 executes the workload, the CPU 104 is subjected to a power reduction transition from a relatively higher power state of the two or more power states to a relatively lower power state. In some embodiments, the power reduction transition is performed after a predetermined time period (e.g., 5 seconds) starting from the completion of a given workload has expired. Although some embodiments are not limited in this regard, during the LPS mode, the CPU 104 transitions between some or all of the two or more power states multiple times - for example, while the platform temperature control component 124 (or other suitable logic of the system 100) performs additional monitoring to detect whether power management is to transition from the LPS mode.

[0047] For example, during LPS mode, the platform temperature control component 124 performs an evaluation to detect whether the thermal condition (e.g., the current level of the surface temperature, the average of the surface temperature, the integral of the surface temperature, etc.) is below the same (or some other) threshold level. In the event that the thermal condition is below said threshold level, the platform temperature control component 124 generates one or more signals for causing one or more components of the system 100 to transition from the LPS mode to another (non-LPS) mode that makes a relatively large number of power states available to the CPU 104 (and / or to the GPU 106).

[0048] Figure 2 Features of a system 200 for providing a limited power state mode to manage the operation of a processor are shown according to an embodiment. System 200 illustrates an example of an embodiment in which a determination as to whether an LPS mode is to be configured is performed based on an estimate of thermal conditions, in this case an estimate of surface temperature. In some embodiments, system 200 includes features of system 100.

[0049] like Figure 2As shown in , system 200 includes chip 202, memory 220, and radio component 228, which are located on separate chips within housing 214. In this example, chip 202 includes CPU core component 204, which includes multiple processing cores, which are not shown separately. Chip 202 also includes GPU 206, system agent 212, and cache 208. System agent 212 performs various control and input / output functions, including memory control, display control, etc. In this embodiment, a temperature sensor 210 is provided to measure the temperature of CPU core component 204. For example, temperature sensor 210 is a discrete sensor, or alternatively, in some embodiments, temperature sensor 210 is integrated into the circuit within CPU core component 204. The temperature sensor 210 is alternatively positioned proximate to the CPU core assembly 204 (e.g., where the temperature sensor 210 is thermally coupled via one or more points on a die comprising the chip 202) such that temperature measurements recorded by the temperature sensor 210 provide a measurement of the processor temperature (also referred to herein as the "junction temperature") with sufficient accuracy.

[0050] exist Figure 2 In some embodiments, the platform temperature control component 224 is coupled to the temperature sensor 210 to monitor the temperature readings generated by the temperature sensor 210 as needed. The platform temperature control component 224 is further operable to adjust the power of the CPU core component 204 based on the temperature sensor data provided by the temperature sensor 210. In some embodiments, by monitoring the junction temperature using the temperature sensor 210, the actual junction temperature is recorded in real time. This allows the average junction temperature to be estimated or calculated in real time to determine when the average junction temperature (for example) approaches a current limit, such as a limit corresponding to a surface temperature limit for the housing 214.

[0051] System 200 illustrates an example embodiment in which a transition to LPS mode is performed based on respective temperatures of one or more components within the housing structure—wherein the one or more component temperatures indicate whether a surface temperature of the housing structure is above a threshold maximum value. For example, some embodiments use the one or more component temperatures to estimate a surface temperature of housing 214. In one such embodiment, platform temperature control assembly 224 includes some or all of the features of platform temperature control assembly 124. Additionally or alternatively, functionality such as functionality of power control unit 114 is provided, for example, with platform temperature control assembly 224 and / or CPU core assembly 204.

[0052] In an illustrative scenario according to one embodiment, the platform temperature control component 224 and / or the CPU core component 204 includes, is coupled to, or otherwise operates based on reference information that specifies or otherwise indicates the correspondence of various temperature levels (e.g., various surface temperature levels of the housing 214) to different corresponding temperature levels determined based on information from the temperature sensor 210. For example, the reference information includes a lookup table, a function, and / or various other suitable types of information that identify the correspondence of the surface temperature levels to different corresponding levels of temperature at the CPU core component 204. In one such embodiment, the platform temperature control component 224 or the power management logic of the CPU core component 204 performs a lookup, calculation, or other suitable operation to determine an estimated (or actual) surface temperature level based on the reference information and the temperature level detected using the temperature sensor 210. The surface temperature level is evaluated based on (e.g., compared to) a threshold level to determine whether power management of the CPU core component 204 is to be performed according to the LPS mode. In one such embodiment, the LPS mode remains configured until the (actual or estimated) surface temperature level is below a predetermined threshold level.

[0053] Figure 3 Features of a system 300 for determining power consumption caused by a processor are shown according to another embodiment. Figure 3 An example of an embodiment is illustrated in which a determination as to whether an LPS mode is to be configured is performed based on a plurality of temperatures each sensed in various ways at different respective components in a housing structure. In one such embodiment, an evaluation is performed based on the plurality of component temperatures to determine an estimated surface temperature of the housing structure (e.g., a moving average of the estimated surface temperature). In the event that it is determined that the estimated surface temperature exceeds a threshold maximum temperature level, some embodiments transition power management to an LPS mode that makes a relatively limited number of two or more power states available to the processor. In some embodiments, system 300 includes features of system 100 or system 200.

[0054] like Figure 3 As shown in FIG. 3 , system 300 includes chip 302, memory 308, chipset 312, and radio components 328, which are located on separate chips. In addition to CPU core components 344 (which provide such Figure 2In addition to the functions of the CPU core component 204 in the chip 302, the chip 302 also includes one or more components such as a cache 338 and a graphics processor 304, and the graphics processor 304 includes a temperature sensor 306 to measure the temperature of the graphics processor 304. Even though the graphics processor 304 and the CPU core component 344 are located together on the same chip 302, two different temperature sensors 340, 306 are provided to determine the temperature in a more local manner for each corresponding component (i.e., the CPU core component 344 and the graphics processor 304).

[0055] In addition, Figure 3 In the embodiment of FIG. 3 , the memory 308 includes its own temperature sensor 310, and the chipset has its own temperature sensor 314. Figure 3 As shown in FIG. 1 , each of the temperature sensors 340, 306, 310, and 314 is communicatively coupled to a platform temperature control component 334 (e.g., the platform temperature control component 334 provides the functionality of the platform temperature control component 124 or the platform temperature control component 224). In this manner, the junction temperature of each of the CPU core component 344, the graphics processor 304, the memory 308, and the chipset 312 is independently monitored by the platform temperature control component 334. Figure 3 As further illustrated in , during operation of each or all of these components, platform temperature control component 334 sends control signals for adjusting component operation.

[0056] In an illustrative scenario according to one embodiment, message 320 is sent to CPU core component 344 to adjust core power consumption based on some or all of the junction temperature measurements recorded by temperature sensors 340, 306, 310, and 314. Alternatively or additionally, message 322 is sent to GPU 304 to adjust GPU power consumption based on some or all of the junction temperature measurements recorded by temperature sensors 340, 306, 310, and 314. Although some embodiments are not limited in this respect: another message 324 is sent to memory 308 to adjust memory operations based on some or all of the junction temperature measurements—e.g., at the same time, message 326 is sent to chipset 312 to adjust chipset operations based on some or all of the junction temperature measurements. These adjustments, together or individually, allow the performance of each component to be maximized consistent with maintaining the surface temperature of housing 316 at or below specified limits.

[0057] In detail, for one or more components or devices controlled by the platform, the platform temperature control component 334 receives a single set of temperature sensor measurements or multiple temperature sensor measurements to track the junction temperature (e.g., in real time). In some embodiments, such one or more real-time junction temperature measurements are additionally used to generate a calculated average temperature. In one such embodiment, the platform temperature control component 334 then uses the junction temperature and the calculated average junction temperature value at a given instance to determine whether to adjust the operation of a given controlled device. For example, the platform temperature control component 334 stores, retrieves, or receives a set of one or more restrictions, which in an embodiment include temperature restrictions (e.g., surface temperature restrictions and / or junction temperature restrictions) and / or steady-state junction temperature. In various embodiments, such one or more restrictions are then used (e.g., in real time) to compare with the (one or more) junction temperatures and / or (one or more) average junction temperatures of the controlled device to adjust the operation of the controlled device when the restrictions are broken.

[0058] In an illustrative scenario according to one embodiment, the platform temperature control component 334 operates based on reference information that specifies or otherwise indicates the correspondence of various temperature levels (e.g., individual temperature levels of the surface temperature of the housing 316) to different respective sets of one or more temperature levels sensed in respective manners using the temperature sensors 340, 306, 310, and 314. In one such embodiment, the platform temperature control component 334 performs a lookup, calculation, or other suitable operation to determine an estimated (or actual) surface temperature level of the housing 316 based on the reference information and some or all of the temperature levels detected using the temperature sensors 340, 306, 310, and 314. The surface temperature level is evaluated based on (e.g., compared to) a threshold level to determine whether power management of the CPU core component 344 and / or the graphics processor 304 is to be performed according to the LPS mode. In one such embodiment, the LPS mode remains configured until the surface temperature of the housing 316 is again below a predetermined threshold level.

[0059] Figure 4A Features of a method 400 for operating power management logic according to an embodiment are shown. The method 400 illustrates an example of an embodiment in which a limited power state (LPS) mode of power management is implemented based on a thermal condition. The thermal condition includes or otherwise corresponds to a surface temperature of a housing structure, but other embodiments are not limited in this respect. In various embodiments, one or more operations of the method 400 are performed using circuitry of one of the systems 100, 200, 300. For example, the method 400 is performed, at least in part, using the CPU 104, the power control unit 114, the platform temperature control component 124, and / or other suitable hardware of the system 100.

[0060] like Figure 4A As shown in , method 400 includes (at 410) receiving a first indication of a first thermal condition of a platform including a processor. For example, the platform includes a housing structure and various components (including the processor) disposed therein - for example, wherein the first indication includes one or more temperatures each measured at a corresponding one of the components or measured at the housing structure.

[0061] In one such embodiment, the first indication includes a value representing a direct sense of a surface temperature of the housing structure, or is otherwise determined based on the value. Alternatively or additionally, the first indication includes a value representing a direct sense of a temperature of another structure (e.g., a component) disposed within the housing structure, or is otherwise determined based on the value - for example, wherein the value of the component temperature at least partially corresponds to or otherwise indicates the surface temperature of the housing structure. Alternatively or additionally, the first indication includes a value representing a performance metric and / or power consumption of some or all of the one or more components - for example, wherein the value of the performance metric at least partially corresponds to or otherwise indicates the surface temperature of the housing structure.

[0062] Based on the first indication received at 410, method 400 (at 412) causes power management of the processor to transition to a limited power state (LPS) mode. For example, in some embodiments, method 400 further includes: performing one or more evaluations based on the first indication to identify a first thermal condition and detect whether the first thermal condition satisfies a first test condition for configuring the LPS mode. In one such embodiment, the evaluation includes comparing the first indication (or a value generated based on the first indication) to a threshold value (such as a threshold maximum surface temperature). In various embodiments, the one or more evaluations include (or are based on) any suitable operation of a lookup, calculation, or various other suitable operations for identifying the first thermal condition. By way of illustration and not limitation, the one or more evaluations include: performing one or more of an averaging operation, an integration operation, and a calculation of a rate of change (e.g., a first order rate, a second order rate, etc.) based on the value of the first indication.

[0063] In various embodiments, two or more power states of the processor are enabled during LPS mode, wherein one or more other power states of the processor (e.g., the one or more other power states would have been available during an alternative power management mode) are blocked during LPS mode. For example, the two or more power states include only two power states. In one embodiment, some or all of the one or more other power states (e.g., each of the one or more other power states) are each a relatively higher power state compared to those power states in the two or more power states. In one such embodiment, transitioning power management to LPS mode includes (or otherwise causes) transitioning the processor from one of the one or more power states to one of the two or more power states that is relatively lower in power (e.g., the lowest power state).

[0064] In various embodiments, method 400 additionally or alternatively includes operation 402, which is performed during the LPS mode to which power management is transitioned at 412. By way of illustration and not limitation, during the LPS mode configured at 412, operation 402 monitors (at 414) one or more software processes executed using the processor. In one such embodiment, the monitoring at 414 is used to detect the pendency of a workload (if any) for the one or more software processes. Based on the detection of such workload, operation 402 causes (at 416) the processor to transition between two or more power states made available by the LPS mode—e.g., where the transition at 416 is a power increase transition.

[0065] In some embodiments, operation 402 further includes detecting completion of a workload by the processor, and transitioning the processor between two or more power states based on the completion (e.g., wherein the transitions include power reduction transitions). In one such embodiment, the processor is transitioned between the two or more power states multiple times during the LPS mode—e.g., wherein the power increase transitions during the LPS mode are each used to facilitate a different workload, and wherein the power increase transitions during the LPS mode are each based on completion of a different respective workload.

[0066] In some embodiments, operation 402 further includes monitoring to detect for satisfaction of a test condition indicating that the current instance of the LPM mode is to be terminated (or operation 402 is further performed during monitoring). By way of illustration and not limitation, operation 402 further includes receiving (at 418) a second indication of a second thermal condition of the platform. In one such embodiment, the second indication includes a more recent value of a temperature, metric, or other characteristic previously represented by the first indication, or the second indication is otherwise determined based on the more recent value.

[0067] In one such embodiment, method 400 further includes: performing one or more additional evaluations based on the second indication to identify the second thermal condition and detect whether the second thermal condition satisfies a second test condition for terminating the current instance of the LPS mode. For example, the one or more additional evaluations compare the second indication (or a value generated based on the second indication) to a threshold, such as a threshold minimum surface temperature for remaining in the LPS mode. In various embodiments, the one or more additional evaluations include (or are based on) the performance of any suitable operation of a lookup, calculation, or various other suitable operations for identifying the second thermal condition. By way of illustration and not limitation, the one or more additional evaluations include: performing one or more of an averaging operation, an integration operation, and a calculation of a rate of change (e.g., a first-order rate, a second-order rate, etc.) based on the value of the second indication.

[0068] Based on the second indication, method 400 causes (at 420) power management of the processor to transition from the LPS mode. In an embodiment, the transition at 420 includes increasing the total number of power states available to the processor—e.g., by enabling one or more power states that were blocked during the LPS mode. In one such embodiment, the transition at 420 includes (or causes) a power increase transition of the processor from one of the two or more power states to a previously blocked power state.

[0069] In some embodiments, during another (non-LPS) mode (e.g., prior to the transition at 412), power management of the processor is performed using a first state machine according to which the processor transitions between any of the first plurality of power states in various ways. In contrast, during the LPS mode (e.g., after the transition at 412), power management of the processor is instead performed using a second state machine according to which the processor transitions between any of the second plurality of power states in various ways. The total number of the first plurality of power states is greater than the total number of the second plurality of power states—e.g., where the second plurality of power states is a subset of the first plurality of power states. In one such embodiment, the transition at 412 includes resuming power management of the processor using the first state machine (i.e., instead of continuing to use the second state machine for power management).

[0070] Figure 4B Features of a method 450 for operating power management logic according to an embodiment are shown. Operations such as those of method 450 are performed using any of various combinations of suitable hardware (e.g., circuitry) and / or execution software that provide some or all of the functionality of one of systems 100, 200, 300, for example. Additionally or alternatively, method 450 includes features of method 400.

[0071] like Figure 4B As shown in , method 450 includes (at 460) performing power management using a first plurality of power states that are selectively made available to the processor during a non-LPS mode. In an embodiment, each power state in the first plurality of power states is a power state that is "available" during a non-LPS mode. For example, power management during a non-LPS mode is based on a first state machine according to which the processor is to be transitioned between the first plurality of power states (e.g., between any of the first plurality of power states) over time in various ways.

[0072] The method 450 further includes (at 462) evaluating an indicator of a thermal condition of the platform. For example, the indicator evaluated at 462 is the first indicator received at 410 in the method 400. The method 450 further includes (at 464) determining whether a test criterion (referred to herein as "LPS mode entry criterion") has been met (or, for example, is expected to be met) based on the evaluation at 462. In one such embodiment, the determination at 464 includes comparing the indicator of the thermal condition (or a value identified based on the indicator) to a threshold value (such as a threshold maximum surface temperature value).

[0073] In the event that it is determined at 464 that the LPS mode entry criteria have not been met, method 450 continues to perform power management according to the non-LPS mode, utilizing the first plurality of power states (at 460). In the event that it is alternatively determined at 464 that the LPS mode entry criteria have been met, method 450 enables the LPS mode (at 466). In an embodiment, during the LPS mode, two or more power states are available to the processor, while one or more of the first plurality of power states are blocked (and thus unavailable) during the LPS mode. For example, enabling the LPS mode at 466 includes transitioning between performing power state selection based on the first state machine to performing power state selection based on the second state machine. In one such embodiment, the number of the second plurality of power states enabled by the second state machine is relatively limited compared to the total number of the first plurality of power states.

[0074] During the LPS mode (which is enabled at 466), the method 450 operates the processor (at 468) based on a current power state of two or more available power states. While the processor remains in one of the available power states, the method 450 performs an evaluation (at 470) to determine whether at least some power state transition criteria (e.g., any of a plurality of currently enabled power state transition criteria) has been satisfied. For example, the evaluation at 470 includes (or is otherwise based on) monitoring of software processes executed with the processor to detect the pendency of a workload (if any).

[0075] In the event that it is determined at 470 that the transition criteria have been met, the method 450 causes the processor to transition between two of the available two or more power states at 472, and then operates the processor based on the currently configured power state at 468. In an illustrative scenario according to one embodiment, the evaluation at 470 detects the pendency of a software workload, where the transition at 472 is a power increase transition. In an alternative scenario, the evaluation at 470 detects the completion of a software workload by the processor, where the transition at 472 is a power decrease transition.

[0076] In the event that, instead of determining at 470 that no transition criteria are met, method 450 performs another evaluation (at 474) to determine whether another test criterion (referred to herein as "LPS mode exit criteria") is met. For example, the evaluation at 474 includes determining whether the surface temperature of the housing structure (or other suitable thermal condition) is below some threshold minimum level for power management to remain in LPS mode.

[0077] In the event that it is determined at 474 that the LPS mode exit criteria have not been met, method 450 continues to operate the processor based on a current power state of the two or more power states that are available (at 468). In the event that it is alternatively determined at 474 that the LPS mode exit criteria have been met, method 450 disables LPS mode (at 476). In one such embodiment, disabling at 476 increases the total number of power states to be made available to the processor. For example, disabling LPS mode at 476 includes transitioning between performing power state selection based on the second state machine (described above) to performing power state selection based on the first state machine. After LPS mode is disabled at 476, method 450 again performs power management based on the (relatively large number of) first plurality of power states (at 460).

[0078] Figure 5 Features of a system 500 for configuring a limited power state mode of power management according to an embodiment are shown. In various embodiments, system 500 provides functionality such as functionality of one of systems 100, 200, 300—e.g., where one or more operations of method 400 or method 450 are performed using system 500.

[0079] like Figure 5 , system 500 includes a power management unit 502 coupled to manage one or more components (represented as illustrative component 503 shown) including a processor 504. In some embodiments, the illustrated processor 504 is a CPU, GPU, etc. System 500 further includes one or more sensors (such as illustrative thermal sensor 506 shown) coupled to sense environmental conditions, power / performance metrics, and / or other information including or otherwise indicating a thermal condition of system 500. In one such embodiment, the thermal condition includes or otherwise indicates a surface temperature of a housing structure (not shown) in which component 503 is disposed.

[0080] Thermal sensor 506 provides an indicator of the thermal condition to evaluation unit 508 of system 500. Evaluation unit 508 includes logic (e.g., circuit hardware, firmware, and / or executive software) to perform one or more lookups, calculations, and / or other suitable operations to identify the thermal condition based on the indicator received from thermal sensor 506.

[0081] In an illustrative scenario according to one embodiment, the evaluation unit 508 is operable to calculate an average surface temperature value, an integral of the surface temperature value over time, a rate of change of the surface temperature value, etc. based on the sensor information from the thermal sensor 506. Alternatively or additionally, the evaluation unit 508 includes reference information 510, or is otherwise coupled to access reference information 510, which specifies or otherwise indicates the correspondence of various values ​​(e.g., values ​​of any of temperatures, performance metrics, and / or various other suitable characteristics) to different corresponding values ​​of the surface temperature (or other such thermal conditions to be the basis for providing the LPS mode). In an illustrative scenario according to one embodiment, the reference information 510 includes a table (or other suitable data structure) identifying the correspondence of one or more temperatures of the component 503 to a particular level of the surface temperature. In one such embodiment, the reference information 510 indicates whether some of the components A, B, ... X of the component 503 are (respectively) at temperature levels ta1, tb1, ... tx1, and thereby whether the housing structure is at a surface temperature level Tsk1. Furthermore, the reference information 510 indicates whether the components A, B, . . . X are alternatively (respectively) at temperature levels ta2 , tb2 , . . . tx2 and thus whether the housing structure is at a different surface temperature level Tsk2 .

[0082] Based on any of calculations, table lookups, and / or various other suitable operations, the evaluation unit 508 provides a value (or values) identifying a thermal condition of the system 500, such as a surface temperature of a housing structure, to a comparator 512 of the system 500. The comparator 512 provides for comparing such a value to a threshold 514 (such as a threshold maximum surface temperature)—for example, where such a comparison is used to determine whether a test criterion for entering an LPS mode (or, alternatively, a test criterion for exiting an LPS mode) has been met or is expected to be met.

[0083] In one such embodiment, comparator 512 indicates satisfaction of LPS mode entry criteria (or, for example, satisfaction of LPS mode exit criteria) to monitoring unit 540 of power management unit 502. Based on such indications from comparator 512, power management by system 500 (e.g., including monitoring unit 540, power management of processor 504, and / or power management of one or more other components of component 503) transitions between two or more power management modes, including a first (non-LPS) mode and a second (LPS) mode.

[0084] In an illustrative scenario according to one embodiment, a first mode makes a first plurality of power states 520 available to processor 504—e.g., wherein, during the first mode, each of power states 520 is a candidate for becoming a possible power state for processor 504. In contrast, a second (LPS) mode makes a second plurality of power states 522 available to processor 504, wherein the total number of first plurality of power states 520 is greater than the total number of second plurality of power states 522. In the example embodiment shown, power states 522 are a subset of power states 520—e.g., power states 520 further include one or more additional power states in addition to any of power states 522.

[0085] By way of illustration and not limitation, during the first (non-LPS) mode, power management of processor 504 is performed using power management unit 502's (or alternatively, processor 504's) state machine 530, which facilitates various transitions of processor 504 between any of power states 520. In contrast, during the second (LPS) mode, power management of processor 504 is performed using power management unit 502's (or alternatively, processor 504's) state machine 532, where state machine 532 facilitates various transitions of processor 504 between any of power states 522.

[0086] In some embodiments, a first power state in power states 520 (other than any power state in power states 522) is a blocked power state during the second (LPS) mode—that is, wherein during the second mode, processor 504 is blocked from transitioning to the first power state. In one such embodiment, the first power state is a relatively higher power state compared to each of the power states in power states 522. In an illustrative scenario according to one embodiment, the first (non-LPS) mode enables a power management unit 502, processor 504, or other suitable logic of system 500 to use a first test criterion to determine whether processor 504 is to transition to (or, alternatively, from) the first power state. However, such use of the first test criterion is disabled during the second (LPS) mode. For example, based on the first test criterion, the first (non-LPS) mode blocks any evaluation from triggering a transition of processor 504 to (or, alternatively, from) the first power state. By way of illustration and not limitation, such evaluation (e.g., including comparing a threshold value to another value representing an identified thermal condition) is disabled during the first (non-LPS) mode. In one such embodiment, monitoring for identifying thermal conditions is also disabled during the first mode.

[0087] Figure 6A diagram 600 illustrating operations for transitioning a processor between power states according to an embodiment is shown. Diagram 600 illustrates transitioning power management to a limited power state (LPS) mode, according to which the processor can transition between two or more power states. In various embodiments, diagram 600 represents power management at one of systems 100, 200, 300, 500—e.g., where one or more operations of method 400 or method 450 include or otherwise cause the features shown in diagram 600.

[0088] like Figure 6 As shown in , the diagram 600 includes a first plot 610 illustrating a change in a surface temperature (Tsk) 602 (such as the surface temperature of the housing 102) during a time 605. The diagram 600 further includes a second plot 620 and a third plot 630 that represent the power state change of the processor (such as the CPU 104 or the GPU 106) during the time 605 in various ways. More specifically, the plot 620 represents a change in the operating frequency of the processor during the time 605, while the plot 630 represents a change in the amount of power consumed by the processor during the time 605. Figure 6 6 , an axis 604 of the graph 600 represents both power consumed and operating frequency—ie, where along the axis 604 , 1 Watt (W) of power consumed corresponds to an operating frequency of 100 Megahertz (MHz).

[0089] As illustrated by plot 610 in diagram 600, during a first portion of time 605, the processor is operated in a first (relatively higher) power state, the first power state comprising or otherwise corresponding to an operating frequency of approximately 5 gigahertz (GHz) and a power consumption of approximately 20 W. During this first portion of time 605, the surface temperature Tsk increases steadily until it exceeds a threshold maximum value, which in this example embodiment is equal to 44 degrees Celsius (°C). Based on the surface temperature Tsk exceeding the threshold maximum value, power management of the processor is transitioned from a first (non-LPS) mode to a second (LPS) mode. By way of illustration and not limitation, the second mode enables the second power state and the third power state to be available to the processor, while the first power state is blocked (i.e., unavailable) at least during the LPS mode.

[0090] In the example embodiment shown, the second power state includes or otherwise corresponds to an operating frequency of approximately 2.5 GHz and a power consumption of approximately 10 W. In contrast, the third power state includes or otherwise corresponds to an operating frequency of approximately 4.5 GHz and a power consumption of approximately 17.5 W. In some embodiments, the second power management mode makes any of a variety of additional or alternative power states available to the processor (e.g., while preventing at least the first power state).

[0091] During the second (LPS) mode, the processor is subject to being transitioned between the second power state and the third power state one or more times - for example, until the surface temperature (Tsk) again drops below a threshold maximum value (or below some other threshold temperature). By way of illustration and not limitation, multiple power increase transitions (from the second power state to the third power state) are performed in various ways during the second mode, wherein each such transition is used to facilitate the execution of a different corresponding workload by the processor. In one such embodiment, multiple power decrease transitions (from the third power state to the second power state) are also performed in various ways during the second mode, wherein each such transition is after the completion of a different corresponding workload by the processor.

[0092] Figure 7 A computer system or computing device 700 (also referred to as device 700) is illustrated in accordance with some embodiments, wherein power management of a processor is conditionally performed according to a limited power state (LPS) mode. It should be noted that Figure 7 Those elements having the same reference numerals (or names) as elements of any other figure may operate or function in any manner similar to that described, but are not limited thereto.

[0093] In some embodiments, device 700 represents a suitable computing device, such as a computing tablet, a mobile phone or smartphone, a laptop computer, a desktop computer, an Internet-of-Things (IOT) device, a server, a wearable device, a set-top box, a wireless-enabled e-reader, etc. It will be understood that certain components are shown generally, and not all components of such a device are shown in device 700.

[0094] In the example, the device 700 includes a SoC (System-on-Chip) 701. Figure 7 Example boundaries of SOC 701 are illustrated using dashed lines, with some example components illustrated as being included within SOC 701—however, SOC 701 may include any suitable components of device 700 .

[0095] In some embodiments, the device 700 includes a processor 704. The processor 704 may include one or more physical devices, such as a microprocessor, an application processor, a microcontroller, a programmable logic device, a processing core, or other processing means. The processing operations performed by the processor 704 include the execution of an operating platform or operating system on which applications and / or device functions are executed. The processing operations include operations related to I / O (input / output) with a human user or other device, operations related to power management, operations related to connecting the computing device 700 to another device, and / or similar operations. The processing operations may also include operations related to audio I / O and / or display I / O.

[0096] In some embodiments, processor 704 includes multiple processing cores (also referred to as cores) 708a, 708b, 708c. Figure 7 Only three cores 708a, 704b, 708c are illustrated, but the processor 704 may include any other suitable number of processing cores, for example, dozens or even hundreds of processing cores. The processing cores 708a, 708b, 708c may be implemented on a single integrated circuit (IC) chip. Moreover, the chip may include one or more shared and / or private caches, buses or interconnects, graphics and / or memory controllers or other components.

[0097] In some embodiments, the processor 704 includes a cache 706. In an example, portions of the cache 706 may be dedicated to respective cores 708 (e.g., a first portion of the cache 706 is dedicated to core 708a, a second portion of the cache 706 is dedicated to core 708b, and so on). In an example, one or more portions of the cache 706 may be shared between two or more cores 708. The cache 706 may be divided into different levels, such as a level 1 (L1) cache, a level 2 (L2) cache, a level 3 (L3) cache, and the like.

[0098] In some embodiments, a given processor core (e.g., core 708a) may include a fetch unit for fetching instructions (including instructions with conditional branches) for execution by core 708a. The instructions may be fetched from any storage device such as memory 730. Processor core 708a may also include a decode unit for decoding the fetched instructions. For example, the decode unit may decode the fetched instructions into a plurality of micro-operations. Processor core 708a may include a dispatch unit for performing various operations associated with storing decoded instructions. For example, the dispatch unit may save data from the decode unit until the instruction is ready for dispatch, for example, until all source values ​​of the decoded instruction become available. In one embodiment, the dispatch unit may dispatch the decoded instructions to the execution unit for execution, and / or issue (or dispatch) the decoded instructions to the execution unit for execution.

[0099] The execution unit may execute the dispatched instruction after the instruction is decoded (e.g., by the decode unit) and dispatched (e.g., by the dispatch unit). In an embodiment, the execution unit may include more than one execution unit (such as an imaging computing unit, a graphics computing unit, a general computing unit, etc.). The execution unit may also perform various arithmetic operations, such as addition, subtraction, multiplication, and / or division, and may include one or more arithmetic logic units (ALUs). In an embodiment, a coprocessor (not shown) may be combined with the execution unit to perform various arithmetic operations.

[0100] Further, the execution unit may execute instructions out of order. Thus, in one embodiment, the processor core 708a (for example) may be an out-of-order processor core. The processor core 708a may also include a retirement unit. The retirement unit may retire the executed instructions after they are committed. In an embodiment, retiring the executed instructions may cause: the processor state is committed from the execution of these instructions, the physical registers used by these instructions are deallocated, and the like. The processor core 708a may also include a bus unit for implementing communication between components of the processor core 708a and other components via one or more buses. The processor core 708a may also include one or more registers for storing data accessed by various components of the core 708a (such as values ​​associated with the assigned application priority and / or subsystem state (mode)).

[0101] In some embodiments, device 700 includes connectivity circuitry 731. For example, connectivity circuitry 731 includes hardware devices (e.g., wireless and / or wired connectors and communication hardware) and / or software components (e.g., drivers, protocol stacks), for example, to enable device 700 to communicate with external devices. Device 700 can be separate from external devices (such as other computing devices, wireless access points or base stations, etc.).

[0102] In an example, the connectivity circuit 731 may include a variety of different types of connectivity. In summary, the connectivity circuit 731 may include cellular connectivity circuits, wireless connectivity circuits, etc. The cellular connectivity circuits of the connectivity circuit 731 generally refer to cellular network connectivity provided by a wireless operator, such as provided via GSM (Global System for Mobile Communications) or variants or derivatives, CDMA (Code Division Multiple Access) or variants or derivatives, TDM (Time Division Multiplexing) or variants or derivatives, 3rd Generation Partnership Project (3GPP) Universal Mobile Telecommunications System (UMTS) system or variants or derivatives, 3GPP Long-Term Evolution (LTE) system or variants or derivatives, 3GPP LTE Advanced (LTE-Advanced, LTE-A) system or variants or derivatives, Fifth Generation (5G) wireless system or variants or derivatives, 5G mobile network system or variants or derivatives, 5G New Radio (NR) system or variants or derivatives, or other cellular service standards. The wireless connectivity circuitry (or wireless interface) of the connectivity circuitry 731 refers to non-cellular wireless connectivity and may include personal area networks (such as Bluetooth, near field, etc.), local area networks (such as Wi-Fi) and / or wide area networks (such as WiMax) and / or other wireless communications. In an example, the connectivity circuitry 731 may include a network interface (such as a wired interface or a wireless interface), for example, so that the system embodiment can be incorporated into a wireless device, such as a cellular phone or a personal digital assistant.

[0103] In some embodiments, the device 700 includes a control hub 732, which represents hardware devices and / or software components related to interaction with one or more I / O devices. For example, the processor 704 can communicate with one or more of the display 722, one or more peripheral devices 724, a storage device 728, one or more other external devices 729, etc. via the control hub 732. The control hub 732 can be a chipset, a platform control hub (Platform Control Hub, PCH), etc.

[0104] For example, control hub 732 illustrates one or more connection points for additional devices connected to device 700, for example, through which a user can interact with the system. For example, devices that can be attached to device 700 (e.g., device 729) include microphone devices, speakers or stereo systems, audio devices, video systems or other display devices, keyboards or keypad devices, or other I / O devices for use with specific applications (such as card readers or other devices).

[0105] As mentioned above, the control hub 732 can interact with audio devices, display 722, and the like. For example, input through a microphone or other audio device can provide input or commands for one or more applications or functions of the device 700. Additionally, audio output can be provided as a substitute or in addition to display output. In another example, if the display 722 includes a touch screen, the display 722 also acts as an input device, which can be at least partially managed by the control hub 732. Additional buttons or switches may also be present on the computing device 700 to provide I / O functions managed by the control hub 732. In one embodiment, the control hub 732 manages devices such as accelerometers, cameras, light sensors or other environmental sensors, or other hardware that may be included in the device 700. The input can be part of direct user interaction, as well as providing environmental input to the system to affect its operation (such as filtering noise, adjusting the display for brightness detection, applying a camera flash, or other features).

[0106] In some embodiments, the control hub 732 can be coupled to various devices using any appropriate communication protocol, such as PCIe (Peripheral Component Interconnect Express), USB (Universal Serial Bus), Thunderbolt, High Definition Multimedia Interface (HDMI), Firewire, etc.

[0107] In some embodiments, the display 722 represents hardware (e.g., display device) and software (e.g., driver) components that provide a visual and / or tactile display for a user to interact with the device 700. The display 722 may include a display interface, a display screen, and / or a hardware device for providing a display to a user. In some embodiments, the display 722 includes a touch screen (or touchpad) device that provides both output and input to the user. In an example, the display 722 can communicate directly with the processor 704. The display 722 can be one or more of the following: an internal display device, such as in a mobile electronic device or a laptop device; or an external display device attached via a display interface (e.g., a display port (DisplayPort) or the like). In one embodiment, the display 722 can be a head mounted display (HMD), such as a stereoscopic display device used in a virtual reality (VR) application or an augmented reality (AR) application.

[0108] In some embodiments, and although not illustrated in the figures, in addition to (or in lieu of) processor 704 , device 722 may include a graphics processing unit (GPU) comprising one or more graphics processing cores that may control one or more aspects of displaying content on display 722 .

[0109] The control hub 732 (or platform controller hub) may include hardware interfaces and connectors, as well as software components (eg, drivers, protocol stacks) to make peripheral connections, such as to peripheral devices 724 .

[0110] It will be understood that device 700 can be both a peripheral device that connects to other computing devices and can have peripheral devices connected to device 700. Device 700 can have a "docking" connector for connecting to other computing devices for purposes such as managing (e.g., downloading and / or uploading, changing, synchronizing) content on device 700. Additionally, the docking connector can allow device 700 to connect to certain peripheral devices that allow computing device 700 to control content output, such as to an audio-visual or other system.

[0111] In addition to a dedicated docking connector or other dedicated connection hardware, the device 700 may also make peripheral connections via common or standards-based connectors. Common types may include a Universal Serial Bus (USB) connector (which may include any of several different hardware interfaces), a DisplayPort including a MiniDisplayPort (MDP), a High-Definition Multimedia Interface (HDMI), FireWire, or other types.

[0112] In some embodiments, for example, the connectivity circuit 731 may be coupled to a control hub 732 in addition to or instead of being directly coupled to the processor 704. In some embodiments, for example, the display 722 may be coupled to a control hub 732 in addition to or instead of being directly coupled to the processor 704.

[0113] In some embodiments, the device 700 includes a memory 730 coupled to the processor 704 via a memory interface 734. The memory 730 includes a memory device for storing information in the device 700. The memory may include a non-volatile (the state does not change in the case of power interruption to the memory device) and / or a volatile (the state is uncertain in the case of power interruption to the memory device) memory device. The memory device 730 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or some other memory device with suitable performance to act as a process memory. In one embodiment, the memory 730 may operate as a system memory of the device 700 to store data and instructions for use when one or more processors 704 execute applications or processes. The memory 730 may store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of applications and functions of the device 700.

[0114] The elements of various embodiments and examples are also provided as a machine-readable medium (e.g., memory 730) for storing computer-executable instructions (e.g., instructions for implementing any other process discussed herein). The machine-readable medium (e.g., memory 730) may include, but is not limited to, flash memory, optical disk, CD-ROM, DVD ROM, RAM, EPROM, EEPROM, magnetic or optical card, phase change memory (PCM), or other types of machine-readable media suitable for storing electronic instructions or computer-executable instructions. For example, embodiments of the present disclosure may be downloaded as a computer program (e.g., BIOS), which may be transmitted from a remote computer (e.g., server) to a requesting computer (e.g., client) via a communication link (e.g., modem or network connection) by means of a data signal.

[0115] In some embodiments, the device 700 includes a temperature measurement circuit 740, which is used, for example, to measure the temperature of various components of the device 700. In an example, the temperature measurement circuit 740 can be embedded, coupled, or attached to various components whose temperatures are to be measured and monitored. For example, the temperature measurement circuit 740 can measure the temperature of one or more of the cores 708a, 708b, 708c, the voltage regulator 701, the memory 700, the motherboard of the SOC 701, and / or any appropriate components of the device 700 (or can measure the temperature within one or more of these components).

[0116] In some embodiments, the device 700 includes a power measurement circuit 742, which is used, for example, to measure the power consumed by one or more components of the device 700. In an example, in addition to measuring power, or instead of measuring power, the power measurement circuit 742 can also measure voltage and / or current. In an example, the power measurement circuit 742 can be embedded, coupled or attached to various components whose power, voltage and / or current consumption is to be measured and monitored. For example, the power measurement circuit 742 can measure the power, current and / or voltage supplied by one or more voltage regulators 714; the power supplied to the SOC 701; the power supplied to the device 700; the power consumed by the processor 700 (or any other component) of the device 704; and the like.

[0117] In some embodiments, the device 700 includes one or more voltage regulator circuits, generally referred to as voltage regulators (VRs) 714. VR 714 generates signals at appropriate voltage levels that can be supplied to operate any appropriate component of the device 700. By way of example only, VR 714 is illustrated as supplying signals to the processor 700 of the device 704. In some embodiments, VR 714 receives one or more voltage identification (VID) signals and generates voltage signals at appropriate levels based on the VID signals. Various types of VRs can be used for VR 714. For example, VR 714 can include a "buck" VR, a "boost" VR, a combination of a buck VR and a boost VR, a low dropout (LDO) regulator, a switching DC-DC regulator, and the like. Buck VRs are typically used in power delivery applications where an input voltage needs to be converted to an output voltage at a ratio less than 1. Boost VRs are typically used in power delivery applications where an input voltage needs to be converted to an output voltage at a ratio greater than 1. In some embodiments, each processor core has its own VR, which is controlled by the PCU 710a, 710b and / or PMIC 712. In some embodiments, each core has a network with distributed LDOs to provide efficient control of power management. The LDOs can be digital, analog, or a combination of digital or analog LDOs.

[0118] In some embodiments, the device 700 includes one or more clock generator circuits, generally referred to as clock generator 716. The clock generator 716 generates a clock signal at an appropriate frequency level, which can be supplied to any appropriate component of the device 700. By way of example only, the clock generator 716 is illustrated as supplying a clock signal to the processor 704 of the device 700. In some embodiments, the clock generator 716 receives one or more frequency identification (Frequency Identification, FID) signals and generates a clock signal at an appropriate frequency based on the FID signals.

[0119] In some embodiments, the device 700 includes a battery 718 that supplies power to various components of the device 718. By way of example only, the battery 718 is illustrated as supplying power to the processor 704. Although not illustrated in the drawings, the device 700 may include a charging circuit, for example, to recharge the battery based on an AC power supply received from an alternating current (AC) adapter.

[0120] In some embodiments, the device 700 includes a power control unit (PCU) 710 (also referred to as a power management unit (PMU), a power controller, etc.). In an example, some parts of the PCU 710 may be implemented by one or more processing cores 708, and these parts of the PCU 710 are symbolically shown using dashed boxes and are labeled as PCU 710a. In an example, some other parts of the PCU 710 may be implemented outside the processing core 708, and these parts of the PCU 710 are symbolically shown using dashed boxes and are labeled as PCU 710b. The PCU 710 may implement various power management operations for the device 700. The PCU 710 may include hardware interfaces, hardware circuits, connectors, registers, etc., as well as software components (e.g., drivers, protocol stacks) to implement various power management operations for the device 700.

[0121] In some embodiments, the device 700 includes a power management integrated circuit (PMIC) 712, so as to implement various power management operations for the device 700. In some embodiments, the PMIC 712 is a reconfigurable power management IC (RPMIC) and / or an IMVP ( Shift voltage positioning). In an example, the PMIC is in an IC chip separate from the processor 704. The PMIC can implement various power management operations for the device 700. The PMIC 712 may include hardware interfaces, hardware circuits, connectors, registers, etc., as well as software components (e.g., drivers, protocol stacks), so as to implement various power management operations for the device 700, for example.

[0122] In an example, the device 700 includes one or both of the PCU 710 or the PMIC 712. In an example, either the PCU 710 or the PMIC 712 may not be present in the device 700, and thus, these components are illustrated using dashed lines.

[0123] Various power management operations of the device 700 may be performed by the PCU 710, by the PMIC 712, or by a combination of the PCU 710 and the PMIC 712. For example, the PCU 710 and / or the PMIC 712 may select a power state (e.g., a P-state) for various components of the device 700. For example, the PCU 710 and / or the PMIC 712 may select a power state for various components of the device 700 (e.g., in accordance with the ACPI (Advanced Configuration and Power Interface) specification). By way of example only, the PCU 710 and / or the PMIC 712 may cause various components of the device 700 to transition to a sleep state, transition to an active state, transition to an appropriate C-state (e.g., a C0 state or another appropriate C-state in accordance with the ACPI specification), etc. In an example, the PCU 710 and / or the PMIC 712 may control a voltage output by the VR 714 and / or a frequency of a clock signal output by the clock generator, for example, by outputting a VID signal and / or a FID signal, respectively. For example, PCU 710 and / or PMIC 712 may control battery power usage, charging of battery 718, and features related to power saving operations.

[0124] The clock generator 716 may include a phase locked loop (PLL), a frequency locked loop (FLL), or any suitable clock source. In some embodiments, each core of the processor 704 has its own clock source. Thus, each core can operate at a frequency independent of the operating frequency of other cores. In some embodiments, the PCU 710 and / or the PMIC 712 perform adaptive or dynamic frequency scaling or adjustment. For example, if the core is not operating at its maximum power consumption threshold or limit, the clock frequency of the processor core can be increased. In some embodiments, the PCU 710 and / or the PMIC 712 determine the operating status of each core of the processor, and when it is determined that the core is operating below the target performance level, the PCU 710 and / or the PMIC 712 opportunistically adjust the frequency and / or power supply voltage of the core without losing lock on the core clock source (e.g., the PLL of the core). For example, if a core is drawing less current from a power rail than the total current allocated for the core or processor 704, the PCU 710 and / or PMIC 712 may temporarily increase the power draw of the core or processor 704 (e.g., by increasing the clock frequency and / or the power supply voltage level) so that the core or processor 704 may perform at a higher performance level. Thus, the voltage and / or frequency of the processor 704 may be temporarily increased without violating product reliability.

[0125] In an example, the PCU 710 and / or PMIC 712 may perform power management operations, for example, based at least in part on measurements received from the power measurement circuit 742, the temperature measurement circuit 740, based on the charge level of the battery 718, and / or based on any other appropriate information that may be used for power management. To this end, the PMIC 712 is communicatively coupled to one or more sensors to sense / detect various values / changes of one or more factors that have an impact on the power / thermal performance of the system / platform. Examples of the one or more factors include current, voltage drop, temperature, operating frequency, operating voltage, power consumption, inter-core communication activity, etc. One or more of these sensors may be arranged to be physically close to (and / or thermally contact / coupled with) one or more components or logic / IP blocks of the computing system. Additionally, in at least one embodiment, (one or more) sensors may be directly coupled to the PCU 710 and / or PMIC 712 to allow the PCU 710 and / or PMIC 712 to manage processor core energy based at least in part on (one or more) values ​​detected by one or more of these sensors.

[0126] Also illustrated is an example software stack for the device 700 (although not all elements of the software stack are illustrated). By way of example only, the processor 704 may execute an application 750, an operating system 752, one or more power management (PM) specific applications (e.g., collectively referred to as PM applications 758), and the like. The PM applications 758 may also be executed by the PCU 710 and / or the PMIC 712. The OS 752 may also include one or more PM applications 756a, 756b, 756c. The OS 752 may also include various drivers 754a, 754b, 754c, and the like, some of which may be specific to power management purposes. In some embodiments, the device 700 may further include a basic input / output system (BIOS) 720. The BIOS 720 may communicate with the OS 752 (e.g., via one or more drivers 754), communicate with the processor 704, and the like.

[0127] For example, one or more of the PM applications 758, 756, driver 754, BIOS 720, etc. may be used to implement power management specific tasks, such as controlling the voltage and / or frequency of various components of the device 700, controlling the wake state, sleep state, and / or any other appropriate power state of various components of the device 700, controlling battery power usage, charging of the battery 718, features related to power saving operations, and the like.

[0128] In some embodiments, the pCode (p-code) executed on the PCU 710a, 710b has the ability to implement computing and telemetry resources for the runtime support of the pCode. Here, pCode refers to firmware executed by the PCU 710a / b for managing the performance of the SoC701. For example, the pCode can set the frequency and appropriate voltage for the processor 704. For example, parts of the pCode can be accessed via the OS 752. In various embodiments, mechanisms and methods are provided to dynamically change the Energy Performance Preference (EPP) value based on workload, user behavior and / or system conditions. There may be a well-defined interface between the OS752 and the pCode. The interface may allow or facilitate software configuration of several parameters and / or may provide prompts for the pCode. As an example, the EPP parameters may inform the pCode algorithm whether performance or battery life is more important. In some embodiments, one or more energy-performance preference (EPP) parameters and / or any of various other OS hints (e.g., including OS hints for transitioning to LPS mode) are stored in registers associated with processor 704 (e.g., associated with a particular one of cores 708a, 708b, 708c), such as machine specific registers (MSRs).

[0129] This support may also be accomplished by OS 752 by including machine learning support and / or other suitable support (for example) as part of OS 752, by tuning the EPP values ​​that OS prompts to hardware (e.g., various components of SOC 701) via machine learning predictions, or by delivering machine learning predictions to pCode in a manner similar to that performed by a Dynamic Tuning Technology (DTT) driver. In this model, OS 752 may have visibility to a set of telemetry, and the same set of telemetry may be available to DTT. As a result of the DTT machine learning prompt setting, pCode may tune its internal algorithms to implement LPS mode functionality as described herein. In one such embodiment, pCode may include an algorithm for dynamic EPP that may take two inputs (one from OS 752 and the other from software such as DTT) and may selectively choose to enable or disable LPS mode functionality. As part of this approach, pCode may implement options in DTT to tune its reaction to DTT for different types of activities. Exemplary Computer Architecture

[0130] The exemplary computer architecture, instruction format, etc. supporting the above instructions are described in detail below. Other system designs and configurations known in the art for laptop computers, desktop computers, handheld personal computers (personal computers, PCs), personal digital assistants, engineering workstations, servers, decomposed servers, network devices, network hubs, switches, routers, embedded processors, digital signal processors (digital signal processors, DSPs), graphics devices, video game devices, set-top boxes, microcontrollers, cellular phones, portable media players, handheld devices, and a large variety of other electronic devices are also suitable. In short, various systems or electronic devices that can contain processors and / or other execution logic disclosed herein are generally suitable.

[0131] Figure 8 An exemplary system is illustrated. Multiprocessor system 800 is a point-to-point interconnect system and includes multiple processors, including a first processor 870 and a second processor 880 coupled via a point-to-point interconnect 850. In some examples, the first processor 870 and the second processor 880 are isomorphic. In some examples, the first processor 870 and the second processor 880 are heterogeneous. Although exemplary system 800 is shown as having two processors, the system can have three or more processors, or can be a single processor system.

[0132] Processors 870 and 880 are shown as including integrated memory controller (IMC) unit circuits 872 and 882, respectively. Processor 870 also includes point-to-point (PP) interfaces 876 and 878 as part of its interconnect controller unit; similarly, second processor 880 includes PP interfaces 886 and 888. Processors 870, 880 can exchange information via PP interconnect 850 using point-to-point (PP) interface circuits 878, 888. IMCs 872 and 882 couple processors 870, 880 to respective memories, namely memory 832 and memory 834, which can be part of the main memory locally attached to the respective processors.

[0133] Processors 870, 880 can each exchange information with chipset 890 via respective PP interconnects 852, 854 using point-to-point interface circuits 876, 894, 886, 898. Chipset 890 can optionally exchange information with coprocessor 838 via a high-performance interface 892. In some examples, coprocessor 838 is a special-purpose processor, such as a high-throughput MIC processor, a network or communication processor, a compression engine, a graphics processor, a general purpose graphics processing unit (GPGPU), a neural-network processing unit (NPU) embedded processor, and the like.

[0134] A shared cache (not shown) may be included in either processor 870, 880, or external to both processors but connected to these processors via the PP interconnect, so that if a processor is placed in a low power mode, local cache information of either or both processors may also be stored in the shared cache.

[0135] Chipset 890 can be coupled to a first interconnect 816 via interface 896. In some examples, first interconnect 816 can be a Peripheral Component Interconnect (PCI) interconnect, or an interconnect such as a PCI Express interconnect or another I / O interconnect. In some examples, one of these interconnects is coupled to a power control unit (PCU) 817, which can include circuits, software, and / or firmware to perform power management operations with respect to processors 870, 880, and / or coprocessor 838. PCU 817 provides control information to a voltage regulator (not shown) so that the voltage regulator generates an appropriate regulated voltage. PCU 817 also provides control information to control the generated operating voltage. In various examples, PCU 817 can include various power management logic units (circuits) to perform hardware-based power management. Such power management may be entirely processor controlled (e.g., controlled by various processor hardware and may be triggered by workload and / or power constraints, thermal constraints, or other processor constraints), and / or power management may be performed in response to an external source (e.g., a platform or power management source or system software).

[0136] PCU 817 is illustrated as existing as logic separate from processor 870 and / or processor 880. In other cases, PCU 817 may execute on a given one or more cores in the core (not shown) of processor 870 or 880. In some cases, PCU 817 may be implemented as a microcontroller (dedicated or general purpose) or other control logic that is configured to execute its own dedicated power management code (sometimes referred to as P-code). In yet other examples, the power management operations to be performed by PCU 817 may be implemented outside the processor, such as by a separate power management integrated circuit (PMIC) or another component external to the processor. In yet other examples, the power management operations to be performed by PCU 817 may be implemented within BIOS or other system software.

[0137] Various I / O devices 814 and a bus bridge 818 can be coupled to the first interconnect 816, and the interconnect (bus) bridge 818 couples the first interconnect 816 to the second interconnect 820. In some examples, one or more additional processors 815 are coupled to the first interconnect 816, such as a coprocessor, a high-throughput many integrated core (MIC) processor, a GPGPU, an accelerator (such as a graphics accelerator or a digital signal processing (DSP) unit), a field programmable gate array (FPGA), or any other processor. In some examples, the second interconnect 820 can be a low pin count (LPC) interconnect. Various devices can be coupled to the second interconnect 820, including, for example, a keyboard and / or mouse 822, a communication device 827, and a storage circuit 828. The storage unit circuit 828 can be one or more non-transitory machine-readable storage media as described below, such as a disk drive or other mass storage device, which in some examples may include instructions / code and data 830. In addition, audio I / O 824 can be coupled to second interconnect 820. Note that other architectures are possible in addition to the point-to-point architecture described above. For example, a system such as multiprocessor system 800 can implement a multi-drop interconnect or other such architecture instead of a point-to-point architecture. Exemplary Core Architectures, Processors, and Computer Architectures

[0138] Processor cores can be implemented in different ways, for different purposes, and in different processors. For example, implementations of these cores may include: 1) general-purpose in-order cores for general-purpose computing purposes; 2) high-performance general-purpose out-of-order cores for general-purpose computing purposes; 3) special-purpose cores, mainly for graphics and / or scientific (throughput) computing purposes. Implementations of different processors may include: 1) a CPU including one or more general-purpose in-order cores for general-purpose computing purposes and / or one or more general-purpose out-of-order cores for general-purpose computing purposes; and 2) a coprocessor including one or more special-purpose cores mainly for graphics and / or scientific (throughput) computing purposes. These different processors give rise to different computer system architectures, which may include: 1) coprocessors on separate chips from the CPU; 2) coprocessors on separate dies in the same package as the CPU; 3) coprocessors on the same die as the CPU (in which case such coprocessors are sometimes referred to as dedicated logic, such as integrated graphics and / or scientific (throughput) logic, or as dedicated cores); and 4) systems on a chip (SoCs), which may include the above-described coprocessors and additional functionality on the same die as the described CPUs (sometimes referred to as application core(s) or application processor(s). An exemplary core architecture is described next, followed by a description of exemplary processor and computer architectures.

[0139] Fig. 9 A block diagram of an example processor 900 that may have more than one core and may have an integrated memory controller is illustrated. The processor 900 illustrated by the solid line box has a single core 902A, a system agent unit circuit 910, and a set of one or more interconnect controller unit circuits 916, while the optionally added dashed line box illustrates an alternative processor 900 as having multiple cores 902A-N, a set of one or more integrated memory control unit circuits 914 in the system agent unit circuit 910, dedicated logic 908, and a set of one or more interconnect controller unit circuits 916. Note that the processor 900 may be Figure 8 One of the processors 870 or 880 or the coprocessors 838 or 815.

[0140] Thus, different implementations of processor 900 may include: 1) a CPU, where the dedicated logic 908 is integrated graphics and / or scientific (throughput) logic (which may include one or more cores, not shown), and cores 902A-N are one or more general purpose cores (e.g., general purpose in-order cores, general purpose out-of-order cores, or a combination of the two); 2) a coprocessor, where cores 902A-N are a large number of dedicated cores primarily for graphics and / or scientific (throughput) purposes; and 3) a coprocessor, where cores 902A-N are a large number of general purpose in-order cores. Thus, processor 900 may be a general purpose processor, a coprocessor, or a special purpose processor, such as a network or communication processor, a compression engine, a graphics processor, a GPGPU (general purpose graphics processing unit circuit), a high throughput many integrated core (MIC) coprocessor (including 30 or more cores), an embedded processor, etc. The processor may be implemented on one or more chips. Processor 900 may be part of one or more substrates and / or may be implemented on one or more substrates using any of a variety of process technologies, such as complementary metal oxide semiconductor (CMOS), bipolar CMOS (BiCMOS), P-type metal oxide semiconductor (PMOS), or N-type metal oxide semiconductor (NMOS).

[0141] The memory hierarchy includes one or more levels of cache unit circuits 904A-N within the cores 902A-N, a set of one or more shared cache unit circuits 906, and an external memory (not shown) coupled to the set of integrated memory controller unit circuits 914. The set of one or more shared cache unit circuits 906 may include one or more intermediate level caches, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, such as last level cache (LLC), and / or combinations thereof. While in some examples a ring-based interconnect network circuit 912 interconnects the dedicated logic 908 (e.g., integrated graphics logic), the set of (one or more) shared cache unit circuits 906, and the system agent unit circuit 910, alternative examples use any number of well-known techniques to interconnect these units. In some examples, coherency is maintained between one or more of the (one or more) shared cache unit circuits 906 and the cores 902A-N.

[0142] In some examples, one or more of the cores 902A-N have multi-threading capabilities. The system agent unit circuit 910 includes those components that coordinate and operate the cores 902A-N. The system agent unit circuit 910 may include, for example, a power control unit (PCU) circuit and / or a display unit circuit (not shown). The PCU may be (or may include) logic and components required to adjust the power state of the cores 902A-N and / or the dedicated logic 908 (e.g., integrated graphics logic). The display unit circuit is used to drive one or more externally connected displays.

[0143] The cores 902A-N may be homogeneous with respect to instruction set architecture (ISA). Alternatively, the cores 902A-N may be heterogeneous with respect to ISA software; that is, a subset of the cores 902A-N may be capable of executing one ISA, while other cores may only be capable of executing a subset of the ISA or may be capable of executing another ISA. Exemplary Core Architecture In-order and out-of-order core block diagram

[0144] Fig. 10A The block diagram of illustrates both an exemplary in-order pipeline and an exemplary register renaming, out-of-order issue / execution pipeline according to examples. Fig. 10B The block diagram illustrates both an exemplary example of an in-order architecture core and an exemplary register renaming, out-of-order issue / execution architecture core to be included in a processor, according to an example. Figure 10A-10B The solid line boxes in illustrate the in-order pipeline and in-order core, while the optionally added dashed line boxes illustrate the register renaming, out-of-order issue / execution pipeline and core. Considering that the in-order aspect is a subset of the out-of-order aspect, the out-of-order aspect will be described.

[0145] exist Fig. 10A, the processor pipeline 1000 includes a fetch stage 1002, an optional length decode stage 1004, a decode stage 1006, an optional allocation (Alloc) stage 1008, an optional rename stage 1010, a dispatch (also called dispatch or issue) stage 1012, an optional register read / memory read stage 1014, an execute stage 1016, a write back / memory write stage 1018, an optional exception handling stage 1022, and an optional commit stage 1024. One or more operations may be performed in each of these processor pipeline stages. For example, during the fetch stage 1002, one or more instructions are fetched from the instruction memory, and during the decode stage 1006, the fetched one or more instructions may be decoded, an address using a forwarding register port (e.g., a load store unit (LSU) address) may be generated, and branch forwarding (e.g., an immediate offset or a link register (LR)) may be performed. In one example, the decode stage 1006 and the register read / memory read stage 1014 may be combined into one pipeline stage. In one example, during the execution stage 1016, decoded instructions may be executed, LSU address / data pipelining to an Advanced Microcontroller Bus (AMB) interface may be performed, multiplication and addition operations may be performed, arithmetic operations with branch results may be performed, and the like.

[0146] As an example, Fig. 10B The exemplary register renaming, out-of-order issue / execution architecture core of the invention may implement the pipeline 1000 in the following manner: 1) instruction fetch circuit 1038 performs fetch and length decode stages 1002 and 1004; 2) decode circuit 1040 performs decode stage 1006; 3) rename / allocator unit circuit 1052 performs allocate stage 1008 and rename stage 1010; 4) (one or more) scheduler circuit 1056 performs schedule stage 1012; 5) (one or more) physical register file circuit 1058 and memory unit circuit 1070 perform register read / memory read stage 1014; (one or more) execution cluster 1060 performs execute stage 1016; 6) memory unit circuit 1070 and (one or more) physical register file circuit 1058 perform write back / memory write stage 1018; 7) various circuits may be involved in the exception handling stage 1022; and 8) retirement unit circuit 1054 and (one or more) physical register file circuit 1058 perform commit stage 1024.

[0147] Fig. 10BProcessor core 1090 is shown to include front end unit circuit 1030 coupled to execution engine unit circuit 1050, and both are coupled to memory unit circuit 1070. Core 1090 can be a reduced instruction set architecture computing (RISC) core, a complex instruction set architecture computing (CISC) core, a very long instruction word (VLIW) core, or a hybrid or alternative core type. As another option, core 1090 can be a special purpose core, such as a network or communication core, a compression engine, a coprocessor core, a general purpose computing graphics processing unit (GPGPU) core, a graphics core, etc.

[0148] The front end unit circuit 1030 may include a branch prediction unit circuit 1032 coupled to an instruction cache circuit 1034 coupled to an instruction translation lookaside buffer (TLB) 1036 coupled to an instruction fetch circuit 1038 coupled to a decode circuit 1040. In one example, the instruction cache circuit 1034 is included in the memory unit circuit 1070 instead of the front end circuit 1030. The decode circuit 1040 (or decoder) may decode the instruction and generate one or more micro-operations, microcode entry points, micro-instructions, other instructions, or other control signals as outputs, which are decoded from the original instruction, or otherwise reflect the original instruction, or are derived from the original instruction. The decode circuit 1040 may also include an address generation unit (AGU, not shown) circuit. In one example, the AGU uses the forwarded register port to generate the LSU address and may further perform branch forwarding (e.g., immediate offset branch forwarding, LR register branch forwarding, etc.). The decode circuit 1040 may be implemented using a variety of different mechanisms. Examples of suitable mechanisms include, but are not limited to, a lookup table, a hardware implementation, a programmable logic array (PLA), a microcode read only memory (ROM), and the like. In one example, the core 1090 includes a microcode ROM (not shown) or other medium that stores microcode for certain macroinstructions (e.g., in the decode circuit 1040 or otherwise within the front end circuit 1030). In one example, the decode circuit 1040 includes a micro-op or operation cache (not shown) to save / cache decoded operations, micro-tags, or micro-operations generated during decoding or other stages of the processor pipeline 1000. The decode circuit 1040 may be coupled to the rename / allocator unit circuit 1052 in the execution engine circuit 1050.

[0149] The execution engine circuit 1050 includes a rename / allocator unit circuit 1052 coupled to a retirement unit circuit 1054 and a set of one or more scheduler circuits 1056. The scheduler circuits 1056 represent any number of different schedulers, including reservation stations, central instruction windows, and the like. In some examples, the scheduler circuit(s) 1056 may include an arithmetic logic unit (ALU) scheduler / scheduling circuit, an ALU queue, an address generation unit (AGU) scheduler / scheduling circuit, an AGU queue, and the like. The scheduler circuit(s) 1056 are coupled to physical register file(s) circuit(s) 1058. Each of the physical register file(s) circuit(s) 1058 represents one or more physical register files, different ones of which store one or more different data types, such as scalar integers, scalar floating points, packed integers, packed floating points, vector integers, vector floating points, status (e.g., instruction pointers, i.e., the address of the next instruction to be executed), and the like. In one example, the (one or more) physical register file circuits 1058 include vector register unit circuits, write mask register unit circuits, and scalar register unit circuits. These register units can provide architectural vector registers, vector mask registers, general registers, etc. The (one or more) physical register file circuits 1058 are coupled to the retirement unit circuit 1054 (also called the retirement queue) to demonstrate various ways that register renaming and out-of-order execution can be implemented (e.g., using (one or more) reorder buffers (ROB) and (one or more) retirement register files; using (one or more) future stacks, (one or more) history buffers, and (one or more) retirement register files; using register maps and pools of registers; etc.). The retirement unit circuit 1054 and the (one or more) physical register file circuits 1058 are coupled to (one or more) execution clusters 1060. The (one or more) execution clusters 1060 include a set of one or more execution unit circuits 1062 and a set of one or more memory access circuits 1064. The execution unit circuit(s) 1062 may perform various arithmetic, logical, floating point, or other types of operations (e.g., shifts, additions, subtractions, multiplications) on various types of data (e.g., scalar integer, scalar floating point, packed integer, packed floating point, vector integer, vector floating point). While some examples may include several execution units or execution unit circuits dedicated to a particular function or set of functions, other examples may include only one execution unit circuit or multiple execution units / execution unit circuits that all perform all functions.Scheduler circuit(s) 1056, physical register file circuit(s) 1058, and execution cluster(s) 1060 are shown as possibly multiple because some examples create separate pipelines for certain types of data / operations (e.g., scalar integer pipelines, scalar floating point / packed integer / packed floating point / vector integer / vector floating point pipelines, and / or memory access pipelines, each with its own scheduler circuit(s), physical register file circuit(s), and / or execution cluster—and in the case of a separate memory access pipeline, only the execution cluster of that pipeline has memory access unit circuit(s) 1064 in some examples of the implementation). It should also be understood that where separate pipelines are used, one or more of these pipelines may be out-of-order issue / execution, while the rest are in-order.

[0150] In some examples, execution engine unit circuit 1050 may perform load store unit (LSU) address / data pipelining to an advanced microcontroller bus (AMB) interface (not shown), as well as address stage and writeback, data stage loads, stores, and branches.

[0151] A set of memory access circuits 1064 are coupled to the memory cell circuit 1070, which includes a data TLB circuit 1072, which is coupled to a data cache circuit 1074, which is coupled to a level 2 (L2) cache circuit 1076. In one illustrative example, the memory access circuit 1064 may include a load unit circuit, a storage address unit circuit, and a storage data unit circuit, each of which is coupled to the data TLB circuit 1072 in the memory cell circuit 1070. The instruction cache circuit 1034 is further coupled to the level 2 (L2) cache unit circuit 1076 in the memory cell circuit 1070. In one example, the instruction cache 1034 and the data cache 1074 are combined into a single instruction and data cache in the L2 cache circuit 1076, a level 3 (L3) cache circuit (not shown), and / or a main memory (not shown). The L2 cache circuit 1076 is coupled to one or more other levels of cache and ultimately to the main memory.

[0152] Core 1090 may support one or more instruction sets (e.g., x86 instruction set architecture (optionally with some extensions that have been added with newer versions); MIPS instruction set architecture; ARM instruction set architecture (optionally with optional additional extensions, such as NEON)) that include the instruction(s) described herein. In one example, core 1090 includes logic to support packed data instruction set architecture extensions (e.g., AVX1, AVX2), allowing operations used by many multimedia applications to be performed using packed data. Exemplary Execution Unit Circuit(s)

[0153] Fig.11 An example of (one or more) execution unit circuits such as (one or more) execution unit circuits 1062 of 10B is illustrated. As shown, (one or more) execution unit circuits 1062 may include one or more ALU circuits 1101, optional vector / single instruction multiple data (single instruction multiple data, SIMD) circuits 1103, load / store circuits 1105, branch / jump circuits 1107, and / or floating-point unit (FPU) circuits 1109. ALU circuits 1101 perform integer arithmetic and / or Boolean operations. Vector / SIMD circuits 1103 perform vector / SIMD operations on compressed data (e.g., SIMD / vector registers). Load / store circuits 1105 execute load and store instructions to load data from memory into registers, or store data from registers to memory. Load / store circuits 1105 may also generate addresses. Branch / jump circuits 1107 cause branches or jumps to a certain memory address depending on the instruction. FPU circuits 1109 perform floating-point arithmetic. The width of the execution unit circuit(s) 1062 varies depending on the example, and may range from 16 bits to 1024 bits, for example. In some examples, two or more smaller execution units are logically combined to form a larger execution unit (e.g., two 128-bit execution units are logically combined to form a 256-bit execution unit). Exemplary Register Architecture

[0154] Fig.12 1 is a block diagram of a register architecture 1200 according to some examples. As shown, the register architecture includes a vector / SIMD register 1210, whose width varies from 128 bits to 1024 bits. In some examples, the vector / SIMD register 1210 is physically 512 bits, and only some low-order bits are used depending on the mapping. For example, in some examples, the vector / SIMD register 1210 is a 512-bit ZMM register: the low-order 256 bits are used for the YMM register, and the low-order 128 bits are used for the XMM register. Therefore, there is an overlay of registers. In some examples, the vector length field selects between the maximum length and one or more other shorter lengths, wherein each such shorter length is half the length of the previous length. Scalar operations are operations performed on the lowest-order data element position in the ZMM / YMM / XMM register; higher-order data element positions are either maintained as the same as before the instruction, or are zeroed, depending on the example.

[0155] In some examples, the register architecture 1200 includes a write mask / predicate register 1215. For example, in some examples, there are 8 write mask / predicate registers (sometimes referred to as k0 to k7), each of which is 16 bits, 32 bits, 64 bits, or 128 bits in size. The write mask / predicate register 1215 can allow merging (e.g., allowing any set of elements in the destination to be protected from update during the execution of any operation) and / or zeroing (e.g., a zeroing vector mask allows any set of elements in the destination to be zeroed during the execution of any operation). In some examples, each data element position in a given write mask / predicate register 1215 corresponds to a data element position in the destination. In other examples, the write mask / predicate register 1215 is scalable and consists of a set number of enable bits for a given vector element (e.g., 8 enable bits for each 64-bit vector element).

[0156] The register architecture 1200 includes a plurality of general purpose registers 1225. These registers may be 16 bits, 32 bits, 64 bits, etc., and may be used for scalar operations. In some examples, these registers are referred to by the names RAX, RBX, RCX, RDX, RBP, RSI, RDI, RSP, and R8 to R15.

[0157] In some examples, register architecture 1200 includes scalar floating-point (FP) registers 1245, which are used to perform scalar floating-point operations on 32 / 64 / 80-bit floating-point data using x87 instruction set architecture extensions, or as MMX registers to perform operations on 64-bit packed integer data, and to store operands for some operations performed between MMX and XMM registers.

[0158] One or more flag registers 1240 (e.g., EFLAGS, RFLAGS, etc.) store status and control information for arithmetic, comparison, and system operations. For example, one or more flag registers 1240 can store condition code information, such as carry, parity, auxiliary carry, zero, sign, and overflow. In some examples, one or more flag registers 1240 are referred to as program status and control registers.

[0159] Segment registers 1220 contain segment points for accessing memory. In some examples, these registers are referred to by the names CS, DS, SS, ES, FS, and GS.

[0160] Machine-specific registers (MSRs) 1235 control and report processor performance. Most MSRs 1235 handle system-related functions and are not accessible to applications. Machine check registers 1260 consist of control, status, and error reporting MSRs used to detect and report hardware errors.

[0161] One or more instruction pointer registers 1230 store instruction pointer values. Control register(s) 1255 (e.g., CR0-CR4) determine the operating mode of the processor (e.g., processor 870, 880, 838, 818, and / or 900) and the characteristics of the task currently being executed. Debug registers 1250 control and allow monitoring of debug operations of the processor or core.

[0162] Memory (mem) management registers 1265 specify the location of data structures used in protected mode memory management. These registers may include the GDTR, IDTR, task register, and LDTR registers.

[0163] Alternative examples may use wider or narrower registers. In addition, alternative examples may use more, fewer, or different register files and registers. The register architecture 1200 may be used, for example, in (one or more) physical register file unit circuits 1058. Instruction Set Architecture

[0164] An instruction set architecture (ISA) may include one or more instruction formats. A given instruction format may define various fields (e.g., the number of bits, the position of the bits) to specify the operation to be performed (e.g., opcode) and the (one or more) operands and / or other (one or more) data fields (e.g., mask) on which the operation is to be performed, etc. Some instruction formats are further decomposed by the definition of instruction templates (or subformats). For example, an instruction template of a given instruction format may be defined as having different subsets of the fields of the instruction format (the included fields are usually in the same order, but at least some have different bit positions because there are fewer included fields) and / or defined as having a given field interpreted in a different manner. Thus, each instruction of the ISA is expressed using a given instruction format (and, if defined, expressed in a given instruction template in the instruction format), and includes fields for specifying the operation and the operand. For example, the exemplary ADD instruction has a specific opcode and instruction format, the instruction format includes an opcode field to specify the opcode, and includes an operand field to select the operand (source 1 / destination and source 2); and the appearance of this ADD instruction in the instruction stream will have specific content in the operand field to select the specific operand. In addition, although the following description is performed in the context of the x86 ISA, it is also within the knowledge of those skilled in the art to apply the teachings of the present disclosure to another ISA. Example instruction format

[0165] The examples of the (one or more) instructions described herein may be implemented in different formats. In addition, exemplary systems, architectures, and pipelines are described in detail below. The examples of (one or more) instructions may be executed on these systems, architectures, and pipelines, but are not limited to those described in detail.

[0166] Fig.13 An example of an instruction format is illustrated. As shown, an instruction may include multiple components, including, but not limited to, one or more fields for: one or more prefixes 1301, an opcode 1303, addressing information 1305 (e.g., a register identifier, memory addressing information, etc.), a displacement value 1307, and / or an immediate value 1309. Note that some instructions utilize some or all of the fields of the format, while other instructions may only use the opcode 1303 field. In some examples, the illustrated order is the order in which the fields are to be encoded, however, it should be understood that in other examples, the fields may be encoded in another order, combined, etc.

[0167] (One or more) prefix fields 1301 modify the instruction when used. In some examples, one or more prefixes are used to repeat string instructions (e.g., 0xF0, 0xF2, 0xF3, etc.), provide section override (e.g., 0x2E, 0x36, 0x3E, 0x26, 0x64, 0x65, 0x2E, 0x3E, etc.), perform bus lock operations, and / or change operation objects (e.g., 0x66) and address sizes (e.g., 0x67). Some instructions require mandatory prefixes (e.g., 0x66, 0xF2, 0xF3, etc.). Some of these prefixes can be considered as "traditional" prefixes. Other prefixes (one or more examples of which are described in detail herein) indicate and / or provide further capabilities, such as specifying specific registers, etc. These other prefixes are usually followed by the "traditional" prefix.

[0168] The opcode field 1303 is used to at least partially define the operation to be performed when the instruction is decoded. In some examples, the length of the primary opcode encoded in the opcode field 1303 is one, two or three bytes. In other examples, the primary opcode can be other lengths. The additional 3-bit opcode field is sometimes encoded in another field.

[0169] The addressing field 1305 is used to address one or more operands of the instruction, such as a location in memory or one or more registers. Fig.14 An example of an addressing field 1305 is illustrated. In this illustration, an optional MOD R / M byte 1402 and an optional scale, index, base (SIB) byte 1404 are shown. The MOD R / M byte 1402 and SIB byte 1404 are used to encode up to two operands of the instruction, each operand being a direct register or an effective memory address. Note that each of these fields is optional, i.e., not all instructions include one or more of these fields. The MOD R / M byte 1402 includes a MOD field 1442, a register (reg) field 1444, and an R / M field 1446.

[0170] The content of MOD field 1442 distinguishes between memory access and non-memory access modes. In some examples, when MOD field 1442 has a binary value of 11 (11b), register direct addressing mode is utilized, otherwise register indirect addressing is used.

[0171] Register field 1444 may encode a destination register operand or a source register operand, or may encode an opcode extension and not be used to encode any instruction operand. The contents of register index field 1444 specify the location (in a register or in memory) of the source or destination operand directly or through address generation. In some examples, register field 1444 is supplemented with additional bits from a prefix (e.g., prefix 1301) to allow for greater addressing.

[0172] R / M field 1446 may be used to encode an instruction operand that references a memory address, or may be used to encode a destination register operand or a source register operand. Note that in some examples, R / M field 1446 may be combined with MOD field 1442 to specify an addressing mode.

[0173] SIB byte 1404 includes a scale field 1452, an index field 1454, and a base address field 1456 for address generation. Scaling field 1452 indicates a scaling factor. Index field 1454 specifies the index register to be used. In some examples, index field 1454 is complemented with additional bits from a prefix (e.g., prefix 1301) to allow for larger addressing. Base address field 1456 specifies the base address register to be used. In some examples, base address field 1456 is complemented with additional bits from a prefix (e.g., prefix 1301) to allow for larger addressing. In practice, the contents of scale field 1452 allow the contents of index field 1454 to be scaled for memory address generation (e.g., for memory addresses using 2 缩放 * address generation of index + base address).

[0174] Some addressing forms use displacement values ​​to generate memory addresses. For example, 缩放 *index+base+displacement, index*scale+displacement, r / m+displacement, instruction pointer (RIP / EIP)+displacement, register+displacement, etc. to generate a memory address. The displacement can be a value of 1 byte, 2 bytes, 4 bytes, etc. In some examples, displacement 1307 provides this value. In addition, in some examples, the use of a displacement factor is encoded in the MOD field of addressing field 1305, which indicates a compressed displacement scheme for which the displacement value is calculated and stored in displacement field 1307.

[0175] In some examples, the immediate value field 1309 specifies an immediate value for the instruction. The immediate value may be encoded as a 1-byte value, a 2-byte value, a 4-byte value, and so on.

[0176] Fig.15An example of a first prefix 1301(A) is illustrated. In some examples, the first prefix 1301(A) is an example of a REX prefix. Instructions using this prefix can specify general registers, 64-bit packed data registers (e.g., single instruction multiple data (SIMD) registers or vector registers), and / or control registers and debug registers (e.g., CR8-CR15 and DR8-DR15).

[0177] Instructions using the first prefix 1301(A) can specify up to three registers using a 3-bit field, depending on the format: 1) using the reg field 1444 and the R / M field 1446 of the MOD R / M byte 1402; 2) using the MOD R / M byte 1402 with the SIB byte 1404, including using the reg field 1444 as well as the base field 1456 and the index field 1454; or 3) using the register field of the opcode.

[0178] In the first prefix 1301 (A), bit positions 7:4 are set to 0100. Bit position 3 (W) can be used to determine the operand size, but cannot determine the operand width alone. Therefore, when W=0, the operand size is determined by the code segment descriptor (CS.D), and when W=1, the operand size is 64 bits.

[0179] Note that adding another bit allows for 16 (2 4 ) registers, while the separate MOD R / M reg field 1444 and the R / M field 1446 of MOD R / M can only address 8 registers each.

[0180] In the first prefix 1301(A), bit position 2 (R) may be an extension of the MOD R / M reg field 1444 and may be used to modify the MOD R / M reg field 1444 when the field encodes a general register, a 64-bit packed data register (e.g., an SSE register), or a control or debug register. When the MOD R / M byte 1402 specifies another register or defines an extended opcode, R is ignored.

[0181] Bit position 1 (X) may modify the SIB byte index field 1454 .

[0182] Bit position 0 (B) may modify the base address in R / M field 1446 or SIB byte base address field 1456 of MOD R / M; or it may modify the opcode register field used to access a general register (eg, general register 1225).

[0183] Figures 16A-16DAn example of how the R, X, and B fields of the first prefix 1301 (A) are used is illustrated. Fig.16A It is illustrated that when the SIB byte 1404 is not used for memory addressing, the R and B from the first prefix 1301 (A) are used to extend the reg field 1444 and the R / M field 1446 of the MOD R / M byte 1402. Fig. 16B It is illustrated that when the SIB byte 1404 is not used, the R and B from the first prefix 1301 (A) are used to extend the reg field 1444 and the R / M field 1446 of the MOD R / M byte 1402 (register-register addressing). Fig. 16C It is illustrated that when the SIB byte 1404 is used for memory addressing, R, X, and B from the first prefix 1301 (A) are used to extend the reg field 1444 of the MOD R / M byte 1402 as well as the index field 1454 and the base address field 1456. Fig.16D It is illustrated that when a register is encoded in the opcode 1303 , the B from the first prefix 1301 (A) is used to extend the reg field 1444 of the MOD R / M byte 1402 .

[0184] Figure 17A-17B An example of a second prefix 1301(B) is illustrated. In some examples, the second prefix 1301(B) is an example of a VEX prefix. The second prefix 1301(B) encoding allows instructions to have more than two operands and allows SIMD vector registers (e.g., vector / SIMD registers 1210) to be longer than 64 bits (e.g., 128 bits and 256 bits). The use of the second prefix 1301(B) provides a syntax for three operands (or more). For example, a previous two-operand instruction performs an operation such as A=A+B, which overwrites the source operand. The use of the second prefix 1301(B) enables the operands to perform non-destructive operations, such as A=B+C.

[0185] In some examples, the second prefix 1301(B) has two forms - a two-byte form and a three-byte form. The two-byte second prefix 1301(B) is mainly used for 128-bit, scalar and some 256-bit instructions; while the three-byte second prefix 1301(B) provides a compact replacement for 3-byte opcode instructions and the first prefix 1301(A).

[0186] Fig.17AAn example of a two-byte form of a second prefix 1301 (B) is illustrated. In one example, the format field 1701 (byte 0 1703) contains a value of C5H. In one example, byte 1 1705 includes an "R" value in bit [7]. This value is the complement of the "R" value of the first prefix 1301 (A). Bit [2] is used to specify the length (L) of the vector (wherein the value of 0 is a scalar or 128-bit vector, and the value of 1 is a 256-bit vector). Bit [1:0] provides an opcode extensibility equivalent to some traditional prefixes (e.g., 00=no prefix, 01=66H, 10=F3H, and 11=F2H). Bits [6:3], shown as vvvv, can be used to: 1) encode a first source register operand, which is specified in inverted (complement) form and is valid for instructions with 2 or more source operands; 2) encode a destination register operand, which is specified in complement form for certain vector shifts; or 3) not encode any operand, the field is reserved and should contain a value, such as 1111b.

[0187] Instructions using this prefix may use the R / M field 1446 of MOD R / M to encode an instruction operand that references a memory address, or to encode a destination register operand or a source register operand.

[0188] Instructions using this prefix may use the reg field 1444 of MOD R / M to encode either a destination register operand or a source register operand, treated as an opcode extension and not used to encode any instruction operand.

[0189] For instruction syntax supporting four operands, vvvv, the R / M field 1446 of MOD R / M, and the reg field 1444 of MOD R / M encode three of the four operands. Bits [7:4] of immediate 1309 are then used to encode the third source register operand.

[0190] Fig. 17B An example of a three-byte form of the second prefix 1301 (B) is illustrated. In one example, the format field 1711 (byte 0 1713) contains the value C4H. Byte 1 1715 includes "R", "X" and "B" in bits [7:5], which are the complements of these values ​​of the first prefix 1301 (A). Bits [4:0] (shown as mmmm) of byte 1 1715 include content that encodes one or more implicit leading opcode bytes as needed. For example, 00001 means 0FH leading opcode, 00010 means 0F38H leading opcode, 00011 means 0F3AH leading opcode, and so on.

[0191] The use of bit [7] of byte 2 1717 is similar to W of the first prefix 1301 (A), including helping to determine the size of the operand that can be promoted. Bit [2] is used to specify the length (L) of the vector (where a value of 0 is a scalar or 128-bit vector, and a value of 1 is a 256-bit vector). Bits [1:0] provide opcode extensibility equivalent to some traditional prefixes (e.g., 00=no prefix, 01=66H, 10=F3H, and 11=F2H). Bits [6:3], shown as vvvv, can be used to: 1) encode the first source register operand, which is specified in inverted (inverse) form, valid for instructions with 2 or more source operands; 2) encode the destination register operand, which is specified in inverse form for certain vector shifts; or 3) do not encode any operand, this field is reserved and should contain a value, such as 1111b.

[0192] Instructions using this prefix may use the R / M field 1446 of MOD R / M to encode an instruction operand that references a memory address, or to encode a destination register operand or a source register operand.

[0193] Instructions using this prefix may use the reg field 1444 of MOD R / M to encode a destination register operand or a source register operand, or be treated as an opcode extension and not used to encode any instruction operand.

[0194] For instruction syntax supporting four operands, vvvv, the R / M field 1446 of MOD R / M, and the reg field 1444 of MOD R / M encode three of the four operands. Bits [7:4] of immediate 1309 are then used to encode the third source register operand.

[0195] Fig.18 An example of a third prefix 1301(C) is illustrated. In some examples, the third prefix 1301(C) is an example of an EVEX prefix. The third prefix 1301(C) is a four-byte prefix.

[0196] The third prefix 1301 (C) can encode 32 vector registers (e.g., 128-bit, 256-bit, and 512-bit registers) in 64-bit mode. In some examples, write masks / operation masks are used (see the discussion of registers in previous figures, e.g. Fig.12 ) or predicate instructions utilize this prefix. The operation mask register allows conditional processing or selection control. Operation mask instructions whose source / destination operands are operation mask registers and treat the contents of the operation mask register as a single value are encoded using the second prefix 1301 (B).

[0197] The third prefix 1301(C) may encode functionality specific to the instruction class (e.g., a packed instruction with “load+operation” semantics may support an embedded broadcast functionality, a floating-point instruction with rounding semantics may support a static rounding functionality, a floating-point instruction with non-rounding arithmetic semantics may support a “suppress all exceptions” functionality, etc.).

[0198] The first byte of the third prefix 1301 (C) is the format field 1811, which in one example has a value of 62 H. The subsequent bytes are called payload bytes 1815-1819, and together form a 24-bit value of P[23:0], providing specific capabilities in the form of one or more fields (described in detail herein).

[0199] In some examples, P[1:0] of payload byte 1819 is the same as the two mm bits in the lower order. In some examples, P[3:2] is reserved. Bit P[4] (R') allows access to the upper 16 vector register sets when combined with P[7] and the reg field 1444 of MOD R / M. When SIB type addressing is not required, P[6] can also provide access to the upper 16 vector registers. P[7:5] consists of R, X, and B, which are operand specifier modifier bits for vector registers, general registers, and memory addressing, and when combined with the MOD R / M register field 1444 and the R / M field 1446 of MOD R / M, access to the next set of 8 registers beyond the lower 8 registers is allowed. P[9:8] provides opcode extensibility equivalent to some traditional prefixes (e.g., 00=no prefix, 01=66H, 10=F3H, and 11=F2H). P

[10] is a fixed value of 1 in some examples. P[14:11], shown as vvvv, can be used to: 1) encode a first source register operand, which is specified in inverted (complement) form, valid for instructions with 2 or more source operands; 2) encode a destination register operand, which is specified in complement form, used for certain vector shifts; or 3) not encode any operand, the field is reserved and should contain a value, such as 1111b.

[0200] P

[15] is similar to W of the first prefix 1301(A) and the second prefix 1301(B), and can be used as an opcode extension bit or an operand size increase.

[0201] P[18:16] specifies the index of a register in the operation mask (write mask) register (e.g., write mask / predicate register 1215). In one example, the particular value aaa=000 has special behavior, implying that no operation mask is used for this particular instruction (this can be implemented in a variety of ways, including using an operation mask hardwired to all ones or hardware that bypasses the masking hardware). When merging, the vector mask allows any set of elements in the destination to be protected from update during the execution of any operation (specified by the basic operation and the enhanced operation); in another example, the old value of each element of the destination is retained (if the corresponding mask bit has a value of 0). In contrast, when zeroing, the vector mask allows any set of elements in the destination to be zeroed during the execution of any operation (specified by the basic operation and the enhanced operation); in one example, the elements of the destination are set to 0 when the corresponding mask bit has a value of 0. A subset of this functionality is the ability to control the vector length of the operation being performed (i.e., the span of elements modified, from first to last); however, the elements modified do not have to be consecutive. Thus, the operation mask field enables a subset of vector operations, including loads, stores, arithmetic, logical, etc. Although in the described examples, the contents of the operation mask field select which of several operation mask registers contains the operation mask to be used (so that the contents of the operation mask field indirectly identify the masking to be performed), alternative examples alternatively or additionally allow the contents of the mask write field to directly specify the masking to be performed.

[0202] P

[19] can be combined with P[14:11] to encode a second source vector register in a non-destructive source syntax that can utilize P

[19] to access the upper 16 vector registers. P

[20] encodes various features that vary in different classes of instructions and can affect the meaning of the vector length / rounding control specifier field (P[22:21]). P

[23] indicates support for merge-write masking (e.g., when set to 0) or support for zeroing and merge-write masking (e.g., when set to 1).

[0203] The following table details illustrative examples of encoding of registers in instructions using the third prefix 1301 (C). Table 1: 32-register support in 64-bit mode Table 2: Encoding register specifiers in 32-bit mode Table 3: Operation Mask Register Specifier Encoding

[0204] Program code can be applied to input information to perform the functions described herein and generate output information. Output information can be applied to one or more output devices in a known manner. For the present application, processing system includes any system with a processor, such as a digital signal processor (DSP), a microcontroller, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a microprocessor or any combination of the above.

[0205] Program code can be implemented in a process-oriented or object-oriented high-level programming language to communicate with the processing system. If desired, program code can also be implemented in assembly or machine language. In fact, the mechanism described herein is not limited to any specific programming language in scope. In any case, the language can be a compiled language or an interpreted language.

[0206] Examples of the mechanisms disclosed herein can be implemented in hardware, software, firmware, or a combination of these implementation approaches. Examples can be implemented as computer programs or program codes, executed on a programmable system including at least one processor, a storage system (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device.

[0207] One or more aspects of at least one example may be implemented by representative instructions stored on a machine-readable medium, which represent various logic within a processor, which, when read by a machine, causes the machine to fabricate logic for performing the techniques described herein. These representations, known as "IP cores," may be stored on a tangible machine-readable medium and provided to various customers or manufacturing facilities to be loaded into a fabrication machine that actually fabricates the logic or processor.

[0208] These machine-readable storage media may include, but are not limited to, non-transitory tangible arrangements of items manufactured or formed by a machine or device, including storage media such as: hard disks, any other type of disk (including floppy disks, optical disks, compact disk read-only memory (CD-ROM), compact disk rewritable (CD-RW), and magneto-optical disks), semiconductor devices (e.g., read-only memory (ROM), random access memory (RAM) such as dynamic random access memory (DRAM), static random access memory (SRAM), erasable programmable read-only memory (EPROM), flash memory, electrically erasable programmable read-only memory (EEPROM), phase change memory (PCM)), magnetic cards or optical cards, or any other type of medium suitable for storing electronic instructions.

[0209] Therefore, examples also include non-transitory tangible machine-readable media containing instructions or design data, such as hardware description languages ​​(HDL), that define the structures, circuits, devices, processors and / or system features described herein. Such examples may also be referred to as program products. Emulation (including binary translation, code deformation, etc.)

[0210] In some cases, the instruction converter can be used to convert instructions from a source instruction set architecture to a target instruction set architecture. For example, the instruction converter can translate (e.g., using static binary translation, dynamic binary translation including dynamic compilation), deform, simulate or otherwise convert instructions to one or more other instructions to be processed by the core. The instruction converter can be implemented with software, hardware, firmware or a combination thereof. The instruction converter can be on the processor, outside the processor, or partly on the processor and partly outside the processor.

[0211] Fig.19The block diagram of using a software instruction converter to convert binary instructions in a source instruction set architecture into binary instructions in a target instruction set architecture according to the comparison of examples is illustrated. In the illustrated example, the instruction converter is a software instruction converter, but alternatively, the instruction converter can be implemented in software, firmware, hardware, or various combinations thereof. Fig.19 A program in a high-level language 1902 is shown to be compiled using a first ISA compiler 1904 to generate first ISA binary code 1906 that can be natively executed by a processor 1916 having at least one first ISA instruction set architecture core. The processor 1916 having at least one first ISA instruction set architecture core represents any processor that is capable of executing or otherwise processing (1) a substantial portion of the instruction set architecture of the first ISA instruction set architecture core or (2) executing a program in a first ISA instruction set architecture core having at least one first ISA instruction set architecture core. The first ISA compiler 1904 represents a compiler operable to generate first ISA binary code 1906 (e.g., object code) that can be executed on a processor 1916 having at least one first ISA instruction set architecture core with or without additional linking processing. Similarly, Fig.19 It is shown that a program in a high-level language 1902 can be compiled using an alternative instruction set architecture compiler 1908 to generate an alternative instruction set architecture binary code 1910, which can be natively executed by a processor 1914 without a first ISA instruction set architecture core. An instruction converter 1912 is used to convert the first ISA binary code 1906 into code that can be natively executed by a processor 1914 without a first ISA instruction set architecture core. This converted code is not necessarily the same as the alternative instruction set architecture binary code 1910; however, the converted code will implement the overall operation and be composed of instructions from the alternative instruction set architecture. Thus, the instruction converter 1912 represents software, firmware, hardware, or a combination thereof that allows a processor or other electronic device without a first ISA instruction set architecture processor or core to execute the first ISA binary code 1906 through simulation, emulation, or any other process.

[0212] In one or more first embodiments, a device includes a first circuit and a second circuit, the first circuit being configured to: receive a first indication of a first thermal condition of a platform including a processor; and based on the first indication, transition power management of the processor to a restricted power state (LPS) mode, wherein two or more power states of the processor are allowed during the LPS mode, and one or more other power states of the processor are blocked during the LPS mode; the second circuit being configured to: monitor one or more software processes executed using the processor; and based on detection of a workload of the first or more software processes, signal the first circuit to transition the processor between two or more power states, during the LPS mode, wherein the first circuit is further configured to: receive a second indication of a second thermal condition of the platform; and based on the second indication, transition the processor from the LPS mode, wherein the first circuit is configured to enable availability of one or more other power states.

[0213] In one or more second embodiments, further to the first embodiment, the thermal condition is based on a surface temperature of a housing structure in which the processor is disposed.

[0214] In one or more third embodiments, further to the second embodiment, the thermal condition is an average surface temperature of the housing structure.

[0215] In one or more fourth embodiments, further to the second embodiment, the thermal condition is based on an integral of the surface temperature over time.

[0216] In one or more fourth embodiments, further to the second embodiment, the thermal condition is based on a rate of change of surface temperature.

[0217] In one or more sixth embodiments, further to the first embodiment or the second embodiment, the one or more other power states include a first power state that is a high power state relative to each of the two or more power states.

[0218] In one or more seventh embodiments, further for the first embodiment or the second embodiment, the two or more power states include a first power state and a second power state, wherein the first power state is a low power state relative to the second power state, the first circuit is used to transition the processor from the first power state to the second power state based on detection of the workload, and the first circuit is further used to transition the processor from the second power state to the first power state based on completion of the workload.

[0219] In one or more eighth embodiments, further for the first embodiment or the second embodiment, the first circuit causes the power management of the processor to transition to the LPS mode, including the first circuit transitioning from a first state machine to a second state machine, the first state machine facilitating the transition of the processor between any power states in a first plurality of power states, the second state machine facilitating the transition of the processor between any power states in a second plurality of power states, and the total number of the first plurality of power states is greater than the total number of the second plurality of power states.

[0220] In one or more ninth embodiments, further to the eighth embodiment, the second plurality of power states is a subset of the first plurality of power states.

[0221] In one or more tenth embodiments, a method includes: receiving a first indication of a first thermal condition of a platform including a processor; transitioning power management of the processor to a restricted power state (LPS) mode based on the first indication, wherein two or more power states of the processor are allowed during the LPS mode, and one or more other power states of the processor are blocked during the LPS mode; during the LPS mode, performing the following operations: monitoring one or more software processes executed using the processor; transitioning the processor between two or more power states based on detection of a workload of the first or more software processes; receiving a second indication of a second thermal condition of the platform; and transitioning power management of the processor from the LPS mode based on the second indication, including enabling availability of one or more other power states.

[0222] In one or more eleventh embodiments, further to the tenth embodiment, the thermal condition is based on a surface temperature of a housing structure in which the processor is disposed.

[0223] In one or more twelfth embodiments, further to the eleventh embodiment, the thermal condition is an average surface temperature of the housing structure.

[0224] In one or more thirteenth embodiments, further to the eleventh embodiment, the thermal condition is based on an integral of a surface temperature over time.

[0225] In one or more fourteenth embodiments, further to the eleventh embodiment, the thermal condition is based on a rate of change of a surface temperature.

[0226] In one or more fifteenth embodiments, further to the tenth embodiment or the eleventh embodiment, the one or more other power states include a first power state that is a high power state relative to each of the two or more power states.

[0227] In one or more sixteenth embodiments, further for the tenth embodiment or the eleventh embodiment, the two or more power states include a first power state and a second power state, wherein the first power state is a low power state relative to the second power state, the processor is transitioned from the first power state to the second power state based on detection of a workload, and the method further includes transitioning the processor from the second power state to the first power state based on completion of the workload.

[0228] In one or more seventeenth embodiments, further for the tenth embodiment or the eleventh embodiment, transitioning the power management of the processor to the LPS mode includes transitioning from providing power management using a first state machine to providing power management using a second state machine, wherein the first state machine facilitates transitions of the processor between any power states in a first plurality of power states, the second state machine facilitates transitions of the processor between any power states in a second plurality of power states, and the total number of the first plurality of power states is greater than the total number of the second plurality of power states.

[0229] In one or more eighteenth embodiments, further to the seventeenth embodiment, the second plurality of power states is a subset of the first plurality of power states.

[0230] In one or more nineteenth embodiments, a system includes: one or more sensors, the one or more sensors being used to generate a first indication of a first thermal condition of the system; a first circuit, the first circuit being used to receive the first indication and further being used to transition power management of a processor of the system to a restricted power state (LPS) mode based on the first indication, wherein two or more power states of the processor are allowed during the LPS mode, and one or more other power states of the processor are blocked during the LPS mode; and a second circuit, the second circuit being used to monitor one or more software processes executed using the processor during the LPS mode, and further being used to signal the first circuit to transition the processor between two or more power states based on detection of a workload of the one or more software processes; wherein the first circuit is further used to: receive a second indication of a second thermal condition of the system; and transition the processor from the LPS mode based on the second indication, wherein the first circuit is used to enable availability of one or more other power states.

[0231] In one or more twentieth embodiments, further with respect to the nineteenth embodiment, the thermal condition is based on a surface temperature of a housing structure in which the processor is disposed.

[0232] In one or more twenty-first embodiments, further with respect to the twentieth embodiment, the thermal condition is an average surface temperature of the housing structure.

[0233] In one or more twenty-second embodiments, further to the twentieth embodiment, the thermal condition is based on an integral of a surface temperature over time.

[0234] In one or more twenty-third embodiments, further to the twentieth embodiment, the thermal condition is based on a rate of change of surface temperature.

[0235] In one or more twenty-fourth embodiments, further for the nineteenth embodiment or the twentieth embodiment, the one or more other power states include a first power state that is a high power state relative to each of the two or more power states.

[0236] In one or more twenty-fifth embodiments, further for the nineteenth embodiment or the twentieth embodiment, the two or more power states include a first power state and a second power state, wherein the first power state is a low power state relative to the second power state, the first circuit is used to transition the processor from the first power state to the second power state based on detection of the workload, and the first circuit is further used to transition the processor from the second power state to the first power state based on completion of the workload.

[0237] In one or more twenty-sixth embodiments, further for the nineteenth embodiment or the twentieth embodiment, the first circuit causes the power management of the processor to transition to the LPS mode, including the first circuit transitioning from a first state machine to a second state machine, the first state machine facilitating the transition of the processor between any power states in a first plurality of power states, the second state machine facilitating the transition of the processor between any power states in a second plurality of power states, and the total number of the first plurality of power states is greater than the total number of the second plurality of power states.

[0238] In one or more twenty-seventh embodiments, further to the twenty-sixth embodiment, the second plurality of power states is a subset of the first plurality of power states.

[0239] References to "one example," "an example," etc. indicate that the example being described may include a particular feature, structure, or characteristic, but not every example may necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same example. In addition, when a particular feature, structure, or characteristic is described in conjunction with an example, it is considered to be within the knowledge of those skilled in the art to affect such feature, structure, or characteristic in conjunction with other examples, whether or not explicitly described.

[0240] Moreover, in the examples described above, unless specifically noted otherwise, separating language such as phrases "at least one of A, B, or C" or "A, B and / or C" are intended to be understood to mean A, B, or C, or any combination thereof (i.e., A and B, A and C, B and C, and A, B and C).

[0241] Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the disclosure as set forth in the claims.

Claims

1. A device for determining a power state, the device comprising: A first circuit, wherein the first circuit is configured to: receiving a first indication of a first thermal condition of a platform including a processor; as well as causing power management of the processor to transition to a restricted power state (LPS) mode based on the first indication, wherein two or more power states of the processor are allowed during the LPS mode and one or more other power states of the processor are prevented during the LPS mode; and a second circuit, the second circuit being configured during the LPS mode to: monitoring one or more software processes executed by the processor; and signaling the first circuit to cause the processor to transition between the two or more power states based on detecting a workload of the first one or more software processes; Wherein, the first circuit is further used for: receiving a second indication of a second thermal condition of the platform; and The processor is caused to transition from the LPS mode based on the second indication, wherein the first circuit is configured to enable availability of the one or more other power states.

2. The device according to claim 1, wherein: The thermal condition is based on a surface temperature of a housing structure in which the processor is disposed.

3. The device of claim 2, wherein: The thermal condition is an average surface temperature of the housing structure.

4. The device of claim 2, wherein: The thermal condition is based on an integral of the surface temperature over time.

5. The device of claim 2, wherein: The thermal condition is based on a rate of change of the surface temperature.

6. The apparatus of claim 1 or claim 2, wherein: The one or more other power states include a first power state that is a high power state relative to each of the two or more power states.

7. The apparatus of claim 1 or claim 2, wherein: The two or more power states include a first power state and a second power state, wherein the first power state is a lower power state relative to the second power state; The first circuit is configured to cause the processor to transition from the first power state to the second power state based on detection of the workload; and The first circuit is further configured to cause the processor to transition from the second power state to the first power state based on completion of the workload.

8. The apparatus of claim 1 or claim 2, wherein: The first circuit causing the power management of the processor to transition to the LPS mode includes the first circuit transitioning from a first state machine to a second state machine; the first state machine facilitating transitions of the processor between any power states of a first plurality of power states; the second state machine facilitates transitions of the processor between any power states in a second plurality of power states; and A total number of the first plurality of power states is greater than a total number of the second plurality of power states.

9. The device of claim 8, wherein: The second plurality of power states is a subset of the first plurality of power states.

10. A method for determining a power state, the method comprising: receiving a first indication of a first thermal condition of a platform including a processor; The power management of the processor is changed to a limited power state (LPS) mode based on the first indication, wherein: Two or more power states of the processor are enabled during the LPS mode; and one or more other power states of the processor are prevented during the LPS mode; During the LPS mode: monitoring one or more software processes executed using the processor; causing the processor to transition between the two or more power states based on detecting a workload of the first one or more software processes; receiving a second indication of a second thermal condition of the platform; The power management of the processor is caused to transition from the LPS mode based on the second indication, the power management of the processor being caused to transition from the LPS mode comprising enabling availability of the one or more other power states.

11. The method of claim 10, wherein: The thermal condition is based on a surface temperature of a housing structure in which the processor is disposed.

12. The method of claim 11, wherein: The thermal condition is an average surface temperature of the housing structure.

13. The method of claim 11, wherein: The thermal condition is based on an integral of the surface temperature over time.

14. The method of claim 11, wherein: The thermal condition is based on a rate of change of the surface temperature.

15. The method of claim 10 or claim 11, wherein: The one or more other power states include a first power state that is a high power state relative to each of the two or more power states.

16. The method of claim 10 or claim 11, wherein: The two or more power states include a first power state and a second power state, wherein the first power state is a lower power state relative to the second power state; The processor is transitioned from the first power state to the second power state based on detection of the workload; and The method further includes transitioning the processor from the second power state to the first power state based on completion of the workload.

17. The method of claim 10 or claim 11, wherein: Transitioning the power management of the processor to the LPS mode includes: transitioning from providing the power management using a first state machine to providing the power management using a second state machine; the first state machine facilitating transitions of the processor between any power states of a first plurality of power states; the second state machine facilitates transitions of the processor between any power states in a second plurality of power states; and A total number of the first plurality of power states is greater than a total number of the second plurality of power states.

18. The method of claim 17, wherein: The second plurality of power states is a subset of the first plurality of power states.

19. A system for determining a power state, the system comprising: one or more sensors for generating a first indication of a first thermal condition of the system; a first circuit configured to receive the first indication and to cause power management of a processor of the system to transition to a limited power state (LPS) mode based on the first indication, wherein two or more power states of the processor are allowed during the LPS mode and one or more other power states of the processor are prevented during the LPS mode; and second circuitry for monitoring one or more software processes executed with the processor during the LPS mode and further for signaling the first circuitry to transition the processor between the two or more power states based on detection of a workload of the one or more software processes; Wherein, the first circuit is further used for: receiving a second indication of a second thermal condition of the system; and The processor is caused to transition from the LPS mode based on the second indication, wherein the first circuit is configured to enable availability of the one or more other power states.

20. The system of claim 19, wherein: The thermal condition is based on a surface temperature of a housing structure in which the processor is disposed.

21. The system of claim 20, wherein: The thermal condition is an average surface temperature of the housing structure.

22. The system of claim 20, wherein: The thermal condition is based on an integral of the surface temperature over time.

23. The system of claim 20, wherein: The thermal condition is based on a rate of change of the surface temperature.

24. The system of claim 19 or claim 20, wherein: The one or more other power states include a first power state that is a high power state relative to each of the two or more power states.

25. The system of claim 19 or claim 20, wherein: The two or more power states include a first power state and a second power state, wherein the first power state is a lower power state relative to the second power state; The first circuit is configured to cause the processor to transition from the first power state to the second power state based on detection of the workload; and The first circuit is further configured to cause the processor to transition from the second power state to the first power state based on completion of the workload.

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