System and method for realizing FPGA online upgrading based on BPI interface logic

Abstract

The invention relates to a system and method for achieving FPGA online upgrading based on BPI interface logic, and belongs to the technical field of computers. The FPGA online upgrading system and the FPGA online upgrading method are designed based on high parallelism of the BPI aiming at an application scene that the FPGA needs remote online upgrading, and the FPGA online upgrading system with better performance can be realized.

Description

Technical Field

[0001] The present invention belongs to the field of computer technology, and in particular relates to a system and method for implementing FPGA online upgrade based on BPI interface logic. Background Art

[0002] With the continuous development of electronic technology, logic devices such as CPLD and FPGA have been more widely used in the computer field. CPLD can not only control the power-on timing of the computer CPU, peripheral reset, etc., but also expand low-speed interfaces such as computer serial ports, IIC interfaces, and general IO ports. FPGA implements high-speed interfaces such as PCIe interfaces and SRIO interfaces, thereby realizing high-speed data communication between the CPU and the outside. Due to the parallel design of FPGA, FPGA can also realize algorithm acceleration and improve algorithm performance in the computer field.

[0003] The more widely CPLD and FPGA are used in the computer field, the more diverse their application scenarios are. There is an application scenario where maintenance personnel cannot get close to the equipment during operation, or it is inconvenient to get close to it. In this case, the firmware of CPLD and FPGA cannot be upgraded on-site and needs to be upgraded online. The online upgrade of firmware varies depending on the type of firmware selected, and there are mainly two types: SPI interface and BPI interface. Summary of the invention

[0004] 1. Technical issues to be resolved

[0005] The technical problem to be solved by the present invention is: how to realize efficient FPGA online upgrade.

[0006] (II) Technical solution

[0007] In order to solve the above technical problems, the present invention provides a method for realizing online upgrade of FPGA based on BPI interface logic. The method is realized based on four parts: local controller, remote controller, FPGA and BPI Flash. The local controller and the remote controller are connected through an Ethernet interface to realize data interaction between the two. The remote controller and the FPGA communicate through a data communication interface. The FPGA and the BPI Flash are connected through a BPI interface, and the BPI interface can transmit control signals, data signals and address signals.

[0008] In FPGA, the BPI interface logic is implemented by four parts: BPI scheduling module, BPI read control module, BPI erase control module and BPI write control module; among them, the BPI scheduling module implements the BPI interface logic scheduling function, the BPI read control module implements the BPI Flash read function, the BPI erase control module implements the BPI Flash erase function, and the BPI write control module implements the BPIFlash write function;

[0009] The BPI scheduling module parses the data frames sent by the data communication interface. The data frames include two types, namely control command frames and data frames. The control command types include erase control commands, write data control commands and read data control commands. The content of the data frame is the data to be written into the BPI Flash. When the BPI scheduling module parses the control command frame as an erase control command, the BPI erase control module is called to implement the BPI Flash erase function. After parsing the control command frame as a write data control command, the BPI write control module is called to implement the BPI Flash write function. After parsing the control command frame as a read data control command, the BPI read control module is called to implement the BPI Flash read function.

[0010] The present invention also provides a system for implementing the method.

[0011] The invention also provides an application of the method in the field of computer technology.

[0012] The invention also provides an application of the system in the field of computer technology.

[0013] (III) Beneficial effects

[0014] Aiming at the application scenario where FPGA needs to be remotely online upgraded, the present invention designs an FPGA online upgrade system and method based on the high parallelism of the BPI interface, and can realize an FPGA online upgrade system with better performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is the principle diagram of the FPGA online upgrade system of the present invention;

[0016] Figure 2 It is a block diagram of the BPI interface logic implementation of the present invention;

[0017] Figure 3 The BPI interface logic erases Flash flow chart of the present invention;

[0018] Figure 4 Programming Flash flow chart for BPI interface logic of the present invention;

[0019] Figure 5This is the BPI interface logic Flash reading flow chart of the present invention. DETAILED DESCRIPTION

[0020] In order to make the purpose, content and advantages of the present invention more clear, the specific implementation methods of the present invention are further described in detail below in conjunction with the drawings and examples.

[0021] Design of BPI interface FPGA online upgrade solution

[0022] There are two main types of FPGA firmware, SPI Flash and BPI Flash, both of which are widely used in FPGA logic design. The main difference between BPI Flash and SPI Flash is that BPI Flash has higher parallelism and faster configuration speed. The present invention provides a system and method for implementing FPGA online upgrade based on BPI interface logic, and relates to the application of BPI interface in FPGA online upgrade.

[0023] The FPGA online upgrade system mainly consists of four parts: local controller, remote controller, FPGA, and BPI Flash. Figure 1 As shown in the figure, both the local controller and the remote controller are mainly implemented by CPU, DSP, ARM, MCU, etc. The local controller and the remote controller are connected through the Ethernet interface to realize data interaction between the two. The data communication interface between the remote controller and the FPGA can be realized through the PCIe high-speed interface, or through the serial port, IIC interface and other low-speed interfaces. The interface between the FPGA and the BPI Flash is the BPI interface. The BPI interface mainly transmits control signals, data signals and address signals.

[0024] BPI interface logic design

[0025] The BPI interface logic is implemented in FPGA, which is specifically implemented by four parts, namely BPI scheduling module, BPI read control module, BPI erase control module and BPI write control module. Figure 2 The BPI scheduling module implements the BPI interface logic scheduling function, the BPI read control module implements the BPI Flash read function, the BPI erase control module implements the BPI Flash erase function, and the BPI write control module implements the BPI Flash write function.

[0026] The BPI scheduling module parses the data frames sent by the data communication interface. The data frames mainly include two types, namely control command frames and data frames. The control command types include erase control commands, write data control commands and read data control commands. The content of the data frame is the data to be written into the BPI Flash. When the BPI scheduling module parses the control command frame as an erase control command, it calls the BPI erase control module to implement the BPI Flash erase function. When the control command frame is parsed as a write data control command, it calls the BPI write control module to implement the BPI Flash write function. When the control command frame is parsed as a read data control command, it calls the BPI read control module to implement the BPI Flash read function.

[0027] The following describes the FPGA online upgrade and BPI interface logic workflow by taking the CPU as the local controller and the remote controller (i.e., the local controller is the local CPU controller and the remote controller is the remote CPU controller) and the PCIe interface as the data communication interface. The FPGA online upgrade mainly includes three processes: erasing, programming, and verification.

[0028] The online upgrade of FPGA first requires erasing the BPI Flash. The local CPU controller issues an erase control command and sends it to the remote CPU controller through the Ethernet interface. After the remote CPU controller receives the erase control command, it sends it to the FPGA through the PCIe interface. The FPGA internally forwards the erase control command to the BPI scheduling module. After receiving the erase control command, the BPI scheduling module calls the BPI erase control module to perform the entire chip erase. After the entire chip is erased, the BPI scheduling module calls the BPI read control module to determine whether the content in the BPI Flash is all F. If not, it erases it again and determines the data in the BPI Flash. If the content in the BPI Flash is all F, the erase work is completed. The BPI scheduling module feeds back the completion information to the remote CPU controller through the PCIe interface. The remote CPU controller then sends the completion information to the local CPU controller through the Ethernet interface, and the BPI Flash erase work is now completed. The BPI interface logic Flash erase process is as follows: Figure 3 shown.

[0029] Then, the BPI Flash write function is needed to implement BPI Flash programming (i.e., programming BPI Flash). Programming BPI Flash mainly involves writing the FPGA loading file with new functions into BPI Flash, so that the FPGA can run the new function when it is powered on again. The local CPU controller issues a write data control command and sends it to the remote CPU controller through the Ethernet interface; after the remote CPU controller receives the write data control command, it sends it to the FPGA through the PCIe interface, and the FPGA forwards the write data control command to the BPI scheduling module; after receiving the write data control command, the BPI scheduling module calls the BPI write control module and feeds back write waiting information to the remote CPU controller through the PCIe interface. After receiving the write waiting information, the remote CPU controller transmits the write waiting information to the local CPU controller through the Ethernet interface. After receiving the write waiting information, the local CPU controller sends the data of the FPGA loading file to the remote CPU controller through the Ethernet interface. The remote CPU controller sends the data to the FPGA through the PCIe interface, and the FPGA forwards the data to the BPI scheduling module and the BPI write control module, and the BPI write control module writes the data into the BPI Flash. After all data is written, the BPI scheduling module feeds back the write completion information to the remote CPU controller through the PCIe interface. The remote CPU controller sends the write completion information to the local CPU controller through the Ethernet interface to complete the BPI Flash write function. Figure 4 shown.

[0030] Finally, the BPI Flash needs to be verified through the BPI Flash read function. To verify the BPI Flash, the data written to BPIFlash is read out to the local CPU controller and compared with the data written to BPI Flash. If the read data is exactly the same as the written data, the FPGA online upgrade is completed, otherwise the data is rewritten to BPI Flash. The specific process is as follows: the local CPU controller issues a read data control command and sends it to the remote CPU controller through the Ethernet interface; after the remote CPU controller receives the read data control command, it sends it to the FPGA through the PCIe interface, and the FPGA forwards the read data control command to the BPI scheduling module; after receiving the read data control command, the BPI scheduling module calls the BPI read control module, and then the BPI read control module starts to read the data in the BPI Flash, and the FPGA transmits the read data to the remote CPU controller through the PCIe interface, and the remote CPU controller transmits the data to the local CPU controller through the Ethernet interface. After the local CPU controller receives the data, it stores it; after waiting for all the data to be read, the BPI scheduling module sends a read completion message to the remote CPU controller through the PCIe interface via the FPGA, and the remote CPU controller sends the read completion message to the local CPU controller through the Ethernet interface; after receiving the read completion message, the local CPU controller performs a data comparison. If the comparison fails, the BPI Flash is erased and the BPI Flash is programmed again until the comparison is successful. After the comparison is successful, the FPGA online upgrade is completed. The BPI interface logic read Flash process is as follows Figure 5 shown.

[0031] It can be seen that the present invention uses the CPU as the controller and takes the PCIe interface as an example of the data communication interface between the remote controller and the FPGA to illustrate the online upgrade of the FPGA, and focuses on describing the implementation of the BPI interface logic. In actual design, the controller can use DSP, ARM, MCU, etc. as a replacement, and the data communication interface between the remote controller and the FPGA can use a low-speed interface such as a serial port and an IIC interface. The BPI interface logic is mainly implemented by a BPI scheduling module, a BPI read control module, a BPI erase control module, and a BPI write control module. The BPI interface logic is mainly used to implement erasing, reading and writing BPI Flash chips.

[0032] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A method for implementing FPGA online upgrade based on BPI interface logic, characterized in that: The method is implemented based on four parts: local controller, remote controller, FPGA and BPIFlash. The local controller and the remote controller are connected through an Ethernet interface to realize data interaction between the two. The remote controller and the FPGA communicate through a data communication interface. The FPGA and the BPIFlash are connected through a BPI interface, which can transmit control signals, data signals and address signals. In FPGA, the BPI interface logic is implemented by four parts: BPI scheduling module, BPI read control module, BPI erase control module and BPI write control module; among them, the BPI scheduling module implements the BPI interface logic scheduling function, the BPI read control module implements the BPIFlash read function, the BPI erase control module implements the BPIFlash erase function, and the BPI write control module implements the BPIFlash write function; The BPI scheduling module parses the data frames sent by the data communication interface. The data frames include two types, namely control command frames and data frames. The control command types include erase control commands, write data control commands and read data control commands. The content of the data frame is the data to be written into BPIFlash. When the BPI scheduling module parses the control command frame as an erase control command, the BPI erase control module is called to implement the BPIFlash erase function. After parsing the control command frame as a write data control command, the BPI write control module is called to implement the BPIFlash write function. After parsing the control command frame as a read data control command, the BPI read control module is called to implement the BPIFlash read function.

2. The method according to claim 1, characterized in that Both the local controller and the remote controller are implemented by CPU, DSP, ARM or MCU.

3. The method according to claim 2, characterized in that The data communication interface between the remote controller and the FPGA is implemented through a PCIe interface, a serial port or an IIC interface.

4. The method according to claim 3, characterized in that Assume that both the local controller and the remote controller are implemented by CPU, that is, the local controller is a local CPU controller, the remote controller is a remote CPU controller, and the data communication interface is a PCIe interface. Then, the FPGA online upgrade includes three processes, namely, erasing, programming, and verification. The specific implementation process is as follows: The FPGA online upgrade first needs to erase BPIFlash. The local CPU controller issues an erase control command and sends it to the remote CPU controller through the Ethernet interface. After receiving the erase control command, the remote CPU controller sends it to the BPI scheduling module of the FPGA through the PCIe interface. After receiving the erase control command, the BPI scheduling module calls the BPI erase control module to perform the whole chip erase work. After the whole chip is erased, the BPI scheduling module calls the BPI read control module to determine whether the content in the BPI Flash is all F. If not, it will re-erase and determine the data in the BPI Flash; if the content in the BPIFlash is all F, the erase work is completed, and the BPI scheduling module will feedback the completion information to the remote CPU controller through the PCIe interface. The remote CPU controller then sends the completion information to the local CPU controller through the Ethernet interface, and the BPI Flash erase work is completed; Then, the BPI Flash is programmed through the BPI Flash write function. Programming the BPI Flash is to write the FPGA loading file with the new function into the BPI Flash, so that the FPGA can run the new function when it is powered on again. Finally, BPIFlash is verified through the BPIFlash read function. Verifying BPIFlash is to read the data written into BPIFlash to the local CPU controller and compare it with the data written into BPIFlash. If the read data is exactly the same as the written data, the FPGA online upgrade is completed, otherwise the data is rewritten into BPIFlash.

5. The method according to claim 4, characterized in that The implementation process of programming BPIFlash is as follows: the local CPU controller issues a write data control command and sends it to the remote CPU controller through the Ethernet interface; after receiving the write data control command, the remote CPU controller sends it to the FPGA through the PCIe interface, and the FPGA forwards the write data control command to the BPI scheduling module; After receiving the write data control command, the BPI scheduling module calls the BPI write control module and feeds back the write waiting information to the remote CPU controller through the PCIe interface. After receiving the write waiting information, the remote CPU controller transmits the write waiting information to the local CPU controller through the Ethernet interface. After receiving the write waiting information, the local CPU controller sends the data of the FPGA loading file to the remote CPU controller through the Ethernet interface. The remote CPU controller sends the data to the BPI scheduling module and the BPI write control module in the FPGA through the PCIe interface. The BPI write control module writes the data into BPIFlash. After waiting for all data to be written, the BPI scheduling module feeds back the write completion information to the remote CPU controller through the PCIe interface, and the remote CPU controller sends the write completion information to the local CPU controller through the Ethernet interface to complete the BPIFlash write function.

6. The method according to claim 5, characterized in that The specific process of verifying BPIFlash is as follows: the local CPU controller issues a read data control command and sends it to the remote CPU controller through the Ethernet interface; after receiving the read data control command, the remote CPU controller sends it to the BPI scheduling module in the FPGA through the PCIe interface; After receiving the read data control command, the BPI scheduling module calls the BPI read control module, and then the BPI read control module starts to read the data in BPIFlash. The FPGA transmits the read data to the remote CPU controller through the PCIe interface, and the remote CPU controller transmits the data to the local CPU controller through the Ethernet interface. The local CPU controller stores the data after receiving it. After waiting for all the data to be read, the BPI scheduling module sends the read completion information to the remote CPU controller through the PCIe interface via the FPGA, and the remote CPU controller sends the read completion information to the local CPU controller through the Ethernet interface. After receiving the read completion information, the local CPU controller performs data comparison. If the comparison fails, the BPIFlash is erased and the BPIFlash is programmed again until the comparison is successful. After the comparison is successful, the FPGA online upgrade is completed.

7. A system for implementing the method according to any one of claims 1 to 6.

8. The system according to claim 7, characterized in that The system includes a local controller, a remote controller, FPGA, and BPIFlash.

9. Application of the method according to any one of claims 1 to 6 in the field of computer technology.

10. An application of the system according to claim 8 in the field of computer technology.

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