Circuitry and method for implementing one or more KECCAK instructions

Abstract

Circuitry and methods for implementing one or more Keccak permutation instructions are described. In some examples, a hardware processor includes decoder circuitry to decode a first instruction to a decoded first instruction, the first instruction including a first word storing a Keccak state value according to the SHA3 standard, a second register to first, second, and third registers to store a word of the Keccak state value, and a third register to store a word of the Keccak state value according to the SHA3 standard. The opcode is used to indicate vector execution circuitry comprising a plurality of channels to perform a column parity operation of a theta step of a Keccak permutation according to the SHA3 standard using only a single channel of the plurality of channels to determine a calculated parity value for an input of a word for a Keccak state value, and storing the calculated parity value in the unused high word of the first register; and vector execution circuitry to execute the decoded first instruction according to the opcode.

Description

Background Art

[0001] A processor or a collection of processors executes instructions from an instruction set (e.g., an instruction set architecture (ISA)). An instruction set is the programming-related portion of a computer architecture and generally includes native data types, instructions, register architecture, addressing modes, memory architecture, interrupt and exception handling, and external input and output (I / O). It should be noted that the term instruction may refer to macroinstructions or microinstructions herein, such as instructions provided to a processor for execution, or microinstructions such as instructions decoded by a processor's decoder from macroinstructions. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] Various examples according to the present disclosure will be described with reference to the accompanying drawings, in which:

[0003] Figure 1 A block diagram of a hardware processor including data registers having multiple lanes coupled to corresponding execution circuits of vector execution circuitry is illustrated according to examples of the present disclosure.

[0004] Figure 2 is a simplified flow chart of operations implemented with Keccak permutation according to the SHA-3 standard according to an example of the present disclosure.

[0005] Figure 3A is a block diagram illustrating a state representation of the SHA-3 standard according to examples of the present disclosure.

[0006] Figure 3B is a block diagram illustrating an initial state representation of the SHA-3 standard according to examples of the present disclosure, where each row is stored within three (eg, XMM) registers.

[0007] Figure 4 Illustrated is an example of computing hardware for processing Keccak instruction(s) according to examples of the present disclosure.

[0008] Figure 5 An example method executed by a processor to process a Keccak theta (Θ) step instruction according to examples of the present disclosure is illustrated.

[0009] Figure 6 An example method of processing a Keccak theta (Θ) step instruction using emulation or binary translation according to examples of the present disclosure is illustrated.

[0010] Figure 7An example method executed by a processor to process Keccak theta (Θ) step and rho (ρ) step instructions that update multiple elements (eg, words) according to examples of the present disclosure is illustrated.

[0011] Figure 8 An example method for processing Keccak theta (Θ) step and rho (ρ) step instructions that update multiple elements (eg, words) using emulation or binary translation is illustrated according to examples of the present disclosure.

[0012] Fig. 9 An example method executed by a processor to process Keccak theta (Θ) step and rho (ρ) step instructions that update a single element (eg, a single word) according to an example of the present disclosure is illustrated.

[0013] Fig.10 An example method for processing Keccak theta (Θ) step and rho (ρ) step instructions that update a single element (eg, a single word) using emulation or binary translation is illustrated according to examples of the present disclosure.

[0014] Fig.11A is a block diagram illustrating the positions of elements (eg, words) in a set of (eg, XMM) registers prior to the pi (π) step of a Keccak permutation of a SHA-3 calculation according to an example of the present disclosure.

[0015] Fig. 11B is a block diagram illustrating the positions of elements (eg, words) in a set of (eg, XMM) registers after the pi (π) step of a Keccak permutation of a SHA-3 calculation according to an example of the present disclosure.

[0016] Fig.12 An example method executed by a processor to process a pi (π) step instruction according to examples of the present disclosure is illustrated.

[0017] Fig.13 An example method of processing a pi (π) step instruction using emulation or binary translation according to examples of the present disclosure is illustrated.

[0018] Fig.14 An example method executed by a processor to process a chi(χ) step instruction according to an example of the present disclosure is illustrated.

[0019] Fig.15 An example method of processing a chi(χ) step instruction using emulation or binary translation according to an example of the present disclosure is illustrated.

[0020] Fig.16 An example computing system is illustrated.

[0021] Fig.17 A block diagram illustrating an example processor and / or System on a Chip (SoC) that may have one or more cores and an integrated memory controller.

[0022] Fig.18 is a block diagram illustrating a computing system 1800 configured to implement one or more aspects of the examples described herein.

[0023] Fig.19A Figure 1 shows an example of a parallel processor.

[0024] Fig.19B An example of a block diagram of a partition unit is illustrated.

[0025] Fig.19C An example of a block diagram illustrating a processing cluster within a parallel processing unit.

[0026] Fig.19D An example of a graphics multiprocessor is illustrated, wherein the graphics multiprocessor is coupled with a pipeline manager of a processing cluster.

[0027] Figure 20A-20C Additional graphics multiprocessors are illustrated according to examples.

[0028] Fig.21 A parallel computing system 2100 is shown according to some examples.

[0029] Figure 22A-22B Illustrate a hybrid logical / physical view of a decomposed parallel processor according to examples described herein.

[0030] Fig.23A is a block diagram illustrating both an example in-order pipeline and an example register renaming, out-of-order issue / execution pipeline according to an example.

[0031] Fig. 23B is a block diagram illustrating both an example in-order architecture core and an example register renaming, out-of-order issue / execution architecture core to be included in a processor according to an example.

[0032] Fig.24 Examples of execution unit circuitry, such as execution unit circuitry, are illustrated.

[0033] Fig.25 is a block diagram of a register architecture according to some examples.

[0034] Fig.26 An example of the instruction format is shown.

[0035] Fig. 27 Figure 1 shows an example of an addressing information field.

[0036] Fig.28 An example of the first prefix is ​​illustrated.

[0037] Figure 29A-Figure 29D An example of how the R, X, and B fields of the first prefix are used is illustrated.

[0038] Figure 30A-Figure 30B An example of the second prefix is ​​shown in the figure.

[0039] Fig.31 An example of the third prefix is ​​shown in FIG.

[0040] Figure 32A-32B Thread execution logic including an array of processing elements employed in a graphics processor core is illustrated according to examples described herein.

[0041] Fig.33 Additional execution units are illustrated according to an example.

[0042] Fig.34 is a block diagram illustrating a graphics processor instruction format 3400 according to some examples.

[0039] Fig.35 is a block diagram of another example of a graphics processor.

[0044] Fig.36A is a block diagram illustrating a graphics processor command format according to some examples.

[0045] Fig.36B is a block diagram illustrating a graphics processor command sequence according to an example.

[0046] Fig.37 is a block diagram illustrating converting binary instructions in a source ISA to binary instructions in a target ISA using a software instruction converter according to an example.

[0047] Fig.38 is a block diagram illustrating an IP core development system 3800 that may be used to fabricate an integrated circuit to perform operations according to some examples. DETAILED DESCRIPTION

[0048] The present disclosure relates to methods, apparatus, systems, and non-transitory computer-readable storage media for Keccak instructions. According to some examples herein, one or more Keccak instructions are used to enhance the performance of a processor when implementing Keccak, for example, by limiting Keccak execution to those instructions within a single lane of a multi-lane circuitry (e.g., AVX2 vector circuitry) (e.g., as part of an instruction set architecture (ISA)).

[0049] The Secure Hash Algorithm (SHA), currently the latest version is SHA-3 or SHA3, is a NIST standard with a wide range of applications. SHA-3 (or its variants) is used as a component of many candidates for future Post-Quantum Cryptography (PQC) standards, such as Crystals-Kyber for Key Encapsulation Mechanism (KEM) and CrystalsDilithium and Falcon for Digital Signatures (DS). Therefore, communication protocols (e.g., TLS, MACSec, and / or IPSec) will be upgraded with PQC schemes to protect against quantum attacks. Some examples of SHA3 utilize the Keccak algorithm (e.g., Keccak permutations) as part of the standard. An example Keccak permutation of an element (e.g., a word) of a Keccak state value is Figure 2 If such a PQC scheme is based on SHA3 (eg, according to a Keccak permutation of SHA3), a large percentage of the computation time is spent on SHA3 (eg, according to a Keccak permutation of SHA3).

[0050] To address these and other issues, provided herein are new instructions for accelerating the internal sub-operations involved in SHA3 / Keccak round functions. These instructions are based on a single channel using multi-channel (e.g., AVX2) registers, multi-channel data paths, and / or multi-channel execution circuits to accelerate the execution of complex bit manipulations and byte (e.g., 64-bit "word" elements) reordering of (e.g., 1600-bit) Keccak states (e.g., Keccak state values).

[0051] In some examples, the SHA3 single-pass parity instruction (with the mnemonic SHA3-SL-PAR) accelerates the (e.g., 64-bit) parity calculation of the theta (Θ) step of a Keccak permutation. In some examples, the SHA3 single-pass theta (Θ) step XOR rotate instruction (with the mnemonic SHA3-SL-TXR1) accelerates certain of the theta (Θ) and rho (ρ) steps of a Keccak permutation of multiple updated words for generating a Keccak state value. In some examples, the SHA3 single-pass theta (Θ) step XOR rotate instruction (with the mnemonic SHA3-SL-TXR2) accelerates certain of the theta (Θ) and rho (ρ) steps of a Keccak permutation of a single updated word for generating a Keccak state value. In some examples, the SHA3 single-pass pi (π) step instruction (with the mnemonic SHA3-SL-PI) accelerates the pi (π) step of a Keccak permutation. In some examples, the SHA3 single-pass chi(χ) step instruction (with the mnemonic SHA3-SL-CHI) accelerates the chi(χ) step of the Keccak permutation.

[0052] The instructions disclosed herein are improvements to the operation of the processor (e.g., of a computer) itself, as the instructions implement the above functions by electrically altering a general-purpose computer (e.g., decoder circuitry and / or execution circuitry of a general-purpose computer) by creating electrical pathways within the computer (e.g., within the decoder circuitry and / or execution circuitry of the computer). These electrical pathways create a special-purpose machine for performing specific functions.

[0053] The instructions disclosed herein are improvements to the operation of a processor (e.g., of a computer) itself. Instruction decoding circuitry (e.g., decoder circuitry 102 and / or decoder circuitry 405) that does not have such instructions as part of its instruction set will not decode as discussed herein. Execution circuitry (e.g., vector execution circuitry 116 and / or vector execution circuitry 409) that does not have such instructions as part of its instruction set will not execute as discussed herein. For example, Keccak instructions according to the present disclosure are improvements to the operation of a processor (e.g., of a computer) itself because these Keccak instructions speed up internal sub-operations involved in the SHA3 / Keccak round function.

[0054] Some processors (e.g., those implementing AVX2 or other vector extensions) have multiple (e.g., two) channels, each of which has 128 bits, for example. In some examples, data access from one channel to another channel takes multiple cycles, which causes a longer latency for implementing Keccak instructions that utilize cross-channel access (e.g., input and / or output across channels). As a technical solution to this technical problem, some examples herein involve accelerating the execution of complex bit manipulation and element (e.g., "word") reordering of (e.g., 1600 bits) Keccak states using only a single channel of multi-channel (e.g., AVX2) registers, multi-channel data paths, and / or multi-path execution circuits. In some embodiments, the single-channel Keccak instruction herein has a single latency cycle, which is contrasted with, for example, cross-channel Keccak instructions that have more (e.g., 3 or more cycles) latency due to (one or more) cross-channel accesses. Accelerating Keccak execution on (e.g., general-purpose) processor cores improves the performance of PQC schemes to implement secure communication protocols (e.g., TLS). In some examples, execution of a Keccak instruction permuted by Keccak1600 within a single lane of a multi-lane (e.g., AVX2) datapath enables it to perform better by using lower latency (e.g., 1 cycle) instructions than cross-lane techniques utilizing longer latency (e.g., 3 or more cycles) instructions. Additionally, the single-lane Keccak instruction disclosed herein allows for parallel execution of multiple (e.g., 2) Keccak (e.g., Keccak1600) permutations on corresponding (e.g., two) lanes of a multi-lane (e.g., AVX2) register, a multi-lane datapath, and / or a multi-lane execution circuit.

[0055] Now turning to the attached figure, Figure 1A block diagram of a hardware processor 100 (e.g., a core) according to an example of the present disclosure is illustrated, the hardware processor 100 (e.g., a core) including a data register 112 having multiple lanes (e.g., an upper lane 112U and a lower lane 112L) coupled to corresponding execution circuits (e.g., upper execution circuits 120U and lower execution circuits 120L, respectively) of a vector execution (e.g., single instruction multiple data (SIMD)) circuit system 116. The depicted hardware processor 100 includes a hardware decoder circuit system 102 (e.g., a decode unit) and a hardware execution circuit system 104 (e.g., (one or more) execution units). The depicted hardware processor 100 includes registers 106. In some examples, registers 106 include (one or more) control registers 110, e.g., to control the Keccak functionality discussed herein. In some examples, registers 106 include register renaming circuit system 124, e.g., to control the register renaming functionality discussed herein (e.g., to implement Keccak).

[0056] In some examples, registers 106 include (one or more) multi-channel (e.g., packed data or vector) data registers 112 for accessing (e.g., loading and / or storing) data in registers 106, e.g., in addition to or instead of accessing (e.g., loading or storing) data in another storage device (e.g., cache 108 and / or system memory). Cache 108 may include one or more cache banks for accessing (e.g., loading and / or storing) data in cache 108, e.g., in addition to or instead of accessing (e.g., loading or storing) data in registers 106 or other storage devices.

[0057] In some examples, data registers 112 include multiple channels (e.g., high channel 112U and low channel 112L) that are coupled to corresponding execution circuits (e.g., high execution circuit 120U and low execution circuit 120L, respectively) of vector execution (e.g., single instruction multiple data (SIMD)) circuit system 116. In some examples, data registers include an "N" number of registers, shown as R 0 to R N-1 In some examples, the entire register has a first width (e.g., 256 bits wide), and each channel has a smaller second width (e.g., 128 bits wide). In some examples, the first channel is referred to as the upper channel 112U (e.g., the leftmost), and the second channel is referred to as the lower channel 112L (e.g., the rightmost). In some examples, the entire width of a multi-channel register is indicated by the first subscript of the register index (e.g., for the first register R0 Register index 0 for the second register R 1 Register index 1, and so on until the last register R N-1 In some examples, for example, in x86 verbiage, the entire register is, for example, a YMM register having 256 bits, and each channel is 128 bits wide (for example, where the element (e.g., word) width is 64 bits, each channel stores two elements, and each register stores four elements). In some examples, data registers 112 are YMM registers, for example, registers YMM0 to YMM15. In some examples, each of the YMM registers is 256 bits wide. In some examples, the lower 128 bits of YMM register 112 are aliased to a corresponding 128-bit XMM register. In some embodiments, registers YMM0-YMM15 are constructed from two 128-bit channels. In some examples, the lower 128-bit channel 112L (bits 0 to 127) corresponds to an XMM register. In some examples, the lower 128-bit channel 112L (bits 0 to 127) and the upper 128-bit channel 112U (bits 128 to 255) correspond to YMM registers.

[0058] In some examples, the upper portion of the register is indicated by the second subscript of the channel index (e.g., for the first register R 0 The channel index 1 of the upper half is R 0_1 (or YMM in 256-bit x86 jargon 0_1 ), for the first register R 0 The channel index 0 in the lower half is R 0_0 (or YMM in 256-bit x86 jargon 0_1 ), etc.). YMM 0_0 Can also be represented as XMM 0 Although two channels are discussed herein, it should be understood that the processor 100 (eg, data registers 112, data channels 118U / L, and / or vector / SIMD execution circuitry 116) may have three, four, or more channels.

[0059] The depicted execution circuitry 104 includes scalar circuitry 114 (e.g., operating on single elements (e.g., words)) and vector / single instruction multiple data (SIMD) circuitry 116. In some embodiments, only one or any combination of scalar circuitry 114 and / or vector / single instruction multiple data (SIMD) circuitry 116 is present. In some embodiments, scalar circuitry 114 operates on scalar values ​​(e.g., multiples of single numbers). In some embodiments, vector / SIMD circuitry 116 operates on vector or packed data values.

[0060] In some examples, each register channel is coupled to a corresponding data path, such as a high channel data path 118U (e.g., 128 bits wide) and a low channel data path 118L (e.g., 128 bits wide). In some examples, each register channel and / or data path is coupled to a corresponding execution circuit, such as, for example, where the high channel data path 118U couples the high channel 112U of the data register 112 to the high channel execution circuit 120U, and / or the low pass data path 118L couples the low channel 112L of the data register 112 to the low channel execution circuit 120L.

[0061] Certain (e.g., AVX) instructions are referred to as "cross-lane" instructions, where data from a first lane (e.g., data in the high lane execution circuitry 120U or the low lane execution circuitry 120L) is to be utilized in (one or more) operations in a second lane (e.g., using data from the high lane execution circuitry 120U in the low lane execution circuitry 120L, or using data from the low lane execution circuitry 120L in the high lane execution circuitry 120U). In some examples, the vector execution circuitry 116 includes cross-lane operation circuitry 122, for example, to perform cross-lane operations.

[0062] In some examples, each execution circuit of the vector execution circuit system 116 is used to perform its own (one or more) operations separately from another (e.g., all) execution circuits, for example, the high channel execution circuit 120U operates on one or more elements from its channel separately from the low channel execution circuit 120L operating on one or more elements from its channel; and / or the low channel execution circuit 120L operates on one or more elements from its channel separately from the high channel execution circuit 120U operating on one or more elements from its channel.

[0063] Note that the figures herein may not depict all data communication connections. Those of ordinary skill in the art will appreciate that this is to avoid obscuring certain details in the figures. Note that a bidirectional arrow in the figures may not require bidirectional communication, for example, it may indicate unidirectional communication (e.g., to or from that component or device). Any or all combinations of communication paths may be utilized in certain embodiments herein.

[0064] Certain examples herein relate to Keccak instructions that utilize only a single lane, e.g., cross-lane operations are disabled (e.g., Keccak instructions do not utilize cross-lane operation circuitry 122). Figure 4-Figure 15 Let's discuss.

[0065] In some embodiments, hardware decoder circuit system 102 receives (e.g., a single) instruction (e.g., a macroinstruction) and decodes the instruction into, for example, microinstructions and / or micro-operations. In some embodiments, hardware execution circuit system 104 (e.g., high channel execution circuit 120U or low channel execution circuit 120L) executes the decoded instruction (e.g., macroinstruction) to perform one or more operations. For example, the instruction decoded by decoder circuit system 102 and the decoded instruction executed by execution circuit system 104 (e.g., high channel execution circuit 120U or low channel execution circuit 120L) can be, for example, in the present invention. Figure 4-Figure 15 Any of the instructions discussed in .

[0066] In some examples, the Keccak operation includes multiple iterations of the Keccak permutation, for example, a sequence of n r Round R, with i r Index, i r From 0 to n r-1 In some examples, a round includes five steps.

[0067] Figure 2 2 is a simplified flow chart of operation 200 implemented with Keccak permutation according to the SHA-3 standard according to an example of the present disclosure. The depicted operation 200 includes a Theta (Θ) step 204, a Rho (ρ) step 206, a Pi (π) step 208, a Chi (χ) step 210, and an Iota (ι) step 212. In some examples of SHA3, i=6, so it has 12+2*i (=24) rounds, which are applied to 1600 bits of state, so the cycle is implemented using the counter initialized in operation 202, the test applied in operation 214, and the increment operation applied in operation 216.

[0068] Figure 3A 3 is a block diagram 300 illustrating a state representation of the SHA-3 standard according to examples of the present disclosure. In some examples, state variables include Figure 3A 25 words (indexed from 0 to 24) each with 64 bits are shown in FIG. In some examples, this is a two-dimensional state for Keccak1600 with 5x5 64-bit words (which can be represented as x=0 to 4, and y=0 to 4). In some examples, for internal memory representation, the two-dimensional (2D) state is converted to a one-dimensional (1D) state by indexing i=5y+x.

[0069] Figure 3B301 is a block diagram illustrating an initial state representation of the SHA-3 standard according to an example of the present disclosure, wherein each row is stored in three (e.g., XMM) registers. In some examples, the first (labeled "word") column [elements 0, 1, 2, 3, and 4] are stored in half (e.g., the upper half or the lower half) of a lane of each of the plurality of data registers 112. In some examples, the element pairs in the second and third columns are stored in a lane of each of the plurality of data registers (e.g., the same lane as storing half of a single word), and the element pairs in the fourth and fifth columns are stored in a lane of each of the plurality of data registers (e.g., the same lane as storing half of a single word and storing the second and third columns of state). For example, the state element at index [0] is stored in register xmm 10 The lower half (for example, xmm 10_0 ), the state element at index [5] is stored in register xmm 0 The upper half (for example, xmm 0_1 ), the state element at index

[10] is stored in register xmm 0 The lower half (for example, xmm 0_0 ), the state element at index

[15] is stored in register xmm 1 The upper half (for example, xmm 1_1 ), the state element at index

[20] is stored in register xmm 1 The lower half (for example, xmm 1_0 ), etc.

[0070] Figure 4 An example of computing hardware for processing (one or more) Keccak instructions 401 according to an example of the present disclosure is illustrated. The instruction can be a Keccak (e.g., Theta (Θ) step 204, Rho (ρ) step 206, Pi (π) step 208, Chi (χ) step 210, and / or Iota (ι) step 212) instruction, such as, one or more of the following: (1) SHA3-SL-PAR instruction, (2) SHA3-SL-TXR1 instruction, (3) SHA3-SL-TXR2 instruction, (4) SHA3-SL-PI instruction, and / or SHA3-SL-CHI instruction.

[0071] As illustrated, storage device 403 stores Keccak instructions 401 to be executed.

[0072] Instruction 401 is received by decoder circuitry 405. For example, decoder circuitry 405 receives the instruction from fetch circuitry (not shown). The instruction may be in any suitable format, such as described below with reference to Fig.26 The format described. In an example, the instruction includes fields for an opcode, three registers (e.g., five 64-bit words of a Keccak state value), and a destination identifier. In some examples, the source and destination are registers, and in other examples, one or more of the source and destination are memory locations. In some examples, one or more of the sources may be immediate operands. In some examples, the opcode details a SHA3 single-pass parity instruction (with the mnemonic SHA3-SL-PAR) that accelerates the (e.g., 64-bit) parity calculation of the theta (Θ) step of a Keccak permutation. In some examples, the opcode details a SHA3 single-pass theta (Θ) step logical exclusive or circular shift instruction (with the mnemonic SHA3-SL-TXR1) that accelerates certain steps of the theta (Θ) and rho (ρ) steps of a Keccak permutation of multiple updated words used to generate a Keccak state value. In some examples, the opcodes detail a SHA3 single-pass theta (Θ) step logical exclusive OR rotate shift instruction (with the mnemonic SHA3-SL-TXR2), which accelerates certain of the theta (Θ) and rho (ρ) steps of a Keccak permutation of a single updated word used to generate a Keccak state value. In some examples, the opcodes detail a SHA3 single-pass pi (π) step instruction (with the mnemonic SHA3-SL-PI), which accelerates the pi (π) step of a Keccak permutation. In some examples, the opcodes detail a SHA3 single-pass chi (χ) step instruction (with the mnemonic SHA3-SL-CHI), which accelerates the chi (χ) step of a Keccak permutation.

[0073] A more detailed example of at least one instruction format for the instruction will be described in detail later. Decoder circuit system 405 decodes the instruction into one or more operations. In some examples, the decoding includes generating a plurality of micro-operations to be executed by the execution circuit system (e.g., single-channel execution circuit 120U or 120L). In some examples, decoder circuit system 405 also decodes the instruction prefix.

[0074] In some examples, the register renaming, register allocation, and / or scheduling circuitry 407 provides functionality for one or more of: 1) renaming logical operand values ​​to physical operand values ​​(e.g., a register alias table in some examples), 2) assigning status bits and flags to decoded instructions, and 3) scheduling decoded instructions from an instruction pool for execution by the execution circuitry (e.g., using a reservation station in some examples).

[0075] Registers (register file) and / or memory 408 store data as an operation target for instructions to be operated by execution circuit system 409. Example register types include packed data registers, general purpose registers (GPRs), and floating point registers.

[0076] The execution circuit system 409 executes the decoded instructions. The execution circuit system of the example detailed includes Figure 1 The execution circuit system 104 shown in FIG. Fig. 23B , etc. In some examples, execution of the decoded instructions causes the execution circuitry to perform Keccak operations (eg, one or more steps) in accordance with the opcodes.

[0077] In some examples, retirement / writeback circuitry 411 architecturally commits the destination register to register or memory 408 and retires the instruction.

[0078] An example of a format for a Keccak instruction is OPCODE DST / SRC0, SRC1, SRC2 (and optionally, an immediate value, e.g., for storing a Keccak circular shift control value). In some examples, OPCODE is the opcode mnemonic for the instruction. DST is a field for the location of the destination operand (such as a general register, a packed data register, or a memory). SRC0, SRC1, and SRC2 are fields for the location of the source operand (such as a general register, a packed data register, and / or a memory). In some examples, the opcode is provided by fields 2603, 3412, or 3604. In some examples, the source and / or destination location is provided by one or more bits from the following: prefix 2601 (e.g., R bit, VVVV, etc.), addressing information 2605 (e.g., reg 2744, R / M 2646, SIB byte 2704, etc.), 2218, 2220, 2222, 2224, 2226, etc. Theta (Θ) step - column parity:

[0079] In some examples, the theta (Θ) step of the Keccak permutation modifies the state variable A as follows (referred to herein as Equation 1): In 0...4 In 0...4 In (0...4,0...4) where the operation computed for C[x] represents a column parity calculation, which XORs (a logical operation that is true if and only if its arguments are different; one is true and the other is false) the five columns and generates their parity. Figure 3B Shows an example of an initial state representation, e.g., where the numbers are indices rather than actual values.

[0080] In some examples, a single-pass instruction (SHA3-SL-PAR) is defined to compute these parities as follows: SHA3-SL-PAR: Input: xmmi, xmmj, xmmk Calculation: Parity – XOR of five words (xmm i_0 1,xmm j is 1, and xmm k For 2) Output: stored in xmm i_1 Parity in

[0081] In some embodiments, five calls to SHA3-SL-PAR are used to calculate Figure 3A or Figure 3B In some examples, the results are stored in five xmm registers (xmm 10_1 ,xmm 11_1 ,xmm 12_1 ,xmm 13_1, xmm 14_1 ) in the high 64 bits of the word: 1.SHA3-SL-PAR(xmm 10 ,xmm 0 ,xmm 1 ) 2.SHA3-SL-PAR(xmm 11 ,xmm 2 ,xmm 3 ) 3.SHA3-SL-PAR(xmm 12 ,xmm 4 ,xmm 5 ) 4.SHA3-SL-PAR(xmm 13 ,xmm 6 ,xmm 7 ) 5.SHA3-SL-PAR(xmm 14 ,xmm 8 ,xmm 9 )

[0082] Figure 5 An example method executed by a processor to process a Keccak theta (Θ) step instruction (e.g., SHA3-SL-PAR) according to an example of the present disclosure is illustrated. Fig. 23B , Figure 1 or Figure 4 The method is performed by a processor core shown in FIG. , a pipeline as described in detail below, etc.

[0083] At 501, an instance of a single instruction is obtained. For example, a Keccak theta (Θ) step instruction is obtained. The instruction includes an identifier of a first register, a second register, a third register, and an opcode, the first register being used to store a first word of a Keccak state value according to a SHA3 standard, the second register being used to store a second word of the Keccak state value and a third word of the Keccak state value, the third register being used to store a fourth word of the Keccak state value and a fifth word of the Keccak state value, and the opcode being used to instruct a vector execution circuit system including multiple channels to use only a single channel of the multiple channels to perform a column parity operation of a theta step of a Keccak permutation according to the SHA3 standard to determine a calculated parity value for an input of each of the following, and storing the calculated parity value in an unused (e.g., high or low) word of the first register: the first word of the Keccak state value, the second word of the Keccak state value, the third word of the Keccak state value, the fourth word of the Keccak state value, and the fifth word of the Keccak state value. In some examples, the instruction further includes a field for writing a mask. In some examples, the instruction is retrieved from an instruction cache. The opcode indicates the operation to be performed. In some examples, the term "unused" for an element (e.g., word) of a register means that it is not used in the current calculation (e.g., not used as an input operand in the execution of the current instruction), for example, "unused" should not be interpreted as meaning that no data has been written to that element (e.g., word) in the register before.

[0084] The fetched instruction is decoded at 503. For example, the fetched Keccak theta (Θ) step instruction is decoded by decoder circuitry, such as decoder circuitry 405 or decode circuitry 2340 described in detail herein.

[0085] At 505, when the decoded instruction is dispatched, data values ​​associated with the source operands of the decoded instruction are retrieved. For example, when one or more of the source operands are memory operands, data is retrieved from the indicated memory location.

[0086] At 507, the decoded instructions are executed by execution circuitry (hardware), such as Figure 1 The execution circuit system 104 shown in Figure 4 The execution circuit system 409 shown in Fig. 23B 2360. In some examples, for a Keccak theta (Θ) step instruction, execution causes the execution circuitry to perform the operations described above.

[0087] In some examples, at 509 , the instruction is committed or retired.

[0088] Figure 6 An example method of processing a Keccak theta (Θ) step instruction (eg, SHA-SL-PAR) using emulation or binary translation according to examples of the present disclosure is illustrated.

[0089] For example, Fig. 23B , Figure 1 or Figure 4 The processor core, pipeline, and / or emulation / translation layer shown in perform various aspects of the method.

[0090] At 601, an instance of a single instruction of a first instruction set architecture is obtained. The instance of the single instruction of the first instruction set architecture includes an identifier of a first register, a second register, a third register, and an opcode, the first register being used to store a first word of a Keccak state value according to a SHA3 standard, the second register being used to store a second word of the Keccak state value and a third word of the Keccak state value, the third register being used to store a fourth word of the Keccak state value and a fifth word of the Keccak state value, and the opcode being used to instruct a vector execution circuit system including a plurality of channels to use only a single channel of the plurality of channels to perform a column parity operation of a theta step of a Keccak permutation according to the SHA3 standard to determine a calculated parity value for an input of each of the following, and storing the calculated parity value in an unused (e.g., high or low) word of the first register: the first word of the Keccak state value, the second word of the Keccak state value, the third word of the Keccak state value, the fourth word of the Keccak state value, and the fifth word of the Keccak state value. In some examples, the instruction further includes a field for writing a mask. In some examples, the instruction is obtained from an instruction cache. The opcode indicates the operation to be performed.

[0091] At 602, the retrieved single instruction of the first instruction set architecture is translated into one or more instructions of the second instruction set architecture. In some examples, this translation is performed by a translation and / or emulation layer of software. In some examples, the translation is performed by a software program such as Fig. 27 , which is performed by the instruction converter 2712 shown in . In some examples, the translation is performed by hardware translation circuitry.

[0092] At 603, one or more translated instructions of the second instruction set architecture are decoded. For example, the translated instructions are decoded by decoder circuitry, such as decoder circuitry 405 or decode circuitry 2340 described in detail herein. In some examples, the operations of translation and decoding at 602 and 603 are combined.

[0093] At 605, data values ​​associated with source operand(s) of the decoded one or more instructions of the second instruction set architecture are retrieved and the one or more instructions are scheduled. For example, when one or more of the source operands are memory operands, data is retrieved from the indicated memory location.

[0094] At 607, the decoded instruction(s) of the second instruction set architecture are executed by execution circuitry (hardware) such as Figure 1 The execution circuit system 104 shown in Figure 4The execution circuit system 409 shown in Fig. 23B 2360) is executed to perform the operation(s) indicated by the opcode of the single instruction of the first instruction set architecture. In some examples, for a Keccak theta (Θ) step instruction, the execution will cause the execution circuit system to perform the operations described above.

[0095] In some examples, at 609 , the instruction is committed or retired. Theta (Θ) step and Rho (ρ) step:

[0096] In some examples, after the parity is calculated, the next part of the θ step (e.g., as defined in Equation 1) and the ρ step are calculated by combined instructions. This optimizes the number of instructions and the overall execution latency of the Keccak round function.

[0097] Two new instructions are defined below for representing Theta-XOR and Rotation shift of SHA3 in single pass SHA3-SL-TXR1 and SHA3-SL-TXR2. SHA3-SL-TXR1: Input: xmm i ,xmm j ,xmm k ,#id1(e.g., (e.g., 64-bit) immediate value) Output: Updated xmm i register Calculation: Update xmm as follows i register: xmm i_0 =ROL64(xmm i_0 ^xmm j_1 ^ROL64(xmm k_1 ,1),rot1), xmm i_1 =ROL64(xmm i_1 ^xmm j_1 ^ROL64(xmm k_1 ,1),rot2), Among them, #id1 represents the cyclic shift value [rot1,rot2]: #0:[36,5],#1:[41,18],#2:[44,10],#3:[45,2],#4:[6,43],#5:[15,61], #6:[55,25],#7:[21,56],#8:[20,39],#9:[8,14] And ROL64 represents a circular left shift of the corresponding 64-bit value.

[0098] Some examples utilize 10 calls of the SHA3-SL-TXR1 instruction as follows: 1.SHA3-SL-TXR1(xmm 0 ,xmm 14 ,xmm 11 ,#0, from the above cyclic shift 1 value and cyclic shift 2 value) 2.SHA3-SL-TXR1(xmm 1 ,xmm 14 ,xmm 11 ,#1) 3.SHA3-SL-TXR1(xmm 2 ,xmm 10 ,xmm 12 ,#2) 4.SHA3-SL-TXR1(xmm 3 ,xmm 10 ,xmm 12 ,#3) 5.SHA3-SL-TXR1(xmm 4 ,xmm 11 ,xmm 13 ,#4) 6.SHA3-SL-TXR1(xmm 5 ,xmm 11 ,xmm 13 ,#5) 7.SHA3-SL-TXR1(xmm 6 ,xmm 12 ,xmm 14 ,#6) 8.SHA3-SL-TXR1(xmm 7 ,xmm 12 ,xmm 14 ,#7) 9.SHA3-SL-TXR1(xmm 8 ,xmm 13 ,xmm 10 ,#8) 10.SHA3-SL-TXR1(xmm 9 ,xmm 13 ,xmm 10 ,#9) SHA3-SL-TXR2: Input: xmm i ,xmm j ,xmmk ,#id2(e.g., (e.g., 64-bit) immediate value) Output: Updated xmm i A register (e.g., an element thereof) Calculation: Update word xmm as follows i_0 : xmmi_0=ROL64(xmmi_0^xmmj_1^ROL64(xmmk_1,1),rot1), Among them, #id2 represents the cyclic shift value [rot1]: #0:[0],#1:[1],#2:

[62] ,#3:

[28] ,#4:

[27]

[0099] Some examples utilize five calls to the SHA3-SL-TXR2 instruction as follows: 1.SHA3-SL-TXR2(xmm 10 ,xmm 14 ,xmm 11 ,#0) 2.SHA3-SL-TXR2(xmm 11 ,xmm 10 ,xmm 12 ,#1) 3.SHA3-SL-TXR2(xmm 12 ,xmm 11 ,xmm 13 ,#2) 4.SHA3-SL-TXR2(xmm 13 ,xmm 12 ,xmm 14 ,#3) 5.SHA3-SL-TXR2(xmm 14 ,xmm 13 ,xmm 10 ,#4)

[0100] Figure 7 An example method executed by a processor to process a Keccak theta (Θ) step and rho (ρ) step instruction (e.g., SHA3-SL-TXR1) that updates multiple elements (e.g., words) according to an example of the present disclosure is illustrated. For example, Fig. 23B , Figure 1 or Figure 4 The method is performed by a processor core shown in FIG. , a pipeline as described in detail below, etc.

[0101] At 701, an instance of a single instruction is obtained. For example, a Keccak theta (Θ) step and rho (ρ) step instruction is obtained. The instruction includes an identifier of a first register, a second register, a third register, and an operation code, the first register is used to store a first word of a Keccak state value according to a SHA3 standard, the second register is used to store a second word of the Keccak state value and a third word of the Keccak state value, the third register is used to store a fourth word of the Keccak state value and a fifth word of the Keccak state value, and the operation code is used to instruct a vector execution circuit system including multiple channels to use only a single channel of the multiple channels to perform an exclusive OR operation of the theta step of a Keccak permutation according to the SHA3 standard and perform a circular shift operation of the rho step of a Keccak permutation according to the SHA3 standard to determine multiple updated words of Keccak state values ​​for the following inputs, and store the multiple updated words of the Keccak state value in the first register: the first word of the Keccak state value, the second word of the Keccak state value, the third word of the Keccak state value, the fourth word of the Keccak state value, and the fifth word of the Keccak state value. In some examples, the instruction further includes a field for writing a mask. In some examples, the instruction is fetched from an instruction cache. The opcode indicates the operation to be performed.

[0102] The fetched instructions are decoded at 703. For example, the fetched Keccak theta (Θ) step and rho (ρ) step instructions are decoded by decoder circuitry, such as decoder circuitry 405 or decode circuitry 2340 described in detail herein.

[0103] At 705, when the decoded instruction is dispatched, data values ​​associated with the source operands of the decoded instruction are retrieved. For example, when one or more of the source operands are memory operands, data is retrieved from the indicated memory location.

[0104] At 707, the decoded instructions are executed by execution circuitry (hardware), such as Figure 1 The execution circuit system 104 shown in Figure 4 The execution circuit system 409 shown in Fig. 23B 2360. In some examples, for Keccak theta (Θ) step and rho (ρ) step instructions, execution causes the execution circuitry to perform the operations described above.

[0105] In some examples, at 709 , the instruction is committed or retired.

[0106] Figure 8 An example method for processing Keccak theta (Θ) step and rho (ρ) step instructions (eg, SHA3-SL-TXR1) that update multiple elements (eg, words) using emulation or binary translation is illustrated according to examples of the present disclosure.

[0107] For example, Fig. 23B , Figure 1 or Figure 4 The processor core, pipeline, and / or emulation / translation layer shown in perform various aspects of the method.

[0108] At 801, an instance of a single instruction of a first instruction set architecture is obtained. The instance of the single instruction of the first instruction set architecture includes an identifier of a first register, a second register, a third register, and an opcode, the first register being used to store a first word of a Keccak state value according to a SHA3 standard, the second register being used to store a second word of the Keccak state value and a third word of the Keccak state value, the third register being used to store a fourth word of the Keccak state value and a fifth word of the Keccak state value, and the opcode being used to instruct a vector execution circuit system including a plurality of lanes to perform an exclusive-or operation of a theta step of a Keccak permutation according to the SHA3 standard and a circular shift operation of a rho step of a Keccak permutation according to the SHA3 standard using only a single lane of the plurality of lanes to determine a plurality of updated words of Keccak state values ​​for input of the following, and store the plurality of updated words of the Keccak state value into the first register: the first word of the Keccak state value, the second word of the Keccak state value, the third word of the Keccak state value, the fourth word of the Keccak state value, and the fifth word of the Keccak state value. In some examples, the instruction further includes a field for writing a mask. In some examples, the instruction is fetched from an instruction cache.The opcode indicates the operation to be performed.

[0109] At 802, the retrieved single instruction of the first instruction set architecture is translated into one or more instructions of the second instruction set architecture. In some examples, this translation is performed by a translation and / or emulation layer of software. In some examples, the translation is performed by a software program such as Fig. 27 , which is performed by the instruction converter 2712 shown in . In some examples, the translation is performed by hardware translation circuitry.

[0110] At 803, one or more translated instructions of the second instruction set architecture are decoded. For example, the translated instructions are decoded by a decoder circuit system, such as decoder circuit system 405 or decoding circuit system 2340 described in detail herein. In some examples, the operations of translation and decoding at 802 and 803 are combined.

[0111] At 805, data values ​​associated with the source operand(s) of the decoded one or more instructions of the second instruction set architecture are retrieved and the one or more instructions are scheduled. For example, when one or more of the source operands are memory operands, data is retrieved from the indicated memory location.

[0112] At 807, the decoded instruction(s) of the second instruction set architecture are executed by execution circuitry (hardware) such as Figure 1 The execution circuit system 104 shown in Figure 4 The execution circuit system 409 shown in Fig. 23B 2360) to execute to perform the operation(s) indicated by the opcode of the single instruction of the first instruction set architecture. In some examples, for Keccak theta (Θ) step and rho (ρ) step instructions, the execution will cause the execution circuit system to perform the operations described above.

[0113] In some examples, at 809 , the instruction is committed or retired.

[0114] Fig. 9 An example method executed by a processor to process Keccak theta (Θ) step and rho (ρ) step instructions (e.g., SHA3-SL-TXR2) that update a single element (e.g., a single word) according to an example of the present disclosure is illustrated. For example, Fig. 23B , Figure 1 or Figure 4 The method is performed by a processor core shown in FIG. , a pipeline as described in detail below, etc.

[0115] At 901, an instance of a single instruction is obtained. For example, a Keccak theta (Θ) step and rho (ρ) step instruction is obtained. The instruction includes an identifier of a first register, a second register, a third register, and an operation code, the first register is used to store a first word of a Keccak state value according to a SHA3 standard, the second register is used to store a second word of the Keccak state value and a third word of the Keccak state value, the third register is used to store a fourth word of the Keccak state value and a fifth word of the Keccak state value, and the operation code is used to instruct a vector execution circuit system including multiple channels to use only a single channel of the multiple channels to perform an exclusive-or operation of the theta step of a Keccak permutation according to the SHA3 standard and perform a circular shift operation of the rho step of a Keccak permutation according to the SHA3 standard to determine a single updated word of the Keccak state value for the input of the following items, and store the single updated word of the Keccak state value in the first register: the first word of the Keccak state value, the second word of the Keccak state value, the third word of the Keccak state value, the fourth word of the Keccak state value, and the fifth word of the Keccak state value. In some examples, the instruction further includes a field for writing a mask. In some examples, the instruction is fetched from an instruction cache. The opcode indicates the operation to be performed.

[0116] The fetched instructions are decoded at 903. For example, the fetched Keccak theta (Θ) step and rho (ρ) step instructions are decoded by decoder circuitry, such as decoder circuitry 405 or decode circuitry 2340 described in detail herein.

[0117] At 905, when the decoded instruction is dispatched, data values ​​associated with the source operands of the decoded instruction are retrieved. For example, when one or more of the source operands are memory operands, data is retrieved from the indicated memory location.

[0118] At 907, the decoded instructions are executed by execution circuitry (hardware), such as Figure 1 The execution circuit system 104 shown in Figure 4 The execution circuit system 409 shown in Fig. 23B 2360. In some examples, for Keccak theta (Θ) step and rho (ρ) step instructions, execution causes the execution circuitry to perform the operations described above.

[0119] In some examples, at 909 , the instruction is committed or retired.

[0120] Fig.10 An example method for processing a Keccak theta (Θ) step and rho (ρ) step instruction (e.g., SHA3-SL-TXR2) that updates a single element (e.g., a single word) using emulation or binary translation according to an example of the present disclosure is illustrated. Fig. 23B , Figure 1 or Figure 4 The processor core, pipeline, and / or emulation / translation layer shown in perform various aspects of the method.

[0121] At 1001, an instance of a single instruction of a first instruction set architecture is obtained. The instance of the single instruction of the first instruction set architecture includes identifiers of a first register, a second register, a third register, and an opcode, the first register being used to store a first word of a Keccak state value according to a SHA3 standard, the second register being used to store a second word of the Keccak state value and a third word of the Keccak state value, the third register being used to store a fourth word of the Keccak state value and a fifth word of the Keccak state value, and the opcode being used to instruct a vector execution circuit system including a plurality of lanes to perform an exclusive-or operation of a theta step of a Keccak permutation according to the SHA3 standard and to perform a circular shift operation of a rho step of a Keccak permutation according to the SHA3 standard using only a single lane of the plurality of lanes to determine a single updated word of the Keccak state value for input of each of the following, and store the single updated word of the Keccak state value into (e.g., an unused word of) the first register. In some examples, the instruction further includes a field for writing a mask. In some examples, the instruction is fetched from an instruction cache. The opcode indicates the operation to be performed.

[0122] At 1002, the retrieved single instruction of the first instruction set architecture is translated into one or more instructions of the second instruction set architecture. In some examples, this translation is performed by a translation and / or emulation layer of software. In some examples, the translation is performed by a software program such as Fig. 27 , which is performed by the instruction converter 2712 shown in . In some examples, the translation is performed by hardware translation circuitry.

[0123] At 1003, one or more translated instructions of the second instruction set architecture are decoded. For example, the translated instructions are decoded by decoder circuitry, such as decoder circuitry 405 or decode circuitry 2340 described in detail herein. In some examples, the operations of translation and decoding at 1002 and 1003 are combined.

[0124] At 1005, data values ​​associated with source operand(s) of the decoded one or more instructions of the second instruction set architecture are retrieved and the one or more instructions are scheduled. For example, when one or more of the source operands are memory operands, data is retrieved from the indicated memory location.

[0125] At 1007, the decoded instruction(s) of the second instruction set architecture are executed by execution circuitry (hardware) such as Figure 1 The execution circuit system 104 shown in Figure 4 The execution circuit system 409 shown in Fig. 23B 2360) to execute to perform the operation(s) indicated by the opcode of the single instruction of the first instruction set architecture. In some examples, for Keccak theta (Θ) step and rho (ρ) step instructions, the execution will cause the execution circuit system to perform the operations described above.

[0126] In some examples, at 1009 , the instruction is committed or retired. Pi(π) step: data rearrangement

[0127] Fig.11A is a block diagram illustrating the positions of elements (eg, words) in a set of (eg, XMM) registers prior to the pi (π) step of a Keccak permutation of a SHA-3 calculation according to an example of the present disclosure.

[0128] Fig. 11B is a block diagram illustrating the positions of elements (eg, words) in a set of (eg, XMM) registers after the pi step of a Keccak permutation of a SHA-3 calculation according to an example of the present disclosure.

[0129] Some examples in this article define a new instruction SHA3-SL-PI as follows. SHA3-SL-PI:

[0130] Some examples in this article utilize 12 calls of the SHA3-SL-PI instruction to compute π steps. 1.SHA3-SL-PI(xmm 15 ,xmm 14 ,xmm 12 ,0x82) 2.SHA3-SL-PI(xmm 14 ,xmm 13 ,xmm11 ,0x82) 3.SHA3-SL-PI(xmm 12 ,xmm 6 ,xmm 0 ,0x81) 4.SHA3-SL-PI(xmm 13 ,xmm 8 ,xmm 2 ,0x81) 5.SHA3-SL-PI(xmm 0 ,xmm 0 ,xmm 6 ,0x82) 6.SHA3-SL-PI(xmm 8 ,xmm 8 ,xmm 4 ,0x82) 7.SHA3-SL-PI(xmm 4 ,xmm 4 ,xmm 4 ,0x83) 8.SHA3-SL-PI(xmm 11 ,xmm 1 ,xmm 5 ,0x81) 9.SHA3-SL-PI(xmm 6 ,xmm 3 ,xmm 7 ,0x81) 10.SHA3-SL-PI(xmm 5 ,xmm 5 ,xmm 1 ,0x82) 11.SHA3-SL-PI(xmm 3 ,xmm 3 ,xmm 9 ,0x82) 12.SHA3-SL-PI(xmm 9 ,xmm 9 ,xmm 9 ,0x83)

[0131] Some examples herein (e.g., further) utilize 18 register renaming operations (e.g., via Figure 1 Register renaming circuit system 124 in. 1.xmm 1 =xmm 15(e.g. rename xmm register 15 and its contents to xmm register 1). 2.xmm 15 =xmm 0 3.xmm 0 =xmm 14 4.xmm 14 =xmm 9 5.xmm 9 =xmm 6 6.xmm 6 =xmm 3 7.xmm 3 =xmm 15 8.xmm 15 =xmm 4 9.xmm 4 =xmm 12 10.xmm 12 =xmm 15 11.xmm 15 =xmm 5 12.xmm 5 =xmm 13 13.xmm 13 =xmm 7 14.xmm 7 =xmm 15 15.xmm 15 =xmm 2 16.xmm 2 =xmm 8 17.xmm 8 =xmm 11 18.xmm 11 =xmm 15

[0132] Fig.12 An example method executed by a processor to process a pi (π) step instruction (e.g., SHA3-SL-PI) according to an example of the present disclosure is illustrated. Fig. 23B , Figure 1 or Figure 4The method is performed by a processor core shown in FIG. , a pipeline as described in detail below, etc.

[0133] At 1201, an instance of a single instruction is obtained. For example, a pi (π) step instruction is obtained. The instruction includes an identifier of a first register, a second register, a third register, and an opcode, the first register being used to store a first word of a Keccak state value according to a SHA3 standard, a second register being used to store a second word of a Keccak state value and a third word of a Keccak state value, a third register being used to store a fourth word of a Keccak state value and a fifth word of a Keccak state value, and an opcode being used to instruct a vector execution circuit system including multiple channels to use only a single channel of the multiple channels to perform a data rearrangement operation of a pi step of a Keccak permutation according to a SHA3 standard to determine an updated word of an input Keccak state value for each of the following items, and storing the updated word of the Keccak state value in the first register (e.g., an unused word): a first word of a Keccak state value, a second word of a Keccak state value, a third word of a Keccak state value, a fourth word of a Keccak state value, and a fifth word of a Keccak state value. In some examples, the instruction further includes a field for writing a mask. In some examples, the instruction is obtained from an instruction cache. The opcode indicates the operation to be performed.

[0134] At 1203, the fetched instruction is decoded. For example, the fetched pi (π) step instruction is decoded by decoder circuitry, such as decoder circuitry 405 or decode circuitry 2340 described in detail herein.

[0135] At 1205, when the decoded instruction is dispatched, data values ​​associated with the source operands of the decoded instruction are retrieved. For example, when one or more of the source operands are memory operands, data is retrieved from the indicated memory location.

[0136] At 1207, the decoded instructions are executed by execution circuitry (hardware), such as Figure 1 The execution circuit system 104 shown in Figure 4 The execution circuit system 409 shown in Fig. 23B 2360. In some examples, for pi (π) step instructions, execution will cause the execution circuit system to perform the operations described above.

[0137] In some examples, at 1209 , the instruction is committed or retired.

[0138] Fig.13An example method of processing a pi (π) step instruction (e.g., SHA3-SL-PI) using emulation or binary translation according to an example of the present disclosure is illustrated. Fig. 23B , Figure 1 or Figure 4 The processor core, pipeline, and / or emulation / translation layer shown in perform various aspects of the method.

[0139] At 1301, an instance of a single instruction of a first instruction set architecture is obtained. The instance of the single instruction of the first instruction set architecture includes an identifier of a first register, a second register, a third register, and an opcode, the first register being used to store a first word of a Keccak state value according to a SHA3 standard, the second register being used to store a second word of a Keccak state value and a third word of a Keccak state value, the third register being used to store a fourth word of a Keccak state value and a fifth word of a Keccak state value, and the opcode being used to instruct a vector execution circuit system including a plurality of channels to perform a data rearrangement operation of a pi step of a Keccak permutation according to a SHA3 standard using only a single channel of the plurality of channels to determine an updated word of an input Keccak state value for each of the following items, and storing the updated word of the Keccak state value in the first register: a first word of a Keccak state value, a second word of a Keccak state value, a third word of a Keccak state value, a fourth word of a Keccak state value, and a fifth word of a Keccak state value. In some examples, the instruction further includes a field for writing a mask. In some examples, the instruction is obtained from an instruction cache. The opcode indicates an operation to be performed.

[0140] At 1302, the retrieved single instruction of the first instruction set architecture is translated into one or more instructions of the second instruction set architecture. In some examples, this translation is performed by a translation and / or emulation layer of software. In some examples, the translation is performed by a software program such as Fig. 27 , which is performed by the instruction converter 2712 shown in . In some examples, the translation is performed by hardware translation circuitry.

[0141] At 1303, one or more translated instructions of the second instruction set architecture are decoded. For example, the translated instructions are decoded by decoder circuitry, such as decoder circuitry 405 or decode circuitry 2340 described in detail herein. In some examples, the operations of translation and decoding at 1302 and 1303 are combined.

[0142] At 1305, data values ​​associated with source operand(s) of the decoded one or more instructions of the second instruction set architecture are retrieved and the one or more instructions are scheduled. For example, when one or more of the source operands are memory operands, data is retrieved from the indicated memory location.

[0143] At 1307, the decoded instruction(s) of the second instruction set architecture are executed by execution circuitry (hardware) such as Figure 1 The execution circuit system 104 shown in Figure 4 The execution circuit system 409 shown in Fig. 23B 2360) is executed to perform the (one or more) operations indicated by the opcode of the single instruction of the first instruction set architecture. In some examples, for the pi (π) step instruction, the execution will cause the execution circuit system to perform the operations described above.

[0144] In some examples, at 1309 , the instruction is committed or retired. Chi(χ) step: Logical operation XOR-NOT-AND

[0145] In some examples, the chi(χ) step computes XOR-NOT-AND on the three words and updates the first word as defined in Equation 2 below: In (0…4,0…4)

[0146] Some examples herein involve Figure 3B The state represented in accelerates the new instructions for that step. SHA3-SL-CHI: Input: xmm i ,xmm i+1 ,xmm i+2 Output: Updated xmm i =xmm i ^(~xmm i+1 )&xmm i+2

[0147] Certain examples use the following calls to SHA3-SL-CHI and an “andnot” instruction (e.g., having the format ANDNOT destination, source1, source2, e.g., which performs a bitwise logical AND of the inverted first source operand and the second source operand, and the result is stored in the destination operand) and an XOR instruction. 1.andnot(xmm 15 ,xmm 8 ,xmm0 ) 2.SHA3-SL-CHI(xmm 0 ,xmm 2 ,xmm 4 ) 3.SHA3-SL-CHI(xmm 4 ,xmm 6 ,xmm 8 ) 4.SHA3-SL-CHI(xmm 8 ,xmm 0 ,xmm 2 ) 5.SHA3-SL-CHI(xmm 2 ,xmm 4 ,xmm 6 ) 6.xor(xmm 6 ,xmm 6 ,xmm 15 ) 7.andnot(xmm 15 ,xmm 9 ,xmm 1 ) 8.SHA3-SL-CHI(xmm 1 ,xmm 3 ,xmm 5 ) 9.SHA3-SL-CHI(xmm 5 ,xmm 7 ,xmm 9 ) 10.SHA3-SL-CHI(xmm 9 ,xmm 1 ,xmm 3 ) 11.SHA3-SL-CHI(xmm 3 ,xmm 5 ,xmm 7 ) 12.xor(xmm 7 ,xmm 7 ,xmm 15 ) 13.andnot(xmm 15 ,xmm 14 ,xmm 10 ) 14.SHA3-SL-CHI(xmm 10 ,xmm 11 ,xmm12 ) 15.SHA3-SL-CHI(xmm 12 ,xmm 13 ,xmm 14 ) 16.SHA3-SL-CHI(xmm 14 ,xmm 10 ,xmm 11 ) 17.SHA3-SL-CHI(xmm 11 ,xmm 12 ,xmm 13 ) 18.xor(xmm 13 ,xmm 13 ,xmm 15 )

[0148] In some examples, the SHA3-SL-CHI instruction operates independently on either lane of a (e.g., ymm) register, data path, and / or execution circuit, e.g., as opposed to operating on both lanes in a single instruction. In some examples, a processor (e.g., via a user's request) may execute two independent SHA3-SL-CHI instructions on a low lane and a high lane of a vector (e.g., AVX2) data path. In some examples, an out-of-order (OOO) execution circuitry of a processor may schedule independent instructions within a single Keccak on two (e.g., AVX2) lanes using instructions disclosed herein.

[0149] Fig.14 An example method executed by a processor to process a chi(χ) step instruction (e.g., SHA3-SL-CHI) according to an example of the present disclosure is illustrated. Fig. 23B , Figure 1 or Figure 4 The method is performed by a processor core shown in FIG. , a pipeline as described in detail below, etc.

[0150] At 1401, an instance of a single instruction is obtained. For example, a chi(χ) step instruction is obtained. The instruction includes an identifier of a first register, a second register, a third register, and an opcode, the first register being used to store a first word of a Keccak state value according to a SHA3 standard, the second register being used to store a second word of a Keccak state value and a third word of a Keccak state value, the third register being used to store a fourth word of a Keccak state value and a fifth word of a Keccak state value, and the opcode being used to indicate that a vector execution circuit system including multiple channels is used to perform a logical operation of a chi step of a Keccak permutation according to a SHA3 standard using only a single channel of the multiple channels to determine an updated word of an input Keccak state value for each of the following items, and storing the updated word of the Keccak state value in the first register: the first word of the Keccak state value, the second word of the Keccak state value, the third word of the Keccak state value, the fourth word of the Keccak state value, and the fifth word of the Keccak state value. In some examples, the instruction further includes a field for writing a mask. In some examples, the instruction is obtained from an instruction cache. The opcode indicates the operation to be performed.

[0151] At 1403, the fetched instruction is decoded. For example, the fetched chi(χ) step instruction is decoded by a decoder circuit system, such as decoder circuit system 405 or decode circuit system 2340 described in detail herein.

[0152] At 1405, when the decoded instruction is dispatched, data values ​​associated with the source operands of the decoded instruction are retrieved. For example, when one or more of the source operands are memory operands, data is retrieved from the indicated memory location.

[0153] At 1407, the decoded instructions are executed by execution circuitry (hardware), such as Figure 1 The execution circuit system 104 shown in Figure 4 The execution circuit system 409 shown in Fig. 23B 2360. In some examples, for the chi(χ) step instruction, execution will cause the execution circuit system to perform the operations described above.

[0154] In some examples, at 1409 , the instruction is committed or retired.

[0155] Fig.15 An example method of processing chi(χ) step instructions using simulation or binary translation according to an example of the present disclosure is shown. Fig. 23B , Figure 1 or Figure 4 The processor core, pipeline, and / or emulation / translation layer shown in perform various aspects of the method.

[0156] At 1501, an instance of a single instruction of a first instruction set architecture is obtained. The instance of the single instruction of the first instruction set architecture includes an identifier of a first register, a second register, a third register, and an opcode, the first register being used to store a first word of a Keccak state value according to a SHA3 standard, the second register being used to store a second word of a Keccak state value and a third word of a Keccak state value, the third register being used to store a fourth word of a Keccak state value and a fifth word of a Keccak state value, and the opcode being used to instruct a vector execution circuit system including a plurality of channels to use only a single channel of the plurality of channels to perform a logical operation of a chi step of a Keccak permutation according to the SHA3 standard to determine an updated word of an input Keccak state value for each of the following items, and storing the updated word of the Keccak state value in the first register: the first word of the Keccak state value, the second word of the Keccak state value, the third word of the Keccak state value, the fourth word of the Keccak state value, and the fifth word of the Keccak state value. In some examples, the instruction further includes a field for writing a mask. In some examples, the instruction is obtained from an instruction cache. The opcode indicates an operation to be performed.

[0157] At 1502, the retrieved single instruction of the first instruction set architecture is translated into one or more instructions of the second instruction set architecture. In some examples, this translation is performed by a translation and / or emulation layer of software. In some examples, the translation is performed by a software program such as Fig. 27 , which is performed by the instruction converter 2712 shown in . In some examples, the translation is performed by hardware translation circuitry.

[0158] At 1503, one or more translated instructions of the second instruction set architecture are decoded. For example, the translated instructions are decoded by decoder circuitry, such as decoder circuitry 405 or decode circuitry 2340 described in detail herein. In some examples, the operations of translation and decoding at 1502 and 1503 are combined.

[0159] At 1505, data values ​​associated with source operand(s) of the decoded one or more instructions of the second instruction set architecture are retrieved and the one or more instructions are scheduled. For example, when one or more of the source operands are memory operands, data is retrieved from the indicated memory location.

[0160] At 1507, the decoded instruction(s) of the second instruction set architecture are executed by execution circuitry (hardware) such as Figure 1 The execution circuit system 104 shown in Figure 4 The execution circuit system 409 shown in Fig. 23B 2360) is executed to perform the (one or more) operations indicated by the opcode of the single instruction of the first instruction set architecture. In some examples, for the chi (χ) step instruction, the execution will cause the execution circuit system to perform the operations described above.

[0161] In some examples, at 1509 , the instruction is committed or retired.

[0162] In some examples, the Keccak instruction operates independently on either lane of a (e.g., ymm) register, data path, and / or execution circuit, e.g., as opposed to operating on both lanes in a single instruction. In some examples, a processor (e.g., via a user's request) may execute two independent SHA3-SL-CHI instructions on a low lane and a high lane of a vector (e.g., AVX2) data path. In some examples, an out-of-order (OOO) execution circuitry of a processor may schedule independent instructions within a single Keccak on two (e.g., AVX2) lanes using instructions disclosed herein. Iota(ι) Step: Logical XOR

[0163] In some examples, the Keccak permutation XORs the round constant with the zeroth word of the state, which is stored, for example, in Figure 3B Register xmm in 10 In the zeroth word of . Load (ld) xmm 15_0 The wheel constant in ·Execute xor(xmm10_0,xmm10_0,xmm15_0)

[0164] Some examples utilize the instruction formats described herein. Some examples are implemented in one or more computer architectures, cores, accelerators, etc. Some examples are generated or are IP cores. Some examples utilize simulation and / or translation.

[0165] At least some examples of the disclosed technology can be described according to the following examples.

[0166] In a set of examples, a device (e.g., a processor core) includes: a decoder circuit system for decoding a first instruction into a decoded first instruction, the first instruction including an identifier of a first register, a second register, a third register, and an opcode, the first register for storing a first word of a Keccak state value according to a SHA3 standard, the second register for storing a second word of the Keccak state value and a third word of the Keccak state value, the third register for storing a fourth word of the Keccak state value and a fifth word of the Keccak state value, the opcode for indicating that a vector execution circuit system including a plurality of lanes is used to perform a column parity operation of a theta step of a Keccak permutation according to the SHA3 standard using only a single lane of the plurality of lanes to determine a calculated parity value for an input of each of the following, and storing the calculated parity value in the first register: the first word of the Keccak state value, the second word of the Keccak state value, the third word of the Keccak state value, the fourth word of the Keccak state value, and the fifth word of the Keccak state value; and a vector execution circuit system for executing the decoded first instruction according to the opcode. In some examples, the single lane is 128 bits wide. In some examples, the first register, the second register, and the third register are each 128 bits wide. In some examples, a decoder circuit system is used to decode a second instruction into a decoded second instruction, the second instruction including a register for storing a sixth word of a Keccak state value according to a SHA3 standard, a register for storing a seventh word of the Keccak state value and an eighth word of the Keccak state value, a register for storing a ninth word of the Keccak state value and a cross of the Keccak state value, and an identifier of an opcode, the opcode being used to instruct a vector execution circuit system including multiple channels to perform an XOR operation of a theta step of a Keccak permutation according to the SHA3 standard and to perform a circular shift operation of a rho step of a Keccak permutation according to the SHA3 standard using only a single channel of the multiple channels to determine multiple updated words of Keccak state values ​​for input of the following items, and store the multiple updated words of the Keccak state value into one of the registers: the sixth word of the Keccak state value, the seventh word of the Keccak state value, the eighth word of the Keccak state value, the ninth word of the Keccak state value, and the cross of the Keccak state value; and the vector execution circuit system is used to execute the decoded second instruction according to the opcode.In some examples, a decoder circuit system is used to decode a second instruction into a decoded second instruction, the second instruction including a register for storing a sixth word of a Keccak state value according to a SHA3 standard, a register for storing a seventh word of the Keccak state value and an eighth word of the Keccak state value, a register for storing a ninth word of the Keccak state value and a cross of the Keccak state value, and an identifier of an opcode, the opcode being used to instruct a vector execution circuit system including multiple channels to perform an XOR operation of a theta step of a Keccak permutation according to the SHA3 standard and to perform a circular shift operation of a rho step of a Keccak permutation according to the SHA3 standard using only a single channel of the multiple channels to determine a single updated word of the Keccak state value for input of each of the following items, and store the single updated word of the Keccak state value in one of the registers: the sixth word of the Keccak state value, the seventh word of the Keccak state value, the eighth word of the Keccak state value, the ninth word of the Keccak state value, and the cross of the Keccak state value; and the vector execution circuit system is used to execute the decoded second instruction according to the opcode. In some examples, a decoder circuit system is used to decode a second instruction into a decoded second instruction, the second instruction including a register for storing a sixth word of a Keccak state value according to a SHA3 standard, a register for storing a seventh word of the Keccak state value and an eighth word of the Keccak state value, a register for storing a ninth word of the Keccak state value and a cross of the Keccak state value, and an identifier of an opcode, the opcode being used to instruct a vector execution circuit system including multiple channels to perform a data rearrangement operation of a pi step of a Keccak permutation according to the SHA3 standard using only a single channel of the multiple channels to determine an updated word of the Keccak state value for input of each of the following items, and store the updated word of the Keccak state value in one of the registers: the sixth word of the Keccak state value, the seventh word of the Keccak state value, the eighth word of the Keccak state value, the ninth word of the Keccak state value, and the cross of the Keccak state value; and the vector execution circuit system is used to execute the decoded second instruction according to the opcode.In some examples, a decoder circuit system is used to decode a second instruction into a decoded second instruction, the second instruction including a register for storing a sixth word of a Keccak state value according to a SHA3 standard, a register for storing a seventh word of the Keccak state value and an eighth word of the Keccak state value, a register for storing a ninth word of the Keccak state value and a cross of the Keccak state value, and an identifier of an opcode, the opcode being used to instruct a vector execution circuit system including multiple channels to perform a logical operation of a chi step of a Keccak permutation according to the SHA3 standard using only a single channel of the multiple channels to determine an updated word of the Keccak state value for input of each of the following items, and store the updated word of the Keccak state value in one of the registers: the sixth word of the Keccak state value, the seventh word of the Keccak state value, the eighth word of the Keccak state value, the ninth word of the Keccak state value, and the cross of the Keccak state value; and the vector execution circuit system is used to execute the decoded second instruction according to the opcode.

[0167] In another set of examples, a method includes: decoding, by a decoder circuit system, a first instruction into a decoded first instruction, the first instruction including an identifier of a first register, a second register, a third register, and an opcode, the first register being used to store a first word of a Keccak state value according to a SHA3 standard, the second register being used to store a second word of the Keccak state value and a third word of the Keccak state value, the third register being used to store a fourth word of the Keccak state value and a fifth word of the Keccak state value, the opcode being used to instruct a vector execution circuit system including a plurality of lanes to perform a column parity operation of a theta step of a Keccak permutation according to the SHA3 standard using only a single lane of the plurality of lanes to determine a calculated parity value for an input of each of the following, and storing the calculated parity value in the first register: the first word of the Keccak state value, the second word of the Keccak state value, the third word of the Keccak state value, the fourth word of the Keccak state value, and the fifth word of the Keccak state value; and executing, by the vector execution circuit system, the decoded first instruction according to the opcode. In some examples, the single lane is 128 bits wide. In some examples, the first register, the second register, and the third register are each 128 bits wide. In some examples, the method includes: decoding, by a decoder circuit system, a second instruction into a decoded second instruction, the second instruction including a register for storing a sixth word of a Keccak state value according to a SHA3 standard, a register for storing a seventh word of the Keccak state value and an eighth word of the Keccak state value, a register for storing a ninth word of the Keccak state value and a cross of the Keccak state value, and an identifier of an opcode, the opcode being used to instruct a vector execution circuit system including multiple channels to use only a single channel of the multiple channels to perform an XOR operation of a theta step of a Keccak permutation according to the SHA3 standard and to perform a circular shift operation of a rho step of a Keccak permutation according to the SHA3 standard to determine multiple updated words of Keccak state values ​​for input of the following items, and storing the multiple updated words of the Keccak state value into one of the registers: the sixth word of the Keccak state value, the seventh word of the Keccak state value, the eighth word of the Keccak state value, the ninth word of the Keccak state value, and the cross of the Keccak state value; and executing, by the vector execution circuit system, the decoded second instruction according to the opcode.In some examples, the method includes: decoding, by a decoder circuit system, a second instruction into a decoded second instruction, the second instruction including a register for storing a sixth word of a Keccak state value according to a SHA3 standard, a register for storing a seventh word of the Keccak state value and an eighth word of the Keccak state value, a register for storing a ninth word of the Keccak state value and a cross of the Keccak state value, and an identifier of an opcode, the opcode being used to instruct a vector execution circuit system including multiple channels to use only a single channel of the multiple channels to perform an XOR operation of a theta step of a Keccak permutation according to the SHA3 standard and to perform a circular shift operation of a rho step of a Keccak permutation according to the SHA3 standard to determine multiple updated words of Keccak state values ​​for input of the following items, and storing the multiple updated words of the Keccak state value into one of the registers: the sixth word of the Keccak state value, the seventh word of the Keccak state value, the eighth word of the Keccak state value, the ninth word of the Keccak state value, and the cross of the Keccak state value; and executing, by the vector execution circuit system, the decoded second instruction according to the opcode. In some examples, the method includes: decoding, by a decoder circuit system, a second instruction into a decoded second instruction, the second instruction including a register for storing a sixth word of a Keccak state value according to a SHA3 standard, a register for storing a seventh word of the Keccak state value and an eighth word of the Keccak state value, a register for storing a ninth word of the Keccak state value and a cross of the Keccak state value, and an identifier of an opcode, the opcode being used to instruct a vector execution circuit system including multiple channels to perform a data rearrangement operation of a pi step of a Keccak permutation according to the SHA3 standard using only a single channel of the multiple channels to determine an updated word of the Keccak state value for input of each of the following items, and storing the updated word of the Keccak state value in one of the registers: the sixth word of the Keccak state value, the seventh word of the Keccak state value, the eighth word of the Keccak state value, the ninth word of the Keccak state value, and the cross of the Keccak state value; and executing, by the vector execution circuit system, the decoded second instruction according to the opcode.In some examples, the method includes: decoding, by a decoder circuit system, a second instruction into a decoded second instruction, the second instruction including a register for storing a sixth word of a Keccak state value according to a SHA3 standard, a register for storing a seventh word of the Keccak state value and an eighth word of the Keccak state value, a register for storing a ninth word of the Keccak state value and a cross of the Keccak state value, and an identifier of an opcode, the opcode being used to instruct a vector execution circuit system including multiple channels to perform a logical operation of a chi step of a Keccak permutation according to the SHA3 standard using only a single channel of the multiple channels to determine an updated word of the Keccak state value for input of the following items, and storing the updated word of the Keccak state value in one of the registers: the sixth word of the Keccak state value, the seventh word of the Keccak state value, the eighth word of the Keccak state value, the ninth word of the Keccak state value, and the cross of the Keccak state value; and executing, by the vector execution circuit system, the decoded second instruction according to the opcode.

[0168] In another set of examples, a non-transitory machine-readable medium stores code that, when executed by a machine, causes the machine to execute a method comprising the following steps: decoding a first instruction into a decoded first instruction by a decoder circuit system, the first instruction comprising identifiers of a first register, a second register, a third register, and an opcode, the first register being used to store a first word of a Keccak state value according to a SHA3 standard, the second register being used to store a second word of the Keccak state value and a third word of the Keccak state value, the third register being used to store a fourth word of the Keccak state value and a fifth word of the Keccak state value, the opcode being used to instruct a vector execution circuit system comprising multiple channels to perform a column parity operation of a theta step of a Keccak permutation according to the SHA3 standard using only a single channel of the multiple channels to determine a calculated parity value for an input of each of the following items, and storing the calculated parity value in the first register: the first word of the Keccak state value, the second word of the Keccak state value, the third word of the Keccak state value, the fourth word of the Keccak state value, and the fifth word of the Keccak state value; and executing the decoded first instruction by the vector execution circuit system according to the opcode. In some examples, a single channel is 128 bits wide.In some examples, the first register, the second register, and the third register are each 128 bits wide. In some examples, the method includes: decoding, by a decoder circuit system, a second instruction into a decoded second instruction, the second instruction including a register for storing a sixth word of a Keccak state value according to a SHA3 standard, a register for storing a seventh word of the Keccak state value and an eighth word of the Keccak state value, a register for storing a ninth word of the Keccak state value and a cross of the Keccak state value, and an identifier of an opcode, the opcode being used to instruct a vector execution circuit system including multiple channels to use only a single channel of the multiple channels to perform an XOR operation of a theta step of a Keccak permutation according to the SHA3 standard and to perform a circular shift operation of a rho step of a Keccak permutation according to the SHA3 standard to determine multiple updated words of Keccak state values ​​for input of the following items, and storing the multiple updated words of the Keccak state value into one of the registers: the sixth word of the Keccak state value, the seventh word of the Keccak state value, the eighth word of the Keccak state value, the ninth word of the Keccak state value, and the cross of the Keccak state value; and executing, by the vector execution circuit system, the decoded second instruction according to the opcode.In some examples, the method includes: decoding, by a decoder circuit system, a second instruction into a decoded second instruction, the second instruction including a register for storing a sixth word of a Keccak state value according to a SHA3 standard, a register for storing a seventh word of the Keccak state value and an eighth word of the Keccak state value, a register for storing a ninth word of the Keccak state value and a cross of the Keccak state value, and an identifier of an opcode, the opcode being used to instruct a vector execution circuit system including multiple channels to perform an XOR operation of a theta step of a Keccak permutation according to the SHA3 standard and to perform a circular shift operation of a rho step of a Keccak permutation according to the SHA3 standard using only a single channel of the multiple channels to determine a single updated word of the Keccak state value for input of each of the following items, and storing the single updated word of the Keccak state value in one of the registers: the sixth word of the Keccak state value, the seventh word of the Keccak state value, the eighth word of the Keccak state value, the ninth word of the Keccak state value, and the cross of the Keccak state value; and executing, by the vector execution circuit system, the decoded second instruction according to the opcode. In some examples, the method includes: decoding, by a decoder circuit system, a second instruction into a decoded second instruction, the second instruction including a register for storing a sixth word of a Keccak state value according to a SHA3 standard, a register for storing a seventh word of the Keccak state value and an eighth word of the Keccak state value, a register for storing a ninth word of the Keccak state value and a cross of the Keccak state value, and an identifier of an opcode, the opcode being used to instruct a vector execution circuit system including multiple channels to perform a data rearrangement operation of a pi step of a Keccak permutation according to the SHA3 standard using only a single channel of the multiple channels to determine an updated word of the Keccak state value for input of each of the following items, and storing the updated word of the Keccak state value in one of the registers: the sixth word of the Keccak state value, the seventh word of the Keccak state value, the eighth word of the Keccak state value, the ninth word of the Keccak state value, and the cross of the Keccak state value; and executing, by the vector execution circuit system, the decoded second instruction according to the opcode.In some examples, the method includes: decoding, by a decoder circuit system, a second instruction into a decoded second instruction, the second instruction including a register for storing a sixth word of a Keccak state value according to a SHA3 standard, a register for storing a seventh word of the Keccak state value and an eighth word of the Keccak state value, a register for storing a ninth word of the Keccak state value and a cross of the Keccak state value, and an identifier of an opcode, the opcode being used to instruct a vector execution circuit system including multiple channels to perform a logical operation of a chi step of a Keccak permutation according to the SHA3 standard using only a single channel of the multiple channels to determine an updated word of the Keccak state value for input of the following items, and storing the updated word of the Keccak state value in one of the registers: the sixth word of the Keccak state value, the seventh word of the Keccak state value, the eighth word of the Keccak state value, the ninth word of the Keccak state value, and the cross of the Keccak state value; and executing, by the vector execution circuit system, the decoded second instruction according to the opcode.

[0169] The following details exemplary architectures, systems, etc. that may be used in the above. The following details exemplary instruction formats for Keccak / SHA3 instructions. Example Architecture

[0170] The description of the example computer architecture is described in detail below. Other system designs and configurations for laptops, desktop computers, handheld personal computers (PCs), personal digital assistants, engineering workstations, servers, separate servers, network devices, network hubs, switches, routers, embedded processors, digital signal processors (DSPs), graphics devices, video game devices, set-top boxes, microcontrollers, cellular phones, portable media players, handheld devices, and various other electronic devices known in the art are also suitable. In general, various systems or electronic devices that can contain processors and / or other execution logic as disclosed herein are generally suitable. Example System

[0171] Fig.16An example computing system is shown. Multiprocessor system 1600 is a system provided with an interface and includes multiple processors or cores, including a first processor 1670 and a second processor 1680 coupled via an interface 1650 such as a point-to-point (PP) interconnect, a fabric, and / or a bus. In some examples, the first processor 1670 and the second processor 1680 are isomorphic. In some examples, the first processor 1670 and the second processor 1680 are heterogeneous. Although example system 1600 is shown as having two processors, the system can have three or more processors, or can be a single processor system. In some examples, the computing system is a system on a chip (SoC).

[0172] Processor 1670 and processor 1680 are shown as including integrated memory controller (IMC) circuitry 1672 and 1682, respectively. Processor 1670 also includes interface circuitry 1676 and 1678; similarly, second processor 1680 includes interface circuitry 1686 and 1688. Processors 1670, 1680 may exchange information via interface 1650 using interface circuitry 1678, 1688. IMCs 1672 and 1682 couple processors 1670, 1680 to respective memories, namely memory 1632 and memory 1634, which may be portions of main memory locally attached to the respective processors.

[0173] Processors 1670, 1680 can each use interface circuits 1676, 1694, 1686, 1698 to exchange information with a network interface (NW I / F) 1690 via separate interfaces 1652, 1654. Network interface 1690 (e.g., one or more of an interconnect, bus, and / or fabric, and in some examples, a chipset) can optionally exchange information with a coprocessor 1638 via interface circuit 1692. In some examples, coprocessor 1638 is a special-purpose processor such as, for example, a high-throughput processor, a network or communication processor, a compression engine, a graphics processor, a general purpose graphics processing unit (GPGPU), a neural-network processing unit (NPU), an embedded processor, and the like.

[0174] A shared cache (not shown) may be included in either processor 1670, 1680, or external to both processors but connected to these processors via an interface (such as, the PP interconnect) so that if the processor is placed in a low power mode, local cache information of either or both processors can be stored in the shared cache.

[0175] The network interface 1690 can be coupled to the first interface 1616 via the interface circuit 1696. In some examples, the first interface 1616 can be an interface such as a peripheral component interconnect (PCI) interconnect, a PCI express interconnect, or another I / O interconnect. In some examples, the first interface 1616 is coupled to a power control unit (PCU) 1617, which may include circuitry, software, and / or firmware for performing power management operations related to the processors 1670, 1680, and / or the coprocessor 1638. The PCU 1617 provides control information to a voltage regulator (not shown) so that the voltage regulator generates an appropriate regulated voltage. The PCU 1617 also provides control information to control the generated operating voltage. In various examples, the PCU 1617 may include various power management logic units (circuitry) for performing hardware-based power management. Such power management may be entirely controlled by the processor (e.g., by various processor hardware, and which may be triggered by workload and / or power, thermal constraints, or other processor constraints), and / or power management may be performed in response to an external source (such as a platform or power management source or system software).

[0176] PCU 1617 is illustrated as existing as logic separate from processor 1670 and / or processor 1680. In other cases, PCU 1617 may execute on a given one or more cores (not shown) of the cores of processor 1670 or 1680. In some cases, PCU 1617 may be implemented as a (dedicated or general purpose) microcontroller or other control logic configured to execute its own dedicated power management code (sometimes referred to as P-code). In still other examples, the power management operations to be performed by PCU 1617 may be implemented external to the processor, such as by way of a separate power management integrated circuit (PMIC) or another component external to the processor. In still other examples, the power management operations to be performed by PCU 1617 may be implemented within BIOS or other system software.

[0177] Various I / O devices 1614 may be coupled to the first interface 1616 along with a bus bridge 1618, which couples the first interface 1616 to the second interface 1620. In some examples, one or more additional processors 1615 (such as a coprocessor, a high-throughput many integrated core (MIC) processor, a GPGPU, an accelerator (such as a graphics accelerator or a digital signal processing (DSP) unit), a field programmable gate array (FPGA), or any other processor) are coupled to the first interface 1616. In some examples, the second interface 1620 may be a low pin count (LPC) interface. Various devices may be coupled to the second interface 1620, including, for example, a keyboard and / or mouse 1622, a communication device 1627, and a storage circuit system 1628. Storage circuit system 1628 can be one or more non-transitory machine-readable storage media as described below, such as a disk drive or other mass storage device, which in some examples can include instructions / code and data 1630 and can implement storage device 403. Further, audio I / O 1624 can be coupled to second interface 1620. Note that other architectures are possible in addition to the point-to-point architecture described above. For example, a system such as multiprocessor system 1600 can implement a multi-drop interface or other such architecture instead of a point-to-point architecture.

[0178] Exemplary Core Architectures, Processors, and Computer Architectures

[0179] Processor cores can be implemented in different ways, for different purposes, and in different processors. For example, implementations of such cores may include: 1) a general-purpose in-order core intended for general-purpose computing; 2) a high-performance general-purpose out-of-order core intended for general-purpose computing; 3) a special-purpose core intended primarily for graphics and / or scientific (throughput) computing. Different processor implementations may include: 1) a CPU that includes one or more general-purpose in-order cores intended for general-purpose computing and / or one or more general-purpose out-of-order cores intended for general-purpose computing; and 2) a coprocessor that includes one or more special-purpose cores intended primarily for graphics and / or scientific (throughput) computing. Such different processors lead to different computer system architectures, which may include: 1) a coprocessor on a separate chip from the CPU; 2) a coprocessor in the same package as the CPU but on a separate die; 3) a coprocessor on the same die as the CPU (in which case such a coprocessor is sometimes referred to as dedicated logic or as a dedicated core, such as integrated graphics and / or scientific (throughput) logic); and 4) a system on a chip (SoC), which may include the described CPU (sometimes referred to as application core(s) or application processor(s), the coprocessor described above, and additional functionality on the same die. An example core architecture is described next, followed by a description of an example processor and computer architecture.

[0180] Fig.17 A block diagram of an example processor and / or SoC 1700 that may have one or more cores and an integrated memory controller is illustrated. The solid lined box illustrates a processor 1700 having a single core 1702A, a system agent unit circuitry 1710, and a collection of one or more interface controller unit circuitry 1716, while the optional addition of dashed lined boxes illustrates an alternative processor 1700 having multiple cores 1702A-1702N, a collection of one or more integrated memory controller units 1714 in the system agent unit circuitry 1710, and dedicated logic 1708 and a collection of one or more interface controller unit circuitry 1716. Note that the processor 1700 may be Fig.16 one of processors 1670 or 1680, or coprocessors 1638 or 1615.

[0181] Thus, different implementations of processor 1700 may include: 1) a CPU, where the dedicated logic 1708 is integrated graphics and / or scientific (throughput) logic (which may include one or more cores, not shown), and cores 1702A-1702N are one or more general purpose cores (e.g., general purpose in-order cores, general purpose out-of-order cores, a combination of the two); 2) a coprocessor, where cores 1702A-1702N are a large number of dedicated cores intended primarily for graphics and / or scientific (throughput); and 3) a coprocessor, where cores 1702A-1702N are a large number of general purpose in-order cores. Thus, processor 1700 may be a general purpose processor, a coprocessor, or a dedicated processor, such as, for example, a network or communication processor, a compression engine, a graphics processor, a GPGPU (general purpose graphics processing unit), a high throughput many integrated core (MIC) coprocessor (including 30 or more cores), an embedded processor, etc. The processor may be implemented on one or more chips. Processor 1700 may be part of and / or implemented on one or more substrates using any of a variety of process technologies, such as, for example, complementary metal-oxide-semiconductor (CMOS), bipolar CMOS (BiCMOS), P-type metal oxide semiconductor (PMOS), or N-type metal oxide semiconductor (NMOS).

[0182] The memory hierarchy includes one or more levels of cache unit circuitry 1704A-1704N within the cores 1702A-1702N, a set of one or more shared cache unit circuitry 1706, and external memory (not shown) coupled to a set of (one or more) integrated memory controller unit circuitry 1714. The set of one or more shared cache unit circuitry 1706 may include one or more intermediate levels of cache (such as level 2 (L2), level 3 (L3), level 4 (L4)) or other levels of cache (such as last level cache (LLC)) and / or combinations thereof. Although in some examples, an interface network circuitry 1712 (e.g., a ring interconnect) provides an interface to dedicated logic 1708 (e.g., integrated graphics logic), a set of (one or more) shared cache unit circuitry 1706, and a system agent unit circuitry 1710, alternative examples use any number of well-known techniques for providing an interface to such units. In some examples, coherency is maintained between the shared cache unit circuitry 1706 and one or more of the cores 1702A-1702N. In some examples, the interface controller unit circuitry 1716 couples the core 1702 to one or more other devices 1718, such as one or more I / O devices, storage, one or more communication devices (e.g., a wireless network, a wired network, etc.), etc.

[0183] In some examples, one or more of the cores 1702A-1702N may be capable of multithreading. System agent unit circuitry 1710 includes those components that coordinate and operate the cores 1702A-1702N. System agent unit circuitry 1710 may include, for example, power control unit (PCU) circuitry and / or display unit circuitry (not shown). The PCU may be, or may include, the logic and components required to regulate the power state of the cores 1702A-1702N and / or the dedicated logic 1708 (e.g., integrated graphics logic). The display unit circuitry is used to drive one or more externally connected displays.

[0184] The cores 1702A-1702N may be homogeneous in terms of instruction set architecture (ISA). Alternatively, the cores 1702A-1702N may be heterogeneous in terms of ISA; that is, a subset of the cores 1702A-1702N may be able to execute an ISA, while other cores may only be able to execute a subset of that ISA or another ISA.

[0185] Fig.18 1800 is a block diagram illustrating a computing system 1800 configured to implement one or more aspects of the examples described herein. The computing system 1800 includes a processing subsystem 1801 having one or more processors 1802 and a system memory 1804 communicating via an interconnect path, which may include a memory hub 1805. The memory hub 1805 may be a separate component within a chipset component, or may be integrated within one or more processors 1802. The memory hub 1805 is coupled to an I / O subsystem 1811 via a communication link 1806. The I / O subsystem 1811 includes an I / O hub 1807, which may enable the computing system 1800 to receive input from one or more input devices 1808. Additionally, the I / O hub 1807 may enable a display controller (which may be included in one or more processors 1802) to provide output to one or more display devices 1810A. In some examples, one or more display devices 1810A coupled to I / O hub 1807 may include local, internal, or embedded display devices.

[0186] The processing subsystem 1801 includes, for example, one or more parallel processors 1812 coupled to a memory hub 1805 via a bus or other communication link 1813. The communication link 1813 can be one of any number of standard-based communication link technologies or protocols, such as but not limited to PCI Express, or can be a vendor-specific communication interface or communication fabric. The one or more parallel processors 1812 can form a parallel or vector processing system in a computational concentration that can include a large number of processing cores and / or processing clusters, such as, for example, many integrated core (MIC) processors. For example, the one or more parallel processors 1812 form a graphics processing subsystem that can output pixels to one of the one or more display devices 1810A coupled via the I / O hub 1807. The one or more parallel processors 1812 may also include a display controller and a display interface (not shown) for enabling direct connection to one or more display devices 1810B.

[0187] Within the I / O subsystem 1811, a system storage unit 1814 may be connected to the I / O hub 1807 to provide a storage mechanism for the computing system 1800. An I / O switch 1816 may be used to provide an interface mechanism to enable connections between the I / O hub 1807 and other components, such as a network adapter 1818 and / or a wireless network adapter 1819 that may be integrated into the platform, and various other devices that may be added via one or more plug-in devices 1820. The plug-in device(s) 1820 may also include, for example, one or more external graphics processor devices, graphics cards, and / or computing accelerators. The network adapter 1818 may be an Ethernet adapter or another wired network adapter. The wireless network adapter 1819 may include one or more of the following: Wi-Fi, Bluetooth, near field communication (NFC), or other network devices including one or more wireless radio devices.

[0188] The computing system 1800 may include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, etc., which may also be connected to the I / O hub 1807. Fig.18 The communication paths for interconnecting the various components in the system may be implemented using any suitable protocol, such as a PCI (Peripheral Component Interconnect) based protocol (e.g., PCI Express), or any other bus or point-to-point communication interface and / or protocol(s), such as NVLink high-speed interconnect, Compute Express Link, or the like. TM (ComputeExpress Link TM , CXL TM) (e.g., CXL.mem), Infinity Fabric (IF), Ethernet (IEEE802.3), remote direct memory access (RDMA), InfiniBand, Internet Wide Area RDMA Protocol (iWARP), Transmission Control Protocol (TCP), User Datagram Protocol (UDP), quick UDP Internet Connections (QUIC), RDMA over Converged Ethernet (RoCE), Intel Quick Path Interconnect (QPI), Intel Ultra Path Interconnect (UPI), Intel On-Chip System Fabric (IOSF), Omnipath, HyperTransport, Advanced Microcontroller Bus Architecture (AMBA) interconnect, OpenCAPI, Gen-Z, Cache Coherent Interconnect for Accelerators The data may be copied or stored to a virtualized storage node using protocols such as NVMe (non-volatile memory express over Fabrics, NVME-oF) or NVMe.

[0189] One or more parallel processors 1812 may include circuitry optimized for graphics and video processing (including, for example, video output circuitry) and constitute a graphics processing unit (GPU). Alternatively or additionally, as described in more detail herein, one or more parallel processors 1812 may include circuitry optimized for general-purpose processing while retaining the underlying computing architecture. The components of the computing system 1800 may be integrated on a single integrated circuit with one or more other system elements. For example, one or more parallel processors 1812, a memory hub 1805, (one or more) processors 1802, and an I / O hub 1807 may be integrated into a system-on-chip (SoC) integrated circuit. Alternatively, the components of the computing system 1800 may be integrated into a single package to form a system-in-package (SIP) configuration. In some examples, at least a portion of the components of the computing system 1800 may be integrated into a multi-chip module (MCM), which may be interconnected with other multi-chip modules into a modular computing system.

[0190] It will be appreciated that the computing system 1800 shown herein is illustrative, and variations and modifications are possible. The connection topology, including the number and arrangement of bridges, the number of (one or more) processors 1802, and the number of (one or more) parallel processors 1812, may be modified as desired. For example, the system memory 1804 may be connected to the (one or more) processors 1802 directly rather than through a bridge, while other devices communicate with the system memory 1804 via the memory hub 1805 and the (one or more) processors 1802. In other alternative topologies, the (one or more) parallel processors are connected to the I / O hub 1807 or directly to one of the one or more processors 1802, rather than to the memory hub 1805. In other examples, the I / O hub 1807 and the memory hub 1805 may be integrated into a single chip. It is also possible for two or more sets of processors 1802 to be attached via multiple slots, which may be coupled to two or more instances of (one or more) parallel processors 1812.

[0191] Some of the specific components shown herein are optional and may not be included in all implementations of computing system 1800. For example, any number of plug-in cards or peripherals may be supported, or some components may be eliminated. In addition, some architectures may be specific to the Fig.18 Different terminology is used for components similar to those illustrated in FIG. 1804. For example, memory hub 1805 may be referred to as a north bridge in some architectures, while I / O hub 1807 may be referred to as a south bridge.

[0192] Fig.19A An example of a parallel processor 1900 is shown. The parallel processor 1900 may be a GPU, a GPGPU, etc. as described herein. The various components of the parallel processor 1900 may be implemented using one or more integrated circuit devices, such as a programmable processor, an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA). The illustrated parallel processor 1900 may be Fig.18 One or more of the parallel processor(s) 1812 shown in .

[0193] Parallel processor 1900 includes parallel processing unit 1902. Parallel processing unit includes I / O unit 1904 that enables communication with other devices, including other instances of parallel processing unit 1902. I / O unit 1904 can be directly connected to other devices. For example, I / O unit 1904 is connected to other devices via the use of a hub or switch interface (such as memory hub 1805). The connection between memory hub 1805 and I / O unit 1904 forms a communication link 1813. Within parallel processing unit 1902, I / O unit 1904 is connected to host interface 1906 and memory cross switch 1916, wherein host interface 1906 receives commands related to performing processing operations and memory cross switch 1916 receives commands related to performing memory operations.

[0194] When the host interface 1906 receives the command buffer via the I / O unit 1904, the host interface 1906 can direct the work operations for executing those commands to the front end 1908. In some examples, the front end 1908 is coupled with a scheduler 1910, which is configured to distribute commands or other work items to the processing cluster array 1912. The scheduler 1910 ensures that the processing cluster array 1912 is properly configured and in a valid state before the task is distributed to the processing clusters in the processing cluster array 1912. The scheduler 1910 can be implemented via firmware logic executed on a microcontroller. The microcontroller-implemented scheduler 1910 can be configured to perform complex scheduling and work distribution operations at coarse and fine granularity, thereby achieving fast preemption and context switching of threads executed on the processing cluster array 1912. Preferably, the host software can confirm the workload for scheduling on the processing cluster array 1912 via one of a plurality of graphics processing doorbells. In other examples, polling for new workloads or interrupts may be used to identify or indicate the availability of work to be performed. The workload may then be automatically distributed across the processing cluster array 1912 by the scheduler 1910 logic within the scheduler microcontroller.

[0195] The processing cluster array 1912 may include up to "N" processing clusters (e.g., cluster 1914A, cluster 1914B to cluster 1914N). Each cluster 1914A-1914N in the processing cluster array 1912 may execute a large number of concurrent threads. The scheduler 1910 may use various scheduling and / or work distribution algorithms to assign work to the clusters 1914A-1914N in the processing cluster array 1912, which may vary depending on the workload generated for each type of program or calculation. Scheduling may be handled dynamically by the scheduler 1910, or may be partially assisted by compiler logic during the compilation of program logic configured for execution by the processing cluster array 1912. Optionally, different clusters 1914A-1914N in the processing cluster array 1912 may be assigned to process different types of programs or to perform different types of calculations.

[0196] Processing cluster array 1912 may be configured to perform various types of parallel processing operations. For example, processing cluster array 1912 is configured to perform general-purpose parallel computing operations. For example, processing cluster array 1912 may include logic for performing processing tasks including filtering of video and / or audio data, performing modeling operations including physical operations, and performing data transformations.

[0197] Processing cluster array 1912 is configured to perform parallel graphics processing operations. In such examples where parallel processor 1900 is configured to perform graphics processing operations, processing cluster array 1912 may include additional logic for supporting the execution of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations, and tessellation logic and other vertex processing logic. In addition, processing cluster array 1912 may be configured to execute graphics processing related shader programs, such as but not limited to vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. Parallel processing unit 1902 may transfer data from system memory via I / O unit 1904 for processing. During processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 1922) during processing, and then the data may be written back to system memory.

[0198] In examples where parallel processing units 1902 are used to perform graphics processing, scheduler 1910 may be configured to divide the processing workload into tasks of approximately equal size to better enable distribution of graphics processing operations to multiple clusters 1914A-1914N in processing cluster array 1912. In some of these examples, portions of processing cluster array 1912 may be configured to perform different types of processing. For example, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tessellation and geometry shading, and a third portion may be configured to perform pixel shading or other screen space operations to produce a rendered image for display. Intermediate data generated by one or more of clusters 1914A-1914N may be stored in a buffer to allow the intermediate data to be transferred between clusters 1914A-1914N for further processing.

[0199] During operation, the processing cluster array 1912 may receive processing tasks to be executed via the scheduler 1910, which receives commands defining the processing tasks from the front end 1908. For graphics processing operations, the processing tasks may include data to be processed, such as surface (patch) data, primitive data, vertex data, and / or pixel data, and state parameters and commands defining how the data is to be processed (e.g., what program is to be executed). The scheduler 1910 may be configured to fetch an index corresponding to a task, or may receive an index from the front end 1908. The front end 1908 may be configured to ensure that the processing cluster array 1912 is configured to a valid state before a workload specified by an incoming command buffer (e.g., a batch buffer, a push buffer, etc.) is initiated.

[0200] Each of the one or more instances of parallel processing unit 1902 may be coupled to parallel processor memory 1922. Parallel processor memory 1922 may be accessed via memory crossbar switch 1916, which may receive memory requests from processing cluster array 1912 and I / O unit 1904. Memory crossbar switch 1916 may access parallel processor memory 1922 via memory interface 1918. Memory interface 1918 may include a plurality of partition units (e.g., partition unit 1920A, partition unit 1920B, up to partition unit 1920N), each of which may be coupled to a portion (e.g., memory unit) of parallel processor memory 1922. The number of partition units 1920A-1920N may be configured to be equal to the number of memory units, such that a first partition unit 1920A has a corresponding first memory unit 1924A, a second partition unit 1920B has a corresponding second memory unit 1924B, and an Nth partition unit 1920N has a corresponding Nth memory unit 1924N. In other examples, the number of partition units 1920A-1920N may not be equal to the number of memory devices.

[0201] The memory units 1924A-1924N may include various types of memory devices, including dynamic random-access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. Optionally, the memory units 1924A-1924N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). Those skilled in the art will appreciate that the specific implementation of the memory units 1924A-1924N may vary and may be selected from one of a variety of conventional designs. Rendering targets such as frame buffers or texture maps may be stored across the memory units 1924A-1924N, allowing the partition units 1920A-1920N to write portions of each rendering target in parallel to efficiently use the available bandwidth of the parallel processor memory 1922. In some examples, local instances of parallel processor memory 1922 may be eliminated in favor of a unified memory design utilizing system memory in conjunction with local cache memory.

[0202] Optionally, any of the clusters 1914A-1914N in the processing cluster array 1912 has the capability to process data to be written to any of the memory units 1924A-1924N within the parallel processor memory 1922. The memory crossbar 1916 may be configured to transfer the output of each cluster 1914A-1914N to any partition unit 1920A-1920N or to another cluster 1914A-1914N, which may perform additional processing operations on the output. Each cluster 1914A-1914N may communicate with a memory interface 1918 via the memory crossbar 1916 to read from or write to various external memory devices. In one example with a memory crossbar 1916, the memory crossbar 1916 has connections to a memory interface 1918 to communicate with the I / O unit 1904 and has connections to a local instance of a parallel processor memory 1922, thereby enabling processing units within different processing clusters 1914A-1914N to communicate with system memory or other memory that is not local to the parallel processing unit 1902. In general, the memory crossbar 1916 may be able to separate traffic flows between the clusters 1914A-1914N and the partition units 1920A-1920N using virtual channels, for example.

[0203] Although a single instance of parallel processing unit 1902 is illustrated within parallel processor 1900, any number of instances of parallel processing unit 1902 may be included. For example, multiple instances of parallel processing unit 1902 may be provided on a single plug-in card, or multiple plug-in cards may be interconnected. For example, parallel processor 1900 may be a plug-in device, such as, Fig.18 Plug-in device 1820, which can be a graphics card (such as a discrete graphics card including one or more GPUs, one or more memory devices, and device-to-device or network or structure interfaces). Different instances of parallel processing unit 1902 can be configured to interoperate even if different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configuration differences. Optionally, some instances of parallel processing unit 1902 may include higher precision floating point units relative to other instances. Systems including one or more instances of parallel processing unit 1902 or parallel processor 1900 can be implemented in various configurations and form factors, including but not limited to desktop computers, laptop computers, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems. The orchestrator can use one or more of the following to form a composite node for workload execution: decomposed processor resources, cache resources, memory resources, storage resources, and networking resources.

[0204] In some examples, the parallel processing unit 1902 can be partitioned into multiple instances. Those multiple instances can be configured to execute workloads associated with different clients in an isolated manner, so that a predetermined quality of service is provided for each client. For example, each cluster 1914A-1914N can be partitioned and isolated from other clusters, thereby allowing the processing cluster array 1912 to be divided into multiple computing partitions or instances. In such a configuration, the workload executed on the isolated partition is protected from errors or errors associated with different workloads executed on different partitions. Partition units 1920A-1920N can be configured to enable dedicated paths and / or isolated paths to the memory of the cluster 1914A-1914N associated with the corresponding computing partition. This data path isolation enables the computing resources within the partition to communicate with one or more assigned memory units 1924A-1924N without being disturbed by the activities of other partitions.

[0205] Fig.19B is a block diagram of the partition unit 1920. The partition unit 1920 may be Fig.19A 1920A-1920N. As illustrated, partition unit 1920 includes L2 cache 1921, frame buffer interface 1925, and ROP 1926 (raster operation unit). L2 cache 1921 is a read / write cache configured to perform load and store operations received from memory crossbar switch 1916 and ROP 1926. Read misses and urgent writeback requests are output by L2 cache 1921 to frame buffer interface 1925 for processing. Updates may also be sent to the frame buffer via frame buffer interface 1925 for processing. In some examples, frame buffer interface 1925 communicates with memory units in parallel processor memory (such as, for example, within parallel processor memory 1922). Fig.19A Partition unit 1920 may also additionally or alternatively interface with one of the memory units in the parallel processor memory via a memory controller (not shown).

[0206] In graphics applications, ROP 1926 is a processing unit that performs raster operations such as stenciling, z-testing, blending, etc. ROP 1926 then outputs processed graphics data, which is stored in graphics memory. In some examples, ROP 1926 includes or is coupled to a codec (CODEC) 1927 that includes compression logic for compressing depth or color data written to memory or L2 cache 1921 and decompressing depth or color data read from memory or L2 cache 1921. The compression logic may be lossless compression logic that utilizes one or more of a variety of compression algorithms. The type of compression performed by CODEC 1927 may vary based on the statistical characteristics of the data to be compressed. For example, in some examples, delta color compression is performed on depth and color data on a slice-by-slice basis. In some examples, CODEC 1927 includes compression and decompression logic that can compress and decompress computational data associated with machine learning operations. CODEC 1927 can, for example, compress sparse matrix data for sparse machine learning operations. CODEC 1927 can also compress sparse matrix data encoded in a sparse matrix format (e.g., coordinate list encoding (COO), compressed sparse row (CSR), compressed sparse column (CSC), etc.) to generate compressed and encoded sparse matrix data. The compressed and encoded sparse matrix data can be decompressed and / or decoded before being processed by a processing element, or the processing element can be configured to consume compressed, encoded, or compressed and encoded data for processing.

[0207] ROP 1926 may be included in each processing cluster (e.g., Fig.19A 1914A-1914N) rather than being included in partition unit 1920. In such examples, read and write requests for pixel data rather than pixel fragment data are transmitted through memory crossbar switch 1916. The processed graphics data may be displayed on a display device (such as, Fig.18 1810A-1810B), is routed for further processing by (one or more) processors 1802, or is routed for processing by Fig.19A One of the processing entities within parallel processor 1900 further processes.

[0208] Fig.19Cis a block diagram of a processing cluster 1914 within a parallel processing unit. For example, a processing cluster is Fig.19A An instance of a processing cluster in the processing clusters 1914A-1914N. Processing cluster 1914 may be configured to execute many threads in parallel, wherein the term "thread" refers to an instance of a specific program executed on a set of specific input data. Optionally, a single-instruction, multiple-data (SIMD) instruction issuance technique may be used to support the parallel execution of a large number of threads without providing multiple independent instruction units. Alternatively, a single-instruction, multiple-thread (SIMT) technique may be used to support the parallel execution of a large number of threads that are generally synchronized using a common instruction unit configured to issue instructions to a set of processing engines within each processing cluster in the processing cluster. Unlike the SIMD execution mechanism in which all processing engines typically execute the same instruction, SIMT execution allows different threads to more easily follow the divergent execution path through a given thread program. Those skilled in the art will appreciate that the SIMD processing mechanism represents a functional subset of the SIMT processing mechanism.

[0209] The operation of the processing cluster 1914 may be controlled via a pipeline manager 1932 that distributes processing tasks to SIMT parallel processors. The pipeline manager 1932 receives data from Fig.19A The graphics multiprocessor 1934 may be used to process the graphics multiprocessor 1934 and / or the texture unit 1936. The graphics multiprocessor 1934 is an exemplary embodiment of a SIMT parallel processor. However, various types of SIMT parallel processors of different architectures may be included in the processing cluster 1914. One or more instances of the graphics multiprocessor 1934 may be included in the processing cluster 1914. The graphics multiprocessor 1934 may process data, and the data crossbar 1940 may be used to distribute the processed data to one of a plurality of possible destinations, including other shader units. The pipeline manager 1932 may facilitate the distribution of processed data by specifying a destination for the processed data to be distributed via the data crossbar 1940.

[0210] Each graphics multiprocessor 1934 within a processing cluster 1914 may include an identical set of function execution logic (e.g., arithmetic logic units, load-store units, etc.). The function execution logic may be configured in a pipelined manner in which new instructions may be issued before previous instructions are completed. The function execution logic supports a variety of operations, including integer and floating point arithmetic, comparison operations, Boolean operations, bit shifts, and calculation of various algebraic functions. The same functional unit hardware may be utilized to perform different operations, and any combination of functional units may exist.

[0211] The instructions transmitted to the processing cluster 1914 constitute threads. A collection of threads executed across a collection of parallel processing engines is a thread group. A thread group executes the same program on different input data. Each thread within a thread group may be assigned to a different processing engine within the graphics multiprocessor 1934. A thread group may include fewer threads than the number of processing engines within the graphics multiprocessor 1934. When a thread group includes fewer threads than the number of processing engines, one or more of the processing engines may be idle during the cycle during which the thread group is being processed. A thread group may also include more threads than the number of processing engines within the graphics multiprocessor 1934. When a thread group includes more threads than the number of processing engines within the graphics multiprocessor 1934, processing may be performed in consecutive clock cycles. Optionally, multiple thread groups may be executed concurrently on the graphics multiprocessor 1934.

[0212] The graphics multiprocessor 1934 may include internal cache memory to perform load and store operations. Optionally, the graphics multiprocessor 1934 may abandon the internal cache and use cache memory (e.g., first level (level 1, L1) cache 1948) within the processing cluster 1914. Each graphics multiprocessor 1934 also has a partition unit (e.g., Fig.19A 1920A-1920N), which are shared between all processing clusters 1914 and can be used to transfer data between threads. Graphics multiprocessor 1934 can also access off-chip global memory, which can include one or more of local parallel processor memory and / or system memory. Any memory external to parallel processing unit 1902 can be used as global memory. Embodiments in which processing cluster 1914 includes multiple instances of graphics multiprocessor 1934 can share common instructions and data, which can be stored in L1 cache 1948.

[0213] Each processing cluster 1914 may include an MMU 1945 (memory management unit) configured to map virtual addresses to physical addresses. In other examples, one or more instances of MMU 1945 may reside in Fig.19A 1918. The MMU 1945 includes a set of page table entries (PTEs) for mapping virtual addresses to physical addresses of the slice, and optionally includes a cache line index. The MMU 1945 may include an address translation lookaside buffer (TLB) or cache that may reside within the graphics multiprocessor 1934 or L1 cache 1948 of the processing cluster 1914. The physical addresses are processed to distribute surface data access locality, thereby allowing efficient request interleaving between partition units. The cache line index can be used to determine whether a request for a cache line is a hit or a miss.

[0214] In graphics and compute applications, the processing clusters 1914 may be configured such that each graphics multiprocessor 1934 is coupled to a texture unit 1936 for performing texture mapping operations, such as determining texture sample locations, reading texture data, and filtering texture data. Texture data is read from an internal texture L1 cache (not shown), or in some examples, from an L1 cache within the graphics multiprocessor 1934 and retrieved from an L2 cache, local parallel processor memory, or system memory as needed. Each graphics multiprocessor 1934 outputs processed tasks to a data crossbar 1940 to provide the processed tasks to another processing cluster 1914 for further processing, or to store the processed tasks in an L2 cache, local parallel processor memory, or system memory via a memory crossbar 1916. A pre-raster operations unit 1942 is configured to receive data from the graphics multiprocessor 1934, direct the data to ROP units, which may be coupled to partition units (e.g., Fig.19A The preROP 1942 unit may perform optimizations for color blending, organize pixel color data, and perform address translation.

[0215] It will be appreciated that the core architecture described herein is illustrative, and variations and modifications are possible. Any number of processing units (e.g., graphics multiprocessors 1934, texture units 1936, preROPs 1942, etc.) may be included within a processing cluster 1914. Further, while only one processing cluster 1914 is shown, a parallel processing unit as described herein may include any number of instances of a processing cluster 1914. Optionally, each processing cluster 1914 may be configured to operate independently of other processing clusters 1914 using separate and distinct processing units, L1 caches, L2 caches, etc.

[0216] Fig.19D An example of a graphics multiprocessor 1934 is shown, where the graphics multiprocessor 1934 is coupled to a pipeline manager 1932 of a processing cluster 1914. The graphics multiprocessor 1934 has an execution pipeline that includes, but is not limited to, an instruction cache 1952, an instruction unit 1954, an address mapping unit 1956, a register file 1958, one or more general purpose graphics processing unit (GPGPU) cores 1962, and one or more load / store units 1966. The GPGPU cores 1962 and the load / store units 1966 are coupled to a cache memory 1972 and a shared memory 1970 via a memory and cache interconnect 1968. The graphics multiprocessor 1934 may additionally include a tensor and / or ray tracing core 1963 that includes hardware logic for accelerating matrix and / or ray tracing operations.

[0217] The instruction cache 1952 may receive an instruction stream to be executed from the pipeline manager 1932. The instructions are cached in the instruction cache 1952 and dispatched for execution by the instruction unit 1954. The instruction unit 1954 may dispatch the instructions as a thread group (e.g., a unit group (warp)), wherein each thread in the thread group is assigned to a different execution unit within the GPGPU core 1962. The instruction may access any of the local address space, the shared address space, or the global address space by specifying an address within the unified address space. The address mapping unit 1956 may be used to translate the address in the unified address space into different memory addresses that may be accessed by the load / store unit 1966.

[0218] The register file 1958 provides a collection of registers for the functional units of the graphics multiprocessor 1934. The register file 1958 provides temporary storage for operands of data paths connected to the functional units of the graphics multiprocessor 1934 (e.g., GPGPU core 1962, load / store unit 1966). The register file 1958 may be divided between each of the functional units so that each functional unit is assigned a dedicated portion of the register file 1958. For example, the register file 1958 may be divided between different groups of units executed by the graphics multiprocessor 1934.

[0219] The GPGPU cores 1962 may each include a floating point unit (FPU) and / or an integer arithmetic logic unit (ALU) for executing instructions of the graphics multiprocessor 1934. In some implementations, the GPGPU core 1962 may include hardware logic that may otherwise reside within the tensor and / or ray tracing core 1963. The GPGPU cores 1962 may be similar in architecture, or may be different in architecture. For example and in some examples, the first portion of the GPGPU core 1962 includes a single-precision FPU and an integer ALU, while the second portion of the GPGPU core includes a double-precision FPU. Optionally, the FPU may implement the IEEE 754-2008 standard for floating-point arithmetic, or enable variable-precision floating-point arithmetic. The graphics multiprocessor 1934 may additionally include one or more fixed-function or special-function units for performing specific functions, such as copying rectangles or pixel blending operations. One or more of the GPGPU cores in the GPGPU core may also include fixed-function or special-function logic.

[0220] GPGPU core 1962 may include SIMD logic capable of executing a single instruction to multiple sets of data. Optionally, GPGPU core 1962 may physically execute SIMD4, SIMD8 and SIMD16 instructions, and logically execute SIMD1, SIMD2 and SIMD32 instructions. SIMD instructions for GPGPU cores may be generated by a shader compiler at compile time, or automatically generated when executing a program written and compiled for a single program multiple data (SPMD) or SIMT architecture. Multiple threads of a program configured for a SIMT execution model may be executed via a single SIMD instruction. For example and in some examples, eight SIMT threads may be executed in parallel via a single SIMD8 logic unit, and these eight SIMT threads perform the same or similar operations.

[0221] The memory and cache interconnect 1968 is an interconnect network that connects each of the functional units of the graphics multiprocessor 1934 to the register file 1958 and to the shared memory 1970. For example, the memory and cache interconnect 1968 is a crossbar interconnect that allows the load / store unit 1966 to implement load and store operations between the shared memory 1970 and the register file 1958. The register file 1958 can operate at the same frequency as the GPGPU core 1962, so data transfers between the GPGPU core 1962 and the register file 1958 are very low latency. The shared memory 1970 can be used to enable communication between threads executing on the functional units within the graphics multiprocessor 1934. The cache memory 1972 can be used as a data cache, for example, to cache texture data passed between the functional unit and the texture unit 1936. The shared memory 1970 can also be used as a managed cached program. The shared memory 1970 and the cache memory 1972 can be coupled with the data crossbar 1940 to enable communication with other components of the processing cluster. Threads executing on GPGPU core 1962 can programmatically store data in shared memory in addition to automatically cached data stored in cache memory 1972.

[0222] Figure 20A-20C An additional graphics multiprocessor is illustrated according to an example. Figure 20A-20B The graphics multiprocessors 2025 and 2050 are shown in the figure. The graphics multiprocessors 2025 and 2050 are Fig.19C The graphics multiprocessor 1934 of FIG. 1 is related to the graphics multiprocessor 1934 of FIG. 1 and can be used instead of one of those graphics multiprocessors. Therefore, the disclosure of any feature in this article in conjunction with the graphics multiprocessor 1934 also discloses the corresponding combination with the graphics multiprocessors 2025 and 2050, but is not limited to this. Fig. 20C A graphics processing unit (GPU) 2080 is illustrated, which includes a collection of dedicated graphics processing resources arranged as multi-core groups 2065A-2065N, which correspond to the graphics multiprocessors 2025, 2050. The illustrated graphics multiprocessors 2025, 2050 and multi-core groups 2065A-2065N may be streaming multiprocessors (SMs) capable of executing a large number of execution threads simultaneously.

[0223] Fig. 20A The graphics multiprocessor 2025 includes relative Fig.19DThe graphics multiprocessor 2025 may include multiple additional instances of execution resource units of the graphics multiprocessor 1934. For example, the graphics multiprocessor 2025 may include multiple instances of instruction units 2032A-2032B, register files 2034A-2034B, and (one or more) texture units 2044A-2044B. The graphics multiprocessor 2025 also includes multiple sets of graphics or compute execution units (e.g., GPGPU cores 2036A-2036B, tensor cores 2037A-2037B, ray tracing cores 2038A-2038B) and multiple sets of load / store units 2040A-2040B. The execution resource units have a common instruction cache 2030, texture and / or data cache memory 2042, and shared memory 2046.

[0224] The components may communicate via the interconnect fabric 2027. The interconnect fabric 2027 may include one or more crossbar switches to enable communication between the components of the graphics multiprocessor 2025. The interconnect fabric 2027 is a separate, high-speed network fabric layer on which each component of the graphics multiprocessor 2025 is stacked. The components of the graphics multiprocessor 2025 communicate with remote components via the interconnect fabric 2027. For example, the cores 2036A-2036B, 2037A-2037B, and 2038A-2038B may each communicate with the shared memory 2046 via the interconnect fabric 2027. The interconnect fabric 2027 may arbitrate communications within the graphics multiprocessor 2025 to ensure fair bandwidth allocation between components.

[0225] Fig. 20B The graphics multiprocessor 2050 includes a plurality of execution resource sets 2056A-2056D, wherein Fig.19D and Fig. 20A As shown in FIG. 1 , each set of execution resources includes multiple instruction units, register files, GPGPU cores, and load storage units. Execution resources 2056A-2056D can work in conjunction with (one or more) texture units 2060A-2060D for texture operations while sharing instruction cache 2054 and shared memory 2053. For example, execution resources 2056A-2056D can share multiple instances of instruction cache 2054 and shared memory 2053 and texture and / or data cache memory 2058A-2058B. Each component can be connected to the CPU via the CPU. Fig. 20A The interconnect structure 2027 communicates with a similar interconnect structure 2052 .

[0226] Those skilled in the art will understand that Fig.18 , Figures 19A-19D as well as Figure 20A-20BThe architecture described in is illustrative and not limiting in scope of the current examples. Thus, the techniques described herein may be implemented on any appropriately configured processing unit without departing from the scope of the examples described herein, including but not limited to: one or more mobile application processors; one or more desktop or server central processing units (CPUs), including multi-core CPUs; one or more parallel processor units, such as, Fig.19A Parallel processing unit 1902 and one or more graphics processors or special processing units.

[0227] The parallel processor or GPGPU described herein can be communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. The GPU can be communicatively coupled to the host processor / core via a bus or another interconnect (e.g., a high-speed interconnect, such as PCIe, NVLink, or other known protocols, standardized protocols, or proprietary protocols). In other examples, the GPU can be integrated on the same package or chip as the core and communicatively coupled to the core via an internal processor bus / interconnect (i.e., inside the package or chip). Regardless of the manner in which the GPU is connected, the processor core can assign work to the GPU in the form of a sequence of commands / instructions contained in a work descriptor. The GPU then uses a dedicated circuit system / logic to efficiently process these commands / instructions.

[0228] Fig. 20C A graphics processing unit (GPU) 2080 is shown, which includes a dedicated set of graphics processing resources arranged as multi-core groups 2065A-2065N. Although details of only a single multi-core group 2065A are provided, it will be appreciated that other multi-core groups 2065B-2065N may be equipped with the same or similar set of graphics processing resources. The details described with respect to multi-core groups 2065A-2065 may also be applied to any graphics multiprocessor 1934, 2025, 2050 described herein.

[0229] As illustrated, the multi-core group 2065A may include a set of graphics cores 2070, a set of tensor cores 2071, and a set of ray tracing cores 2072. The scheduler / dispatcher 2068 schedules and dispatches the graphics thread for execution on the respective cores 2070, 2071, 2072. The set of register files 2069 stores operand values ​​used by the cores 2070, 2071, 2072 when executing the graphics thread. These register files may include, for example, integer registers for storing integer values, floating point registers for storing floating point values, vector registers for storing packed data elements (integer and / or floating point data elements), and slice registers for storing tensor / matrix values. The slice registers may be implemented as a combined set of vector registers.

[0230] One or more combined first level (L1) caches and shared memory units 2073 store graphics data locally within each multi-core group 2065A, such as texture data, vertex data, pixel data, light data, bounding volume data, etc. One or more texture units 2074 may also be used to perform texture operations, such as texture mapping and sampling. A second level (L2) cache 2075 shared by all multi-core groups 2065A-2065N or a subset of multi-core groups 2065A-2065N stores graphics data and / or instructions for multiple concurrent graphics threads. As shown, the L2 cache 2075 may be shared across multiple multi-core groups 2065A-2065N. One or more memory controllers 2067 couple the GPU 2080 to a memory 2066, which may be a system memory (e.g., DRAM) and / or a dedicated graphics memory (e.g., GDDR6 memory).

[0231] The input / output (I / O) circuit system 2063 couples the GPU 2080 to one or more I / O devices 2062, such as a digital signal processor (DSP), a network controller, or a user input device. On-chip interconnects may be used to couple the I / O devices 2062 to the GPU 2080 and memory 2066. One or more I / O memory management units (IOMMUs) 2064 of the I / O circuit system 2063 directly couple the I / O devices 2062 to the system memory 2066. Optionally, the IOMMUs 2064 manage multiple sets of page tables for mapping virtual addresses to physical addresses in the system memory 2066. The I / O devices 2062, the CPU(s) 2061, and the GPU(s) 2080 may then share the same virtual address space.

[0232] In one implementation of the IOMMU 2064, the IOMMU 2064 supports virtualization. In this case, the IOMMU 2064 can manage a first set of page tables for mapping guest / graphics virtual addresses to guest / graphics physical addresses and a second set of page tables for mapping guest / graphics physical addresses to system / host physical addresses (e.g., within system memory 2066). The base address of each of the first set of page tables and the second set of page tables can be stored in a control register and swapped out at context switch (e.g., so that the new context is provided with access to the relevant set of page tables). Although not described in detail in the prior art, the IOMMU 2064 can manage a first set of page tables for mapping guest / graphics virtual addresses to guest / graphics physical addresses and a second set of page tables for mapping guest / graphics physical addresses to system / host physical addresses (e.g., within system memory 2066). Fig. 20C , but each of the cores 2070, 2071, 2072 and / or multi-core groups 2065A-2065N may include a translation lookaside buffer (TLB) for caching guest virtual to guest physical translations, guest physical to host physical translations, and guest virtual to host physical translations.

[0233] (One or more) CPU 2061, GPU 2080 and I / O device 2062 can be integrated on a single semiconductor chip and / or chip package. The illustrated memory 2066 can be integrated on the same chip, or can be coupled to a memory controller 2067 via an off-chip interface. In one implementation, memory 2066 includes GDDR6 memory that shares the same virtual address space as other physical system-level memories, but the basic principles described herein are not limited to this particular implementation.

[0234] Tensor core 2071 may include multiple execution units specifically designed to perform matrix operations, which are basic computational operations for performing deep learning operations. For example, synchronized matrix multiplication operations may be used for neural network training and inference. Tensor core 2071 may perform matrix processing using a variety of operand precisions, including single-precision floating point (e.g., 32 bits), half-precision floating point (e.g., 16 bits), integer words (16 bits), bytes (8 bits), and half bytes (4 bits). For example, a neural network implementation extracts features of each rendered scene, potentially combining details from multiple frames to build a high-quality final image.

[0235] In a deep learning implementation, parallel matrix multiplication work may be scheduled for execution on the tensor core 2071. The training of neural networks in particular requires a large number of matrix dot product operations. To handle the inner product formulation of the N x N x N matrix multiplication, the tensor core 2071 may include at least N dot product processing elements. Before the matrix multiplication begins, a complete matrix is ​​loaded into the slice register, and for each of the N cycles, at least one column of the second matrix is ​​loaded. For each cycle, there are N dot products that are processed.

[0236] Depending on the specific implementation, matrix elements can be stored with different precisions, including 16-bit words, 8-bit bytes (e.g., INT8), and 4-bit nibbles (e.g., INT4). Different precision modes can be specified for the Tensor Core 2071 to ensure that the most efficient precision is used for different workloads (e.g., such as inference workloads, which can tolerate quantization to bytes and nibbles). Supported formats additionally include 64-bit floating point (FP64) and non-IEEE floating point formats, such as the bfloat16 format (e.g., Brain floating point), a 16-bit floating point format with one sign bit, eight exponent bits, and eight significand bits (seven of which are explicitly stored). An example includes support for a reduced precision tensor floating point (TF32) mode that performs calculations using the range of FP32 (8 bits) and the precision of FP16 (10 bits). Reduced-precision TF32 operations can be performed on FP32 inputs and produce FP32 outputs with higher performance relative to FP32 and increased precision relative to FP16. In some examples, one or more 8-bit floating point formats (FP32) are supported.

[0237] In some examples, the tensor core 2071 supports sparse operation modes for matrices in which the vast majority of values ​​are zero. The tensor core 2071 includes support for sparse input matrices encoded with sparse matrix representations (e.g., coordinate list encoding (COO), compressed sparse rows (CSR), compressed sparse columns (CSC), etc.). The tensor core 2071 also includes support for compressed sparse matrix representations in the case where the sparse matrix representation can be further compressed. Compressed matrix data, encoded matrix data, and / or compressed and encoded matrix data and associated compression and / or encoding metadata can be read by the tensor core 2071, and non-zero values ​​can be extracted. For example, for a given input matrix A, non-zero values ​​can be loaded from at least a portion of the compressed and / or encoded representation of matrix A. Based on the position of the non-zero value in matrix A (which can be determined from the index or coordinate metadata associated with the non-zero value), the corresponding value in the input matrix B can be loaded. Depending on the operation to be performed (e.g., multiplication), loading values ​​from input matrix B may be bypassed if the corresponding value is a zero value. In some examples, the pairing of values ​​for certain operations (such as multiplication operations) may be pre-scanned by the scheduler logic, and only operations between non-zero inputs are scheduled. Depending on the dimensions of matrix A and matrix B and the operation to be performed, the output matrix C may be dense or sparse. In the case where the output matrix C is sparse and depending on the configuration of the tensor core 2071, the output matrix C may be output in a compressed format, sparse coding, or compressed sparse coding.

[0238] The ray tracing core 2072 can accelerate ray tracing operations for both real-time ray tracing implementations and non-real-time ray tracing implementations. Specifically, the ray tracing core 2072 may include a ray traversal / intersection circuit system that uses a bounding volume hierarchy (BVH) to perform ray traversals and identify intersections between rays and primitives enclosed within the BVH volume. The ray tracing core 2072 may also include circuit systems for performing depth testing and culling (e.g., using a Z buffer or similar arrangement). In one implementation, the ray tracing core 2072 performs traversal and intersection operations in conjunction with the image denoising techniques described herein, at least portions of which may be performed on the tensor core 2071. For example, the tensor core 2071 may implement a deep learning neural network to perform denoising on frames generated by the ray tracing core 2072. However, the CPU(s) 2061, graphics core 2070, and / or ray tracing core 2072 may also implement all or portions of the denoising and / or deep learning algorithms.

[0239] In addition, as described above, a distributed approach to noise reduction may be employed, wherein GPU 2080 is in a computing device coupled to other computing devices via a network or high-speed interconnect. According to the distributed approach, the interconnected computing devices may share neural network learning / training data to improve the speed at which the entire system learns to perform noise reduction for different types of image frames and / or different graphics applications.

[0240] The ray tracing core 2072 can handle all BVH traversals and / or ray-primitive intersections, thereby preventing the graphics core 2070 from being overloaded with thousands of instructions for each ray. For example, each ray tracing core 2072 includes a first set of specialized circuit systems for performing bounding box tests (e.g., for traversal operations) and / or a second set of specialized circuit systems for performing ray-triangle intersection tests (e.g., intersecting rays that have been traversed). Thus, for example, the multi-core group 2065A can simply start ray detection, and the ray tracing core 2072 independently performs ray traversals and intersections and returns hit data (e.g., hits, no hits, multiple hits, etc.) to the thread context. While the ray tracing core 2072 performs traversal and intersection operations, the other cores 2070, 2071 are freed up to perform other graphics or computational work.

[0241] Optionally, each ray tracing core 2072 may include a traversal unit for performing BVH test operations and / or an intersection unit for performing ray-primitive intersection tests. The intersection unit generates a "hit", "no hit", or "multiple hits" response, which it provides to the appropriate thread. During traversal and intersection operations, execution resources of other cores (e.g., graphics core 2070 and tensor core 2071) are freed up to perform other forms of graphics work.

[0242] In some of the examples described below, a hybrid rasterization / ray tracing approach is used in which the work is distributed between graphics core 2070 and ray tracing core 2072.

[0243] The ray tracing core 2072 (and / or other cores 2070, 2071) may include hardware support for ray tracing instruction sets, such as Microsoft's DirectX Ray Tracing (DXR), which includes the DispatchRays command; and ray generation shaders, nearest hit shaders, any hit shaders, and miss shaders, which enable unique shader and texture sets to be assigned to each object. Another ray tracing platform that can be supported by the ray tracing core 2072, graphics core 2070, and tensor core 2071 is the Vulkan API (e.g., Vulkan version 1.1.85, or later). However, it should be noted that the basic principles described herein are not limited to any particular ray tracing ISA.

[0244] In general, each core 2072, 2071, 2070 may support a ray tracing instruction set including instructions / functions for one or more of the following: ray generation, nearest hit, any hit, ray-primitive intersection, per-primitive and hierarchy bounding box construction, misses, visits, and exceptions. More specifically, some examples include ray tracing instructions for performing one or more of the following functions: Ray Generation - Ray generation instructions can be executed for each pixel, sample, or other user-defined work assignment. Closest Hit - Closest hit instructions can be executed to locate the closest intersection of a ray with a primitive within the scene. Any Hit - The Any Hit directive identifies multiple intersections between rays and primitives within the scene, potentially identifying a new closest intersection point. Intersect - The Intersect command performs a ray-primitive intersection test and outputs the result. Per-primitive bounding box construction - This instruction builds a bounding box around a given primitive or group of primitives (e.g., when building a new BVH or other acceleration data structure). Miss - Indicates that the ray missed the scene or all geometry within a specified area of ​​the scene. Visits – Indicates the subvolumes that the ray will traverse. Exceptions - includes various types of exception handlers (eg, called for various error conditions).

[0245] In some examples, the ray tracing core 2072 may be adapted to accelerate general computing operations that can be accelerated using computing techniques similar to ray intersection testing. A computing framework may be provided that enables shader programs to be compiled into low-level instructions and / or primitives that perform general computing operations via the ray tracing core. Exemplary computing problems that may benefit from computing operations performed on the ray tracing core 2072 include calculations involving the propagation of beams, waves, rays, or particles in a coordinate space. Interactions associated with that propagation may be calculated relative to geometry or meshes in the coordinate space. For example, calculations associated with the propagation of electromagnetic signals through an environment may be accelerated using instructions or primitives that are executed via the ray tracing core. Refraction and reflection of signals through objects in the environment may be calculated as direct ray tracing simulations.

[0246] The ray tracing core 2072 can also be used to perform calculations that are not directly similar to ray tracing. For example, the ray tracing core 2072 can be used to accelerate mesh projection, mesh refinement, and volume sampling calculations. General coordinate space calculations, such as nearest neighbor calculations, can also be performed. For example, a set of points near a given point can be found by defining a bounding box around the given point in the coordinate space. The BVH and ray detection logic in the ray tracing core 2072 can then be used to determine the set of points that intersect within the bounding box. The intersection constitutes the origin and the nearest neighbor of that origin. The calculations performed using the ray tracing core 2072 can be performed in parallel with the calculations performed on the graphics core 2072 and the tensor core 2071. The shader compiler can be configured to compile a compute shader or other general graphics processing program into a low-level primitive that can be parallelized across the graphics core 2070, the tensor core 2071, and the ray tracing core 2072.

[0247] Building larger and larger silicon dies is challenging for various reasons. As silicon dies get larger, manufacturing yields become smaller, and process technology requirements for different components may vary. On the other hand, in order to have a high-performance system, key components should be interconnected through high-speed, high-bandwidth, low-latency interfaces. These conflicting requirements bring challenges to high-performance chip development.

[0248] The embodiments described herein provide techniques for separating the architecture of a system-on-chip integrated circuit into multiple different chiplets that can be packaged onto a common substrate. In some examples, a graphics processing unit or a parallel processor is composed of various silicon chiplets that are manufactured separately. A chiplet is an integrated circuit that is at least partially packaged, and the at least partially packaged integrated circuit includes different logic units that can be assembled into a larger package with other chiplets. Various chiplet collections with different IP core logic can be assembled into a single device. In addition, the chiplets can be integrated into a base die or base chiplet using active interposer technology. The concepts described herein enable interconnection and communication between different forms of IP within a GPU. IP development on different processes can be mixed. This avoids the complexity of converging multiple IPs to the same process, especially for large SoCs with several styles of IP.

[0249] Enabling the use of multiple process technologies improves time to market and provides a cost-effective way to create multiple product SKUs. For customers, this means getting a product that better suits their requirements in a cost-effective and timely manner. Additionally, the split IP is easier to modify to be independently power-gated, and components that are not in use for a given workload can be turned off, reducing overall power consumption.

[0250] Fig.21 A parallel computing system 2100 according to some examples is shown. In some examples, the parallel computing system 2100 includes a parallel processor 2120, which may be a graphics processor or a computing accelerator as described herein. The parallel processor 2120 includes a global logic unit 2101, an interface 2102, a thread dispatcher 2103, a media unit 2104, a set of computing units 2105A-2105H, and a cache / memory unit 2106. In some examples, the global logic unit 2101 includes global functions for the parallel processor 2120, including device configuration registers, a global scheduler, power management logic, and the like. The interface 2102 may include a front-end interface for the parallel processor 2120. The thread dispatcher 2103 may receive a workload from the interface 2102 and dispatch threads of the workload to the computing units 2105A-2105H. If the workload includes any media operations, at least part of those operations may be performed by the media unit 2104. The media unit may also migrate some operations to the compute units 2105A-2105H. The cache / memory unit 2106 may include cache memory (eg, L3 cache) and local memory (eg, HBM, GDDR) for the parallel processors 2120.

[0251] Figure 22A-22BIllustrate a hybrid logical / physical view of a split parallel processor according to examples described herein. Fig.22A The diagram shows a split parallel computing system 2200 . Fig. 22B A chiplet 2230 of the split parallel computing system 2200 is shown.

[0252] like Fig.22A As shown in , the separate computing system 2200 may include a parallel processor 2220, wherein the components of the parallel processor SOC are distributed across multiple chiplets. Each chiplet may be a different IP core that is independently designed and configured to communicate with other chiplets via one or more common interfaces. The chiplets include, but are not limited to, a computing chiplet 2205, a media chiplet 2204, and a memory chiplet 2206. Each chiplet can be manufactured separately using different process technologies. For example, the computing chiplet 2205 can be manufactured using the smallest or most advanced process technology available at the time of manufacturing, while the memory chiplet 2206 or other chiplets (e.g., I / O, networking, etc.) can be manufactured using larger or less advanced process technologies.

[0253] The individual chiplets may be bonded to a base die 2210 and configured to communicate with each other and logic within the base die 2210 via an interconnect layer 2212. In some examples, the base die 2210 may include a global logic 2201, which may include a scheduler 2211 and power management 2221 logic unit, an interface 2202, a dispatch unit 2203, and an interconnect fabric module 2208 coupled or integrated with one or more L3 cache blocks 2209A-2209N. The interconnect fabric 2208 may be an inter-chiplet fabric integrated into the base die 2210. The logic chiplets may use the fabric 2208 to relay messages between the individual chiplets. Additionally, the L3 cache blocks 2209A-2209N in the base die and / or the L3 cache blocks within the memory chiplet 2206 may cache data read from the DRAM chiplets within the memory chiplet 2206 and transferred to the DRAM chiplets and to the system memory of the host.

[0254] In some examples, the global logic 2201 is a microcontroller that can execute firmware to perform scheduler 2211 and power management 2221 functions for the parallel processor 2220. The microcontroller that executes the global logic can be customized for the target use case of the parallel processor 2220. The scheduler 2211 can perform global scheduling operations for the parallel processor 2220. The power management 2221 function can be used to enable or disable individual chiplets within the parallel processor when those chiplets are not in use.

[0255] The individual chiplets of the parallel processor 2220 may be designed to perform specific functions that would be integrated into a single die in existing designs. The collection of compute chiplets 2205 may include a cluster of compute units (e.g., execution units, streaming multiprocessors, etc.) that include programmable logic for executing compute or graphics shader instructions. The media chiplet 2204 may include hardware logic for accelerating media encoding and decoding operations. The memory chiplet 2206 may include volatile memory (e.g., DRAM) and one or more SRAM cache memory blocks (e.g., L3 blocks).

[0256] like Fig. 22B As shown in , each chiplet 2230 may include common components and dedicated components. The chiplet logic 2236 within the chiplet 2230 may include specific components of the chiplet, such as an array of streaming multiprocessors, computing units, or execution units described herein. The chiplet logic 2236 may be coupled with an optional cache or shared local memory 2238, or a cache or shared local memory may be included within the chiplet logic 2236. The chiplet 2230 may include a fabric interconnect node 2242 that receives commands via an inter-chiplet structure. Commands and data received via the fabric interconnect node 2242 may be temporarily stored in an interconnect buffer 2239. Data transmitted to and received from the fabric interconnect node 2242 may be stored in the interconnect cache 2240. Power control 2232 and clock control 2234 logic may also be included in the chiplet. The power control 2232 and clock control 2234 logic may receive configuration commands via the structure and may configure dynamic voltage and frequency scaling for the chiplet 2230. In some examples, each chiplet can have independent clock and power domains and can be clock-gated and power-gated independently of other chiplets.

[0257] At least some of the components within the illustrated chiplet 2230 may also be included in a Fig.22A The base die 2210 may be within logic within the base die 2210. For example, logic within the base die that communicates with the fabric may include some version of the fabric interconnect node 2242. The base die logic that may be independently clock gated or power gated may include some version of the power control 2232 and / or clock control 2234 logic.

[0258] Thus, while various examples described herein use the term SOC to describe devices and systems having a processor and associated circuitry (e.g., input / output (“I / O”) circuitry, power delivery circuitry, memory circuitry, etc.) monolithically integrated into a single integrated circuit (“Integrated Circuit”) die or chip, the present disclosure is not limited in this respect. For example, in various examples of the present disclosure, a device or system may have one or more processors (e.g., one or more processor cores) and associated circuitry (e.g., input / output (“I / O”) circuitry, power delivery circuitry, etc.) arranged in a discrete collection of discrete dies, slices, and / or chiplets (e.g., one or more discrete processor core dies arranged adjacent to one or more other dies (such as a memory die, an I / O die, etc.)). In such discrete devices and systems, individual dies, slices, and / or chiplets may be physically and / or electrically coupled together by a packaging structure including, for example, individual packaging substrates, interposers, active interposers, photonic interposers, interconnect bridges, etc. A discrete collection of discrete dies, slices, and / or chiplets may also be part of a System-on-Package ("SoP").

[0259] Example Core Architecture - In-order and Out-of-order Core Block Diagram

[0260] Fig.23A The block diagram of illustrates both an example in-order pipeline and an example register renaming, out-of-order issue / execution pipeline according to an example. Fig. 23B The block diagram of illustrates both an example in-order architecture core and an example register renaming, out-of-order issue / execution architecture core to be included in a processor, according to an example. Fig.23A - Fig. 23B The solid line boxes in illustrate the in-order pipeline and in-order core, while the optionally added dashed line boxes illustrate the register renaming, out-of-order issue / execution pipeline and core. Considering that the in-order aspect is a subset of the out-of-order aspect, the out-of-order aspect will be described.

[0261] exist Fig.23A, the processor pipeline 2300 includes a fetch stage 2302, an optional length decode stage 2304, a decode stage 2306, an optional allocation (Alloc) stage 2308, an optional rename stage 2310, a dispatch (also called dispatch or issue) stage 2312, an optional register read / memory read stage 2314, an execute stage 2316, a write back / memory write stage 2318, an optional exception handling stage 2322, and an optional commit stage 2324. One or more operations may be performed in each of these processor pipeline stages. For example, during the fetch stage 2302, one or more instructions are fetched from the instruction memory, and during the decode stage 2306, the fetched one or more instructions may be decoded, an address using a forwarding register port (e.g., a load store unit (LSU) address) may be generated, and branch forwarding (e.g., an immediate offset or a link register (LR)) may be performed. In some examples, the decode stage 2306 and the register read / memory read stage 2314 can be combined into one pipeline stage. In some examples, during the execute stage 2316, decoded instructions can be executed, LSU address / data pipelining to an Advanced Microcontroller Bus (AMB) interface can be performed, multiplication and addition operations can be performed, arithmetic operations with branch results can be performed, and the like.

[0262] As an example, Fig. 23B An example register renaming, out-of-order issue / execution architecture core may implement pipeline 2300 in the following manner: 1) instruction fetch circuit system 2338 performs fetch and length decoding stages 2302 and 2304; 2) decoding circuit system 2340 performs decoding stage 2306; 3) rename / allocator unit circuit system 2352 performs allocation stage 2308 and rename stage 2310; 4) (one or more) scheduler circuit system 2356 performs scheduling stage 2312; 5) (one or more) physical register file circuit system System 2358 and memory unit circuit system 2370 perform register read / memory read phase 2314; execution cluster 2360 performs execution phase 2316; 6) memory unit circuit system 2370 and (one or more) physical register file circuit system 2358 perform write back / memory write phase 2318; 7) various circuit systems may be involved in the exception handling phase 2322; and 8) retirement unit circuit system 2354 and (one or more) physical register file circuit system 2358 perform commit phase 2324.

[0263] Fig. 23BProcessor core 2390 is shown to include front end unit circuitry 2330 coupled to execution engine unit circuitry 2350, and both are coupled to memory unit circuitry 2370. Core 2390 may be a reduced instruction set computing (RISC) core, a complex instruction set computing (CISC) core, a very long instruction word (VLIW) core, or a hybrid or alternative core type. As another option, core 2390 may be a special purpose core, such as a network or communication core, a compression engine, a coprocessor core, a general purpose computing graphics processing unit (GPGPU) core, a graphics core, and the like.

[0264] The front end unit circuit system 2330 may include a branch prediction circuit system 2332, which is coupled to an instruction cache unit circuit system 2334, which is coupled to an instruction translation lookaside buffer (TLB) 2336, which is coupled to an instruction fetch circuit system 2338, which is coupled to a decoding circuit system 2340. In some examples, the instruction cache circuit system 2334 is included in the memory unit circuit system 2370 instead of the front end circuit system 2330. The decoding circuit system 2340 (or decoder) can decode the instruction and generate one or more micro-operations, micro-code entry points, micro-instructions, other instructions or other control signals as output, which are decoded from the original instruction, or otherwise reflect the original instruction, or are derived from the original instruction. The decoding circuit system 2340 may also include an address generation unit (AGU, not shown) circuit system. In some examples, the AGU uses the forwarded register port to generate the LSU address and may further perform branch forwarding (e.g., immediate offset branch forwarding, LR register branch forwarding, etc.). The decode circuit system 2340 may be implemented using a variety of different mechanisms. Examples of suitable mechanisms include, but are not limited to, lookup tables, hardware implementations, programmable logic arrays (PLA), microcode read only memory (ROM), and the like. In some examples, the core 2390 includes a microcode ROM (not shown) or other medium that stores microcode for certain macroinstructions (e.g., in the decode circuit system 2340 or otherwise within the front end circuit system 2330). In some examples, the decode circuit system 2340 includes a micro-op or operation cache (not shown) to save / cache decoded operations, micro-tags, or micro-operations generated during decoding or other stages of the processor pipeline 2300. The decode circuit system 2340 may be coupled to the rename / allocator unit circuit system 2352 in the execution engine circuit system 2350.

[0265] Execution engine circuitry 2350 includes rename / allocator unit circuitry 2352, which is coupled to retirement unit circuitry 2354 and a set of one or more scheduler circuitry 2356. Scheduler circuitry 2356 represents any number of different schedulers, including reservation stations, central instruction windows, etc. In some examples, scheduler circuitry(s) 2356 may include an arithmetic logic unit (ALU) scheduler / scheduling circuitry, an ALU queue, an address generation unit (AGU) scheduler / scheduling circuitry, an AGU queue, etc. Scheduler circuitry(s) 2356 are coupled to physical register file(s) circuitry 2358. Each of the (one or more) physical register file circuit systems 2358 represents one or more physical register files, different ones of which store one or more different data types, such as scalar integers, scalar floating points, packed integers, packed floating points, vector integers, vector floating points, status (e.g., instruction pointers, i.e., the address of the next instruction to be executed), etc. In some examples, the (one or more) physical register file circuit systems 2358 include vector register unit circuit systems, write mask register unit circuit systems, and scalar register unit circuit systems. These register units can provide architectural vector registers, vector mask registers, general registers, etc. The (one or more) physical register cell file circuit systems 2358 are coupled to the retirement unit circuit system 2354 (also called retirement queue) overlap to demonstrate various ways that register renaming and out-of-order execution can be implemented (e.g., using (one or more) reorder buffers (ROBs) and (one or more) retirement register files; using (one or more) future stacks, (one or more) history buffers, and (one or more) retirement register files; using register maps and pools of registers; etc.). Retirement unit circuitry 2354 and physical register file(s) circuitry 2358 are coupled to execution cluster(s) 2360. Execution cluster(s) 2360 include a set of one or more execution unit circuitry 2362 and a set of one or more memory access circuitry 2364. Execution unit circuitry 2362 may perform various arithmetic, logical, floating point, or other types of operations (e.g., shifts, additions, subtractions, multiplications) on various types of data (e.g., scalar integer, scalar floating point, packed integer, packed floating point, vector integer, vector floating point).While some examples may include several execution units or execution unit circuit systems dedicated to a particular function or set of functions, other examples may include only one execution unit circuit system or multiple execution units / execution unit circuit systems that all perform all functions. (One or more) scheduler circuit systems 2356, (one or more) physical register file circuit systems 2358, and (one or more) execution clusters 2360 are shown as possibly multiple because some examples create separate pipelines for certain types of data / operations (e.g., scalar integer pipelines, scalar floating point / packed integer / packed floating point / vector integer / vector floating point pipelines, and / or memory access pipelines, each of which has its own scheduler circuit system, (one or more) physical register file circuit systems, and / or execution clusters - and in the case of a separate memory access pipeline, in some examples implemented, only the execution cluster of the pipeline has (one or more) memory access unit circuit systems 2364). It should also be understood that in the case of using separate pipelines, one or more of these pipelines can be out-of-order issue / execution, while the rest are in-order.

[0266] In some examples, the execution engine unit circuitry 2350 may perform load store unit (LSU) address / data pipelining to an advanced microcontroller bus (AMB) interface (not shown), as well as address stage and writeback, data stage loads, stores, and branches.

[0267] A set of memory access circuitry 2364 is coupled to memory cell circuitry 2370, which includes data TLB circuitry 2372, which is coupled to data cache circuitry 2374, which is coupled to level 2 (L2) cache circuitry 2376. In some examples, memory access circuitry 2364 may include load unit circuitry, store address unit circuitry, and store data unit circuitry, each of which is coupled to data TLB circuitry 2372 in memory cell circuitry 2370. Instruction cache circuitry 2334 is further coupled to level 2 (L2) cache unit circuitry 2376 in memory cell circuitry 2370. In some examples, instruction cache 2334 and data cache 2374 are combined into L2 cache circuitry 2376, level 3 (L3) cache circuitry (not shown), and / or a single instruction and data cache in main memory (not shown). The L2 cache circuitry 2376 is coupled to one or more other levels of cache and ultimately to main memory.

[0268] Core 2390 may support one or more instruction sets (e.g., x86 instruction set architecture (optionally with some extensions that have been added with updated versions); MIPS instruction set architecture; ARM instruction set architecture (optionally with optional additional extensions, such as NEON)) that include the instruction(s) described herein. In some examples, core 2390 includes logic to support packed data instruction set architecture extensions (e.g., AVX1, AVX2), allowing operations used by many multimedia applications to be performed using packed data.

[0269] Example Execution Unit Circuitry

[0270] Fig.24 An example of execution unit circuitry is shown, such as Fig. 23B (One or more) execution unit circuit systems 2362. As shown, (one or more) execution unit circuit systems 2362 may include one or more ALU circuits 2401, optional vector / single instruction multiple data (SIMD) circuits 2403, load / store circuits 2405, branch / jump circuits 2407 and / or floating-point unit (FPU) circuits 2409. ALU circuits 2401 perform integer arithmetic and / or Boolean operations. Vector / SIMD circuits 2403 perform vector / SIMD operations on packed data (e.g., SIMD / vector registers). Load / store circuits 2405 execute load and store instructions to load data from memory into registers, or store data from registers to memory. Load / store circuits 2405 may also generate addresses. Branch / jump circuits 2407 cause branches or jumps to a certain memory address depending on the instruction. FPU circuits 2409 perform floating-point arithmetic. The width of the execution unit circuitry 2362 varies depending on the example, and may range from 16 bits to 1024 bits, for example. In some examples, two or more smaller execution units are logically combined to form a larger execution unit (e.g., two 128-bit execution units are logically combined to form a 256-bit execution unit).

[0271] Example Register Architecture

[0272] Fig.252500 is a block diagram of a register architecture 2500 according to some examples. As shown, the register architecture 2500 includes a vector / SIMD register 2510, whose width varies from 128 bits to 1024 bits. In some examples, the vector / SIMD register 2510 is physically 512 bits, and only some low-order bits are used depending on the mapping. For example, in some examples, the vector / SIMD register 2510 is a 512-bit ZMM register: the low-order 256 bits are used for the YMM register, and the low-order 128 bits are used for the XMM register. Therefore, there is a register coverage. In some examples, the vector length field selects between the maximum length and one or more other shorter lengths, wherein each such shorter length is half the length of the previous length. Scalar operations are operations performed on the lowest-order data element position in the ZMM / YMM / XMM register; higher-order data element positions are either maintained as the same as before the instruction, or are zeroed, depending on the example.

[0273] In some examples, the register architecture 2500 includes a write mask / predicate register 2515. For example, in some examples, there are 8 write mask / predicate registers (sometimes referred to as k0 to k7), each of which is 16 bits, 32 bits, 64 bits, or 128 bits in size. The write mask / predicate register 2515 can allow merging (e.g., allowing any set of elements in the destination to be protected from update during the execution of any operation) and / or zeroing (e.g., a zeroing vector mask allows any set of elements in the destination to be zeroed during the execution of any operation). In some examples, each data element position in a given write mask / predicate register 2515 corresponds to a data element position at the destination. In other examples, the write mask / predicate register 2515 is scalable and consists of a set number of enable bits for a given vector element (e.g., 8 enable bits for each 64-bit vector element).

[0274] The register architecture 2500 includes a plurality of general registers 2525. These registers may be 16 bits, 32 bits, 64 bits, etc., and may be used for scalar operations. In some examples, these registers are referred to by the names RAX, RBX, RCX, RDX, RBP, RSI, RDI, RSP, and R8 to R15.

[0275] In some examples, the register architecture 2500 includes a scalar floating point (FP) register file 2545, which is used to perform scalar floating point operations on 32 / 64 / 80-bit floating point data using the x87 instruction set architecture extension, or as an MMX register to perform operations on 64-bit packed integer data, and to store operands for some operations performed between MMX and XMM registers.

[0276] One or more flag registers 2540 (e.g., EFLAGS, RFLAGS, etc.) store status and control information for arithmetic, comparison, and system operations. For example, one or more flag registers 2540 can store condition code information, such as carry, parity, auxiliary carry, zero, sign, and overflow. In some examples, one or more flag registers 2540 are referred to as program status and control registers.

[0277] Segment registers 2520 contain segment points for accessing memory. In some examples, these registers are referred to by the names CS, DS, SS, ES, FS, and GS.

[0278] Model specific registers or machine-specific registers (MSRs) 2535 control and report processor performance. Most MSRs 2535 handle system-related functions and are not accessible to applications. For example, MSRs may provide control over one or more of the following: performance monitoring counters, debug extensions, memory type range registers, thermal management and power management, instruction-specific support, and / or processor feature / mode support. Machine check registers 2560 consist of control, status, and error reporting MSRs for detecting and reporting hardware errors. (One or more) control registers 2555 (e.g., CR0-CR4) determine the operating mode of the processor (e.g., processors 1670, 1680, 1638, 1618, and / or 1700) and the characteristics of the task currently being executed. In some examples, MSRs 2535 are a subset of control registers 2555.

[0279] One or more instruction pointer registers 2530 store instruction pointer values. Debug registers 2550 control and allow monitoring of debug operations of the processor or core.

[0280] Memory (mem) management registers 2565 specify the location of data structures used in protected mode memory management. These registers may include global descriptor table registers (GDTR), interrupt descriptor table registers (IDTR), task registers, and local descriptor table registers (LDTR) registers.

[0281] Alternative examples may use wider or narrower registers. In addition, alternative examples may use more, fewer, or different register files and registers. The register architecture 2500 may be used, for example, in register file / memory 408, or (one or more) physical register file circuit systems 2358.

[0282] Instruction Set Architecture

[0283] An instruction set architecture (ISA) may include one or more instruction formats. A given instruction format may define various fields (e.g., the number of bits, the position of the bits) to specify the operation to be performed (e.g., opcode) and the (one or more) operands and / or other (one or more) data fields (e.g., mask) on which the operation is to be performed, etc. Some instruction formats are further decomposed by the definition of instruction templates (or subformats). For example, an instruction template of a given instruction format may be defined as having different subsets of the fields of the instruction format (the included fields are usually in the same order, but at least some have different bit positions because there are fewer included fields) and / or defined as having a given field interpreted in a different manner. Thus, each instruction of the ISA is expressed using a given instruction format (and, if defined, expressed in a given instruction template in the instruction format), and includes fields for specifying the operation and the operand. For example, the example ADD instruction has a specific opcode and instruction format, the instruction format includes an opcode field to specify the opcode, and includes an operand field to select the operand (source 1 / destination and source 2); and the appearance of this ADD instruction in the instruction stream will have specific content in the operand field to select the specific operand. In addition, although the following description is made in the context of the x86 ISA, it is within the knowledge of those skilled in the art to apply the teachings of the present disclosure in another ISA.

[0284] Example instruction format

[0285] The examples of the (one or more) instructions described herein may be implemented in different formats. In addition, example systems, architectures, and pipelines are described in detail below. The examples of (one or more) instructions may be executed on these systems, architectures, and pipelines, but are not limited to those described in detail.

[0286] Fig.26 An example of an instruction format is illustrated. As shown, an instruction may include multiple components, including, but not limited to, one or more fields for the following items: one or more prefixes 2601, an opcode 2603, addressing information 2605 (e.g., a register identifier, memory addressing information, etc.), a displacement value 2607, and / or an immediate value 2609. Note that some instructions utilize some or all of the fields of the format, while other instructions may only use the opcode 2603 field. In some examples, the illustrated order is the order in which the fields are to be encoded, however, it should be understood that in other examples, the fields may be encoded in another order, combined, etc.

[0287] (One or more) prefix fields 2601 modify the instruction when used. In some examples, one or more prefixes are used to repeat string instructions (e.g., 0xF0, 0xF2, 0xF3, etc.), provide section override (e.g., 0x2E, 0x36, 0x3E, 0x26, 0x64, 0x65, 0x2E, 0x3E, etc.), perform bus lock operations, and / or change operation objects (e.g., 0x66) and address sizes (e.g., 0x67). Some instructions require mandatory prefixes (e.g., 0x66, 0xF2, 0xF3, etc.). Some of these prefixes can be considered as "traditional" prefixes. Other prefixes (one or more examples of which are described in detail herein) indicate and / or provide further capabilities, such as specifying specific registers, etc. These other prefixes are usually followed by the "traditional" prefix.

[0288] The opcode field 2603 is used to at least partially define the operation to be performed when the instruction is decoded. In some examples, the length of the primary opcode encoded in the opcode field 2603 is one, two or three bytes. In other examples, the primary opcode can be other lengths. Extra 3-bit opcode fields are sometimes encoded in another field.

[0289] The addressing information field 2605 is used to address one or more operands of the instruction, such as a location in memory or one or more registers. Fig. 27An example of an addressing information field 2605 is illustrated. In this illustration, an optional MOD R / M byte 2702 and an optional Scale, Index, Base (SIB) byte 2704 are shown. The MOD R / M byte 2702 and SIB byte 2704 are used to encode up to two operands of the instruction, each operand being a direct register or an effective memory address. Note that these two fields are optional, i.e., not all instructions include one or more of these fields. The MOD R / M byte 2702 includes a MOD field 2742, a register (reg) field 2744, and an R / M field 2746.

[0290] The content of MOD field 2742 distinguishes between memory access and non-memory access modes. In some examples, when MOD field 2742 has a binary value of 11 (11b), register direct addressing mode is utilized, otherwise register indirect addressing is used.

[0291] Register field 2744 may encode a destination register operand or a source register operand, or may encode an opcode extension and not be used to encode any instruction operand. The contents of register field 2744 specify the location (in a register or in memory) of the source or destination operand directly or through address generation. In some examples, register field 2744 is supplemented with additional bits from a prefix (e.g., prefix 2601) to allow for greater addressing.

[0292] R / M field 2746 may be used to encode an instruction operand that references a memory address, or may be used to encode a destination register operand or a source register operand. Note that in some examples, R / M field 2746 may be combined with MOD field 2742 to specify an addressing mode.

[0293] SIB byte 2704 includes a scale field 2752, an index field 2754, and a base address field 2756 for address generation. Scale field 2752 indicates a scale factor. Index field 2754 specifies the index register to be used. In some examples, index field 2754 is supplemented with extra bits from a prefix (e.g., prefix 2601) to allow for larger addressing. Base address field 2756 specifies the base address register to be used. In some examples, base address field 2756 is supplemented with extra bits from a prefix (e.g., prefix 2601) to allow for larger addressing. In practice, the contents of scale field 2752 allow the contents of index field 2754 to be scaled for memory address generation (e.g., for memory addresses using 2 缩放 * address generation of index + base address).

[0294] Some addressing forms use displacement values ​​to generate memory addresses. For example, 缩放 2605, which indicates a compressed displacement scheme for which the displacement value is calculated and stored in the displacement field 2607.

[0295] In some examples, the immediate value field 2609 specifies an immediate value for the instruction. The immediate value may be encoded as a 1-byte value, a 2-byte value, a 4-byte value, and so on.

[0296] Fig.28 An example of a first prefix 2601A is illustrated. In some examples, the first prefix 2601A is an example of a REX prefix. Instructions using this prefix can specify general registers, 64-bit packed data registers (e.g., single instruction multiple data (SIMD) registers or vector registers), and / or control registers and debug registers (e.g., CR8-CR15 and DR8-DR15).

[0297] Instructions using the first prefix 2601A can use a 3-bit field to specify up to three registers, depending on the format: 1) using the reg field 2744 and the R / M field 2746 of the MOD R / M byte 2702; 2) using the MOD R / M byte 2702 with the SIB byte 2704, including using the reg field 2744 as well as the base field 2756 and the index field 2754; or 3) using the register field of the opcode.

[0298] In the first prefix 2601A, bit positions 7:4 of the payload byte are set to 0100. Bit position 3 (W) can be used to determine the operand size, but cannot determine the operand width alone. Therefore, when W=0, the operand size is determined by the code segment descriptor (CS.D), and when W=1, the operand size is 64 bits.

[0299] Note that adding another bit allows for 16 (2 4 ) registers, while the separate MOD R / M reg field 2744 and the R / M field 2746 of MOD R / M can only address 8 registers each.

[0300] In the first prefix 2601A, bit position 2 (R) may be an extension of the MOD R / M reg field 2744 and may be used to modify the MOD R / M reg field 2744 when the field encodes a general register, a 64-bit packed data register (e.g., an SSE register), or a control or debug register. When the MOD R / M byte 2702 specifies other registers or defines an extended opcode, R is ignored.

[0301] Bit position 1 (X) may modify the SIB byte index field 2754 .

[0302] Bit position 0 (B) may modify the base address in the R / M field 2746 or SIB byte base address field 2756 of MOD R / M; or it may modify the opcode register field used to access a general register (eg, general register 2525).

[0303] Figure 29A-Figure 29D An example of how the R, X, and B fields of the first prefix 2601A are used is illustrated. Fig.29A It is illustrated that when the SIB byte 2704 is not used for memory addressing, the R and B from the first prefix 2601A are used to extend the reg field 2744 and the R / M field 2746 of the MOD R / M byte 2702. Fig.29B It is illustrated that when the SIB byte 2704 is not used, the R and B from the first prefix 2601A are used to extend the reg field 2744 and the R / M field 2746 of the MOD R / M byte 2702 (register-register addressing). Fig.29C It is illustrated that when the SIB byte 2704 is used for memory addressing, the R, X, and B from the first prefix 2601A are used to extend the reg field 2744 of the MOD R / M byte 2702 as well as the index field 2754 and the base field 2756. Fig.29D It is illustrated that when a register is encoded in the opcode 2603 , the B from the first prefix 2601A is used to extend the reg field 2744 of the MOD R / M byte 2702 .

[0304] Figure 30A-Figure 30BAn example of a second prefix 2601B is illustrated. In some examples, the second prefix 2601B is an example of a VEX prefix. The second prefix 2601B encoding allows instructions to have more than two operands, and allows SIMD vector registers (e.g., vector / SIMD registers 2510) to be longer than 64 bits (e.g., 128 bits and 256 bits). The use of the second prefix 2601B provides a syntax for three operands (or more). For example, a previous two-operand instruction performs an operation such as A=A+B, which overwrites the source operand. The use of the second prefix 2601B enables the operands to perform non-destructive operations, such as A=B+C.

[0305] In some examples, the second prefix 2601B has two forms - a two-byte form and a three-byte form. The two-byte second prefix 2601B is mainly used for 128-bit, scalar and some 256-bit instructions; while the three-byte second prefix 2601B provides a compact replacement for 3-byte opcode instructions and the first prefix 2601A.

[0306] Fig. 30A An example of a two-byte form of the second prefix 2601B is illustrated. In some examples, the format field 3001 (byte 0 3003) contains the value C5H. In some examples, byte 1 3005 includes an "R" value in bit [7]. This value is the complement of the "R" value of the first prefix 2601A. Bit [2] is used to specify the length (L) of the vector (wherein the value of 0 is a scalar or 128-bit vector, and the value of 1 is a 256-bit vector). Bit [1:0] provides an opcode extensibility equivalent to some traditional prefixes (e.g., 00=no prefix, 01=66H, 10=F3H, and 11=F2H). Bits [6:3], shown as vvvv, can be used to: 1) encode a first source register operand, which is specified in inverted (complement) form and is valid for instructions with 2 or more source operands; 2) encode a destination register operand, which is specified in complement form for certain vector shifts; or 3) not encode any operand, the field is reserved and should contain a value, such as 1111b.

[0307] Instructions using this prefix may use the R / M field 2746 of MOD R / M to encode an instruction operand that references a memory address, or to encode a destination register operand or a source register operand.

[0308] Instructions using this prefix may use the reg field 2744 of MOD R / M to encode a destination register operand or a source register operand, or be treated as an opcode extension and not used to encode any instruction operand.

[0309] For instruction syntax supporting four operands, vvvv, the R / M field 2746 of MOD R / M, and the reg field 2744 of MOD R / M encode three of the four operands. Bits [7:4] of the immediate value field 2609 are then used to encode the third source register operand.

[0310] Fig. 30B An example of a three-byte form of the second prefix 2601B is illustrated. In some examples, the format field 3011 (byte 0 3013) contains the value C4H. Byte 1 3015 includes "R", "X" and "B" in bits [7:5], which are the complements of these values ​​of the first prefix 2601A. Bits [4:0] (shown as mmmm) of byte 1 3015 include content that encodes one or more implicit leading opcode bytes as needed. For example, 00001 means 0FH leading opcode, 00010 means 0F38H leading opcode, 00011 means 0F3AH leading opcode, and so on.

[0311] The use of bit [7] of byte 2 3017 is similar to that of W of the first prefix 2601A, including helping to determine the size of operands that can be promoted. Bit [2] is used to specify the length (L) of the vector (where a value of 0 is a scalar or 128-bit vector, and a value of 1 is a 256-bit vector). Bits [1:0] provide opcode extensibility equivalent to some traditional prefixes (e.g., 00=no prefix, 01=66H, 10=F3H, and 11=F2H). Bits [6:3], shown as vvvv, can be used to: 1) encode the first source register operand, which is specified in inverted (inverse) form, valid for instructions with 2 or more source operands; 2) encode the destination register operand, which is specified in inverse form for certain vector shifts; or 3) do not encode any operand, this field is reserved and should contain a value, such as 1111b.

[0312] Instructions using this prefix may use the R / M field 2746 of MOD R / M to encode an instruction operand that references a memory address, or to encode a destination register operand or a source register operand.

[0313] Instructions using this prefix may use the reg field 2744 of MOD R / M to encode a destination register operand or a source register operand, or be treated as an opcode extension and not used to encode any instruction operand.

[0314] For instruction syntax supporting four operands, vvvv, the R / M field 2746 of MOD R / M, and the reg field 2744 of MOD R / M encode three of the four operands. Bits [7:4] of the immediate value field 2609 are then used to encode the third source register operand.

[0315] Fig.31 An example of a third prefix 2601C is illustrated. In some examples, the third prefix 2601C is an example of an EVEX prefix. The third prefix 2601C is a four-byte prefix.

[0316] The third prefix 2601C can encode 32 vector registers (e.g., 128-bit, 256-bit, and 512-bit registers) in 64-bit mode. In some examples, write masks / operation masks are used (see the discussion of registers in previous figures, e.g. Fig.25 ) or predicate instructions utilize this prefix. The operation mask register allows conditional processing or selection control. Operation mask instructions whose source / destination operands are operation mask registers and treat the contents of the operation mask register as a single value are encoded using the second prefix 2601B.

[0317] The third prefix 2601C can encode features specific to the instruction class (e.g., a packed instruction with "load+operation" semantics can support an embedded broadcast feature, a floating-point instruction with rounding semantics can support a static rounding feature, a floating-point instruction with non-rounding arithmetic semantics can support a "suppress all exceptions" feature, and so on).

[0318] The first byte of the third prefix 2601C is the format field 3111, which in some examples has a value of 62H. The subsequent bytes are called payload bytes 3115-3119, and together form a 24-bit value of P[23:0], providing specific capabilities in the form of one or more fields (described in detail herein).

[0319] In some examples, P[1:0] of payload byte 3119 is the same as the two mm bits in the lower order. In some examples, P[3:2] is reserved. Bit P[4] (R') allows access to the upper 16 vector register sets when combined with P[7] and the reg field 2744 of MOD R / M. When SIB type addressing is not required, P[6] can also provide access to the upper 16 vector registers. P[7:5] consists of R, X, and B, which are operand specifier modifier bits for vector registers, general registers, and memory addressing, and when combined with the MOD R / M register field 2744 and the R / M field 2746 of MOD R / M, access to the next set of 8 registers beyond the lower 8 registers is allowed. P[9:8] provides opcode extensibility equivalent to some traditional prefixes (e.g., 00=no prefix, 01=66H, 10=F3H, and 11=F2H). P

[10] is a fixed value of 1 in some examples. P[14:11], shown as vvvv, can be used to: 1) encode a first source register operand, which is specified in inverted (complement) form, valid for instructions with 2 or more source operands; 2) encode a destination register operand, which is specified in complement form, used for certain vector shifts; or 3) not encode any operand, the field is reserved and should contain a value, such as 1111b.

[0320] P

[15] is similar to W of the first prefix 2601A and the second prefix 2601B, and can be used as an opcode extension bit or an operand size increase.

[0321] P[18:16] specifies the index of a register in the operation mask (write mask) register (e.g., write mask / predicate register 2515). In some examples, the particular value aaa=000 has special behavior, implying that no operation mask is used for this particular instruction (this can be achieved in a variety of ways, including using an operation mask hardwired to all ones or hardware that bypasses the masking hardware). When merging, the vector mask allows any set of elements in the destination to be protected from update during the execution of any operation (specified by the basic operation and the enhanced operation); in some other examples, the old value of each element of the destination is retained (if the corresponding mask bit has a 0 value). In contrast, when zeroing, the vector mask allows any set of elements in the destination to be zeroed during the execution of any operation (specified by the basic operation and the enhanced operation); in some examples, the elements of the destination are set to 0 when the corresponding mask bit has a 0 value. A subset of this functionality is the ability to control the vector length of the operation being performed (i.e., the span of elements modified, from first to last); however, the elements modified do not have to be consecutive. Thus, the operation mask field enables a subset of vector operations, including loads, stores, arithmetic, logical, etc. Although in the described examples, the contents of the operation mask field select which of several operation mask registers contains the operation mask to be used (so that the contents of the operation mask field indirectly identify the masking to be performed), alternative examples alternatively or additionally allow the contents of the mask write field to directly specify the masking to be performed.

[0322] P

[19] can be combined with P[14:11] to encode a second source vector register in a non-destructive source syntax that can utilize P

[19] to access the upper 16 vector registers. P

[20] encodes various features that vary in different classes of instructions and can affect the meaning of the vector length / rounding control specifier field (P[22:21]). P

[23] indicates support for merge-write masking (e.g., when set to 0) or support for zeroing and merge-write masking (e.g., when set to 1).

[0323] The following table details an example of the encoding of registers in instructions using the third prefix 2601C. Table 1: 32-register support in 64-bit mode Table 2: Encoding register specifiers in 32-bit mode Table 3: Operation Mask Register Specifier Encoding

[0324] Graphics Execution Unit

[0325] Figure 32A-32B Thread execution logic 3200 is illustrated including an array of processing elements employed in a graphics processor core according to examples described herein. Figure 32A-32B Elements having the same reference numeral (or name) as elements of any other figure herein may operate or function in any manner similar to that described elsewhere herein, but are not limited thereto. Fig.32A represents an execution unit within a general-purpose graphics processor, and Fig.32B Represents an execution unit that can be used within a computing accelerator.

[0326] As in Fig.32A As illustrated in , in some examples, thread execution logic 3200 includes a shader processor 3202, a thread dispatcher 3204, an instruction cache 3206, a scalable execution unit array including a plurality of execution units 3208A-3208N, a sampler 3210, a shared local memory 3211, a data cache 3212, and a data port 3214. In some examples, the scalable execution unit array can be dynamically scaled by enabling or disabling one or more execution units (e.g., any one of execution units 3208A, 3208B, 3208C, 3208D, up to 3208N-1 and 3208N) based on the computational requirements of the workload. In some examples, the included components are interconnected via an interconnect structure that links to each of the components. In some examples, thread execution logic 3200 includes one or more connections to a memory (such as system memory or cache memory) through instruction cache 3206, data port 3214, sampler 3210, and one or more of execution units 3208A-3208N. In some examples, each execution unit (e.g., 3208A) is a self-contained programmable general-purpose computing unit capable of executing multiple simultaneous hardware threads while processing multiple data elements in parallel for each thread. In various examples, the array of execution units 3208A-3208N is scalable to include any number of separate execution units.

[0327] In some examples, execution units 3208A-3208N are primarily used to execute shader programs. Shader processor 3202 can process various shader programs, and can dispatch execution threads associated with shader programs via thread dispatcher 3204. In some examples, thread dispatcher includes logic for arbitrating thread initiation requests from graphics pipelines and media pipelines and instantiating the requested threads on one or more execution units in execution units 3208A-3208N. For example, a geometry pipeline can dispatch vertex shaders, tessellation shaders, or geometry shaders to thread execution logic for processing. In some examples, thread dispatcher 3204 can also handle runtime thread generation requests from executed shader programs.

[0328] In some examples, execution units 3208A-3208N support an instruction set including native support for many standard 3D graphics shader instructions, so that shader programs from graphics libraries (e.g., Direct 3D and OpenGL) are executed with minimal translation. These execution units support vertex and geometry processing (e.g., vertex programs, geometry programs, vertex shaders), pixel processing (e.g., pixel shaders, fragment shaders) and general processing (e.g., calculation and media shaders). Each execution unit in execution units 3208A-3208N is capable of multi-issue single instruction multiple data (SIMD) execution, and multi-threaded operations enable efficient execution environments when facing memory accesses with higher latency. Each hardware thread in each execution unit has a dedicated high-bandwidth register stack and an associated independent thread state. For pipelines capable of integer operations, single-precision floating-point operations and double-precision floating-point operations, capable of SIMD branching capabilities, capable of logical operations, capable of transcendental operations and capable of other mixed operations, execution is multi-issued for each clock. While waiting for data from a shared function in memory or a shared function, the dependency logic within the execution unit 3208A-3208N puts the waiting thread to sleep until the requested data has been returned. While the waiting thread is sleeping, hardware resources can be dedicated to processing other threads. For example, during a delay associated with a vertex shader operation, the execution unit can perform operations for a pixel shader, a fragment shader, or another type of shader program including different vertex shaders. Each example can be applied to use execution using single instruction multiple threads (SIMT) as an alternative to the use of SIMD, or as an addition to the use of SIMD. References to SIMD cores or operations can also be applied to SIMT, or to a combination of SIMD and SIMT.

[0329] Each of the execution units 3208A-3208N operates on an array of data elements. The number of data elements is the "execution size," or number of lanes for an instruction. An execution lane is a logical unit used for the execution of data element access, masking, and flow control within an instruction. The number of lanes may be independent of the number of physical arithmetic logic units (ALUs) or floating point units (FPUs) used for a particular graphics processor. In some examples, the execution units 3208A-3208N support integer and floating point data types.

[0330] The execution unit instruction set includes SIMD instructions. Various data elements can be stored in registers as compact data types, and the execution unit will process various elements based on the data size of the element. For example, when a 256-bit wide vector is operated, the 256 bits of the vector are stored in registers, and the execution unit operates the vector as four independent 64-bit compact data elements (quad-word (Quad-Word, QW) size data elements), eight independent 32-bit compact data elements (double-word (Double Word, DW) size data elements), sixteen independent 16-bit compact data elements (word (Word, W) size data elements) or thirty-two independent 8-bit data elements (byte (byte, B) size data elements). However, different vector widths and register sizes are possible.

[0331] In some examples, one or more execution units may be combined into a fused execution unit 3209A-3209N having a thread control logic (3207A-3207N) common to the fused EU. Multiple EUs may be fused into a EU group. Each EU in a fused EU group may be configured to execute a separate SIMD hardware thread. The number of EUs in a fused EU group may vary according to the example. Additionally, various SIMD widths may be executed EU by EU, including but not limited to SIMD8, SIMD16, and SIMD32. Each fused graphics execution unit 3209A-3209N includes at least two execution units. For example, a fused execution unit 3209A includes a first EU 3208A, a second EU 3208B, and a thread control logic 3207A common to the first EU 3208A and the second EU 3208B. Thread control logic 3207A controls threads executing on fused graphics execution unit 3209A, allowing each EU within fused execution units 3209A-3209N to execute using a common instruction pointer register.

[0332] One or more internal instruction caches (e.g., 3206) are included in the thread execution logic 3200 to cache thread instructions for the execution unit. In some examples, one or more data caches (e.g., 3212) are included to cache thread data during thread execution. Threads executed on the execution logic 3200 may also store explicitly managed data in the shared local memory 3211. In some examples, a sampler 3210 is included to provide texture sampling for 3D operations and media sampling for media operations. In some examples, the sampler 3210 includes specialized texture or media sampling functions to process texture data or media data during the sampling process before providing the sampled data to the execution unit.

[0333] During execution, the graphics pipeline and the media pipeline send thread initiation requests to the thread execution logic 3200 via thread generation and dispatch logic. Once the group of geometric objects has been processed and rasterized into pixel data, the pixel processor logic (e.g., pixel shader logic, fragment shader logic, etc.) within the shader processor 3202 is called to further calculate output information and cause the results to be written to the output surface (e.g., color buffer, depth buffer, stencil buffer, etc.). In some examples, the pixel shader or fragment shader calculates the value of each vertex attribute, and the value of each vertex attribute is interpolated across the rasterized object. In some examples, the pixel processor logic within the shader processor 3202 then executes the pixel shader program or fragment shader program supplied by the application programming interface (API). In order to execute the shader program, the shader processor 3202 dispatches the thread to the execution unit (e.g., 3208A) via the thread dispatcher 3204. In some examples, the shader processor 3202 uses the texture sampling logic in the sampler 3210 to access the texture data in the texture map stored in the memory. Arithmetic operations on texture data and input geometry data compute pixel color data for each geometry fragment, or discard one or more pixels without further processing.

[0334] In some examples, data port 3214 provides a memory access mechanism for thread execution logic 3200 to output processed data to memory for further processing on a graphics processor output pipeline. In some examples, data port 3214 includes or is coupled to one or more cache memories (e.g., data cache 3212) to cache data for memory access via the data port.

[0335] In some examples, the execution logic 3200 may also include a ray tracer 3205 that may provide ray tracing acceleration functionality. The ray tracer 3205 may support a ray tracing instruction set that includes instructions / functions for ray generation.

[0336] Fig.32B 3226, and a set of dedicated integer SIMD ALUs 3235. The GRF 3224 and ARF 3226 include a set of general register files and architectural register files associated with each synchronous hardware thread that can be active in the graphics execution unit 3208. In some examples, the per-thread architectural state is maintained in the ARF 3226, while the data used during the execution of the thread is stored in the GRF 3224. The execution state of each thread, including the instruction pointer for each thread, can be saved in thread-specific registers in the ARF 3226.

[0337] In some examples, the graphics execution unit 3208 has an architecture that is a combination of Simultaneous Multi-Threading (SMT) and fine-grained Interleaved Multi-Threading (IMT). The architecture has a modular configuration that can be fine-tuned at design time based on the target number of simultaneous threads and the number of registers per execution unit, where the execution unit is divided across the logic for executing multiple simultaneous threads. The number of logical threads that can be executed by the graphics execution unit 3208 is not limited to the number of hardware threads, and multiple logical threads can be assigned to each hardware thread.

[0338] In some examples, the graphics execution unit 3202 may issue multiple instructions in coordination, each of which may be a different instruction. The thread arbiter 3222 of the graphics execution unit thread 3208 may dispatch the instruction to one of the send unit 3230, the branch unit 3232, or (one or more) SIMD FPU 3234 for execution. Each execution thread may access 128 general registers within the GRF 3224, wherein each register may store 32 bytes accessible as a SIMD 8 element vector with 32-bit data elements. In some examples, each execution unit thread has access to 4 kilobytes within the GRF 3224, but the examples are not limited thereto, and more or less register resources may be provided in other examples. In some examples, the graphics execution unit 3208 is partitioned into seven hardware threads that can independently perform computing operations, but the number of threads of each execution unit may also vary according to the example. For example, in some examples, up to 16 hardware threads are supported. In an example where seven threads can access 4 kilobytes, GRF 3224 can store a total of 28 kilobytes. Where 16 threads can access 4 kilobytes, GRF 3224 can store a total of 64 kilobytes. Flexible addressing modes can permit registers to be addressed together, effectively creating wider registers or representing strided rectangular block data structures.

[0339] In some examples, memory operations, sampler operations, and other longer latency system communications are dispatched via "send" instructions executed by message passing send unit 3230. In some examples, branch instructions are dispatched to dedicated branch unit 3232 to facilitate SIMD scatter and eventual convergence.

[0340] In some examples, graphics execution unit 3208 includes one or more SIMD floating point units (FPU(s)) 3234 for performing floating point operations. In some examples, FPU(s) 3234 also support integer computations. In some examples, FPU(s) 3234 can SIMD perform up to M 32-bit floating point (or integer) operations, or SIMD perform up to 2M 16-bit integer or 16-bit floating point operations. In some examples, at least one of the FPU(s) provides extended math capabilities that support high throughput transcendental math functions and double precision 64-bit floating point. In some examples, a set 3235 of 8-bit integer SIMD ALUs are also present and can be specifically optimized to perform operations associated with machine learning computations.

[0341] In some examples, an array of multiple instances of graphics execution unit 3208 may be instantiated in graphics sub-core groupings (e.g., sub-slices). For scalability, product architects may choose the exact number of execution units per sub-core grouping. In some examples, execution unit 3208 may execute instructions across multiple execution lanes. In further examples, each thread executed on graphics execution unit 3208 is executed on a different lane.

[0342] Fig.33 The diagram shows an additional execution unit 3300 according to an example. In some examples, the execution unit 3300 includes a thread control unit 3301, a thread state unit 3302, an instruction fetch / prefetch unit 3303, and an instruction decode unit 3304. The execution unit 3300 additionally includes a register file 3306, which stores registers that can be assigned to hardware threads within the execution unit. The execution unit 3300 additionally includes a dispatch unit 3307 and a branch unit 3308. In some examples, the dispatch unit 3307 and the branch unit 3308 can be used with Fig.32B The sending unit 3230 and the branching unit 3232 of the graphics execution unit 3208 operate in a similar manner.

[0343] The execution unit 3300 also includes a computing unit 3310, which includes a plurality of different types of functional units. In some examples, the computing unit 3310 includes an ALU unit 3311, which includes an array of arithmetic logic units. The ALU unit 3311 can be configured to perform 64-bit, 32-bit, and 16-bit integer and floating-point operations. Integer and floating-point operations can be performed simultaneously. The computing unit 3310 may also include a systolic array 3312 and a mathematical unit 3313. The systolic array 3312 includes a wide W and deep D network of data processing units, which can be used to perform vector or other data parallel operations in a systolic manner. In some examples, the systolic array 3312 may be configured to perform matrix operations, such as matrix dot product operations. In some examples, the systolic array 3312 supports 16-bit floating-point operations and 8-bit and 4-bit integer operations. In some examples, the systolic array 3312 may be configured to accelerate machine learning operations. In such examples, systolic array 3312 may be configured with support for bfloat 16-bit floating point format. In some examples, math unit 3313 may be included to perform a specific subset of math operations in an efficient and lower power manner than ALU unit 3311. Math unit 3313 may include a variation of math logic that may be found in shared functional logic of a graphics processing engine provided by other examples. In some examples, math unit 3313 may be configured to perform 32-bit and 64-bit floating point operations.

[0344] Thread control unit 3301 includes logic for controlling the execution of threads within execution units. Thread control unit 3301 may include thread arbitration logic for starting, stopping, and preempting the execution of threads within execution unit 3300. Thread state unit 3302 may be used to store thread states for threads assigned to execute on execution unit 3300. Storing thread states within execution unit 3300 enables quick preemption of threads when they become blocked or idle. Instruction fetch / prefetch unit 3303 may fetch instructions from instruction caches of higher level execution logic (e.g., Fig.32A The instruction fetch / prefetch unit 3303 may also issue a prefetch request for instructions to be loaded into the instruction cache based on an analysis of the currently executing thread. The instruction decode unit 3304 may be used to decode instructions to be executed by the computing unit. In some examples, the instruction decode unit 3304 may be used as a secondary decoder to decode complex instructions into constituent micro-operations.

[0345] Execution unit 3300 additionally includes a register file 3306 that can be used by hardware threads executing on execution unit 3300. Registers in register file 3306 can be divided across logic used to execute multiple simultaneous threads within compute unit 3310 of execution unit 3300. The number of logical threads that can be executed by graphics execution unit 3300 is not limited to the number of hardware threads, and multiple logical threads can be assigned to each hardware thread. The size of register file 3306 can vary across examples based on the number of hardware threads supported. In some examples, register renaming can be used to dynamically assign registers to hardware threads.

[0346] Fig.34 34 is a block diagram illustrating a graphics processor instruction format 3400 according to some examples. In one or more examples, a graphics processor execution unit supports an instruction set having instructions in a variety of formats. Solid line boxes illustrate components that are typically included in execution unit instructions, while dashed lines include components that are optional or included only in a subset of instructions. In some examples, instruction format 3400 are macroinstructions because they are instructions supplied to the execution unit, as opposed to micro-operations that result from instruction decoding that is performed once the instruction is processed.

[0347] In some examples, the graphics processor execution unit may natively support instructions in a 128-bit instruction format 3410. Based on the selected instructions, instruction options, and the number of operands, a 64-bit compact instruction format 3430 may be used for some instructions. The native 128-bit instruction format 3410 provides access to all instruction options, while some options and operations are limited in the 64-bit format 3430. The native instructions available in the 64-bit format 3430 vary from example to example. In some examples, instructions are partially compressed using a set of index values ​​in an index field 3413. The execution unit hardware references a set of compression tables based on the index values ​​and uses the compression table output to reconstruct the native instructions of the 128-bit instruction format 3410. Instructions of other sizes and formats may be used.

[0348] For each format, the instruction opcode 3412 defines the operation to be performed by the execution unit. The execution unit executes each instruction in parallel across multiple data elements of each operand. For example, in response to an addition instruction, the execution unit performs a synchronous addition operation across each color channel representing a texture element or a picture element. By default, the execution unit executes each instruction across all data channels of the operand. In some examples, the instruction control field 3414 enables control of certain execution options (such as channel selection (e.g., predicates) and data channel order (e.g., swizzle)). For instructions in the 128-bit instruction format 3410, the execution size field 3416 limits the number of data channels that will be executed in parallel. In some examples, the execution size field 3416 is not available for the 64-bit compact instruction format 3430.

[0349] Some execution unit instructions have up to three operands, including two source operands src0 3420, src1 3422, and one destination 3418. In some examples, the execution unit supports dual destination instructions, where one of the destinations is implicit. Data manipulation instructions may have a third source operand (e.g., SRC2 3424), where the instruction opcode 3412 determines the number of source operands. The last source operand of an instruction may be an immediate (e.g., hard-coded) value passed with the instruction.

[0350] In some examples, the 128-bit instruction format 3410 includes an access / addressing mode field 3426 that specifies, for example, whether direct register addressing mode or indirect register addressing mode is used. When direct register addressing mode is used, the register addresses of one or more operands are provided directly by bits in the instruction.

[0351] In some examples, the 128-bit instruction format 3410 includes an access / addressing mode field 3426, which specifies the addressing mode and / or access mode of the instruction. In some examples, the access mode can be used to limit the data access alignment of the instruction. Some examples support access modes including 16-byte aligned access modes and 1-byte aligned access modes, wherein the byte alignment of the access mode determines the access alignment of the instruction operand. For example, when in the first mode, the instruction can use byte-aligned addressing for source operands and destination operands, and when in the second mode, the instruction can use 16-byte aligned addressing for all source operands and destination operands.

[0352] In some examples, the addressing mode portion of the access / addressing mode field 3426 determines whether the instruction uses direct addressing or indirect addressing. When direct register addressing mode is used, the bits in the instruction directly provide the register address of one or more operands. When indirect register addressing mode is used, the register address of one or more operands can be calculated based on the address register value and the address immediate field in the instruction.

[0353] In some examples, instructions are grouped based on the opcode 3412 bit field to simplify opcode decoding 3440. For 8-bit opcodes, bit 4, bit 5, and bit 6 allow the execution unit to determine the type of opcode. The exact opcode grouping shown is only an example. In some examples, the move and logic opcode group 3442 includes data movement and logic instructions (e.g., move (mov), compare (cmp)). In some examples, the move and logic group 3442 shares five most significant bits (most significant bit, MSB), wherein the move (mov) instruction adopts the form of 0000xxxxb, and the logic instruction adopts the form of 0001xxxxb. The flow control instruction group 3444 (e.g., call (call), jump (jmp)) includes instructions in the form of 0010xxxxb (e.g., 0x20). The miscellaneous instruction group 3446 includes a mixture of instructions, including synchronization instructions (e.g., wait (wait), send (send)) in the form of 0011xxxxb (e.g., 0x30). The parallel math instruction group 3448 includes component-by-component arithmetic instructions (e.g., addition, multiplication (mul)) of the form 0100xxxxb (e.g., 0x40). The parallel math group 3448 performs arithmetic operations in parallel across data channels. The vector math group 3450 includes arithmetic instructions (e.g., dp4) of the form 0101xxxxb (e.g., 0x50). The vector math group performs arithmetic on vector operands, such as dot product calculations. In some examples, the illustrated opcode decoding 3440 can be used to determine which portion of the execution unit will be used to execute the decoded instructions. For example, some instructions may be designated as systolic instructions to be executed by a systolic array. Other instructions, such as ray tracing instructions (not shown), may be routed to a ray tracing core or ray tracing logic within a slice or partition of the execution logic.

[0354] Graphics Pipeline

[0355] Fig.35 is a block diagram of another example of a graphics processor 3500 . Fig.35 Elements having the same reference numeral (or name) as elements of any other figure herein may operate or function in any manner similar to that described elsewhere herein, but are not limited thereto.

[0356] In some examples, graphics processor 3500 includes geometry pipeline 3520, media pipeline 3530, display engine 3540, thread execution logic 3550, and rendering output pipeline 3570. In some examples, graphics processor 3500 is a graphics processor within a multi-core processing system that includes one or more general-purpose processing cores. The graphics processor is controlled by register writes to one or more control registers (not shown) or via commands issued to graphics processor 3500 through ring interconnect 3502. In some examples, ring interconnect 3502 couples graphics processor 3500 to other processing components (such as other graphics processors or general-purpose processors). Commands from ring interconnect 3502 are interpreted by command stream converter 3503, which supplies instructions to various components of geometry pipeline 3520 or media pipeline 3530.

[0357] In some examples, command stream converter 3503 directs the operation of vertex fetcher 3505, which reads vertex data from memory and executes vertex processing commands provided by command stream converter 3503. In some examples, vertex fetcher 3505 provides vertex data to vertex shader 3507, which performs coordinate space transformation and lighting operations on each vertex. In some examples, vertex fetcher 3505 and vertex shader 3507 can execute vertex processing instructions by dispatching execution threads to execution units 3552A-3552B via thread dispatcher 3531.

[0358] In some examples, execution units 3552A-3552B are arrays of vector processors with instruction sets for performing graphics operations and media operations. In some examples, execution units 3552A-3552B may have an attached L1 cache 3551 that is dedicated to each array or shared between arrays. The cache may be configured as a data cache, an instruction cache, or partitioned into a single cache containing data and instructions in different partitions.

[0359] In some examples, the geometry pipeline 3520 includes a tessellation component for performing hardware-accelerated tessellation of 3D objects. In some examples, the programmable shell shader 3511 configures the tessellation operation. The programmable domain shader 3517 provides back-end evaluation of the tessellation output. The tessellation 3513 operates under the direction of the shell shader 3511 and contains dedicated logic for generating a detailed set of geometric objects based on a coarse geometric model that is provided as input to the geometry pipeline 3520. In some examples, if tessellation is not used, the tessellation components (e.g., the shell shader 3511, the tessellation 3513, and the domain shader 3517) can be bypassed.

[0360] In some examples, the complete geometric object may be processed by geometry shader 3519 via one or more threads dispatched to execution units 3552A-3552B, or may proceed directly to clipper 3529. In some examples, the geometry shader operates on the entire geometric object, rather than on vertices or patches of vertices as in previous stages of the graphics pipeline. If tessellation is disabled, geometry shader 3519 receives input from vertex shader 3507. In some examples, geometry shader 3519 is programmable by a geometry shader program to perform geometry tessellation when the tessellation unit is disabled.

[0361] Before rasterization, the clipper 3529 processes the vertex data. The clipper 3529 can be a fixed function clipper or a programmable clipper with clipping and geometry shader functions. In some examples, the rasterizer and depth test component 3573 in the render output pipeline 3570 dispatches a pixel shader to convert the geometric object into a pixel-by-pixel representation. In some examples, the pixel shader logic is included in the thread execution logic 3550. In some examples, the application can bypass the rasterizer and depth test component 3573 and access the unrasterized vertex data via the outflow unit 3523.

[0362] The graphics processor 3500 has an interconnect bus, an interconnect structure, or some other interconnect mechanism that allows data and messages to be passed between the main components of the processor. In some examples, the execution units 3552A-3552B and associated logic units (e.g., L1 cache 3551, sampler 3554, texture cache 3558, etc.) are interconnected via data ports 3556 to perform memory accesses and communicate with the rendering output pipeline components of the processor. In some examples, the sampler 3554, cache 3551, 3558, and execution units 3552A-3552B each have a separate memory access path. In some examples, the texture cache 3558 may also be configured as a sampler cache.

[0363] In some examples, the render output pipeline 3570 includes a rasterizer and depth test component 3573 that converts vertex-based objects into associated pixel-based representations. In some examples, the rasterizer logic includes a windower / masker unit for performing fixed-function triangle and line rasterization. In some examples, an associated render buffer 3578 and depth buffer 3579 are also available. The pixel operation component 3577 performs pixel-based operations on data, but in some instances, pixel operations associated with 2D operations (e.g., using mixed bit block image transfers) are performed by the 2D engine 3541, or replaced by the display controller 3543 using an overlay display plane when displaying. In some examples, a shared L3 cache 3575 can be used for all graphics components, allowing data to be shared without using main system memory.

[0364] In some examples, the graphics processor media pipeline 3530 includes a media engine 3537 and a video front end 3534. In some examples, the video front end 3534 receives pipeline commands from the command stream converter 3503. In some examples, the media pipeline 3530 includes a separate command stream converter. In some examples, the video front end 3534 processes the media commands before sending them to the media engine 3537. In some examples, the media engine 3537 includes a thread generation function for generating threads for dispatching to the thread execution logic 3550 via the thread dispatcher 3531.

[0365] In some examples, the graphics processor 3500 includes a display engine 3540. In some examples, the display engine 3540 is external to the processor 3500 and is coupled to the graphics processor via a ring interconnect 3502, or some other interconnect bus or structure. In some examples, the display engine 3540 includes a 2D engine 3541 and a display controller 3543. In some examples, the display engine 3540 contains dedicated logic that can operate independently of the 3D pipeline. In some examples, the display controller 3543 is coupled to a display device (not shown), which can be a system-integrated display device such as in a laptop or an external display device attached via a display device connector.

[0366] In some examples, the geometry pipeline 3520 and the media pipeline 3530 may be configured to perform operations based on multiple graphics and media programming interfaces and are not dedicated to any one application programming interface (API). In some examples, the driver software for the graphics processor converts API calls dedicated to a specific graphics or media library into commands that can be processed by the graphics processor. In some examples, support is provided for the Open Graphics Library (OpenGL), the Open Computing Language (OpenCL), and / or the Vulkan graphics and computing APIs all from the Khronos Group. In some examples, support may also be provided for the Direct3D library from Microsoft. In some examples, a combination of these libraries may be supported. Support may also be provided for the Open Source Computer Vision Library (OpenCV). If a mapping from the pipeline of a future API to the pipeline of a graphics processor can be performed, future APIs with compatible 3D pipelines will also be supported.

[0367] Graphics pipeline programming

[0368] Fig.36A is a block diagram of a graphics processor command format 3600 according to some examples. Fig.36B is a block diagram illustrating a graphics processor command sequence 3610 according to an example. Fig.36A The solid-line boxes in illustrate components that are generally included in the graphics commands, while the dashed lines include components that are optional or included only in a subset of the graphics commands. Fig.36A An exemplary graphics processor command format 3600 includes data fields for identifying the client 3602 of the command, a command operation code (opcode) 3604, and data 3606. Subopcodes 3605 and command sizes 3608 are also included in some commands.

[0369] In some examples, client 3602 specifies a client unit of a graphics device that processes command data. In some examples, a graphics processor command parser checks the client field of each command to adjust further processing of the command and routes the command data to the appropriate client unit. In some examples, a graphics processor client unit includes a memory interface unit, a rendering unit, a 2D unit, a 3D unit, and a media unit. Each client unit has a corresponding processing pipeline for processing commands. Once a command is received by a client unit, the client unit reads an opcode 3604 and a sub-opcode 3605 (if present) to determine the operation to be performed. The client unit uses the information in the data field 3606 to execute the command. For some commands, an explicit command size 3608 is expected to specify the size of the command. In some examples, the command parser automatically determines the size of at least some of the commands based on the command opcode. In some examples, commands are aligned via multiples of double words. Other command formats may be used.

[0370] Fig.36B 3610. In some examples, software or firmware of a data processing system featuring an example of a graphics processor may use a version of the command sequence shown to establish, execute, and terminate a set of graphics operations. The sample command sequence is shown and described for example purposes only, as the examples are not limited to these particular commands or command sequences. In addition, commands may be issued as batches of commands in a command sequence so that the graphics processor will process the command sequence in an at least partially concurrent manner.

[0371] In some examples, the graphics processor command sequence 3610 can begin with a pipeline flush command 3612 to cause any active graphics pipeline to complete currently pending commands for the pipeline. In some examples, the 3D pipeline 3622 and the media pipeline 3624 do not operate concurrently. The pipeline flush is performed to cause the active graphics pipeline to complete any pending commands. In response to the pipeline flush, the command parser for the graphics processor will suspend command processing until the active drawing engine completes pending operations and the associated read cache is invalidated. Optionally, any data marked as "dirty" in the rendering cache can be flushed to memory. In some examples, the pipeline flush command 3612 can be used for pipeline synchronization, or can be used before placing the graphics processor in a low power state.

[0372] In some examples, when a command sequence requires the graphics processor to explicitly switch between pipelines, pipeline select command 3613 is used. In some examples, pipeline select command 3613 is only required once in an execution context before issuing pipeline commands, unless the context is issuing commands for both pipelines. In some examples, pipeline flush command 3612 is required immediately before a pipeline switch via pipeline select command 3613.

[0373] In some examples, pipeline control commands 3614 configure the graphics pipeline for operation and are used to program 3D pipeline 3622 and media pipeline 3624. In some examples, pipeline control commands 3614 configure pipeline states for active pipelines. In some examples, pipeline control commands 3614 are used for pipeline synchronization and are used to clear data from one or more cache memories within an active pipeline before processing a batch of commands.

[0374] In some examples, return buffer state commands 3616 are used to configure a set of return buffers for a corresponding pipeline for writing data. Some pipeline operations require the allocation, selection, or configuration of one or more return buffers into which the operation writes intermediate data during processing. In some examples, a graphics processor also uses one or more return buffers to store output data and perform cross-thread communication. In some examples, return buffer state 3616 includes selecting the size and number of return buffers to be used for a set of pipeline operations.

[0375] The remaining commands in the command sequence differ based on the active pipeline for the operation.Based on pipeline decision 3620 , the command sequence is tailored for either the 3D pipeline 3622 starting at 3D pipeline state 3630 , or the media pipeline 3624 starting at media pipeline state 3640 .

[0376] The commands for configuring 3D pipeline state 3630 include 3D state setup commands for vertex buffer state, vertex element state, constant color state, depth buffer state, and other state variables that will be configured before processing 3D primitive commands. The values ​​of these commands are determined at least in part based on the specific 3D API in use. In some examples, 3D pipeline state 3630 commands can also selectively disable or bypass certain pipeline elements if those elements will not be used.

[0377] In some examples, the 3D primitive 3632 command is used to submit a 3D primitive to be processed by the 3D pipeline. The command and associated parameters passed to the graphics processor via the 3D primitive 3632 command are forwarded to the vertex acquisition function in the graphics pipeline. The vertex acquisition function uses the 3D primitive 3632 command data to generate a vertex data structure. The vertex data structure is stored in one or more return buffers. In some examples, the 3D primitive 3632 command is used to perform vertex operations on the 3D primitive via a vertex shader. To process the vertex shader, the 3D pipeline 3622 dispatches the shader execution thread to the graphics processor execution unit.

[0378] In some examples, the 3D pipeline 3622 is triggered via an execute 3634 command or event. In some examples, a register input triggers the command execution. In some examples, the execution is triggered via a "go" or "kick" command in the command sequence. In some examples, the command execution is triggered using a pipeline synchronization command to flush the command sequence through the graphics pipeline. The 3D pipeline will perform geometry processing for 3D primitives. Once the operation is completed, the resulting geometric objects are rasterized and the pixel engine shades the resulting pixels. For those operations, additional commands for controlling pixel shading and pixel backend operations may also be included.

[0379] In some examples, when performing media operations, the graphics processor command sequence 3610 follows the media pipeline 3624 path. In general, the specific purpose and manner of programming the media pipeline 3624 depends on the media or computing operations to be performed. During media decoding, specific media decoding operations can be migrated to the media pipeline. In some examples, the media pipeline can also be bypassed, and the media decoding can be performed in whole or in part using resources provided by one or more general processing cores. In some examples, the media pipeline also includes elements for general purpose graphics processor unit (GPGPU) operations, wherein the graphics processor is used to perform SIMD vector operations using compute shader programs that are not explicitly related to the rendering of graphics primitives.

[0380] In some examples, the media pipeline 3624 is configured in a similar manner as the 3D pipeline 3622. A set of commands for configuring the media pipeline state 3640 is dispatched or placed into a command queue before the media object commands 3642. In some examples, the commands for the media pipeline state 3640 include data for configuring the media pipeline elements that will be used to process the media objects. This includes data for configuring video decoding and video encoding logic within the media pipeline, such as encoding or decoding formats. In some examples, the commands for the media pipeline state 3640 also support the use of one or more pointers to an "indirect" state element that contains a batch of state settings.

[0381] In some examples, media object commands 3642 supply a pointer to a media object for processing by the media pipeline. The media object includes a memory buffer that contains video data to be processed. In some examples, all media pipeline states must be valid before issuing media object commands 3642. Once the pipeline state is configured and media object commands 3642 are queued, media pipeline 3624 is triggered via an execute command 3644 or an equivalent execute event (e.g., a register write). The output from media pipeline 3624 can then be post-processed by operations provided by 3D pipeline 3622 or media pipeline 3624. In some examples, GPGPU operations are configured and executed in a manner similar to media operations.

[0382] Program code can be applied to input information to perform the functions described herein and generate output information. The output information can be applied to one or more output devices in a known manner. For the present application, the processing system includes any system having a processor, such as a digital signal processor (DSP), a microcontroller, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a microprocessor, or any combination thereof.

[0383] Program code can be implemented in a process-oriented or object-oriented high-level programming language to communicate with the processing system. If desired, program code can also be implemented in assembly or machine language. In fact, the mechanism described herein is not limited to any specific programming language in scope. In any case, the language can be a compiled language or an interpreted language.

[0384] Examples of the mechanisms disclosed herein can be implemented in hardware, software, firmware, or a combination of these implementation approaches. Examples can be implemented as computer programs or program codes, executed on a programmable system including at least one processor, a storage system (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device.

[0385] These machine-readable storage media may include, but are not limited to, non-transitory tangible arrangements of items manufactured or formed by a machine or device, including storage media such as: hard disks, any other type of disk (including floppy disks, optical disks, compact disk read-only memory (CD-ROM), compact disk rewritable (CD-RW), and magneto-optical disks), semiconductor devices (e.g., read-only memory (ROM), random access memory (RAM) such as dynamic random access memory (DRAM), static random access memory (SRAM), erasable programmable read-only memory (EPROM), flash memory, electrically erasable programmable read-only memory (EEPROM), phase change memory (PCM)), magnetic cards or optical cards, or any other type of medium suitable for storing electronic instructions.

[0386] Therefore, examples also include non-transitory tangible machine-readable media containing instructions or design data, such as hardware description languages ​​(HDL), that define the structures, circuits, devices, processors and / or system features described herein. Such examples may also be referred to as program products.

[0387] Emulation (including binary translation, code deformation, etc.)

[0388] In some cases, the instruction converter can be used to convert instructions from a source instruction set architecture to a target instruction set architecture. For example, the instruction converter can translate (e.g., using static binary translation, dynamic binary translation including dynamic compilation), deform, simulate or otherwise convert instructions to one or more other instructions to be processed by the core. The instruction converter can be implemented with software, hardware, firmware or a combination thereof. The instruction converter can be on the processor, outside the processor, or partly on the processor and partly outside the processor.

[0389] Fig.37The block diagram of using a software instruction converter to convert binary instructions in a source ISA into binary instructions in a target ISA according to an example is illustrated. In the illustrated example, the instruction converter is a software instruction converter, but alternatively, the instruction converter can be implemented in software, firmware, hardware, or various combinations thereof. Fig.37 A program in a high-level language 3702 is shown to be compiled using a first ISA compiler 3704 to generate first ISA binary code 3706 that can be natively executed by a processor having at least one first ISA core 3716. The processor having at least one first ISA core 3716 represents any processor that is capable of executing or otherwise processing (1) a substantial portion of the first ISA or (2) a program that is natively executed by a processor having at least one first ISA core. The first ISA compiler 3704 represents a compiler operable to generate first ISA binary code 3706 (e.g., object code) that can be executed on a processor 3716 having at least one first ISA core with or without additional linking processing. Similarly, Fig.37 It is shown that a program in a high-level language 3702 can be compiled using an alternative ISA compiler 3708 to generate an alternative ISA binary code 3710, which can be executed natively by a processor 3714 without a first ISA core. An instruction converter 3712 is used to convert the first ISA binary code 3706 into code that can be executed natively by a processor 3714 without a first ISA core. This converted code is not necessarily the same as the alternative ISA binary code 3710; however, the converted code will implement the overall operation and be composed of instructions from the alternative ISA. Thus, the instruction converter 3712 represents software, firmware, hardware, or a combination thereof that allows a processor or other electronic device without a first ISA processor or core to execute the first ISA binary code 3706 through simulation, emulation, or any other process.

[0390] IP core implementation

[0391] One or more aspects of at least some examples may be implemented by representative code stored on a machine-readable medium that represents and / or defines logic within an integrated circuit (such as a processor). For example, a machine-readable medium may include instructions representing various logic within a processor. When read by a machine, the instructions may cause the machine to manufacture logic for performing the techniques described herein. Such representations (referred to as "IP cores") are reusable units of logic for an integrated circuit that can be stored on a tangible, machine-readable medium as a hardware model describing the structure of the integrated circuit. The hardware model may be supplied to each customer or manufacturing facility that loads the hardware model on a manufacturing machine that manufactures the integrated circuit. The integrated circuit may be manufactured so that the circuit performs the operations described in association with any of the examples described herein.

[0392] Fig.38 38 is a block diagram illustrating an IP core development system 3800 that can be used to manufacture an integrated circuit to perform operations according to some examples. The IP core development system 3800 can be used to generate modular, reusable designs that can be incorporated into a larger design or used to build an entire integrated circuit (e.g., a SOC integrated circuit). The design facility 3830 can generate a software simulation 3810 of the IP core design in a high-level programming language (e.g., C / C++). The software simulation 3810 can be used to design, test, and verify the behavior of the IP core using a simulation model 3812. The simulation model 3812 can include functional simulation, behavioral simulation, and / or timing simulation. A register transfer level (RTL) design 3815 can then be created or synthesized from the simulation model 3812. The RTL design 3815 is an abstraction of the behavior of an integrated circuit (including associated logic executed using the modeled digital signals) that models the flow of digital signals between hardware registers. In addition to the RTL design 3815, a lower level design at the logic level or transistor level can also be created, designed, or synthesized. Thus, the specific details of the initial design and simulation can be different.

[0393] The RTL design 3815 or equivalent may be further synthesized by the design facility into a hardware model 3820, which may be in a hardware description language (HDL) or some other representation of physical design data. The HDL may be further simulated or tested to verify the IP core design. Non-volatile memory 3840 (e.g., a hard disk, flash memory, or any non-volatile storage medium) may be used to store the IP core design for delivery to a third-party manufacturing facility 3865. Alternatively, the IP core design may be transmitted via a wired connection 3850 or a wireless connection 3860 (e.g., via the Internet). The manufacturing facility 3865 may then manufacture an integrated circuit based at least in part on the IP core design. The manufactured integrated circuit may be configured to perform operations according to at least some of the examples described herein.

[0394] References to "some examples," "examples," etc. indicate that the examples described may include a particular feature, structure, or characteristic, but not every example may necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same example. In addition, when a particular feature, structure, or characteristic is described in conjunction with an example, it is considered to be within the knowledge of those skilled in the art to affect such feature, structure, or characteristic in conjunction with other examples, whether or not explicitly described.

[0395] Furthermore, in the examples described above, unless specifically noted otherwise, separating language such as phrases "at least one of A, B, or C" or "A, B and / or C" are intended to be understood to mean A, B, or C, or any combination thereof (i.e., A and B, A and C, B and C, and A, B and C).

[0396] Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the disclosure as set forth in the claims.

Claims

1. A device comprising: a decoder circuit system for decoding a first instruction into a decoded first instruction, the first instruction including identifiers of a first register, a second register, a third register, and an opcode, the first register being used to store a first word of a Keccak status value according to a SHA3 standard, the second register being used to store a second word of the Keccak status value and a third word of the Keccak status value, the third register being used to store a fourth word of the Keccak status value and a fifth word of the Keccak status value, the opcode being used to instruct a vector execution circuit system including a plurality of lanes to perform a column parity operation of a theta step of a Keccak permutation according to the SHA3 standard using only a single lane of the plurality of lanes to determine a calculated parity value for an input of: the first word of the Keccak status value, the second word of the Keccak status value, the third word of the Keccak status value, the fourth word of the Keccak status value, and the fifth word of the Keccak status value, and storing the calculated parity value in an unused high word of the first register; as well as The vector execution circuitry is for executing the decoded first instruction according to the opcode.

2. The device according to claim 1, wherein: The single channel is 128 bits wide.

3. The device as claimed in claim 2, wherein: The first register, the second register and the third register are each 128 bits wide.

4. The device of claim 1, wherein: The decoder circuit system is used to decode the second instruction into a decoded second instruction, the second instruction including a register for storing a sixth word of a Keccak state value according to the SHA3 standard, a register for storing a seventh word of the Keccak state value and an eighth word of the Keccak state value, a register for storing a ninth word of the Keccak state value and a cross of the Keccak state value, and an identifier of an operation code, the operation code being used to instruct the vector execution circuit system including the multiple channels to perform an XOR operation of a theta step of a Keccak permutation according to the SHA3 standard and a circular shift operation of a rho step of a Keccak permutation according to the SHA3 standard using only a single channel of the multiple channels to determine multiple updated words of Keccak state values ​​for input of the following items, and store the multiple updated words of the Keccak state value into one of the registers: the sixth word of the Keccak state value, the seventh word of the Keccak state value, the eighth word of the Keccak state value, the ninth word of the Keccak state value, and the cross of the Keccak state value; and The vector execution circuitry is to execute the decoded second instruction according to the opcode.

5. The device of claim 1, wherein: The decoder circuit system is used to decode the second instruction into a decoded second instruction, the second instruction including a register for storing a sixth word of a Keccak state value according to the SHA3 standard, a register for storing a seventh word of the Keccak state value and an eighth word of the Keccak state value, a register for storing a ninth word of the Keccak state value and a cross of the Keccak state value, and an identifier of an operation code, the operation code being used to instruct the vector execution circuit system including the multiple channels to perform an XOR operation of the theta step of the Keccak permutation according to the SHA3 standard and a circular shift operation of the rho step of the Keccak permutation according to the SHA3 standard using only a single channel of the multiple channels to determine a single updated word of the Keccak state value for input of the following items, and store the single updated word of the Keccak state value in one of the registers: the sixth word of the Keccak state value, the seventh word of the Keccak state value, the eighth word of the Keccak state value, the ninth word of the Keccak state value, and the cross of the Keccak state value; and The vector execution circuitry is to execute the decoded second instruction according to the opcode.

6. The device of claim 1, wherein: The decoder circuit system is used to decode the second instruction into a decoded second instruction, the second instruction including a register for storing a sixth word of a Keccak status value according to the SHA3 standard, a register for storing a seventh word of the Keccak status value and an eighth word of the Keccak status value, a register for storing a ninth word of the Keccak status value and a cross of the Keccak status value, and an identifier of an operation code, the operation code being used to instruct the vector execution circuit system including the multiple channels to perform a data rearrangement operation of a pi step of a Keccak permutation according to the SHA3 standard using only a single channel of the multiple channels to determine an updated word of the Keccak status value for input of the following items, and store the updated word of the Keccak status value in one of the registers: the sixth word of the Keccak status value, the seventh word of the Keccak status value, the eighth word of the Keccak status value, the ninth word of the Keccak status value, and the cross of the Keccak status value; and The vector execution circuitry is to execute the decoded second instruction according to the opcode.

7. The device of claim 1, wherein: The decoder circuit system is used to decode the second instruction into a decoded second instruction, the second instruction including a register for storing a sixth word of a Keccak status value according to the SHA3 standard, a register for storing a seventh word of the Keccak status value and an eighth word of the Keccak status value, a register for storing a ninth word of the Keccak status value and a cross of the Keccak status value, and an identifier of an operation code, the operation code being used to instruct the vector execution circuit system including the multiple channels to perform a logical operation of a chi step of a Keccak permutation according to the SHA3 standard using only a single channel of the multiple channels to determine an updated word of the Keccak status value for the input of the following items, and store the updated word of the Keccak status value in one of the registers: the sixth word of the Keccak status value, the seventh word of the Keccak status value, the eighth word of the Keccak status value, the ninth word of the Keccak status value, and the cross of the Keccak status value; and The vector execution circuitry is to execute the decoded second instruction according to the opcode.

8. A method comprising: a first instruction decoded by a decoder circuit system into a decoded first instruction, the first instruction including identifiers of a first register, a second register, a third register, and an opcode, the first register being used to store a first word of a Keccak status value according to a SHA3 standard, the second register being used to store a second word of the Keccak status value and a third word of the Keccak status value, the third register being used to store a fourth word of the Keccak status value and a fifth word of the Keccak status value, the opcode being used to instruct a vector execution circuit system including a plurality of lanes to perform a column parity operation of a theta step of a Keccak permutation according to the SHA3 standard using only a single lane of the plurality of lanes to determine a calculated parity value for an input of: the first word of the Keccak status value, the second word of the Keccak status value, the third word of the Keccak status value, the fourth word of the Keccak status value, and the fifth word of the Keccak status value, and storing the calculated parity value in an unused high word of the first register; as well as The decoded first instruction is executed by the vector execution circuitry in accordance with the opcode.

9. The method of claim 8, wherein: The single channel is 128 bits wide.

10. The method of claim 9, wherein: The first register, the second register and the third register are each 128 bits wide.

11. The method of claim 8, further comprising: a second instruction decoded by the decoder circuitry into a decoded second instruction, the second instruction comprising a register for storing a sixth word of a Keccak state value according to the SHA3 standard, a register for storing a seventh word of the Keccak state value and an eighth word of the Keccak state value, a register for storing a ninth word of the Keccak state value and a cross of the Keccak state value, and an identifier of an operation code, the operation code being used to instruct the vector execution circuitry including the plurality of lanes to perform an XOR operation of a theta step of a Keccak permutation according to the SHA3 standard and to perform a circular shift operation of a rho step of a Keccak permutation according to the SHA3 standard using only a single lane of the plurality of lanes to determine a plurality of updated words of Keccak state values ​​for input of the following items, and to store the plurality of updated words of the Keccak state value into one of the registers: the sixth word of the Keccak state value, the seventh word of the Keccak state value, the eighth word of the Keccak state value, the ninth word of the Keccak state value, and the cross of the Keccak state value; as well as The decoded second instruction is executed by the vector execution circuitry in accordance with the opcode.

12. The method of claim 8, further comprising: a second instruction decoded by the decoder circuitry into a decoded second instruction, the second instruction comprising a register for storing a sixth word of a Keccak state value according to the SHA3 standard, a register for storing a seventh word of the Keccak state value and an eighth word of the Keccak state value, a register for storing a ninth word of the Keccak state value and a cross of the Keccak state value, and an identifier of an operation code, the operation code being used to instruct the vector execution circuitry including the plurality of lanes to perform an XOR operation of a theta step of a Keccak permutation according to the SHA3 standard and to perform a circular shift operation of a rho step of a Keccak permutation according to the SHA3 standard using only a single lane of the plurality of lanes to determine a single updated word of Keccak state value for input of the following items, and to store the single updated word of the Keccak state value in one of the registers: the sixth word of the Keccak state value, the seventh word of the Keccak state value, the eighth word of the Keccak state value, the ninth word of the Keccak state value, and the cross of the Keccak state value; as well as The decoded second instruction is executed by the vector execution circuitry in accordance with the opcode.

13. The method of claim 8, further comprising: a second instruction decoded by the decoder circuit system into a decoded second instruction, the second instruction including a register for storing a sixth word of a Keccak status value according to the SHA3 standard, a register for storing a seventh word of the Keccak status value and an eighth word of the Keccak status value, a register for storing a ninth word of the Keccak status value and a cross of the Keccak status value, and an identifier of an operation code, the operation code being used to instruct the vector execution circuit system including the plurality of lanes to perform a data rearrangement operation of a pi step of a Keccak permutation according to the SHA3 standard using only a single lane of the plurality of lanes to determine an updated word of the Keccak status value for input of the following items, and to store the updated word of the Keccak status value in one of the registers: the sixth word of the Keccak status value, the seventh word of the Keccak status value, the eighth word of the Keccak status value, the ninth word of the Keccak status value, and the cross of the Keccak status value; as well as The decoded second instruction is executed by the vector execution circuitry in accordance with the opcode.

14. The method of claim 8, further comprising: a second instruction decoded by the decoder circuitry into a decoded second instruction, the second instruction comprising a register for storing a sixth word of a Keccak state value according to the SHA3 standard, a register for storing a seventh word of the Keccak state value and an eighth word of the Keccak state value, a register for storing a ninth word of the Keccak state value and a cross of the Keccak state value, and an identifier of an operation code, the operation code being used to instruct the vector execution circuitry including the plurality of lanes to perform a logical operation of a chi step of a Keccak permutation according to the SHA3 standard using only a single lane of the plurality of lanes to determine an updated word of the Keccak state value for input of the following items, and storing the updated word of the Keccak state value in one of the registers: the sixth word of the Keccak state value, the seventh word of the Keccak state value, the eighth word of the Keccak state value, the ninth word of the Keccak state value, and the cross of the Keccak state value; as well as The decoded second instruction is executed by the vector execution circuitry in accordance with the opcode.

15. A non-transitory machine-readable medium storing code which, when executed by a machine, causes the machine to perform a method comprising: a first instruction decoded by a decoder circuit system into a decoded first instruction, the first instruction including identifiers of a first register, a second register, a third register, and an operation code, the first register being used to store a first word of a Keccak status value according to a SHA3 standard, the second register being used to store a second word of the Keccak status value and a third word of the Keccak status value, the third register being used to store a fourth word of the Keccak status value and a fifth word of the Keccak status value, the operation code being used to instruct a vector execution circuit system including a plurality of channels to perform a column parity operation of a theta step of a Keccak permutation according to the SHA3 standard using only a single channel of the plurality of channels to determine a calculated parity value for an input of each of the following items, and storing the calculated parity value in an unused high word of the first register: the first word of the Keccak status value, the second word of the Keccak status value, the third word of the Keccak status value, the fourth word of the Keccak status value, and the fifth word of the Keccak status value; and The decoded first instruction is executed by the vector execution circuitry in accordance with the opcode.

16. The non-transitory machine-readable medium of claim 15, wherein: The single channel is 128 bits wide.

17. The non-transitory machine-readable medium of claim 15, wherein: The method further comprises: a second instruction decoded by the decoder circuit system into a decoded second instruction, the second instruction including a register for storing a sixth word of a Keccak state value according to the SHA3 standard, a register for storing a seventh word of the Keccak state value and an eighth word of the Keccak state value, a register for storing a ninth word of the Keccak state value and a cross of the Keccak state value, and an identifier of an operation code, the operation code being used to instruct the vector execution circuit system including the multiple channels to perform an XOR operation of a theta step of a Keccak permutation according to the SHA3 standard and a circular shift operation of a rho step of a Keccak permutation according to the SHA3 standard using only a single channel of the multiple channels to determine a plurality of updated words of Keccak state values ​​for input of the following items, and store the plurality of updated words of the Keccak state value into one of the registers: the sixth word of the Keccak state value, the seventh word of the Keccak state value, the eighth word of the Keccak state value, the ninth word of the Keccak state value, and the cross of the Keccak state value; and The decoded second instruction is executed by the vector execution circuitry in accordance with the opcode.

18. The non-transitory machine-readable medium of claim 15, wherein: The method further comprises: a second instruction decoded by the decoder circuit system into a decoded second instruction, the second instruction including a register for storing a sixth word of a Keccak state value according to the SHA3 standard, a register for storing a seventh word of the Keccak state value and an eighth word of the Keccak state value, a register for storing a ninth word of the Keccak state value and a cross of the Keccak state value, and an identifier of an operation code, the operation code being used to instruct the vector execution circuit system including the multiple channels to perform an XOR operation of the theta step of the Keccak permutation according to the SHA3 standard and a circular shift operation of the rho step of the Keccak permutation according to the SHA3 standard using only a single channel of the multiple channels to determine a single updated word of the Keccak state value for input of the following items, and store the single updated word of the Keccak state value in one of the registers: the sixth word of the Keccak state value, the seventh word of the Keccak state value, the eighth word of the Keccak state value, the ninth word of the Keccak state value, and the cross of the Keccak state value; and The decoded second instruction is executed by the vector execution circuitry in accordance with the opcode.

19. The non-transitory machine-readable medium of claim 15, wherein: The method further comprises: a second instruction decoded by the decoder circuit system into a decoded second instruction, the second instruction including a register for storing a sixth word of a Keccak status value according to the SHA3 standard, a register for storing a seventh word of the Keccak status value and an eighth word of the Keccak status value, a register for storing a ninth word of the Keccak status value and a cross of the Keccak status value, and an identifier of an operation code, the operation code being used to instruct the vector execution circuit system including the multiple channels to perform a data rearrangement operation of a pi step of a Keccak permutation according to the SHA3 standard using only a single channel of the multiple channels to determine an updated word of the Keccak status value for input of the following items, and store the updated word of the Keccak status value in one of the registers: the sixth word of the Keccak status value, the seventh word of the Keccak status value, the eighth word of the Keccak status value, the ninth word of the Keccak status value, and the cross of the Keccak status value; and The decoded second instruction is executed by the vector execution circuitry in accordance with the opcode.

20. The non-transitory machine-readable medium of claim 15, wherein: The method further comprises: a second instruction decoded by the decoder circuit system into a decoded second instruction, the second instruction including a register for storing a sixth word of a Keccak status value according to the SHA3 standard, a register for storing a seventh word of the Keccak status value and an eighth word of the Keccak status value, a register for storing a ninth word of the Keccak status value and a cross of the Keccak status value, and an identifier of an operation code, the operation code being used to instruct the vector execution circuit system including the multiple channels to perform a logical operation of a chi step of a Keccak permutation according to the SHA3 standard using only a single channel of the multiple channels to determine an updated word of the Keccak status value for input of the following items, and storing the updated word of the Keccak status value in one of the registers: the sixth word of the Keccak status value, the seventh word of the Keccak status value, the eighth word of the Keccak status value, the ninth word of the Keccak status value, and the cross of the Keccak status value; and The decoded second instruction is executed by the vector execution circuitry in accordance with the opcode.

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