Scheduling Method and Device for Virtual Machine Threads

Abstract

An embodiment of the present disclosure provides a method and device for scheduling virtual machine threads. The method includes: in response to receiving a scheduling instruction for a first VCPU thread on a virtual processor of a virtual machine, determining the processor affinity of the first VCPU thread through a load balancer scheduler; determining that the processor affinity of a second VCPU thread in the virtual processor is a second hyper-thread logical processor in a target physical processor according to the processor affinity of the first VCPU thread; scheduling a first hyper-thread logical processor to run the first VCPU thread according to the processor affinity of the first VCPU thread; and scheduling a second hyper-thread logical processor to run the second VCPU thread according to the processor affinity of the second VCPU thread. This method improves the stability of the virtual machine.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of cloud computing technology, and in particular, to a method and device for scheduling virtual machine threads. Background Art

[0002] In the cloud computing scenario, according to the core binding situation of VCPU (Virtual Central Processing Unit) threads in the virtual processors of virtual machines, virtual processors can be roughly divided into two categories: dedicated instance virtual processors and oversubscribed instance virtual processors. Among them, dedicated instance virtual processors bind VCPU threads to PCPUs (Physical Central Processing Units) one by one, and do not bind multiple VCPU threads to the same PCPU at the same time. Such instances have the highest performance.

[0003] Currently, physical processors with the X86 architecture all provide hyper-threading capabilities, dividing a physical processor into two HT logical cores (Hyper-Threading, hyper-threaded logical processors), which can improve the throughput of the physical processor. Enabling / disabling hyper-threading affects the overall performance of the physical processor. Assuming that after disabling hyper-threading, the maximum computing performance of a physical processor is X, then after enabling hyper-threading, the maximum computing performance of a physical processor is 1.3X, and at this time, two hyper-threaded logical processors run tasks simultaneously.

[0004] The inventors found that the prior art at least has the following technical problems: In the scenario where hyper-threading is enabled on a physical processor, the stability of virtual machine performance is poor. Summary of the Invention

[0005] Embodiments of the present disclosure provide a method and device for scheduling virtual machine threads, which can improve the stability of virtual machine operation.

[0006] In a first aspect, embodiments of the present disclosure provide a method for scheduling virtual machine threads, including:

[0007] In response to receiving a scheduling instruction for a first VCPU thread on a virtual processor of a virtual machine, determine the processor affinity of the first VCPU thread through a load balancer scheduler. The processor affinity of the first VCPU thread is used to configure a first hyper-threaded logical processor for running the first VCPU thread and a target physical processor to which the first hyper-threaded logical processor belongs;

[0008] According to the processor affinity of the first VCPU thread, determine that the processor affinity of a second VCPU thread in the virtual processor is a second hyper-threaded logical processor in the target physical processor;

[0009] Schedule the first hyper-threaded logical processor to run the first VCPU thread according to the processor affinity of the first VCPU thread; and schedule the second hyper-threaded logical processor to run the second VCPU thread according to the processor affinity of the second VCPU thread.

[0010] In a second aspect, an embodiment of the present disclosure provides a scheduling device for virtual machine threads, including:

[0011] A receiving unit, configured to, in response to receiving a scheduling instruction for a first virtual central processing unit (VCPU) thread on a virtual processor of a virtual machine, determine the processor affinity of the first VCPU thread through a load balancer scheduler, where the processor affinity of the first VCPU thread is used to configure a first hyper-threaded logical processor for running the first VCPU thread and a target physical processor to which the first hyper-threaded logical processor belongs;

[0012] A determining unit, configured to determine, according to the processor affinity of the first VCPU thread, that the processor affinity of a second VCPU thread in the virtual processor is a second hyper-threaded logical processor in the target physical processor;

[0013] A scheduling unit, configured to schedule the first hyper-threaded logical processor to run the first VCPU thread according to the processor affinity of the first VCPU thread; and schedule the second hyper-threaded logical processor to run the second VCPU thread according to the processor affinity of the second VCPU thread.

[0014] In a third aspect, an embodiment of the present disclosure provides an electronic device, including: a processor and a memory;

[0015] The memory stores computer-executable instructions;

[0016] The processor executes the computer-executable instructions stored in the memory, so that the at least one processor executes the scheduling method for virtual machine threads as described in the first aspect and various possible designs of the first aspect above.

[0017] In a fourth aspect, an embodiment of the present disclosure provides a computer-readable storage medium, in which computer-executable instructions are stored, and when a processor executes the computer-executable instructions, the scheduling method for virtual machine threads as described in the first aspect and various possible designs of the first aspect above is implemented.

[0018] In a fifth aspect, an embodiment of the present disclosure provides a computer program product, including a computer program, where when the computer program is executed by a processor, the scheduling method for virtual machine threads as described in the first aspect and various possible designs of the first aspect above is implemented.

[0019] The scheduling method and device for virtual machine threads provided in this embodiment. The method includes: in response to receiving a scheduling instruction for the first virtual central processing unit (VCPU) thread on a virtual processor of a virtual machine, determining the processor affinity of the first VCPU thread through a load balancer scheduler, where the processor affinity of the first VCPU thread is used to configure the first hyper-threaded logical processor for running the first VCPU thread and the target physical processor to which the first hyper-threaded logical processor belongs; determining, according to the processor affinity of the first VCPU thread, that the processor affinity of the second VCPU thread in the virtual processor is the second hyper-threaded logical processor in the target physical processor; scheduling the first hyper-threaded logical processor to run the first VCPU thread according to the processor affinity of the first VCPU thread; and scheduling the second hyper-threaded logical processor to run the second VCPU thread according to the processor affinity of the second VCPU thread. In this technical solution, since the processor affinity of the second VCPU thread in the virtual processor is determined according to the processor affinity of the first VCPU thread, it is ensured that the hyper-threaded logical processors running the first VCPU thread and the second VCPU thread are in the same physical processor, solving the performance burst problem caused by two VCPU threads in the same virtual processor running on two physical processors simultaneously, thus improving the stability of the virtual processor operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts. [[ID=⑧]] [[ID=⑨]]

[0021] [[ID=⑩]] Figure 1 [[ID=⑪]]Schematic diagram of the scheduling method for virtual machine threads provided by the prior art[[ID=⑫]] Figure 1 [[ID=⑬]];[[ID=⑭]] [[ID=⑮]]

[0022] [[ID=⑯]] Figure 2 [[ID=⑰]]Flow chart of the scheduling method for virtual machine threads provided by the embodiments of the present disclosure[[ID=⑱]] Figure 1 [[ID=⑲]];[[ID=⑳]] [[ID=㉑]]

[0023] [[ID=㉒]] Figure 3 [[ID=㉓]]Schematic diagram of the scheduling method for virtual machine threads provided by the embodiments of the present disclosure[[ID=㉔]] Figure 1 [[ID=㉕]];[[ID=㉖]] [[ID=㉗]]

[0024] [[ID=㉘]] Figure 4 [[ID=㉙]]Schematic diagram of the scheduling method for virtual machine threads provided by the prior art[[ID=㉚]] Figure 2 [[ID=㉛]]; [[ID=㉜]] [[ID=㉝]]

[0025] [[ID=㉞]] Figure 5Flow chart of the scheduling method for virtual machine threads provided by an embodiment of the present disclosure Figure 2 ;

[0026] Figure 6 Schematic diagram of the scheduling method for virtual machine threads provided by an embodiment of the present disclosure Figure 2 ;

[0027] Figure 7 Schematic structural diagram of the scheduling device for virtual machine threads provided by an embodiment of the present disclosure;

[0028] Figure 8 Schematic structural diagram of the electronic device provided by an embodiment of the present disclosure. Detailed implementation manners

[0029] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Apparently, the described embodiments are some but not all of the embodiments of the present disclosure. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present disclosure without creative efforts shall fall within the protection scope of the present disclosure.

[0030] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Apparently, the described embodiments are some but not all of the embodiments of the present disclosure. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present disclosure without creative efforts shall fall within the protection scope of the present disclosure.

[0031] In the cloud computing scenario, according to the core binding situation of VCPU (Virtual Central Processing Unit) threads in the virtual processors of virtual machines, the virtual processors can be roughly divided into two categories: dedicated instance virtual processors and oversubscribed instance virtual processors. Among them, the dedicated instance virtual processor binds the VCPU thread to the PCPU (Physical Central Processing Unit) one-to-one, and does not bind multiple VCPU threads to the same PCPU at the same time. This type of instance has the highest performance. Among them, the oversubscribed instance virtual processor binds the VCPU threads to multiple PCPUs and sells the PCPUs according to a certain oversubscription ratio. For example: there are 10 PCPUs on a physical processor. If oversubscribed by 2 times, 20 VCPUs will be created on this physical processor. This type of instance is cheap but has relatively large performance jitter.

[0032] All physical processors in the X86 architecture now offer hyper-threading capabilities, which divide a physical processor into two HT logical cores (Hyper-Threading, hyper-threaded logical processors), thereby improving the throughput of the physical processor. Turning hyper-threading on / off will affect the overall performance of the physical processor. Assuming that after hyper-threading is turned off, the maximum computing performance of a physical processor is X. Then, after hyper-threading is turned on, the maximum computing performance of a physical processor is 1.3X. At this time, two hyper-threaded logical processors are running tasks simultaneously. The maximum computing performance of a single hyper-threaded logical processor is still X. At this time, one HT hyper-thread is running tasks, while the other HT hyper-thread is not running tasks.

[0033] This application primarily addresses two performance jitter issues associated with oversold instances in cloud computing scenarios. The first performance jitter issue is how to address performance spikes caused by two VCPU threads in a virtual processor running simultaneously on two physical processors. The second performance jitter issue is how to prevent VCPU threads on different virtual processors from interfering with each other's performance when running simultaneously on the same physical processor.

[0034] The introduction and solution to the first performance jitter problem are as follows: In an oversold scenario, the VCPU threads in the virtual processor of the oversold instance need to be bound to a core range. As a result, two VCPU threads of the same virtual processor will run on two hyperthreaded logical processors of two physical processors. This may cause the computing performance of one virtual processor to be equivalent to that of two physical processors.

[0035] For example, Figure 1 As shown, the virtual processor contains two VCPU threads (such as Figure 1 VCPU thread 0 and VCPU thread 1) run simultaneously on two hyperthreaded logical processors of two physical processors (such as Figure 1 In this case, the computing performance of a virtual processor is the sum of the performance of the two physical processors (for example, 2X). When the two VCPU threads contained in a virtual processor run on the two HT hyperthreads on the same physical processor, the computing performance of a virtual processor is at most 1.3X. This will lead to unstable running performance of the virtual processor. Moreover, in the dedicated scenario, the two VCPU threads of each virtual processor will only be bound to the two hyperthreaded logical processors on one physical processor, so the computing performance of a virtual processor is equal to the computing performance of one physical processor. In this way, the performance of the virtual processor of the cheap oversold instance may be higher than that of the expensive dedicated instance virtual processor, which is not what cloud service providers want.

[0036] The inventor found that the prior art has at least the following technical problems: in the scenario where hyper-threading is enabled on a physical processor, the performance stability of virtual processors is relatively poor.

[0037] In response to the technical problems in the prior art, the technical concept of the inventor is as follows: two VCPU threads of a virtual processor at the same moment can only run on the same physical processor. To ensure that the two VCPU threads in the same virtual processor run on the same physical processor, the running VCPU threads can be dynamically bound to cores.

[0038] Correspondingly, the specific steps may include: in response to receiving a scheduling instruction for the first virtual processor VCPU thread on the virtual processor of the virtual machine, determining the processor affinity of the first VCPU thread through a load balancing scheduler, where the processor affinity of the first VCPU thread is used to configure the first hyper-thread logical processor that runs the first VCPU thread and the target physical processor to which the first hyper-thread logical processor belongs; determining, according to the processor affinity of the first VCPU thread, that the processor affinity of the second VCPU thread in the virtual processor is the second hyper-thread logical processor in the target physical processor; scheduling the first hyper-thread logical processor to run the first VCPU thread according to the processor affinity of the first VCPU thread; and scheduling the second hyper-thread logical processor to run the second VCPU thread according to the processor affinity of the second VCPU thread.

[0039] In this technical solution, since the processor affinity of the second VCPU thread in the virtual processor is determined according to the processor affinity of the first VCPU thread, it is ensured that the hyper-thread logical processor running the first VCPU thread and the hyper-thread logical processor running the second VCPU thread are in the same physical processor, solving the problem of performance mutation caused by the two VCPU threads in the same virtual processor running on two physical processors at the same time. Therefore, the running stability of the virtual processor is improved.

[0040] The following is the specific implementation process of the virtual machine thread scheduling method and device involved in the embodiments of the present disclosure. Some examples are only for illustration and are not limited. The execution subject of the virtual machine thread scheduling method involved in the embodiments of the present disclosure is an electronic device, and the electronic device may be a terminal, a server, etc.

[0041] Figure 2 For the virtual machine thread scheduling method flow provided by the embodiments of the present disclosure Figure 1 , as Figure 2 shown, the virtual machine thread scheduling method may include:

[0042] S201. In response to receiving a scheduling instruction for a first virtual central processing unit (VCPU) thread on a virtual processor of a virtual machine, determine, by means of a load balancing scheduler, the processor affinity of the first VCPU thread, where the processor affinity of the first VCPU thread is used to configure a first hyper-threaded logical processor that runs the first VCPU thread and a target physical processor to which the first hyper-threaded logical processor belongs.

[0043] In an embodiment of the present disclosure, a virtual machine includes one or more virtual processors, and the first VCPU thread and the second VCPU thread represent two different virtual hyper-threads on the same virtual processor. A physical machine includes one or more physical processors, and the first hyper-threaded logical processor and the second hyper-threaded logical processor represent two different hyper-threaded logical processors on the same physical processor. Herein, a hyper-threaded logical processor may also be referred to as a logical core. A physical processor may be referred to as a physical core.

[0044] In some embodiments, schedule the first VCPU thread by means of a load balancing scheduler. Correspondingly, this step may include: in response to receiving a scheduling instruction for a first virtual central processing unit (VCPU) thread on a virtual processor of a virtual machine, determine, by means of a load balancing scheduler, a target physical processor with the least load from multiple candidate physical processors; determine the processor affinity of the first VCPU thread as the first hyper-threaded logical processor in the target physical processor with the least load.

[0045] In an embodiment of the present disclosure, the parity of the thread number of the first VCPU thread and the parity of the thread number of the second VCPU thread are different. Herein, the first VCPU thread may be a VCPU thread with an even thread number or a VCPU thread with an odd thread number. For example, the thread number of the first VCPU thread is even and the thread number of the second VCPU thread is odd, or the thread number of the first VCPU thread is odd and the thread number of the second VCPU thread is even.

[0046] Optionally, the first VCPU thread may be a VCPU thread with an even thread number. Exemplarily, as Figure 3 shown, the first VCPU thread is the VCPU thread 0 in the virtual processor.

[0047] S202. According to the processor affinity of the first VCPU thread, determine the processor affinity of the second VCPU thread in the virtual processor as the second hyper-threaded logical processor in the target physical processor.

[0048] In an embodiment of the present disclosure, the parity of the thread number of the first VCPU thread and the parity of the thread number of the second VCPU thread are different.

[0049] In some embodiments, the thread number of the first VCPU thread is an even number, and the thread number of the second VCPU thread is an odd number; in this case, the processor affinity of the VCPU threads with even numbers can be scheduled by the load balancer scheduler. The processor affinity of the VCPU threads with odd numbers is adjusted as the processor affinity of the VCPU threads with even numbers is adjusted.

[0050] Exemplarily, as Figure 3 shown, the first VCPU thread is the VCPU thread 0 in the virtual processor, and the thread number is an even number. The second VCPU thread is the VCPU thread 1 in the virtual processor, and the thread number is an odd number. The processor affinity of the VCPU thread 0 can be scheduled by the load balancer scheduler. The processor affinity of the VCPU thread 1 is adjusted as the processor affinity of the VCPU thread 0 is adjusted.

[0051] As Figure 3 shown, when the processor affinity of the VCPU thread 0 is the TH hyper-thread 0 on the physical processor 0, then the processor affinity of the VCPU thread 1 is adjusted to be the TH hyper-thread 1 on the physical processor 0. When the processor affinity of the VCPU thread 0 is the TH hyper-thread 0 on the physical processor 1, then the processor affinity of the VCPU thread 1 is adjusted to be the TH hyper-thread 1 on the physical processor 1.

[0052] In other embodiments, the thread number of the first VCPU thread is an odd number, and the thread number of the second VCPU thread is an even number. In this case, the processor affinity of the VCPU threads with odd numbers can be scheduled by the load balancer scheduler. The processor affinity of the VCPU threads with even numbers is adjusted as the processor affinity of the VCPU threads with odd numbers is adjusted.

[0053] S203. Schedule the first hyper-thread logical processor to run the first VCPU thread according to the processor affinity of the first VCPU thread; and schedule the second hyper-thread logical processor to run the second VCPU thread according to the processor affinity of the second VCPU thread.

[0054] In some embodiments, before scheduling the second hyper-thread logical processor to run the second VCPU thread according to the processor affinity of the second VCPU thread, the method further includes: determining the working state of the second VCPU thread on the virtual processor; if the working state of the second VCPU thread is the running state, then schedule the second hyper-thread logical processor to run the second VCPU thread according to the processor affinity of the second VCPU thread.

[0055] An embodiment of the present disclosure provides a method for scheduling virtual machine threads: in response to receiving a scheduling instruction for a first virtual central processing unit (VCPU) thread on a virtual processor of a virtual machine, determining, by a load balancer scheduler, the processor affinity of the first VCPU thread, where the processor affinity of the first VCPU thread is used to configure a first hyper-threaded logical processor for running the first VCPU thread and a target physical processor to which the first hyper-threaded logical processor belongs; determining, according to the processor affinity of the first VCPU thread, that the processor affinity of a second VCPU thread in the virtual processor is a second hyper-threaded logical processor in the target physical processor; scheduling the first hyper-threaded logical processor to run the first VCPU thread according to the processor affinity of the first VCPU thread; and scheduling the second hyper-threaded logical processor to run the second VCPU thread according to the processor affinity of the second VCPU thread. In this technical solution, since the processor affinity of the second VCPU thread in the virtual processor is determined according to the processor affinity of the first VCPU thread, it is ensured that the hyper-threaded logical processors running the first VCPU thread and the hyper-threaded logical processors running the second VCPU thread are in the same physical processor, solving the problem of performance mutation caused by two VCPU threads in the same virtual processor running on two physical processors at the same time, thus improving the stability of the virtual processor operation.

[0056] The introduction and solution to the second performance jitter problem are as follows: in an oversold scenario, there may be performance interference between different virtual processors. Exemplarily, as Figure 4 shown: a VCPU thread 0 in virtual processor 1 and a VCPU thread 1 in virtual processor 2 run on two hyper-threaded logical processors (HT hyper-thread 0 and TH hyper-thread 1) of the same physical processor at the same time. At this time, it will affect the performance of the hyper-threaded logical processor corresponding to virtual processor 1 and the performance of the hyper-threaded logical processor corresponding to virtual processor 2, and further affect the stability of the virtual processor operation.

[0057] The core idea of this solution is: when a VCPU thread in a virtual processor is running and another VCPU thread is not running, ensure that the non-running VCPU thread occupies another hyper-threaded logical processor on the same physical processor. This can prevent the VCPU threads running on other virtual processors from being scheduled to this physical processor. Correspondingly, as Figure 5 shown, the method includes:

[0058] S501. Obtain the working status of two VCPU threads running on each virtual processor.

[0059] Among them, the working states of VCPU threads include: the running state (running); the runnable state (runnable), that is, the state waiting to be scheduled; and the blocked state (blocked).

[0060] S502. If a VCPU thread on the same virtual processor is in the running state and occupies a hyper-thread logical processor of the physical processor, and another VCPU thread is in the blocked state, then wake up the other VCPU thread in the blocked state and preempt another hyper-thread logical processor of the physical processor.

[0061] In this step, when a VCPU thread is being processed by the first hyper-thread logical processor on the physical processor, by waking up the other VCPU thread in the blocked state, it is possible to prevent the VCPU threads running on other virtual processors from being scheduled to this physical processor.

[0062] In some embodiments, a VCPU thread on a virtual processor runs on a hyper-thread logical processor of a physical processor; correspondingly, waking up the other VCPU thread in the blocked state and preempting another hyper-thread logical processor of the physical processor includes: sending a wake-up instruction to the other VCPU thread in the blocked state to wake it up, and making the woken-up VCPU thread execute the mwait (processor wait) instruction to preempt another hyper-thread logical processor of the physical processor; where the mwait instruction is used to make the VCPU thread enter the low-power mode.

[0063] Exemplarily, as Figure 6 shown, the VCPU thread 0 on virtual processor 1 is in the running state, and the VCPU thread 1 on virtual processor 1 is in the blocked state. Among them, the VCPU thread 0 on virtual processor 1 runs on the TH hyper-thread 0 on the physical processor. At this time, in order to prevent the VCPU threads running on other virtual processors from being scheduled to this physical processor, the VCPU thread 1 on virtual processor 1 can be woken up to preempt another hyper-thread logical processor on the same physical processor ( Figure 6 the TH hyper-thread 1 therein).

[0064] Exemplarily, as Figure 6As shown, the VCPU thread 1 on the virtual processor 2 is in the running state, and the VCPU thread 0 on the virtual processor 2 is in the sleep state. Among them, the VCPU thread 1 on the virtual processor 2 runs on the TH hyper-thread 1 on the physical processor. At this time, in order to prevent the VCPU threads running on other virtual processors from being scheduled to this physical processor, the VCPU thread 0 on the virtual processor 2 can be awakened to preempt another hyper-thread logical processor on the same physical processor ( Figure 6 the TH hyper-thread 0 in

[0065] It should be noted that if the working state of a VCPU thread on the same virtual processor switches from the running state to the sleep state, then control the other VCPU thread to stop executing the mwait instruction and switch to the sleep state.

[0066] In the embodiment of the present disclosure, when processing a VCPU thread on a virtual processor through the first hyper-thread logical processor on the physical processor, by awakening another VCPU thread in the sleep state on the virtual processor, it is possible to prevent the VCPU threads running on other virtual processors from being scheduled to this physical processor. At this time, the computing power of the VCPU thread processed by the first hyper-thread logical processor is equivalent to the computing power of the physical processor, thereby ensuring that the performance of the running VCPU thread is not affected.

[0067] It should be noted that the above scheduling method is a virtual machine thread scheduling method based on the KVM (kernel-based virtual machine) side. It not only effectively solves the performance jitter problem of the virtual machine after enabling hyper-threading (abbreviated as TH) in the oversubscription scenario. Moreover, the advantage of the virtual machine thread scheduling method based on the KVM side is that the virtual machine can be flexibly hot-upgraded without depending on the kernel or other component versions.

[0068] Figure 7 The following is a schematic structural diagram of the scheduling device for virtual machine threads provided by the embodiment of the present disclosure. As Figure 7 shown, the scheduling device for virtual machine threads includes:

[0069] A receiving unit 701, configured to determine the processor affinity of the first VCPU thread in response to receiving a scheduling instruction for the first virtual processor VCPU thread on the virtual processor of the virtual machine through a load balancer scheduler. The processor affinity of the first VCPU thread is used to configure the first hyper-thread logical processor for running the first VCPU thread and the target physical processor to which the first hyper-thread logical processor belongs;

[0070] A determination unit 702, configured to determine, according to the processor affinity of the first VCPU thread, that the processor affinity of the second VCPU thread in the virtual processor is the second hyper-thread logical processor in the target physical processor;

[0071] A scheduling unit 703, configured to schedule the first hyper-thread logical processor to run the first VCPU thread according to the processor affinity of the first VCPU thread; and schedule the second hyper-thread logical processor to run the second VCPU thread according to the processor affinity of the second VCPU thread.

[0072] According to one or more embodiments of the present disclosure, the parity of the thread number of the first VCPU thread and the thread number of the second VCPU thread is different.

[0073] According to one or more embodiments of the present disclosure, the scheduling unit 703 is further configured to determine the working state of the second VCPU thread on the virtual processor; if the working state of the second VCPU thread is the running state, schedule the second hyper-thread logical processor to run the second VCPU thread according to the processor affinity of the second VCPU thread.

[0074] According to one or more embodiments of the present disclosure, the virtual machine includes multiple virtual processors, and two VCPU threads are running on each virtual processor; correspondingly, the scheduling unit 703 is further configured to obtain the working states of the two VCPU threads running on each virtual processor; if one VCPU thread on the same virtual processor is in the running state and occupies one hyper-thread logical processor of the physical processor, and the other VCPU thread is in the sleep state, wake up the other VCPU thread in the sleep state and preempt the other hyper-thread logical processor of the physical processor.

[0075] According to one or more embodiments of the present disclosure, the scheduling unit 703 wakes up the other VCPU thread in the sleep state and preempts the other hyper-thread logical processor of the physical processor, including: sending a wake-up instruction to the other VCPU thread in the sleep state to wake up the other VCPU thread in the sleep state, and making the woken-up VCPU thread execute the processor wait mwait instruction to preempt the other hyper-thread logical processor of the physical processor; wherein the mwait instruction is used to make the VCPU thread be in a low-power mode.

[0076] According to one or more embodiments of the present disclosure, the scheduling unit 703 is further configured to, if the working state of a VCPU thread on the same virtual processor switches from the running state to the sleep state, control another VCPU thread to stop executing the mwait instruction and switch to the sleep state.

[0077] According to one or more embodiments of the present disclosure, upon receiving a scheduling instruction for a first virtual processor VCPU thread on the virtual processor of a virtual machine, the determining unit 702 determines the processor affinity of the first VCPU thread through a load balancing scheduler, including: upon receiving a scheduling instruction for a first virtual processor VCPU thread on the virtual processor of a virtual machine, determining, through a load balancing scheduler, a target physical processor with the least load from multiple candidate physical processors; and determining the processor affinity of the first VCPU thread as the first hyper-thread logical processor in the target physical processor with the least load.

[0078] Reference Figure 8 , which shows a schematic structural diagram of an electronic device 800 suitable for implementing embodiments of the present disclosure. The electronic device 800 may be a terminal device or a server. Among them, the terminal device may include, but is not limited to, mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, personal digital assistants (PDAs), tablet computers, portable media players (PMPs), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc. Figure 8 The electronic device shown is only an example and should not impose any limitations on the functions and usage scope of the embodiments of the present disclosure.

[0079] As Figure 8 shown, the electronic device 800 may include a processing device (such as a central processing unit, a graphics processing unit, etc.) 801, which may execute various appropriate actions and processes according to a program stored in a read-only memory (ROM) 802 or a program loaded from a storage device 808 into a random access memory (RAM) 803. In the RAM 803, various programs and data required for the operation of the electronic device 800 are also stored. The processing device 801, the ROM 802, and the RAM 803 are connected to each other through a bus 804. An input / output (I / O) interface 805 is also connected to the bus 804.

[0080] Typically, the following devices can be connected to the I / O interface 805: an input device 806 including, for example, a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 807 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 808 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 809. The communication device 809 can allow the electronic device 800 to communicate with other devices wirelessly or wiredly to exchange data. Although Figure 8 the electronic device 800 with various devices is shown, it should be understood that it is not required to implement or have all the shown devices. Instead, more or fewer devices can be implemented or had.

[0081] Specifically, according to an embodiment of the present disclosure, the process described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present disclosure includes a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program contains program codes for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network through the communication device 809, or installed from the storage device 808, or installed from the ROM 802. When the computer program is executed by the processing device 801, the above functions defined in the method of the embodiment of the present disclosure are executed.

[0082] It should be noted that the computer-readable medium described above in the present disclosure can be a computer-readable signal medium, a computer-readable storage medium, or any combination of the two. A computer-readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the above. More specific examples of a computer-readable storage medium can include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present disclosure, a computer-readable storage medium can be any tangible medium that contains or stores a program, which can be used by or in conjunction with an instruction execution system, apparatus, or device. In the present disclosure, a computer-readable signal medium can include a data signal propagated in a baseband or as part of a carrier wave, which carries computer-readable program code. Such a propagated data signal can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. A computer-readable signal medium can also be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device. The program code contained on a computer-readable medium can be transmitted by any appropriate medium, including but not limited to: wires, optical cables, RF (radio frequency), etc., or any suitable combination of the above.

[0083] The above computer-readable medium can be included in the above electronic device; or it can exist separately and not be assembled into the electronic device.

[0084] The above computer-readable medium carries one or more programs, and when the one or more programs are executed by the electronic device, the electronic device is caused to execute the method shown in the above embodiments.

[0085] Computer program code for performing the operations of the present disclosure may be written in one or more programming languages or combinations thereof. The above-mentioned programming languages include object-oriented programming languages such as Java, Smalltalk, C++, and also include conventional procedural programming languages such as the "C" language or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, executed as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., by connecting through the Internet using an Internet service provider).

[0086] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architectures, functions, and operations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagram may represent a module, a segment of a program, or a part of code that contains one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than marked in the accompanying drawings. For example, two consecutive blocks shown may actually be executed substantially in parallel, and they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, and combinations of blocks in the block diagram and / or flowchart, may be implemented by a dedicated hardware-based system for performing the specified functions or operations, or may be implemented by a combination of dedicated hardware and computer instructions.

[0087] The units involved in the embodiments described in the present disclosure may be implemented in software or in hardware. Among them, the name of the unit does not constitute a limitation to the unit itself in some cases. For example, the first acquisition unit may also be described as "the unit for acquiring at least two Internet protocol addresses".

[0088] The functions described above herein may be performed at least in part by one or more hardware logic components. For example, without limitation, exemplary types of hardware logic components that may be used include: field programmable gate arrays (FPGA), application specific integrated circuits (ASIC), application specific standard products (ASSP), system on a chip (SOC), complex programmable logic devices (CPLD), and so on.

[0089] In a first aspect, according to one or more embodiments of the present disclosure, a method for scheduling virtual machine threads is provided, including:

[0090] In response to receiving a scheduling instruction for a first virtual central processing unit (VCPU) thread on a virtual processor of a virtual machine, determine, by a load balancer scheduler, the processor affinity of the first VCPU thread, where the processor affinity of the first VCPU thread is used to configure a first hyper-threaded logical processor that runs the first VCPU thread and a target physical processor to which the first hyper-threaded logical processor belongs;

[0091] Determine, according to the processor affinity of the first VCPU thread, that the processor affinity of a second VCPU thread in the virtual processor is a second hyper-threaded logical processor in the target physical processor;

[0092] Schedule the first hyper-threaded logical processor to run the first VCPU thread according to the processor affinity of the first VCPU thread; and schedule the second hyper-threaded logical processor to run the second VCPU thread according to the processor affinity of the second VCPU thread.

[0093] According to one or more embodiments of the present disclosure, the parity of the thread number of the first VCPU thread and the thread number of the second VCPU thread is different.

[0094] According to one or more embodiments of the present disclosure, before scheduling the second hyper-threaded logical processor to run the second VCPU thread according to the processor affinity of the second VCPU thread, the method further includes: determining the working state of the second VCPU thread on the virtual processor; if the working state of the second VCPU thread is a running state, then schedule the second hyper-threaded logical processor to run the second VCPU thread according to the processor affinity of the second VCPU thread.

[0095] According to one or more embodiments of the present disclosure, the virtual machine includes multiple virtual processors, and two VCPU threads are running on each virtual processor; correspondingly, the method further includes: obtaining the working states of the two VCPU threads running on each virtual processor; if one VCPU thread on the same virtual processor is in a running state and occupies one hyper-threaded logical processor of a physical processor, and the other VCPU thread is in a dormant state, then wake up the other VCPU thread in the dormant state and preempt the other hyper-threaded logical processor of the physical processor.

[0096] According to one or more embodiments of the present disclosure, waking up another VCPU thread in a processing sleep state and preempting another hyper-threaded logical processor of the physical processor includes: sending a wake-up instruction to another VCPU thread in a processing sleep state to wake up the other VCPU thread in a processing sleep state, and causing the woken-up VCPU thread to execute a processor wait mwait instruction to preempt another hyper-threaded logical processor of the physical processor; wherein, the mwait instruction is used to put the VCPU thread in a low-power mode.

[0097] According to one or more embodiments of the present disclosure, the method further includes: if the working state of a VCPU thread on the same virtual processor switches from a running state to a sleep state, controlling another VCPU thread to stop executing the mwait instruction and switch to a sleep state.

[0098] According to one or more embodiments of the present disclosure, in response to receiving a scheduling instruction for a first virtual processor VCPU thread on a virtual processor of a virtual machine, determining the processor affinity of the first VCPU thread by a load balancing scheduler includes: in response to receiving a scheduling instruction for a first virtual processor VCPU thread on a virtual processor of a virtual machine, determining a target physical processor with the lowest load from multiple candidate physical processors by the load balancing scheduler; determining the processor affinity of the first VCPU thread as the first hyper-threaded logical processor in the target physical processor with the lowest load.

[0099] In a second aspect, according to one or more embodiments of the present disclosure, there is provided a scheduling device for virtual machine threads, including:

[0100] A receiving unit, configured to, in response to receiving a scheduling instruction for a first virtual processor VCPU thread on a virtual processor of a virtual machine, determine the processor affinity of the first VCPU thread by a load balancing scheduler, where the processor affinity of the first VCPU thread is used to configure a first hyper-threaded logical processor for running the first VCPU thread and a target physical processor to which the first hyper-threaded logical processor belongs;

[0101] A determining unit, configured to determine, according to the processor affinity of the first VCPU thread, the processor affinity of a second VCPU thread in the virtual processor as a second hyper-threaded logical processor in the target physical processor;

[0102] A scheduling unit, configured to, according to the processor affinity of the first VCPU thread, schedule the first hyper-threaded logical processor to run the first VCPU thread; and, according to the processor affinity of the second VCPU thread, schedule the second hyper-threaded logical processor to run the second VCPU thread.

[0103] According to one or more embodiments of the present disclosure, the parity of the thread number of the first VCPU thread and the thread number of the second VCPU thread is different.

[0104] According to one or more embodiments of the present disclosure, the scheduling unit is further configured to determine the working state of the second VCPU thread on the virtual processor; if the working state of the second VCPU thread is the running state, then schedule the second hyper-threaded logical processor to run the second VCPU thread according to the processor affinity of the second VCPU thread.

[0105] According to one or more embodiments of the present disclosure, the virtual machine includes multiple virtual processors, and two VCPU threads are running on each virtual processor; correspondingly, the scheduling unit is further configured to obtain the working states of the two VCPU threads running on each virtual processor; if one VCPU thread on the same virtual processor is in the running state and occupies one hyper-threaded logical processor of the physical processor, and the other VCPU thread is in the sleep state, then wake up the other VCPU thread in the sleep state and preempt the other hyper-threaded logical processor of the physical processor.

[0106] According to one or more embodiments of the present disclosure, the scheduling unit wakes up the other VCPU thread in the sleep state and preempts the other hyper-threaded logical processor of the physical processor, including: sending a wake-up instruction to the other VCPU thread in the sleep state to wake up the other VCPU thread in the sleep state, and making the awakened VCPU thread execute the processor wait mwait instruction to preempt the other hyper-threaded logical processor of the physical processor; wherein, the mwait instruction is used to make the VCPU thread enter the low-power mode.

[0107] According to one or more embodiments of the present disclosure, the scheduling unit is further configured to control the other VCPU thread to stop executing the mwait instruction and switch to the sleep state if the working state of one VCPU thread on the same virtual processor switches from the running state to the sleep state.

[0108] According to one or more embodiments of the present disclosure, the determining unit, in response to receiving a scheduling instruction for a first virtual central processing unit (VCPU) thread on a virtual processor of a virtual machine, determines the processor affinity of the first VCPU thread through a load balancing scheduler, including: in response to receiving a scheduling instruction for a first VCPU thread on a virtual processor of a virtual machine, determining, through the load balancing scheduler, a target physical processor with the minimum load from multiple candidate physical processors; and determining the processor affinity of the first VCPU thread as a first hyper-thread logical processor in the target physical processor with the minimum load.

[0109] In a third aspect, according to one or more embodiments of the present disclosure, there is provided an electronic device, including: at least one processor and a memory;

[0110] The memory stores computer-executable instructions;

[0111] The at least one processor executes the computer-executable instructions stored in the memory, so that the at least one processor executes the scheduling method of the virtual machine thread as described in the first aspect above and various possible designs of the first aspect.

[0112] In a fourth aspect, according to one or more embodiments of the present disclosure, there is provided a computer-readable storage medium, in which computer-executable instructions are stored, and when the processor executes the computer-executable instructions, the scheduling method of the virtual machine thread as described in the first aspect above and various possible designs of the first aspect is implemented.

[0113] In a fifth aspect, according to one or more embodiments of the present disclosure, there is provided a computer program product, including a computer program, and when the computer program is executed by a processor, the scheduling method of the virtual machine thread as described in the first aspect above and various possible designs of the first aspect is implemented.

[0114] The above description is only a preferred embodiment of the present disclosure and an explanation of the applied technical principles. Those skilled in the art should understand that the scope of disclosure involved in the present disclosure is not limited to the technical solutions formed by the specific combination of the above technical features, and should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the above disclosure concept. For example, the technical solutions formed by mutually replacing the above features with the technical features (but not limited to) having similar functions disclosed in the present disclosure.

[0115] Moreover, although the operations are depicted in a particular order, this should not be construed as requiring that the operations be performed in the particular order shown or in sequential order. In certain environments, multitasking and parallel processing may be advantageous. Similarly, although several specific implementation details are included in the foregoing discussion, these should not be construed as limitations on the scope of the present disclosure. Certain features that are described in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment may also be implemented separately or in any suitable sub-combination in multiple embodiments.

[0116] Although the subject matter has been described in language specific to structural features and / or methodological acts, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are merely example forms of implementing the claims.

Claims

1. A method for scheduling virtual machine threads, characterized in that: include: In response to receiving a scheduling instruction for a first virtual processor (VCPU) thread on a virtual processor of a virtual machine, determining, by a load balancing scheduler, a processor affinity of the first VCPU thread, wherein the processor affinity of the first VCPU thread is used to configure a first hyperthreaded logical processor running the first VCPU thread and a target physical processor to which the first hyperthreaded logical processor belongs; Determining, based on the processor affinity of the first VCPU thread, a processor affinity of a second VCPU thread in the virtual processor to be a second hyperthreaded logical processor in the target physical processor; Scheduling the first hyperthreaded logical processor to run the first VCPU thread based on the processor affinity of the first VCPU thread; and scheduling the second hyperthreaded logical processor to run the second VCPU thread based on the processor affinity of the second VCPU thread; If the first VCPU thread on a virtual processor is in a running state and occupies a hyperthreaded logical processor of a physical processor, and the second VCPU thread on the virtual processor is in a dormant state, the second VCPU thread is awakened and another hyperthreaded logical processor of the physical processor is preempted.

2. The method according to claim 1, characterized in that The thread number of the first VCPU thread and the thread number of the second VCPU thread have different parities.

3. The method according to claim 1, characterized in that Before scheduling the second hyperthreaded logical processor to run the second VCPU thread according to the processor affinity of the second VCPU thread, the method further includes: Determine the operating status of a second VCPU thread on the virtual processor; If the working state of the second VCPU thread is the running state, the second hyper-threaded logical processor is scheduled to run the second VCPU thread according to the processor affinity of the second VCPU thread.

4. The method according to claim 1, wherein The waking up the second VCPU thread and preempting another hyperthreaded logical processor of the physical processor includes: Send a wake-up instruction to the second VCPU thread to wake up the second VCPU thread, and let the awakened second VCPU thread execute the processor wait mwait instruction to preempt another hyper-threaded logical processor of the physical processor; wherein the mwait instruction is used to put the VCPU thread in low power consumption mode.

5. The method according to claim 1, wherein The method further comprises: If the working state of a VCPU thread on the same virtual processor switches from the running state to the dormant state, the other VCPU thread is controlled to stop executing the mwait instruction and switch to the dormant state.

6. The method according to any one of claims 1 to 5, characterized in that In response to receiving a scheduling instruction for a first virtual processor (VCPU) thread on a virtual processor of a virtual machine, determining the processor affinity of the first VCPU thread by a load balancing scheduler includes: In response to receiving a scheduling instruction for a first virtual processor VCPU thread on a virtual processor of the virtual machine, determining, by a load balancing scheduler, a target physical processor with the smallest load from a plurality of candidate physical processors; The processor affinity of the first VCPU thread is determined to be the first hyperthreaded logical processor in the target physical processor with the least load.

7. A virtual machine thread scheduling device, characterized in that: include: a receiving unit configured to, in response to receiving a scheduling instruction for a first virtual processor (VCPU) thread on a virtual processor of a virtual machine, determine, through a load balancing scheduler, a processor affinity of the first VCPU thread, wherein the processor affinity of the first VCPU thread is used to configure a first hyper-threaded logical processor running the first VCPU thread and a target physical processor to which the first hyper-threaded logical processor belongs; a determining unit, configured to determine, based on the processor affinity of the first VCPU thread, a processor affinity of the second VCPU thread in the virtual processor to be a second hyperthreaded logical processor in the target physical processor; a scheduling unit, configured to schedule the first hyperthreaded logical processor to run the first VCPU thread according to the processor affinity of the first VCPU thread; and schedule the second hyperthreaded logical processor to run the second VCPU thread according to the processor affinity of the second VCPU thread; The scheduling unit is further configured to wake up a first VCPU thread on a virtual processor and preempt another hyperthreaded logical processor of the physical processor if the first VCPU thread on the virtual processor is in a running state and occupies a hyperthreaded logical processor of the physical processor, and the second VCPU thread on the virtual processor is in a dormant state.

8. An electronic device, characterized in that: include: processor and memory; The memory stores computer-executable instructions; The processor executes the computer-executable instructions stored in the memory, so that the processor executes the virtual machine thread scheduling method according to any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer-executable instructions. When a processor executes the computer-executable instructions, the method for scheduling virtual machine threads according to any one of claims 1 to 6 is implemented.

10. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the method for scheduling virtual machine threads according to any one of claims 1 to 6 is implemented.

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