Memory management method and storage device

Abstract

The invention provides a memory management method and a storage device. The method comprises the following steps of: obtaining a backup instruction for indicating to execute a backup operation on data belonging to a first logic range from a host system; after the backup operation is executed, an updating instruction used for indicating to update data belonging to a first logic unit is obtained from the host system, and the first logic unit is contained in a first logic range and mapped to a first entity unit; according to the updating instruction, data updating operation is executed on a second logic unit, the second logic unit is contained in a second logic range, the second logic range is different from the first logic range, and the second logic unit is mapped to a second entity unit; and if the data updating operation is successful, the first logic unit is changed to be mapped to the second entity unit, and the second logic unit is changed to be mapped to the first entity unit. Therefore, the execution efficiency of the storage device can be improved when the host system executes data backup and / or updating.

Description

Technical Field

[0001] The present invention relates to the field of storage technology, and in particular to a memory management method and a storage device. Background Art

[0002] Generally speaking, when a host system (such as a personal computer, server or online platform) needs to perform a data backup and / or update operation, the host system will issue a backup instruction for a specific logical unit (such as a logical block address (LBA)) to the storage device. After the storage device receives the backup instruction, the storage device will first back up and / or update the data belonging to the specific logical unit (also called target data) (for example, storing new data corresponding to the target data in a new storage location). However, during the execution of the backup and / or update operation, the repeated update and / or restoration of the target data consumes time and power, thereby affecting the execution efficiency and service life of the storage device.

[0003] Therefore, how to improve the execution efficiency and service life of the storage device during the period when the host system performs data backup and / or update is a problem that needs to be solved urgently. Summary of the invention

[0004] The present invention provides a memory management method and a storage device, which can improve the execution efficiency and service life of the storage device during the period when the host system executes data backup and / or update.

[0005] An embodiment of the present invention provides a memory management method, which is used for a storage device, wherein the storage device includes a memory module, the memory module includes multiple physical units, and the memory management method includes: obtaining a backup instruction from a host system, wherein the backup instruction is used to instruct to perform a backup operation on data belonging to a first logical range; after performing the backup operation, obtaining an update instruction from the host system, wherein the update instruction is used to instruct to update data belonging to a first logical unit, the first logical unit is included in the first logical range, and the first logical unit is mapped to a first physical unit among the multiple physical units; according to the update instruction, performing a data update operation on a second logical unit, wherein the second logical unit is included in a second logical range, the second logical range is different from the first logical range, and the second logical unit is mapped to a second physical unit among the multiple physical units; judging whether the data update operation is successful; and if the data update operation is successful, changing the first logical unit to be mapped to the second physical unit, and changing the second logical unit to be mapped to the first physical unit.

[0006] An embodiment of the present invention further provides a storage device, which includes a connection interface, a memory module and a memory controller. The connection interface is used to connect to a host system. The memory controller is connected to the connection interface and the memory module. The memory module includes a plurality of physical units, and the memory controller is used to: obtain a backup instruction from the host system, wherein the backup instruction is used to instruct to perform a backup operation on data belonging to a first logical range; after performing the backup operation, obtain an update instruction from the host system, wherein the update instruction is used to instruct to update data belonging to a first logical unit, the first logical unit is included in the first logical range, and the first logical unit is mapped to a first physical unit among the plurality of physical units; according to the update instruction, perform a data update operation on a second logical unit, wherein the second logical unit is included in a second logical range, the second logical range is different from the first logical range, and the second logical unit is mapped to a second physical unit among the plurality of physical units; determine whether the data update operation is successful; and if the data update operation is successful, change the first logical unit to be mapped to the second physical unit, and change the second logical unit to be mapped to the first physical unit.

[0007] Based on the above, after obtaining the backup instruction from the host system, the backup operation can be performed on the data belonging to the first logical range. After performing the backup operation, the update instruction can be obtained from the host system. In particular, the update instruction can be used to indicate the update of data belonging to the first logical unit, the first logical unit is included in the first logical range, and the first logical unit is mapped to the first physical unit. According to the update instruction, the data update operation can be performed on the second logical unit. In particular, the second logical unit is included in the second logical range, the second logical range is different from the first logical range, and the second logical unit is mapped to the second physical unit. After performing the data update operation, if it is determined that the data update operation is successful, the first logical unit can be changed to be mapped to the second physical unit, and the second logical unit can be changed to be mapped to the first physical unit. Therefore, the memory management method and storage device provided by the present invention can effectively improve the execution efficiency and service life of the storage device during the period when the host system performs data backup and / or update. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a schematic diagram of a data storage system according to an embodiment of the present invention;

[0009] Figure 2 is a schematic diagram of a memory controller according to an embodiment of the present invention;

[0010] Figure 3 is a schematic diagram of a management memory module according to an embodiment of the present invention;

[0011] Figures 4 to 6 is a schematic diagram of updating data belonging to a first logical unit according to an embodiment of the present invention;

[0012] Figure 7 is a flowchart of a memory management method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0013] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0014] Figure 1 is a schematic diagram of a data storage system according to an embodiment of the present invention. Figure 1 , the data storage system 10 includes a host system 11 and a storage device 12. The storage device 12 can be connected to the host system 11 and can be used to store data from the host system 11. For example, the host system 11 can be a smart phone, a tablet computer, a notebook computer, a desktop computer, an industrial computer, a game console, a server, or a computer system disposed in a specific carrier (such as a vehicle, an aircraft, or a ship), and the type of the host system 11 is not limited thereto. In addition, the storage device 12 may include a solid state drive, a USB flash drive, a memory card, or other types of non-volatile storage devices.

[0015] The storage device 12 includes a connection interface 121, a memory module 122, and a memory controller 123. The connection interface 121 is used to connect the storage device 12 to the host system 11. For example, the connection interface 121 can support an embedded Multi-Media Card (eMMC), a Universal Flash Storage (UFS), a Peripheral Component Interconnect Express (PCI Express), a Non-Volatile Memory Express (NVM express), a Serial Advanced Technology Attachment (SATA), a Universal Serial Bus (USB), or other types of connection interface standards. Therefore, the storage device 12 can communicate with the host system 11 via the connection interface 121 (e.g., exchange signals, instructions, and / or data).

[0016] The memory module 122 is used to store data. For example, the memory module 122 may include one or more rewritable non-volatile memory modules. Each rewritable non-volatile memory module may include one or more memory cell arrays. The memory cells in the memory cell array store data in the form of voltage (also called threshold voltage). For example, the memory module 122 may include a single level cell (SLC) NAND type flash memory module, a multi level cell (MLC) NAND type flash memory module, a triple level cell (TLC) NAND type flash memory module, a quad level cell (QLC) NAND type flash memory module and / or other memory modules having the same or similar characteristics.

[0017] The memory controller 123 is connected to the connection interface 121 and the memory module 122. The memory controller 123 can be regarded as the control core of the storage device 12 and is used to control the storage device 12. For example, the memory controller 123 can be used to control or manage the entire or partial operation of the storage device 12. For example, the memory controller 123 may include a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessors, digital signal processors (DSP), programmable controllers, application-specific integrated circuits (ASIC), programmable logic devices (PLD) or other similar devices or combinations of these devices. In one embodiment, the memory controller 123 may include a flash memory controller.

[0018] The memory controller 123 may send a command sequence to the memory module 122 to access the memory module 122. For example, the memory controller 123 may send a write command sequence to the memory module 122 to instruct the memory module 122 to store data in a specific storage unit. For example, the memory controller 123 may send a read command sequence to the memory module 122 to instruct the memory module 122 to read data from a specific storage unit. For example, the memory controller 123 may send an erase command sequence to the memory module 122 to instruct the memory module 122 to erase the data stored in a specific storage unit. In addition, the memory controller 123 may also send other types of command sequences to the memory module 122 to instruct the memory module 122 to perform other types of operations, which are not limited by the present invention. The memory module 122 may receive the command sequence from the memory controller 123 and access the storage unit inside the memory module 122 according to the command sequence.

[0019] Figure 2 FIG. 1 is a schematic diagram of a memory controller according to an embodiment of the present invention. Figure 1 and Figure 2 The memory controller 123 includes a host interface 21, a memory interface 22 and a memory control circuit 23. The host interface 21 is used to connect to the host system 11 through the connection interface 121 to communicate with the host system 11. The memory interface 22 is used to connect to the memory module 122 to access the memory module 122.

[0020] The memory control circuit 23 is connected to the host interface 21 and the memory interface 22. The memory control circuit 23 may be used to control or manage the whole or part of the operation of the memory controller 123. For example, the memory control circuit 23 may communicate with the host system 11 through the host interface 21 and access the memory module 122 through the memory interface 22. For example, the memory control circuit 23 may include a control circuit such as an embedded controller or a microcontroller. In the following embodiments, the description of the memory control circuit 23 is equivalent to the description of the memory controller 123.

[0021] In one embodiment, the memory controller 123 may further include a buffer memory 24. The buffer memory 24 is connected to the memory control circuit 23 and used to cache data. For example, the buffer memory 24 may be used to cache instructions from the host system 11, data from the host system 11, and / or data from the memory module 122.

[0022] In one embodiment, the memory controller 123 may further include a decoding circuit 25. The decoding circuit 25 is connected to the memory control circuit 23 and is used to perform encoding and decoding on the data to ensure the correctness of the data. For example, the decoding circuit 25 may support various encoding / decoding algorithms such as Low Density Parity Check Code (LDPC code), BCH code, Reed-Solomon code (RS code), Exclusive OR (XOR) code, etc. In one embodiment, the memory controller 123 may also include various other types of circuit modules (such as power management circuits, etc.), which are not limited by the present invention.

[0023] Figure 3 FIG. 1 is a schematic diagram of a management memory module according to an embodiment of the present invention. Figures 1 to 3 The memory module 122 includes a plurality of physical units 301 (1) to 301 (B). Each physical unit includes a plurality of storage units and is used to store data in a non-volatile manner. In one embodiment, a physical unit may include one or more physical programming units.

[0024] In one embodiment, a physical programming unit may include multiple physical sectors. For example, the data capacity of a physical sector may be 512 bytes (Bytes, B), and a physical programming unit may include 32 physical sectors. However, the data capacity of a physical sector and / or the total number of physical sectors included in a physical programming unit can be adjusted according to practical needs, and the present invention is not limited thereto. In one embodiment, a physical programming unit can be regarded as a physical page. For example, the storage capacity of a physical programming unit may be 16 kilobytes, and the present invention is not limited thereto.

[0025] In one embodiment, a physical programming unit is a minimum unit for synchronously writing data in the memory module 122. For example, when a programming operation (also referred to as a write operation) is performed on a physical programming unit to write data to the physical programming unit, multiple memory cells in the physical programming unit may be synchronously programmed to store corresponding data. For example, when programming a physical programming unit, a write voltage may be applied to the physical programming unit to change the threshold voltage of at least some of the memory cells in the physical programming unit. For example, the threshold voltage of a memory cell may reflect the bit data stored in the memory cell.

[0026] In one embodiment, a physical erase unit may include a plurality of physical programming units. The plurality of physical programming units in a physical erase unit may be erased synchronously. For example, when performing an erase operation on a physical erase unit, an erase voltage may be applied to the plurality of physical programming units in the physical erase unit to change the threshold voltage of at least some of the storage cells in the physical programming units. By performing an erase operation on a physical erase unit, the data stored in the physical erase unit may be cleared.

[0027] In one embodiment, the memory control circuit 23 can logically associate the physical units 301(1)-301(A) and 301(A+1)-301(B) to the data area 31 and the idle area 32, respectively. The physical units 301(1)-301(A) in the data area 31 all store data (also called user data) from the host system 11. For example, any physical unit in the data area 31 can store valid data and / or invalid data. In addition, the physical units 301(A+1)-301(B) in the idle area 32 do not store data (e.g., valid data).

[0028] In one embodiment, if a physical unit does not store valid data, the physical unit can be associated with the idle area 32. In addition, the physical unit in the idle area 32 can be erased to clear the data in the physical unit. In one embodiment, the physical unit in the idle area 32 is also called an idle physical unit. In one embodiment, the idle area 32 is also called an idle pool.

[0029] In one embodiment, when data is to be stored, the memory control circuit 23 may select one or more physical cells from the idle area 32 and instruct the memory module 122 to store the data in the selected physical cells. After the data is stored in the physical cell, the physical cell may be associated with the data area 31. In other words, one or more physical cells may be used alternately between the data area 31 and the idle area 32.

[0030] In one embodiment, the memory control circuit 23 may configure a plurality of logical units 302(1)-302(C) to map the physical units (i.e., the physical units 301(1)-301(A)) in the data area 31. For example, a logical unit may correspond to a logical block address (LBA) or other logical management units. A logical unit may be mapped to one or more physical units.

[0031] In one embodiment, if a physical unit is currently mapped by any logical unit, the memory control circuit 23 can determine that the data currently stored in the physical unit includes valid data. Conversely, if a physical unit is not currently mapped by any logical unit, the memory control circuit 23 can determine that the physical unit does not currently store any valid data.

[0032] In one embodiment, the memory control circuit 23 may record the mapping relationship between the logical unit and the physical unit in at least one management table (also referred to as a logical-to-physical mapping table). In one embodiment, the memory control circuit 23 may instruct the memory module 122 to perform operations such as data reading, writing or erasing according to the information in the management table (i.e., the logical-to-physical mapping table).

[0033] In one embodiment, the memory control circuit 23 may obtain at least one instruction (also referred to as a backup instruction) from the host system 11. The backup instruction is used to instruct to perform a backup operation on data belonging to a specific logical range (also referred to as a first logical range). For example, the first logical range may include Figure 3 At least two of the logical units 302(1) to 302(C) in the storage device 20. According to the backup instruction, the memory control circuit 23 may perform the backup operation on the data belonging to the first logical range. For example, the backup operation includes backing up the data belonging to the first logical range and additionally saving the backed-up data. For example, assuming that the current host system 11 is performing a backup operation for an operating system (OS) or other data, the software or firmware data of the operating system or other data to be backed up by the host system 11 may be stored in the first logical range.

[0034] In one embodiment, after performing the backup operation, the memory control circuit 23 may obtain at least one instruction (also referred to as an update instruction) from the host system 11. The update instruction may be used to instruct to update data belonging to at least one logical unit (also referred to as a first logical unit). For example, the first logical unit may include Figure 3 In particular, the first logical unit is included in the first logical range. In addition, the first logical unit can be mapped to at least one physical unit (also referred to as the first physical unit) in the memory module 122. For example, the first physical unit may include Figure 3 At least one of the entity units 301(1)~301(A).

[0035] In one embodiment, after obtaining the update instruction, the memory control circuit 23 may perform a data update operation on at least one logic unit (also referred to as the second logic unit) according to the update instruction. For example, the second logic unit may include Figure 3The second logic unit is different from the first logic unit. For example, assuming that the first logic unit includes Figure 3 , the second logical unit may include the logical unit 302(k), and j is not equal to k. In particular, the second logical unit is included in another logical range (also referred to as the second logical range), and the second logical range is different from the first logical range. For example, the first logical range and the second logical range do not overlap with each other. In addition, the second logical unit may be mapped to at least one physical unit (also referred to as the second physical unit) in the memory module 122. For example, the second physical unit may include Figure 3 It should be noted that the second entity unit is also different from the first entity unit. For example, assuming that the first entity unit includes Figure 3 If the second entity unit may include entity unit 301 (p), the second entity unit may include entity unit 301 (q), and p is not equal to q.

[0036] In one embodiment, after obtaining the backup instruction from the host system 11, the memory control circuit 23 may determine the second logical range according to the backup instruction. For example, the second logical range may be arranged continuously or discontinuously after the first logical range, and the first logical range and the second logical range do not overlap each other.

[0037] Specifically, the memory control circuit 23 may record the logical units in the second logical range as logical units that only store backup data, and when executing data recovery instructions subsequently, the corresponding backup data may be directly obtained from the physical units mapped by the logical units in the second logical range.

[0038] In one embodiment, the memory control circuit 23 may determine the second logic range according to the size of the first logic range (e.g., the total number of logic units included in the second logic range). Thus, the memory control circuit 23 may control the size of the second logic range (e.g., the total number of logic units included in the second logic range) to be the same as the size of the first logic range (e.g., the total number of logic units included in the first logic range).

[0039] In one embodiment, the memory control circuit 23 may determine an address offset of the first logical unit compared to the first logical range (also referred to as a first address offset). Then, based on the first address offset, the memory control circuit 23 may determine the second logical unit from the second logical range. For example, the first address offset may be the same as the second address offset of the second logical unit compared to the second logical range. In one embodiment, by controlling the first address offset to be the same as the second address offset, the efficiency of subsequently finding and managing the second logical unit may be accelerated.

[0040] In another embodiment, the memory control circuit 23 can determine the address offset (also called the third address offset) between the logical units corresponding to the first logical range and the second logical range. When a data update operation needs to be performed, the corresponding second logical unit can be directly obtained based on the first logical unit in the first logical range and the third address offset.

[0041] In one embodiment, in the data update operation performed on the second logical unit, the memory control circuit 23 may store the data (also referred to as the first data) in the second physical unit according to the update instruction. For example, the first data may include the (new) data to be stored (or updated) in the first logical unit as indicated by the update instruction.

[0042] Figure 4 FIG. 1 is a schematic diagram of performing a data update operation on a second logic unit according to an embodiment of the present invention. Figure 4 , assuming that logical range 41 is the first logical range. For example, logical range 41 includes logical units 410(1) to 410(D). In the backup operation performed on the data belonging to logical range 41, the data belonging to logical unit 410(i) (i.e., the first logical unit) is stored (i.e., backed up to) physical unit 420(1) (i.e., the first physical unit) for preservation. Therefore, logical range 41 can be mapped to physical unit 420(1).

[0043] In one embodiment, the memory control circuit 23 may determine the logic range 42 (i.e., the second logic range) according to the logic range 41 (or the backup instruction corresponding to the logic range 41). For example, the logic range 42 includes the logic units 410(D+1)-410(E). The logic ranges 41 and 42 do not overlap with each other, and the total number of the logic units 410(1)-410(D) included in the logic range 41 may be the same as the total number of the logic units 410(D+1)-410(E) included in the logic range 42.

[0044] In one embodiment, after performing the backup operation, it is assumed that the memory control circuit 23 obtains an update instruction 401 from the host system 11. The update instruction 401 indicates to update the data belonging to the logical unit 410 (i). For example, the update instruction 401 indicates to update the data belonging to the logical unit 410 (i) from the previously backed up (old) data to the (new) data 420.

[0045] In one embodiment, according to the update instruction 401, the memory control circuit 23 may determine the logical unit 410 (D+i) (i.e., the second logical unit) from the logical range 42. For example, the memory control circuit 23 may first determine the address offset of the logical unit 410 (i) compared to the logical range 41 (i.e., the first address offset). For example, the first address offset is "i". According to the first address offset, the memory control circuit 23 may determine the logical unit 410 (D+i) from the logical range 42. The address offset of the logical unit 410 (D+i) compared to the logical range 42 (i.e., the second address offset) may be the same as the first address offset. For example, the second address offset may also be "i". The memory control circuit 23 may determine the logical unit 410 (D+i) from the logical range 42 according to the second address offset (i.e., "i").

[0046] In another embodiment, the memory control circuit 23 may determine the address offset (also referred to as the third address offset) between the logical units corresponding to the logical range 41 and the logical range 42. For example, the third address offset is "D". Based on the logical unit 410 (i) and the third address offset, the memory control circuit 23 may determine the logical unit 410 (D+i) from the logical range 42. That is, when the update instruction 401 indicates to update the data belonging to the logical unit 410 (i), the logical unit 410 (D+i) is determined according to the third address offset.

[0047] After determining the logical unit 410 (D+i), the memory control circuit 23 may perform a data update operation on the logical unit 410 (D+i) according to the update instruction 401. For example, in the data update operation performed on the logical unit 410 (D+i), the memory control circuit 23 may store the data 420 in the physical unit 420 (2) (i.e., the second physical unit) currently mapped to the logical unit 410 (D+i).

[0048] In one embodiment, after starting to execute the data update operation on the second logical unit, the memory control circuit 23 may determine whether the data update operation executed on the second logical unit is successful. For example, the memory control circuit 23 may determine whether the first data is successfully written (or programmed) into the second physical unit. If the first data is successfully written (or programmed) into the second physical unit, the memory control circuit 23 may determine that the data update operation executed on the second logical unit is successful. However, if the first data is not successfully written (or programmed) into the second physical unit, or the host system abandons the execution of the data update operation, the memory control circuit 23 may determine that the data update operation executed on the second logical unit fails (i.e., is unsuccessful).

[0049] In one embodiment, if the data update operation performed on the second logical unit is successful, the memory control circuit 23 may change the mapping of the first logical unit to the second physical unit. For example, the memory control circuit 23 may change the mapping of the first logical unit originally mapped to the first physical unit to the second physical unit currently storing the first data.

[0050] In one embodiment, the operation of mapping the first logical unit to the second physical unit may include: removing the (old) mapping relationship between the first logical unit and the first physical unit, and establishing the (new) mapping relationship between the first logical unit and the second physical unit.

[0051] In one embodiment, if the data update operation performed on the second logical unit is successful, the memory control circuit 23 may also change the mapping of the second logical unit to the first physical unit. In one embodiment, by changing the mapping of the second logical unit to the first physical unit, the data stored in the first physical unit that was originally instructed to be backed up by the backup instruction can be saved by establishing a mapping relationship between the second logical unit and the first physical unit (that is, the data stored in the first physical unit is maintained as valid data), thereby avoiding the data stored in the first physical unit from being cleared during the subsequent garbage collection process.

[0052] In one embodiment, the operation of mapping the second logical unit to the first physical unit may include: removing the (old) mapping relationship between the second logical unit and the second physical unit, and establishing the (new) mapping relationship between the second logical unit and the first physical unit.

[0053] In one embodiment, the data update operation completed by simply modifying the mapping relationship between the logical unit and the physical unit is also called a fast update of data. The fast update can retain at least part of the data (e.g., data originally stored in the first physical unit) that is originally instructed to be backed up by the backup instruction, avoiding the loss of the previously backed up data (e.g., data originally stored in the first physical unit) due to the subsequent data update failure, and when the backup data is updated, the physical unit storing the backup data is mapped to the logical backup area (i.e., the second logical range), thereby realizing the retention of the backup data, and the backup is not performed by data transfer when the backup instruction is obtained, which is conducive to improving the execution efficiency and service life of the storage device.

[0054] Figure 5 FIG. 1 is a schematic diagram showing how to change the mapping relationship between the logical unit and the physical unit in response to a successful data update operation according to an embodiment of the present invention. Figure 5 , continued by Figure 4In one embodiment, it is assumed that the data update operation performed on the logical unit 410 (D+i) is successful. In response to the success of the data update operation performed on the logical unit 410 (D+i), the memory control circuit 23 may change the mapping of the logical unit 410 (i) originally mapped to the physical unit 420 (1) to the physical unit 420 (2) currently storing the data 420 (i.e., establish a mapping relationship between the logical unit 410 (i) and the physical unit 420 (2)). At the same time, the memory control circuit 23 may disconnect (i.e., remove) the mapping relationship between the logical unit 410 (i) and the physical unit 420 (1) and the mapping relationship between the logical unit 410 (D+i) and the physical unit 420 (2).

[0055] In one embodiment, in response to the data update operation performed on the logical unit 410 (D+i) being successful, the memory control circuit 23 may also change the mapping of the logical unit 410 (D+i) originally mapped to the physical unit 420 (2) to the physical unit 420 (1) storing the previous backup data (i.e., establishing a mapping relationship between the logical unit 410 (D+i) and the physical unit 420 (1)). Thus, the data stored in the physical unit 420 (1) indicated by the original backup instruction can be saved through the mapping relationship between the logical unit 410 (D+i) and the physical unit 420 (1) (i.e., the data stored in the physical unit 420 (1) is maintained as valid data). In other words, the second logical range 42 is a logical backup area, that is, the physical units finally mapped from the logical unit 410 (D+1) to the logical unit 410 (E) are all stored backup data.

[0056] In one embodiment, after the data update operation is successful, that is, after the physical unit storing the backup data is mapped to the second logical unit in the second logical range, if the memory control circuit 23 obtains a data recovery instruction from the host system 11, wherein the data recovery instruction is used to instruct to perform a data recovery operation on the data belonging to the first logical range, the first logical unit is changed to be mapped to the first physical unit, and the mapping relationship between the second logical unit and the first physical unit is removed. That is, when the data recovery instruction instructs the data of the logical unit 410 (i) to perform data recovery, the mapping relationship between the logical unit (D+i) and the physical unit 420 (1) is removed, and the mapping relationship between the logical unit 410 (i) and the physical unit 420 (1) is established.

[0057] In one embodiment, if the data update operation performed on the second logical unit is unsuccessful (i.e., fails), the memory control circuit 23 may maintain the (old) mapping relationship between the first logical unit and the first physical unit. In one embodiment, if the data update operation performed on the second logical unit is unsuccessful (i.e., fails), the memory control circuit 23 may also discard the data (i.e., at least a portion of the first data) stored in the second physical unit through the data update operation performed on the second logical unit.

[0058] In one embodiment, the aforementioned operation of discarding the data (i.e., at least a portion of the first data) stored in the second physical unit by the data update operation performed on the second logical unit may include: removing the mapping relationship between the second logical unit and the second physical unit, and / or marking the data (i.e., at least a portion of the first data) stored in the second physical unit as invalid data. Thereafter, the discarded data (i.e., invalid data) stored in the second physical unit may be cleared by performing garbage collection (CG) or other types of data cleanup operations on the memory module 122.

[0059] In one embodiment, after the data update operation performed by the host system 11 or the memory control circuit 23 on the second logical unit fails, the old data belonging to the first logical unit (e.g., data originally stored in the first physical unit) can be simply and quickly restored (e.g., maintaining the mapping relationship between the first logical unit and the first physical unit storing the old data belonging to the first logical unit). Thus, the operation stability of the storage device 12 can be effectively improved. In one embodiment, the data restoration operation performed by maintaining (or not changing) the mapping relationship between the logical unit and the physical unit is also called fast data restoration.

[0060] Figure 6 FIG. 1 is a schematic diagram showing a method of maintaining a mapping relationship between a logical unit and a physical unit in response to a data update operation failure according to an embodiment of the present invention. Figure 6 , continued by Figure 4 In one embodiment, it is assumed that the data update operation performed on the logical unit 410 (D+i) fails. In response to the failure of the data update operation performed on the logical unit 410 (D+i), the memory control circuit 23 may maintain the mapping relationship between the logical unit 410 (i) and the physical unit 420 (1). At the same time, the memory control circuit 23 may disconnect (i.e., remove) the mapping relationship between the logical unit 410 (D+i) and the physical unit 420 (2), and / or mark the data currently stored in the physical unit 420 (2) (i.e., at least a portion of the data 420) as invalid data.

[0061] In one embodiment, after the data update operation starts to be performed on the second logical unit, if the memory control circuit 23 detects a write completion event reflecting successful storage of the first data to the second physical unit within a predetermined time range, the memory control circuit 23 may determine that the data update operation performed on the second logical unit is successful. However, in one embodiment, after the data update operation starts to be performed on the second logical unit, if the memory control circuit 23 does not detect the write completion event within a predetermined time range, the memory control circuit 23 may determine that the data update operation performed on the second logical unit has failed.

[0062] In one embodiment, after starting to execute the data update operation on the second logical unit, if the memory control circuit 23 obtains confirmation information reflecting the successful update of the data belonging to the first logical unit from the host system 11 within a predetermined time range, the memory control circuit 23 may determine that the data update operation executed on the second logical unit is successful. However, in one embodiment, after starting to execute the data update operation on the second logical unit, if the memory control circuit 23 does not obtain the confirmation information from the host system 11 within a predetermined time range, the memory control circuit 23 may determine that the data update operation executed on the second logical unit has failed.

[0063] Figure 7 is a flow chart of a memory management method according to an embodiment of the present invention. Figure 7 In step S701, a backup instruction is obtained from the host system, wherein the backup instruction is used to instruct to perform a backup operation on data belonging to a first logical range. In step S702, after performing the backup operation, an update instruction is obtained from the host system, wherein the update instruction is used to instruct to update data belonging to a first logical unit, the first logical unit is included in the first logical range, and the first logical unit is mapped to a first physical unit among the multiple physical units. In step S703, according to the update instruction, a data update operation is performed on a second logical unit, wherein the second logical unit is included in a second logical range, the second logical range is different from the first logical range, and the second logical unit is mapped to a second physical unit among the multiple physical units. In step S704, it is determined whether the data update operation is successful. If the data update operation performed on the second logical unit is successful, in step S705, the first logical unit is changed to be mapped to the second physical unit, and the second logical unit is changed to be mapped to the first physical unit. However, if the data update operation performed on the second logical unit fails, in step S706, the mapping relationship between the first logical unit and the first physical unit is maintained.

[0064] However, Figure 7 The steps in the above are described in detail, so I will not repeat them here. It is worth noting that Figure 7 Each step in the above process can be implemented as multiple program codes or circuits, and the present invention is not limited thereto. Figure 7 The method can be used in conjunction with the above exemplary embodiments or can be used alone, and the present invention is not limited thereto.

[0065] In summary, the memory management method and storage device provided in the embodiments of the present invention can quickly back up data belonging to a specific logical unit while the host system performs backup and / or update operations on a specific file, and can retain the old backup data at the same time. In addition, when an update failure is detected, the data that failed to be updated can be quickly restored (for example, restored to the old backup data that was reserved in advance). Therefore, the memory management method and storage device provided by the present invention can effectively improve the operational stability and service life of the storage device while the host system performs data backup and / or update.

[0066] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory management method, characterized in that: For a storage device, wherein the storage device comprises a memory module, the memory module comprises a plurality of entity units, and the memory management method comprises: Obtaining a backup instruction from a host system, wherein the backup instruction is used to instruct to perform a backup operation on data belonging to a first logical range; After performing the backup operation, obtaining an update instruction from the host system, wherein the update instruction is used to instruct to update data belonging to a first logical unit, the first logical unit is included in the first logical range, and the first logical unit is mapped to a first physical unit among the plurality of physical units; According to the update instruction, a data update operation is performed on a second logical unit, wherein the second logical unit is included in a second logical range, the second logical range is different from the first logical range, and the second logical unit is mapped to a second physical unit among the plurality of physical units; Determining whether the data update operation is successful; and If the data update operation is successful, the first logical unit is changed to be mapped to the second physical unit, and the second logical unit is changed to be mapped to the first physical unit.

2. The memory management method according to claim 1, characterized in that: Also includes: The second logical range is determined according to the backup instruction, wherein the first logical range and the second logical range do not overlap with each other.

3. The memory management method according to claim 1, characterized in that: The total number of logical units included in the second logical range is the same as the total number of logical units included in the first logical range.

4. The memory management method according to claim 1, characterized in that: According to the update instruction, the step of performing the data update operation on the second logic unit includes: Determining, according to the update instruction, a first address offset of the first logic unit compared to the first logic range; and The second logic unit is determined within the second logic range according to the first address offset.

5. The memory management method according to claim 4, characterized in that: The first address offset is the same as a second address offset of the second logic unit compared to the second logic range.

6. The memory management method according to claim 1, characterized in that: According to the update instruction, the step of performing the data update operation on the second logic unit includes: According to the update instruction, the first data is stored in the second entity unit.

7. The memory management method according to claim 1, characterized in that: The step of mapping the first logical unit to the second physical unit comprises: removing a mapping relationship between the first logical unit and the first physical unit; and A mapping relationship between the first logical unit and the second physical unit is established.

8. The memory management method according to claim 1, characterized in that: Also includes: Obtaining a data recovery instruction from a host system, wherein the data recovery instruction is used to instruct to perform a data recovery operation on data belonging to a first logical range; The first logical unit is changed to be mapped to the first physical unit, and the mapping relationship between the second logical unit and the first physical unit is removed.

9. The memory management method according to claim 1, characterized in that: Also includes: If the data update operation fails, the mapping relationship between the first logical unit and the first physical unit is maintained.

10. The memory management method according to claim 1, characterized in that: Also includes: If the data update operation fails, the mapping relationship between the second logical unit and the second physical unit is removed, and the data stored in the second physical unit is marked as invalid data.

11. A storage device, characterized in that: include: A connection interface for connecting to a host system; Memory module; as well as a memory controller connected to the connection interface and the memory module, The memory module includes a plurality of physical units, and the memory controller is used to: Obtaining a backup instruction from the host system, wherein the backup instruction is used to instruct to perform a backup operation on data belonging to a first logical range; After performing the backup operation, obtaining an update instruction from the host system, wherein the update instruction is used to instruct to update data belonging to a first logical unit, the first logical unit is included in the first logical range, and the first logical unit is mapped to a first physical unit among the plurality of physical units; According to the update instruction, a data update operation is performed on a second logical unit, wherein the second logical unit is included in a second logical range, the second logical range is different from the first logical range, and the second logical unit is mapped to a second physical unit among the plurality of physical units; Determining whether the data update operation is successful; as well as If the data update operation is successful, the first logical unit is changed to be mapped to the second physical unit, and the second logical unit is changed to be mapped to the first physical unit.

12. The storage device according to claim 11, characterized in that: The memory controller is also used to: The second logical range is determined according to the backup instruction, wherein the first logical range and the second logical range do not overlap with each other.

13. The storage device according to claim 11, characterized in that: The total number of logical units included in the second logical range is the same as the total number of logical units included in the first logical range.

14. The storage device according to claim 11, characterized in that: The operation of the memory controller performing the data update operation on the second logic unit according to the update instruction includes: Determining, according to the update instruction, a first address offset of the first logic unit compared to the first logic range; and The second logic unit is determined within the second logic range according to the first address offset.

15. The storage device according to claim 14, characterized in that: The first address offset is the same as a second address offset of the second logic unit compared to the second logic range.

16. The storage device according to claim 11, characterized in that: The operation of the memory controller performing the data update operation on the second logic unit according to the update instruction includes: According to the update instruction, the first data is stored in the second entity unit.

17. The storage device according to claim 11, characterized in that: The operation of the memory controller mapping the first logical unit to the second physical unit includes: removing a mapping relationship between the first logical unit and the first physical unit; and A mapping relationship between the first logical unit and the second physical unit is established.

18. The storage device according to claim 11, characterized in that: The memory controller is also used to: Obtaining a data recovery instruction from a host system, wherein the data recovery instruction is used to instruct to perform a data recovery operation on data belonging to a first logical range; The first logical unit is changed to be mapped to the first physical unit, and the mapping relationship between the second logical unit and the first physical unit is removed.

19. The storage device according to claim 11, characterized in that The memory controller is also used to: If the data update operation fails, the mapping relationship between the first logical unit and the first physical unit is maintained.

20. The storage device according to claim 11, characterized in that The memory controller is also used to: If the data update operation fails, the mapping relationship between the second logical unit and the second physical unit is removed, and the data stored in the second physical unit is marked as invalid data.

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