Apparatus and method for moderate degradation of redundancy processing

Abstract

The invention relates to an apparatus and method for moderate degradation of redundancy processing. An apparatus and method for redundant data processing with moderate degradation functionality. For example, one embodiment of an apparatus comprises: three processing elements operable in a first redundancy mode, the three processing elements to execute the same instruction sequence to produce three corresponding results; a detection circuit for detecting when any one of the three processing elements produces a different result from the other two of the three processing elements; tracking circuitry to associate an error with one processing element when the one processing element produces a different result than the other two processing elements, where the other two processing elements will operate in a second redundant mode that does not include the one processing element if an error threshold is reached for the one processing element.

Description

Technical Field

[0001] The present disclosure relates generally to the field of computer processors. More specifically, the present disclosure relates to apparatus and methods for graceful degradation of redundant processing, such as processing by redundant processing elements. Background Art

[0002] In safety-critical applications, processor lockstepping and / or multiprocessor voting algorithms are used to detect program flow execution issues. However, once an error is detected, there is no mechanism to allow the system to continue operating with reduced error detection capabilities. Summary of the invention

[0003] According to one aspect of the present disclosure, there is provided an apparatus comprising: three processing elements capable of operating in a first redundant mode, the three processing elements being used to execute the same instruction sequence to produce three corresponding results; a detection circuit for detecting when any one of the three processing elements produces a result different from the other two of the three processing elements; and a tracking circuit for associating an error with the one processing element when the one processing element produces a result different from the other two processing elements, wherein if an error threshold is reached for the one processing element, the other two processing elements will operate in a second redundant mode that does not include the one processing element.

[0004] According to another aspect of the present disclosure, a method is provided, comprising: operating three processing elements in a first redundant mode, the three processing elements being used to execute the same instruction sequence to produce three corresponding results; detecting when any one of the three processing elements produces a result different from the other two of the three processing elements; associating an error with the one processing element when the one processing element produces a result different from the other two processing elements; and operating the other two processing elements in a second redundant mode that does not include the one processing element if an error threshold is reached for the one processing element.

[0005] According to another aspect of the present disclosure, a machine-readable medium having program code stored thereon is provided, wherein when the program code is executed by a processor or a processor component, the processor or the processor component performs operations, the operations comprising: operating three processing elements in a first redundant mode, the three processing elements being used to execute the same instruction sequence to produce three corresponding results; detecting when any one of the three processing elements produces a result different from the other two of the three processing elements; associating an error with the one processing element when the one processing element produces a result different from the other two processing elements; and operating the other two processing elements in a second redundant mode that does not include the one processing element if an error threshold is reached for the one processing element. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] A better understanding of the present disclosure may be obtained through the following detailed description in conjunction with the accompanying drawings, in which:

[0007] Figure 1 illustrates an example computer system architecture;

[0008] Figure 2 A processor including multiple cores is illustrated;

[0009] FIG3(A) illustrates the various stages of the processing pipeline;

[0010] FIG3(B) illustrates details of one embodiment of the core;

[0011] Figure 4 illustrates an execution circuit according to one embodiment;

[0012] Figure 5 One embodiment of a register architecture is illustrated;

[0013] Figure 6 An example of an instruction format is illustrated;

[0014] Figure 7 illustrates an addressing technique according to one embodiment;

[0015] Figure 8 An embodiment of an instruction prefix is ​​illustrated;

[0016] Figure 9(A) to Figure 9(D) illustrates an embodiment of how the R, X, and B fields of the prefix are used;

[0017] Figure 10(A) to Figure 10(B) An example of a second instruction prefix is ​​illustrated;

[0018] Fig.11 illustrates the payload bytes of one embodiment of an instruction prefix;

[0019] Fig.12 The diagram shows how instruction conversion and binary translation are implemented;

[0020] FIG. 13A to FIG. 13C illustrates graceful degradation according to an embodiment of the present disclosure;

[0021] Fig.14 A method according to an embodiment of the present disclosure is illustrated;

[0022] Fig.15 An embodiment including a read-only copy of executable code is illustrated; and

[0023] Fig.16 One embodiment of an architecture upon which embodiments may be implemented is illustrated. DETAILED DESCRIPTION

[0024] In the following description, for the purpose of explanation, many specific details are set forth in order to provide a thorough understanding of the embodiments of the present disclosure described below. However, it will be apparent to those skilled in the art that embodiments of the present disclosure may be practiced without some of these specific details. In other cases, well-known structures and devices are shown in block diagram form to avoid obscuring the basic principles of the embodiments of the present disclosure.

[0025] Exemplary Computer Architecture

[0026] Exemplary computer architecture is described in detail below. Other system designs and configurations for laptops, desktop computers, handheld PCs, personal digital assistants, engineering workstations, servers, network devices, network hubs, switches, embedded processors, digital signal processors (DSP), graphics devices, video game devices, set-top boxes, microcontrollers, cellular phones, portable media players, handheld devices, and various other electronic devices known in the art are also appropriate. In a word, multiple systems or electronic devices that can include processors disclosed herein and / or other execution logics are generally appropriate.

[0027] Figure 1 An embodiment of an exemplary system is illustrated. Multiprocessor system 100 is a point-to-point interconnect system and includes a plurality of processors, including a first processor 170 and a second processor 180 coupled via a point-to-point interconnect 150. In some embodiments, first processor 170 and second processor 180 are isomorphic. In some embodiments, first processor 170 and second processor 180 are heterogeneous.

[0028] Processors 170 and 180 are shown as including integrated memory controller (IMC) unit circuits 172 and 182, respectively. Processor 170 also includes point-to-point (PP) interfaces 176 and 178 as part of its interconnect controller unit; similarly, second processor 180 includes PP interfaces 186 and 188. Processors 170, 180 can exchange information via point-to-point (PP) interconnect 150 using PP interface circuits 178, 188. IMCs 172 and 182 couple processors 170, 180 to respective memories, namely memory 132 and memory 134, which may be portions of main memory locally attached to the respective processors.

[0029] Processors 170, 180 may each utilize point-to-point interface circuits 176, 194, 186, 198 to exchange information with chipset 190 via respective PP interfaces 152, 154. Chipset 190 may optionally exchange information with coprocessor 138 via high-performance interface 192. In some embodiments, coprocessor 138 is a special-purpose processor, such as a high-throughput MIC processor, a network or communication processor, a compression engine, a graphics processor, a GPGPU, an embedded processor, and the like.

[0030] A shared cache (not shown) may be included in either processor 170, 180, or external to both processors but connected to these processors via the PP interconnect, so that if a processor is placed in a low power mode, local cache information of either or both processors may be stored in the shared cache.

[0031] Chipset 190 may be coupled to first interconnect 116 via interface 196. In some embodiments, first interconnect 116 may be a Peripheral Component Interconnect (PCI) interconnect, or an interconnect such as a PCI Express interconnect or another I / O interconnect. In some embodiments, one of the interconnects is coupled to a power control unit (PCU) 117, which may include circuitry, software, and / or firmware to perform power management operations with respect to processors 170, 180, and / or coprocessor 138. PCU 117 provides control information to a voltage regulator so that the voltage regulator generates an appropriate regulated voltage. PCU 117 also provides control information to control the generated operating voltage. In various embodiments, PCU 117 may include various power management logic units (circuits) to perform hardware-based power management. Such power management may be entirely processor controlled (e.g., controlled by various processor hardware and may be triggered by workload and / or power constraints, thermal constraints, or other processor constraints), and / or power management may be performed in response to an external source (e.g., a platform or power management source or system software).

[0032] PCU 117 is illustrated as existing as logic separate from processor 170 and / or processor 180. In other cases, PCU 117 may execute on a given one or more cores of a core (not shown) of processor 170 or 180. In some cases, PCU 117 may be implemented as a microcontroller (dedicated or general purpose) or other control logic that is configured to execute its own dedicated power management code (sometimes referred to as P-code). In still other embodiments, the power management operations to be performed by PCU 117 may be implemented external to the processor, such as by a separate power management integrated circuit (PMIC) or another component external to the processor. In still other embodiments, the power management operations to be performed by PCU 117 may be implemented within BIOS or other system software.

[0033] Various I / O devices 114 can be coupled to the first interconnect 116, as well as an interconnect (bus) bridge 118, which couples the first interconnect 116 to a second interconnect 120. In some embodiments, (one or more) additional processors 115 are coupled to the first interconnect 116, such as a coprocessor, a high throughput MIC processor, a GPGPU, an accelerator (such as a graphics accelerator or a digital signal processing (DSP) unit), a field programmable gate array (FPGA), or any other processor. In some embodiments, the second interconnect 120 can be a low pin count (LPC) interconnect. Various devices can be coupled to the second interconnect 120, including, for example, a keyboard and / or mouse 122, a communication device 127, and a storage unit circuit 128. The storage unit circuit 128 can be a disk drive or other mass storage device, which in some embodiments can include instructions / code and data 130. In addition, an audio I / O 124 can be coupled to the second interconnect 120. Note that other architectures are possible in addition to the point-to-point architecture described above. For example, a system such as multiprocessor system 100 may implement a multi-drop interconnect or other such architecture rather than a point-to-point architecture.

[0034] Exemplary Core Architectures, Processors, and Computer Architectures

[0035] Processor cores can be implemented in different ways, for different purposes, and in different processors. For example, implementations of these cores may include: 1) general-purpose in-order cores, for general-purpose computing purposes; 2) high-performance general-purpose out-of-order cores, for general-purpose computing purposes; 3) special-purpose cores, mainly for graphics and / or scientific (throughput) computing purposes. Implementations of different processors may include: 1) a CPU, including one or more general-purpose in-order cores for general-purpose computing purposes and / or one or more general-purpose out-of-order cores for general-purpose computing purposes; and 2) a coprocessor, including one or more special-purpose cores mainly for graphics and / or scientific (throughput) purposes. These different processors result in different computer system architectures, which may include: 1) coprocessors on separate chips from the CPU; 2) coprocessors on separate dies from the CPU in the same package; 3) coprocessors on the same die as the CPU (in which case such coprocessors are sometimes referred to as dedicated logic, such as integrated graphics and / or scientific (throughput) logic, or as dedicated cores); and 4) systems on a chip, which may include on the same die as the described CPU (sometimes referred to as application core(s) or application processor(s), the coprocessors described above, and additional functionality. An exemplary core architecture is described next, followed by a description of an exemplary processor and computer architecture.

[0036] Figure 2 A block diagram of an embodiment of a processor 200 is illustrated, which may have more than one core, may have an integrated memory controller, and may have integrated graphics. The solid-lined box illustrates the processor 200 as having a single core 202(A), a system agent unit circuit 210, and a set of one or more interconnect controller unit circuits 216, while the optionally added dashed-lined box illustrates an alternative processor 200 as having multiple cores 202(A)-(N), a set of one or more integrated memory control unit circuits 214 in the system agent unit circuit 210, dedicated logic 208, and a set of one or more interconnect controller unit circuits 216. Note that the processor 200 may be Figure 1 One of the processors 170 or 180 or the coprocessors 138 or 115.

[0037] Thus, different implementations of processor 200 may include: 1) a CPU, where dedicated logic 208 is integrated graphics and / or scientific (throughput) logic (which may include one or more cores, not shown), and cores 202(A)-(N) are one or more general purpose cores (e.g., general purpose in-order cores, general purpose out-of-order cores, or a combination of the two); 2) a coprocessor, where cores 202(A)-(N) are a large number of dedicated cores primarily for graphics and / or scientific (throughput) purposes; and 3) a coprocessor, where cores 202(A)-(N) are a large number of general purpose in-order cores. Thus, processor 200 may be a general purpose processor, a coprocessor, or a special purpose processor, such as a network or communication processor, a compression engine, a graphics processor, a GPGPU (general purpose graphics processing unit circuit), a high throughput many integrated core (MIC) coprocessor (including 30 or more cores), an embedded processor, and the like. The processor may be implemented on one or more chips. Processor 200 may be part of one or more substrates and / or may be implemented on one or more substrates using any of a variety of process technologies, such as BiCMOS, CMOS, or NMOS.

[0038] The memory hierarchy includes one or more levels of cache unit circuits 204(A)-(N) within the cores 202(A)-(N), a set of one or more shared cache unit circuits 206, and external memory (not shown) coupled to the set of integrated memory controller unit circuits 214. The set of one or more shared cache unit circuits 206 may include one or more intermediate level caches, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, such as last level cache (LLC), and / or combinations thereof. While in some embodiments, a ring-based interconnect network circuit 212 interconnects the dedicated logic 208 (e.g., integrated graphics logic), the set of shared cache unit circuits 206, and the system agent unit circuit 210, alternative embodiments use any number of well-known techniques to interconnect these units. In some embodiments, coherency is maintained between one or more circuits in the shared cache unit circuits 206 and the cores 202(A)-(N).

[0039] In some embodiments, one or more of the cores 202(A)-(N) have multi-threading capabilities. The system agent unit circuit 210 includes those components that coordinate and operate the cores 202(A)-(N). The system agent unit circuit 210 may include, for example, a power control unit (PCU) circuit and / or a display unit circuit (not shown). The PCU may be (or may include) the logic and components required to adjust the power state of the cores 202(A)-(N) and / or the dedicated logic 208 (e.g., integrated graphics logic). The display unit circuit is used to drive one or more externally connected displays.

[0040] The cores 202(A)-(N) may be homogeneous or heterogeneous with respect to the architectural instruction set; that is, two or more of the cores 202(A)-(N) may be capable of executing the same instruction set, while other cores may be capable of executing only a subset of the instruction set or a different instruction set.

[0041] Exemplary Core Architecture

[0042] In-order and out-of-order core block diagram

[0043] Figure 3(A) is a block diagram illustrating both an exemplary in-order pipeline and an exemplary register renaming, out-of-order issue / execution pipeline according to an embodiment of the present disclosure. Figure 3(B) is a block diagram illustrating both an exemplary embodiment of an in-order architecture core to be included in a processor and an exemplary register renaming, out-of-order issue / execution architecture core according to an embodiment of the present disclosure. Figure 3(A) to Figure 3(B) The solid line boxes in illustrate the in-order pipeline and in-order core, while the optionally added dashed line boxes illustrate the register renaming, out-of-order issue / execution pipeline and core. Considering that the in-order aspect is a subset of the out-of-order aspect, the out-of-order aspect will be described.

[0044] In FIG. 3(A), the processor pipeline 300 includes a fetch stage 302, an optional length decoding stage 304, a decode stage 306, an optional allocation stage 308, an optional rename stage 310, a dispatch (also called dispatch or issue) stage 312, an optional register read / memory read stage 314, an execute stage 316, a write back / memory write stage 318, an optional exception handling stage 322, and an optional commit stage 324. One or more operations may be performed in each of these processor pipeline stages. For example, during the fetch stage 302, one or more instructions are fetched from the instruction memory, during the decode stage 306, the fetched one or more instructions may be decoded, an address using a forwarding register port (e.g., a load store unit (LSU) address) may be generated, and branch forwarding (e.g., an immediate offset or a link register (LR)) may be performed. In one embodiment, the decode stage 306 and the register read / memory read stage 314 may be combined into one pipeline stage. In one embodiment, during the execution stage 316, decoded instructions may be executed, LSU address / data pipelining to an Advanced Microcontroller Bus (AMB) interface may be performed, multiplication and addition operations may be performed, arithmetic operations with branch results may be performed, and the like.

[0045] As an example, the exemplary register renaming, out-of-order issue / execution core architecture may implement pipeline 300 in the following manner: 1) instruction fetch 338 performs fetch and length decode stages 302 and 304; 2) decode unit circuit 340 performs decode stage 306; 3) rename / allocator unit circuit 352 performs allocation stage 308 and rename stage 310; 4) (one or more) scheduler unit circuit 356 performs scheduling stage 312; 5) (one or more) physical register file unit circuit 358 and memory unit circuit 370 perform register read / memory read stage 314; (one or more) execution cluster 360 performs execution stage 316; 6) memory unit circuit 370 and (one or more) physical register file unit circuit 358 perform write back / memory write stage 318; 7) various units (various circuits) may be involved in exception handling stage 322; and 8) retirement unit circuit 354 and (one or more) physical register file unit circuit 358 perform commit stage 324.

[0046] 3(B) shows a processor core 390, which includes a front end unit circuit 330 coupled to an execution engine unit circuit 350, and both circuits are coupled to a memory unit circuit 370. The core 390 can be a reduced instruction set computing (RISC) core, a complex instruction set computing (CISC) core, a very long instruction word (VLIW) core, or a hybrid or alternative core type. As another option, the core 390 can be a special-purpose core, such as a network or communication core, a compression engine, a coprocessor core, a general purpose computing graphics processing unit (GPGPU) core, a graphics core, etc.

[0047] The front end unit circuit 330 may include a branch prediction unit circuit 332, which is coupled to an instruction cache unit circuit 334, which is coupled to an instruction translation lookaside buffer (TLB) 336, which is coupled to an instruction fetch unit circuit 338, which is coupled to a decode unit circuit 340. In one embodiment, the instruction cache unit circuit 334 is included in the memory unit circuit 370 instead of the front end unit circuit 330. The decode unit circuit 340 (or decoder) can decode the instruction and generate one or more micro-operations, microcode entry points, microinstructions, other instructions or other control signals as outputs, which are decoded from the original instruction, or otherwise reflect the original instruction, or are derived from the original instruction. The decode unit circuit 340 may also include an address generation unit (AGU, not shown). In one embodiment, the AGU uses the forwarded register port to generate the LSU address and may further perform branch forwarding (e.g., immediate offset branch forwarding, LR register branch forwarding, etc.). The decode unit circuit 340 may be implemented using a variety of different mechanisms. Examples of suitable mechanisms include, but are not limited to, lookup tables, hardware implementations, programmable logic arrays (PLA), microcode read only memory (ROM), and the like. In one embodiment, the core 390 includes a microcode ROM (not shown) or other medium that stores microcode for certain macroinstructions (e.g., in the decode unit circuit 340 or otherwise within the front end unit circuit 330). In one embodiment, the decode unit circuit 340 includes a micro-op or operation cache (not shown) to save / cache decoded operations, micro-tags, or micro-operations generated during decoding or other stages of the processor pipeline 300. The decode unit circuit 340 may be coupled to the rename / allocator unit circuit 352 in the execution engine unit circuit 350.

[0048] The execution engine circuitry 350 includes a rename / allocator unit circuitry 352 coupled to a retirement unit circuitry 354 and a set of one or more scheduler circuits 356. The scheduler circuitry 356 represents any number of different schedulers, including reservation stations, central instruction windows, and the like. In some embodiments, the scheduler circuitry 356 may include an arithmetic logic unit (ALU) scheduler / scheduling circuit, an ALU queue, an arithmetic generation unit (AGU) scheduler / scheduling circuit, an AGU queue, and the like. The scheduler circuitry 356 is coupled to a physical register file circuitry 358. Each of the physical register file circuitry 358 represents one or more physical register files, different ones of which store one or more different data types, such as scalar integers, scalar floating points, packed integers, packed floating points, vector integers, vector floating points, status (e.g., an instruction pointer that is the address of the next instruction to be executed), and the like. In one embodiment, the physical register file unit circuitry 358 includes vector register unit circuitry, write mask register unit circuitry, and scalar register unit circuitry. These register units may provide architectural vector registers, vector mask registers, general purpose registers, and the like. The physical register file unit circuitry 358 overlaps with the retirement unit circuitry 354 (also referred to as a retirement queue) to demonstrate various ways in which register renaming and out-of-order execution may be implemented (e.g., utilizing reorder buffers (ROBs) and retirement register files (ROBs); utilizing future stacks (ROBs), history buffers (ROBs), and retirement register files (ROBs); utilizing register maps and register pools; and the like). The retirement unit circuitry 354 and the physical register file circuitry 358 are coupled to execution clusters (one or more) 360. The execution clusters (one or more) 360 include a set of one or more execution unit circuits 362 and a set of one or more memory access circuits 364. The execution unit circuit(s) 362 may perform various arithmetic, logical, floating point, or other types of operations (e.g., shifts, additions, subtractions, multiplications) on various types of data (e.g., scalar floating point, packed integer, packed floating point, vector integer, vector floating point). While some embodiments may include several execution units or execution unit circuits dedicated to a particular function or set of functions, other embodiments may include only one execution unit circuit or multiple execution units / execution unit circuits that all perform all functions.Scheduler circuit(s) 356, physical register file unit circuit(s) 358, and execution cluster(s) 360 are shown as possibly multiple because some embodiments create separate pipelines for certain types of data / operations (e.g., scalar integer pipelines, scalar floating point / packed integer / packed floating point / vector integer / vector floating point pipelines, and / or memory access pipelines, each with its own scheduler circuit(s), physical register file unit circuit(s), and / or execution cluster—and in the case of a separate memory access pipeline, some embodiments implemented only the execution cluster of that pipeline has memory access unit circuit(s) 364). It should also be understood that where separate pipelines are used, one or more of these pipelines may be out-of-order issue / execution, while the rest are in-order.

[0049] In some embodiments, the execution engine unit circuit 350 may perform load store unit (LSU) address / data pipelining to an advanced microcontroller bus (AMB) interface (not shown), as well as address stage and writeback, data stage loads, stores, and branches.

[0050] A set of memory access circuits 364 are coupled to the memory cell circuit 370, which includes a data TLB unit circuit 372, which is coupled to a data cache circuit 374, which is coupled to a level 2 (L2) cache circuit 376. In an exemplary embodiment, the memory access unit circuit 364 may include a load unit circuit, a storage address unit circuit, and a storage data unit circuit, each of which is coupled to the data TLB circuit 372 in the memory cell circuit 370. The instruction cache circuit 334 is further coupled to the level 2 (L2) cache unit circuit 376 in the memory cell circuit 370. In one embodiment, the instruction cache 334 and the data cache 374 are combined into a single instruction and data cache in the L2 cache unit circuit 376, a level 3 (L3) cache circuit (not shown), and / or a main memory (not shown). The L2 cache unit circuit 376 is coupled to one or more other levels of cache and ultimately coupled to the main memory.

[0051] Core 390 may support one or more instruction sets (e.g., the x86 instruction set (with some extensions that have been added with newer versions); the MIPS instruction set; the ARM instruction set (with optional additional extensions, such as NEON)) that include the instruction(s) described herein. In one embodiment, core 390 includes logic to support packed data instruction set extensions (e.g., AVX1, AVX2), thereby allowing operations used by many multimedia applications to be performed using packed data.

[0052] Exemplary Execution Unit Circuit(s)

[0053] Figure 4 An embodiment of (one or more) execution unit circuits is illustrated, such as (one or more) execution unit circuits 362 of FIG. 3(B). As shown, (one or more) execution unit circuits 362 may include one or more ALU circuits 401, vector / SIMD unit circuits 403, load / store unit circuits 405, and / or branch / jump unit circuits 407. ALU circuits 401 perform integer arithmetic and / or Boolean operations. Vector / SIMD unit circuits 403 perform vector / SIMD operations on packed data (e.g., SIMD / vector registers). Load / store unit circuits 405 execute load and store instructions to load data from memory into registers, or store data from registers to memory. Load / store unit circuits 405 may also generate addresses. Branch / jump unit circuits 407 cause branches or jumps to a certain memory address depending on the instruction. Floating-point unit (FPU) circuits 409 perform floating-point arithmetic. The width of execution unit circuitry 362 varies depending on the embodiment and may range from 16 bits to 1024 bits. In some embodiments, two or more smaller execution units are logically combined to form a larger execution unit (e.g., two 128-bit execution units are logically combined to form a 256-bit execution unit).

[0054] Exemplary Register Architecture

[0055] Figure 5 5 is a block diagram of a register architecture 500 according to some embodiments. As shown, there is a vector / SIMD register 510, whose width varies from 128 bits to 1024 bits. In some embodiments, the vector / SIMD register 510 is physically 512 bits, and only some low-order bits are used depending on the mapping. For example, in some embodiments, the vector / SIMD register 510 is a 512-bit ZMM register: the low-order 256 bits are used for the YMM register, and the low-order 128 bits are used for the XMM register. Therefore, there is an overlay of registers. In some embodiments, the vector length field selects between the maximum length and one or more other shorter lengths, wherein each such shorter length is half the length of the previous length. Scalar operations are operations performed on the lowest-order data element position in the ZMM / YMM / XMM register; higher-order data element positions are either maintained as the same as before the instruction, or are zeroed, depending on the embodiment.

[0056] In some embodiments, the register architecture 500 includes write mask / predicate registers 515. For example, in some embodiments, there are 8 write mask / predicate registers (sometimes referred to as k0 to k7), each of which is 16 bits, 32 bits, 64 bits, or 128 bits in size. The write mask / predicate registers 515 can allow merging (e.g., allowing any set of elements in the destination to be protected from update during the execution of any operation) and / or zeroing (e.g., a zeroing vector mask allows any set of elements in the destination to be zeroed during the execution of any operation). In some embodiments, each data element position in a given write mask / predicate register 515 corresponds to a data element position in the destination. In other embodiments, the write mask / predicate registers 515 are scalable and include a set number of enable bits for a given vector element (e.g., 8 enable bits for each 64-bit vector element).

[0057] The register architecture 500 includes a plurality of general purpose registers 525. These registers may be 16 bits, 32 bits, 64 bits, etc., and may be used for scalar operations. In some embodiments, these registers are referred to by the names RAX, RBX, RCX, RDX, RBP, RSI, RDI, RSP, and R8 to R15.

[0058] In some embodiments, register architecture 500 includes scalar floating point registers 545, which are used to perform scalar floating point operations on 32 / 64 / 80-bit floating point data using the x87 instruction set extension, or as MMX registers to perform operations on 64-bit packed integer data, and to hold operands for some operations performed between MMX and XMM registers.

[0059] One or more flag registers 540 (e.g., EFLAGS, RFLAGS, etc.) store status and control information for arithmetic, comparison, and system operations. For example, one or more flag registers 540 can store condition code information, such as carry, parity, auxiliary carry, zero, sign, and overflow. In some embodiments, one or more flag registers 1740 are referred to as program status and control registers.

[0060] Segment registers 520 contain segment points for accessing memory. In some embodiments, these registers are referred to by the names CS, DS, SS, ES, FS, and GS.

[0061] Machine-specific registers (MSRs) 535 control and report processor performance. Most MSRs 535 handle system-related functions and are not accessible to applications. Machine check registers 560 include control, status, and error reporting MSRs for detecting and reporting hardware errors.

[0062] One or more instruction pointer registers 530 store instruction pointer values. Control register(s) 555 (e.g., CR0-CR4) determine the operating mode of the processor (e.g., processor 170, 180, 138, 115, and / or 200) and the characteristics of the task currently being executed. Debug registers 550 control and allow monitoring of debug operations of a processor or core.

[0063] Memory management registers 565 specify the location of data structures used in protected mode memory management. These registers may include the GDTR, IDTR, task register, and LDTR registers.

[0064] Alternative embodiments of the present disclosure may use wider or narrower registers. In addition, alternative embodiments of the present disclosure may use more, fewer or different register files and registers.

[0065] Instruction Set

[0066] An instruction set architecture (ISA) may include one or more instruction formats. A given instruction format may define various fields (e.g., the number of bits, the position of the bits) to specify the operation to be performed (e.g., opcode) and the (one or more) operands and / or other (one or more) data fields (e.g., mask) on which the operation is to be performed, etc. Some instruction formats are further decomposed by the definition of instruction templates (or subformats). For example, an instruction template of a given instruction format may be defined as having different subsets of the fields of the instruction format (the included fields are usually in the same order, but at least some have different bit positions because there are fewer included fields) and / or defined as having a given field interpreted in a different manner. Thus, each instruction of the ISA is expressed using a given instruction format (and, if defined, expressed in a given instruction template in the instruction format), and includes fields for specifying the operation and the operand. For example, the exemplary ADD instruction has a specific opcode and instruction format, which includes an opcode field to specify the opcode and an operand field to select the operand (source 1 / destination and source 2); and the appearance of this ADD instruction in the instruction stream will have specific content in the operand field to select the specific operand.

[0067] Example instruction format

[0068] The embodiments of the (one or more) instructions described herein may be implemented in different formats. In addition, exemplary systems, architectures, and pipelines are described in detail below. Embodiments of the (one or more) instructions may be executed on these systems, architectures, and pipelines, but are not limited to those described in detail.

[0069] Figure 6 An embodiment of an instruction format is illustrated. As shown, an instruction may include multiple components, including but not limited to one or more fields for the following items: one or more prefixes 601, opcode 603, addressing information 605 (e.g., register identifier, memory addressing information, etc.), displacement value 607, and / or immediate value 609. Note that some instructions utilize some or all fields of the format, while other instructions may only use the opcode 603 field. In some embodiments, the illustrated order is the order in which these fields are to be encoded, however, it should be understood that in other embodiments, these fields may be encoded in another order, combined, etc.

[0070] (One or more) prefix fields 601 modify the instruction when used. In some embodiments, one or more prefixes are used to repeat string instructions (e.g., 0xF0, 0xF2, 0xF3, etc.), provide section override (e.g., 0x2E, 0x36, 0x3E, 0x26, 0x64, 0x65, 0x2E, 0x3E, etc.), perform bus lock operations, and / or change operation objects (e.g., 0x66) and address sizes (e.g., 0x67). Some instructions require mandatory prefixes (e.g., 0x66, 0xF2, 0xF3, etc.). Some of these prefixes can be considered as "traditional" prefixes. Other prefixes (one or more examples of which are described in detail herein) indicate and / or provide further capabilities, such as specifying specific registers, etc. These other prefixes are usually followed by the "traditional" prefix.

[0071] The opcode field 603 is used to at least partially define the operation to be performed when the instruction is decoded. In some embodiments, the length of the primary opcode encoded in the opcode field 603 is 1 byte, 2 bytes, or 3 bytes. In other embodiments, the primary opcode can be other lengths. The additional 3-bit opcode field is sometimes encoded in another field.

[0072] The addressing field 605 is used to address one or more operands of the instruction, such as a location in memory or one or more registers. Figure 7An embodiment of the addressing field 605 is illustrated. In this illustration, an optional MOD R / M byte 702 and an optional Scale, Index, Base (SIB) byte 704 are shown. The MOD R / M byte 702 and SIB byte 704 are used to encode up to two operands of the instruction, each operand being a direct register or an effective memory address. Note that each of these fields is optional, i.e., not all instructions include one or more of these fields. The MOD R / M byte 702 includes a MOD field 742, a Register field 744, and an R / M field 746.

[0073] The content of MOD field 742 distinguishes between memory access and non-memory access modes. In some embodiments, when MOD field 742 has a value of b11, register direct addressing mode is utilized, otherwise register indirect addressing is used.

[0074] Register field 744 may encode a destination register operand or a source register operand, or may encode an opcode extension and not be used to encode any instruction operand. The contents of register index field 744 specify the location (in a register or in memory) of the source or destination operand directly or through address generation. In some embodiments, register field 744 is supplemented with additional bits from a prefix (e.g., prefix 601) to allow for greater addressing.

[0075] R / M field 746 may be used to encode an instruction operand that references a memory address, or may be used to encode a destination register operand or a source register operand. Note that in some embodiments, R / M field 746 may be combined with MOD field 742 to specify an addressing mode.

[0076] SIB byte 704 includes a scaling field 752, an index field 754, and a base address field 756 for address generation. Scaling field 752 indicates a scaling factor. Index field 754 specifies the index register to be used. In some embodiments, index field 754 is complemented with additional bits from a prefix (e.g., prefix 601) to allow for greater addressing. Base address field 756 specifies the base address register to be used. In some embodiments, base address field 756 is complemented with additional bits from a prefix (e.g., prefix 601) to allow for greater addressing. In practice, the contents of scaling field 752 allow the contents of index field 754 to be scaled for memory address generation (e.g., for memory addresses using 2 缩放 * address generation of index + base address).

[0077] Some addressing forms use displacement values ​​to generate memory addresses. For example,缩放 * index + base + displacement, index * scaling + displacement, r / m + displacement, instruction pointer (RIP / EIP) + displacement, register + displacement, etc. to generate a memory address. The displacement can be a value of 1 byte, 2 bytes, 4 bytes, etc. In some embodiments, the displacement field 607 provides this value. In addition, in some embodiments, the use of a displacement factor is encoded in the MOD field of the addressing field 605, which indicates a compressed displacement scheme, for which the displacement value is calculated by multiplying disp8 with a scaling factor N, which is determined based on the vector length, the value of the b bit, and the input element size of the instruction. The displacement value is stored in the displacement field 607.

[0078] In some embodiments, the immediate value field 609 specifies an immediate value for the instruction. The immediate value may be encoded as a 1-byte value, a 2-byte value, a 4-byte value, etc.

[0079] Figure 8 An embodiment of a first prefix 601(A) is illustrated. In some embodiments, the first prefix 601(A) is an embodiment of a REX prefix. Instructions using this prefix may specify general purpose registers, 64-bit packed data registers (e.g., single instruction, multiple data (SIMD) registers or vector registers), and / or control registers and debug registers (e.g., CR8-CR15 and DR8-DR15).

[0080] Instructions using the first prefix 601(A) can specify up to three registers using a 3-bit field, depending on the format: 1) using the register field 744 and the R / M field 746 of the MOD R / M byte 702; 2) using the MOD R / M byte 702 with the SIB byte 704, including using the register field 744 as well as the base field 756 and the index field 754; or 3) using the register field of the opcode.

[0081] In the first prefix 601 (A), bit positions 7:4 are set to 0100. Bit position 3 (W) can be used to determine the operand size, but cannot determine the operand width alone. Therefore, when W=0, the operand size is determined by the code segment descriptor (CS.D), and when W=1, the operand size is 64 bits.

[0082] Note that adding another bit allows addressing 16 (2 4 ) registers, while the separate MOD R / M register field 744 and MOD R / MR / M field 746 can only address 8 registers each.

[0083] In the first prefix 601(A), bit position 2 (R) may be an extension of the MOD R / M register field 744 and may be used to modify the MOD R / M register field 744 when the field encodes a general register, a 64-bit packed data register (e.g., an SSE register), or a control or debug register. When the MOD R / M byte 702 specifies another register or defines an extended opcode, R is ignored.

[0084] Bit position 1 (X) X bits may modify the SIB byte index field 754 .

[0085] Bit position B (B) B may modify the base address in MOD R / MR / M field 746 or SIB byte base address field 756; or it may modify the opcode register field used to access a general register (eg, general register 525).

[0086] Figure 9(A) to Figure 9(D) An embodiment of how the R, X, and B fields of the first prefix 601 (A) are used is illustrated. FIG. 9 (A) illustrates that when the SIB byte 704 is not used for memory addressing, the R and B from the first prefix 601 (A) are used to extend the register field 744 and the R / M field 746 of the MOD R / M byte 702. FIG. 9 (B) illustrates that when the SIB byte 704 is not used, the R and B from the first prefix 601 (A) are used to extend the register field 744 and the R / M field 746 of the MOD R / M byte 702 (register-register addressing). FIG. 9 (C) illustrates that when the SIB byte 704 is used for memory addressing, the R, X, and B from the first prefix 601 (A) are used to extend the register field 744 and the index field 754 and the base address field 756 of the MOD R / M byte 702. FIG. 9(D) illustrates that when a register is encoded in the opcode 603 , the B from the first prefix 601 (A) is used to extend the register field 744 of the MOD R / M byte 702 .

[0087] Figure 10(A) to Figure 10(B) An embodiment of a second prefix 601(B) is illustrated. In some embodiments, the second prefix 601(B) is an embodiment of a VEX prefix. The second prefix 601(B) encoding allows instructions to have more than two operands and allows SIMD vector registers (e.g., vector / SIMD registers 510) to be longer than 64 bits (e.g., 128 bits and 256 bits). The use of the second prefix 601(B) provides a syntax for three operands (or more operands). For example, a previous two operand instruction performs an operation such as A=A+B, which overwrites the source operand. The use of the second prefix 601(B) enables the operands to perform non-destructive operations, such as A=B+C.

[0088] In some embodiments, the second prefix 601(B) has two forms: a two-byte form and a three-byte form. The two-byte second prefix 601(B) is mainly used for 128-bit, scalar, and some 256-bit instructions; while the three-byte second prefix 601(B) provides a compact replacement for 3-byte opcode instructions and the first prefix 601(A).

[0089] Figure 10 (A) illustrates an embodiment of the two-byte form of the second prefix 601 (B). In one example, the format field 1001 (byte 0 1003) contains the value C5H. In one example, byte 11005 includes an "R" value in bit [7]. This value is the complement of the same value of the first prefix 601 (A). Bit [2] is used to specify the length (L) of the vector (wherein value 0 is a scalar or 128-bit vector, and value 1 is a 256-bit vector). Bit [1:0] provides an operation code extensibility equivalent to some traditional prefixes (e.g., 00=no prefix, 01=66H, 10=F3H, and 11=F2H). Bits [6:3], shown as vvvv, can be used to: 1) encode a first source register operand, which is specified in inverted (complement) form and is valid for instructions with 2 or more source operands; 2) encode a destination register operand, which is specified in complement form for certain vector shifts; or 3) not encode any operand, the field is reserved and should contain a value, such as 1111b.

[0090] Instructions using this prefix may use the MOD R / MR / M field 746 to encode instruction operands that reference memory addresses, or to encode destination register operands or source register operands.

[0091] Instructions using this prefix may use the MOD R / M register field 744 to encode a destination register operand or a source register operand, treated as an opcode extension and not used to encode any instruction operand.

[0092] For instruction syntax supporting four operands, vvvv, MOD R / MR / M field 746, and MOD R / M register field 744 encode three of the four operands. Bits [7:4] of immediate 609 are then used to encode the third source register operand.

[0093] Figure 10 (B) illustrates an embodiment of the three-byte form of the second prefix 601 (B). In one example, the format field 1011 (byte 0 1013) contains the value C4H. Byte 1 1015 includes "R", "X" and "B" in bit [7:5], which are the complements of the same value of the first prefix 601 (A). Bit [4:0] (shown as mmmm) of byte 1 1015 includes the content of encoding one or more implicit leading operation code bytes as needed. For example, 00001 means 0FH leading operation code, 00010 means 0F38H leading operation code, 00011 means 0F3AH leading operation code, etc.

[0094] The use of bit [7] of byte 2 1017 is similar to W of the first prefix 601 (A), including helping to determine the size of operands that can be promoted. Bit [2] is used to specify the length (L) of the vector (where a value of 0 is a scalar or 128-bit vector and a value of 1 is a 256-bit vector). Bits [1:0] provide opcode extensibility equivalent to some traditional prefixes (e.g., 00=no prefix, 01=66H, 10=F3H, and 11=F2H). Bits [6:3], shown as vvvv, can be used to: 1) encode the first source register operand, which is specified in inverted (inverse) form and is valid for instructions with 2 or more source operands; 2) encode the destination register operand, which is specified in inverse form for certain vector shifts; or 3) do not encode any operand, this field is reserved and should contain a value, such as 1111b.

[0095] Instructions using this prefix may use the MOD R / MR / M field 746 to encode instruction operands that reference memory addresses, or to encode destination register operands or source register operands.

[0096] Instructions using this prefix may use the MOD R / M register field 744 to encode a destination register operand or a source register operand, treated as an opcode extension and not used to encode any instruction operand.

[0097] For instruction syntax supporting four operands, vvvv, MOD R / MR / M field 746, and MOD R / M register field 744 encode three of the four operands. Bits [7:4] of immediate 609 are then used to encode the third source register operand.

[0098] Fig.11 An embodiment of a third prefix 601(C) is illustrated. In some embodiments, the third prefix 601(C) is an embodiment of an EVEX prefix. The third prefix 601(C) is a four-byte prefix.

[0099] The third prefix 601(C) can encode 32 vector registers (e.g., 128-bit, 256-bit, and 512-bit registers) in 64-bit mode. In some embodiments, a write mask / operation mask is used (see for example FIG. Figure 5 ) or predicate instructions utilize this prefix. The operation mask register allows conditional processing or selection control. Operation mask instructions whose source / destination operands are operation mask registers and treat the contents of the operation mask register as a single value are encoded using the second prefix 601 (B).

[0100] The third prefix 601(C) may encode functionality specific to the instruction class (e.g., a packed instruction with “load+operation” semantics may support an embedded broadcast functionality, a floating-point instruction with rounding semantics may support a static rounding functionality, a floating-point instruction with non-rounding arithmetic semantics may support a “suppress all exceptions” functionality, etc.).

[0101] The first byte of the third prefix 601 (C) is the format field 1111, which in one example has a value of 62 H. The subsequent bytes are called payload bytes 1115-1119, and together form a 24-bit value of P[23:0], providing specific capabilities in the form of one or more fields (described in detail herein).

[0102] In some embodiments, P[1:0] of payload byte 1119 is the same as the two mmmm bits in the lower order. In some embodiments, P[3:2] is reserved. Bit P[4] (R') allows access to the upper 16 vector register sets when combined with P[7] and MOD R / M register field 744. P[6] can also provide access to the upper 16 vector registers when SIB type addressing is not required. P[7:5] consists of R, X, and B, which are operand specifier modifier bits for vector registers, general registers, and memory addressing, and when combined with MOD R / M register field 744 and MOD R / MR / M field 746, allow access to the next set of 8 registers beyond the lower 8 registers. P[9:8] provides opcode extensibility equivalent to some traditional prefixes (e.g., 00=no prefix, 01=66H, 10=F3H, and 11=F2H). P

[10] is a fixed value of 1 in some embodiments. P[14:11], shown as vvvv, can be used to: 1) encode a first source register operand, which is specified in inverted (complement) form and is valid for instructions with 2 or more source operands; 2) encode a destination register operand, which is specified in complement form for certain vector shifts; or 3) not encode any operand, the field is reserved and should contain some value, such as 1111b.

[0103] P

[15] is similar to W of the first prefix 601 (A) and the second prefix 611 (B), and can be used as an opcode extension bit or an operand size increase.

[0104] P[18:16] specifies the index of a register in an operation mask (write mask) register (e.g., write mask / predicate register 515). In one embodiment of the present disclosure, the particular value aaa=000 has special behavior, implying that no operation mask is used for this particular instruction (this can be implemented in a variety of ways, including using an operation mask hardwired to all ones or hardware that bypasses the masking hardware). When merging, the vector mask allows any set of elements in the destination to be protected from updates during the execution of any operation (specified by the basic operation and the enhanced operation); in another embodiment, the old value of each element of the destination is retained (if the corresponding mask bit has a value of 0). In contrast, when zeroing, the vector mask allows any set of elements in the destination to be zeroed during the execution of any operation (specified by the basic operation and the enhanced operation); in one embodiment, the elements of the destination are set to 0 when the corresponding mask bit has a value of 0. A subset of this functionality is the ability to control the vector length of the operation being performed (i.e., the span of elements modified, from first to last); however, the elements modified do not have to be consecutive. Thus, the operation mask field enables a subset of vector operations, including loads, stores, arithmetic, logical, etc. Although in the described embodiments of the present disclosure, the contents of the operation mask field select which of several operation mask registers contains the operation mask to be used (thus the contents of the operation mask field indirectly identify the masking to be performed), alternative embodiments alternatively or additionally allow the contents of the mask write field to directly specify the masking to be performed.

[0105] P

[19] can be combined with P[14:11] to encode a second source vector register in a non-destructive source syntax that can utilize P

[19] to access the upper 16 vector registers. P

[20] encodes various features that vary in different classes of instructions and can affect the meaning of the vector length / rounding control specifier field (P[22:21]). P

[23] indicates support for merge-write masking (e.g., when set to 0) or support for zeroing and merge-write masking (e.g., when set to 1).

[0106] An exemplary embodiment of the encoding of registers in instructions using the third prefix 601 (C) is detailed in the table below.

[0107]

[0108] Table 1: 32-register support in 64-bit mode

[0109] [2:0] Register Type Common Uses REG MOD R / M Register GPR, vector Destination or source VVVV vvvv GPR, vector Second source or destination RM MOD R / MR / M GPR, vector 1st source or destination Base Address MOD R / MR / M GPR Memory addressing index SIB.Index GPR Memory addressing VIDX SIB.Index vector VSIB Memory Addressing

[0110] Table 2: Encoding register specifiers in 32-bit mode

[0111]

[0112]

[0113] Table 3: Operation Mask Register Specifier Encoding

[0114] Program code can be applied to input instructions to perform the functions described herein and generate output information. The output information can be applied to one or more output devices in a known manner. For the present application, a processing system includes any system having a processor, such as a digital signal processor (DSP), a microcontroller, an application specific integrated circuit (ASIC), or a microprocessor.

[0115] Program code can be implemented in a process-oriented or object-oriented high-level programming language to communicate with the processing system. If desired, program code can also be implemented in assembly or machine language. In fact, the mechanism described herein is not limited to any specific programming language in scope. In any case, the language can be a compiled language or an interpreted language.

[0116] The embodiments of the mechanisms disclosed herein may be implemented in hardware, software, firmware, or a combination of these implementation approaches. The embodiments of the present disclosure may be implemented as a computer program or program code, executed on a programmable system including at least one processor, a storage system (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device.

[0117] One or more aspects of at least one embodiment may be implemented by representative instructions stored on a machine-readable medium, which represent various logic within a processor, which, when read by a machine, causes the machine to fabricate logic for performing the techniques described herein. These representations, known as "IP cores," may be stored on a tangible machine-readable medium and provided to various customers or manufacturing facilities to be loaded into a fabrication machine that actually fabricates the logic or processor.

[0118] These machine-readable storage media may include, but are not limited to, non-transitory tangible arrangements of articles manufactured or formed by a machine or device, including storage media such as: a hard disk, any other type of disk (including floppy disks, optical disks, compact disk read-only memory (CD-ROM), compact disk rewritable (CD-RW), and magneto-optical disks), semiconductor devices (e.g., read-only memory (ROM), random access memory (RAM) such as dynamic random access memory (DRAM), static random access memory (SRAM), erasable programmable read-only memory (EPROM), flash memory, electrically erasable programmable read-only memory (EEPROM), phase change memory (PCM)), magnetic or optical cards, or any other type of medium suitable for storing electronic instructions.

[0119] Therefore, embodiments of the present disclosure also include non-transitory tangible machine-readable media that contain instructions or design data that define the structures, circuits, devices, processors and / or system features described herein, such as hardware description languages ​​(HDL). Such embodiments may also be referred to as program products.

[0120] Emulation (including binary translation, code deformation, etc.)

[0121] In some cases, the instruction converter can be used to convert instructions from a source instruction set to a target instruction set. For example, the instruction converter can translate (e.g., using static binary translation, dynamic binary translation including dynamic compilation), deform, simulate or otherwise convert instructions to one or more other instructions to be processed by the core. The instruction converter can be implemented with software, hardware, firmware or a combination thereof. The instruction converter can be on the processor, outside the processor, or partly on the processor and partly outside the processor.

[0122] Fig.12is a block diagram comparing the use of a software instruction converter according to certain implementations, the software instruction converter being used to convert binary instructions in a source instruction set into binary instructions in a target instruction set. In the illustrated embodiment, the instruction converter is a software instruction converter, but alternatively, the instruction converter may be implemented in software, firmware, hardware, or various combinations thereof. Fig.12 A program in a high-level language 1202 is shown to be compiled using a first ISA compiler 1204 to generate first ISA binary code 1206 that can be natively executed by a processor 1216 having at least one first instruction set core. The processor 1216 having at least one first ISA instruction set core represents any processor that is capable of executing programs with at least one first ISA instruction set core by compatibly executing or otherwise processing (1) a substantial portion of the instruction set of the first ISA instruction set core or (2) an object code version of an application or other software targeted to run on an Intel processor having at least one first ISA instruction set core. The first ISA compiler 1204 represents a compiler operable to generate first ISA binary code 1206 (e.g., object code) that can be executed on a processor 1216 having at least one first ISA instruction set core with or without additional linking processing.

[0123] Similarly, Fig.12 It is shown that a program in a high-level language 1202 can be compiled using an alternative instruction set compiler 1208 to generate an alternative instruction set binary code 1210, which can be executed natively by a processor 1214 without a first ISA instruction set core. An instruction converter 1212 is used to convert the first ISA binary code 1206 into code that can be executed natively by a processor 1214 without a first ISA instruction set core. This converted code is unlikely to be the same as the alternative instruction set binary code 1210, because an instruction converter that can do this is difficult to make; however, the converted code will implement the overall operation and be composed of instructions from the alternative instruction set. Thus, the instruction converter 1212 represents software, firmware, hardware, or a combination thereof that allows a processor or other electronic device that does not have a first ISA instruction set processor or core to execute the first ISA binary code 1206 through simulation, emulation, or any other process.

[0124] Apparatus and method for graceful degradation of processor

[0125] Embodiments of the present disclosure implement techniques to ensure that safety-critical systems and processors continue to operate, but with a gradually reduced safety margin as individual processing components (e.g., cores, processors) fail. These implementations rely on data processing redundancy between multiple cores within an SoC or processor, or between multiple SoCs or processors within a system. Although the embodiments described below focus on redundancy using multiple cores, the basic principles of the present disclosure can be implemented using redundancy of any type of processing element (including but not limited to cores, processors, and SoCs).

[0126] Embodiments of the present disclosure adjust a processor's redundancy protocol in response to detected errors and adjustments to the number of participating cores. These embodiments include circuits and logic for aggregating errors generated by each core over time. When a specific error threshold is reached, such as a specific error rate (e.g., errors / time unit), the misbehaving core is disabled or otherwise removed from participating in the redundancy protocol. Error detection is then modified to gracefully reduce the processor's ability to detect errors and continue to operate correctly.

[0127] As an example and not limitation, the processor may be initialized in a three-core redundant mode that uses commit value voting to verify correctness. In commit value voting, the three cores execute the same code and should therefore produce the same results. If the result of one core differs from the results of the other two cores, the voting block commits the results from the other two cores and records the error of the one core. If the threshold error accumulation for the core is reached, the core is removed and the architecture is degraded to a lockstep implementation with two cores.

[0128] In addition, some embodiments of the present disclosure include an error correction code (ECC) and program counter monitor that compares the requested instruction address with the instruction memory of each core and accumulates indications of ECC corrections (or failures to correct errors) from the memory. A fault tracker records the differences in the requested addresses (e.g., using a majority vote) and also records the frequency of ECC corrections for a given memory.

[0129] When a given core and / or its memory generates more errors than a configurable threshold, the fault tracker disables that core and updates the voting logic block and ECC monitor to operate in lockstep mode for the remaining two cores. In lockstep mode, instruction addresses and committed values ​​for both cores are monitored.

[0130] If the failure is due to memory content corruption, further fault identification can be performed from this point. Specifically, if the two remaining cores are inconsistent, but one exhibits ECC errors and the other does not, the core associated with the ECC errors is removed (or is removed after a threshold number of ECC errors are detected) and the system is downgraded to the single remaining core.

[0131] Fig.13A An embodiment is illustrated having three cores 1301-1303 initially operating in a three-core redundant mode that uses committed value voting to verify correctness. If the result of one core 1301 differs from the results of the other two cores 1302-1303, the voting logic 1330 commits the results 1350 from the other two cores and records the error of the one core (e.g., core 1301) using the fault tracker 1310. In addition, the illustrated embodiment includes an ECC and program counter monitor 1340 that compares the requested instruction addresses sent to the instruction memories 1311-1313 of each core and accumulates indications of ECC corrections (or faults to correct errors) from the memories. The fault tracker 1310 records the differences in the requested addresses from the three cores 1301-1303 (e.g., using majority voting) and also records the ECC corrections for a given memory 1311-1313.

[0132] When a given core 1301 and / or its memory 1311 generates more errors than a configurable threshold, the fault tracker 1310 disables that core (indicated by signal 1390) and updates the voting logic block 1330 and the ECC and program counter monitor 1340 to operate in lockstep mode for the remaining two cores 1312-1313.

[0133] refer to Fig. 13B , in lockstep mode, the ECC and program counter monitor 1340 continues to detect memory errors and compare instruction addresses. The voting logic 1330 compares the results produced by the two cores 1302-1303 to detect differences. If the fault is due to corruption of memory contents, further fault identification can be performed. Specifically, if the remaining two cores 1302-1303 are inconsistent, but one core 1302 exhibits ECC errors and the other does not, the core 1302 associated with the ECC error is removed (e.g., after a threshold number of ECC errors are detected), which is indicated by signal 1391, and the system is downgraded to the single remaining core 1303, as shown. Fig. 13CAs shown. At this stage, the hardware redundancy that may be required is no longer possible, but embodiments of the present disclosure are not limited to safety-critical applications. In this case, the processor needs to be replaced to regain hardware redundancy. However, the single core 1303 will still perform the required functions until it is replaced.

[0134] Fig.14 A method according to one embodiment of the present disclosure is illustrated. The method can be implemented on the architecture described herein, but is not limited to any specific processor, SoC or system architecture.

[0135] At 1401, a processing system is operated with triple redundant voting. As described above, if a result value generated by a first core or processor differs from result values ​​from the other two cores or processors, the result values ​​from the other two cores or processors are committed and an error is associated with the first processor.

[0136] When the number of errors associated with any core or processor reaches a threshold, the failure threshold may be reached, determined at 1402. At 1403, the problematic core is removed and the system operates in a dual processor / core lockstep mode. In this mode, a comparison is made between the result value and the program counter address, and ECC is applied to the instruction or data read from memory. If the result or instruction address of the two cores is different, and if ECC is used for the first of the two cores, the result from the second core is committed and an error is logged for the first core.

[0137] When the number of errors from any core reaches a threshold (determined at 1404), the processor or system downgrades to single processor / core ECC mode at 1405. In this mode, the only protection against errors is the ECC mechanism, but the system will continue to operate until replaced.

[0138] Fig.15 An embodiment is illustrated in which the fault tracker 1510 is enhanced with a secure memory 1500 (e.g., a read-only memory (ROM)) containing a clean software / firmware image and update logic 1520 for recovering the software / firmware in the instruction memories 1311-1313 of the processor cores 1301-1303. This implementation allows errors due to transient effects (e.g., single event upsets (SEUs)) to be fully recoverable, thereby allowing the system to recover operation from single-core operation to dual-core lockstep ( Fig. 13B ), and / or recover from dual-core lockstep to three-core triple modular redundancy (TMR) ( Fig.13A ).

[0139] To ensure the integrity of the secure ROM containing the clean image, the ROM may be replicated three times 1501-1503 and a TMR redundant voting system employed to ensure its contents remain valid. This may be accomplished via existing voting logic 1330 or via voting logic integrated with update logic 1520. If it is determined that the contents of one of the ROMs 1501-1503 have been compromised, no attempt will be made to recover the corrupted memory.

[0140] Alternatively or additionally, secure ROM 1500 may be implemented using a different process technology or circuit structure that is more resistant to tampering and single event upsets, but at the expense of access latency.

[0141] Fig.16 One implementation of a processor on which embodiments of the present disclosure may be implemented is illustrated. However, as noted above, the underlying principles of the present disclosure are not limited to any particular type of processor or system.

[0142] The illustrated processor includes a heterogeneous tile-based architecture (e.g., having multiple heterogeneous dies integrated on a single processor package). The processor includes a CPU tile 1615 having a heterogeneous core group including an efficiency core (E core) and a plurality of performance cores (P cores) 1620-1621 arranged into two E core clusters 1610-1611. Some embodiments of the SoC tile 1610 include a set of E cores 1612-1613 and a memory controller (MC) to couple the processor to a system memory 1650 (e.g., DDR DRAM memory, HBM memory, etc.). Fig.16 Any group of P cores and E cores in the above can participate in FIG. 13A to FIG. 13C and Fig.14 Also illustrated is a GPU tile 1605 that includes a plurality of graphics cores 1607-1608 that can be managed in the same manner as the P-cores and E-cores described herein.

[0143] The CPU tile 1615 includes a plurality of L2 cache areas 1680-1683, each of which can be implemented with an L2 reuse data cache as described herein. The L2 cache area 1683 is highlighted and includes a selector coupled to the L2 cache area and the L2 reuse data cache area. As described above, the L2 reuse data cache area can be a reserved portion of the entire L2 cache 1683 or can be a separate dedicated area. The same or similar reuse data cache architecture can be implemented in an L3 cache 1691-1692 or an L1 cache (not shown).

[0144] The E cores in the E core clusters 1610-1611 and SoC tile 1610 are physically smaller (multiple E cores fit into the physical die space of a P core), are designed to maximize CPU efficiency (measured in performance per watt), and are typically used for scalable multi-threaded performance. The E cores work in conjunction with the P cores 1620-1621 to accelerate tasks that tend to consume a large number of cores. The E cores are optimized to run background tasks efficiently, so smaller tasks are typically offloaded to the E cores (e.g., handling Discord or antivirus software), leaving the P cores 1620-1621 free to drive high-performance tasks such as gaming or 3D rendering.

[0145] P cores 1620-1621 are physically larger high-performance cores tuned for high turbo frequencies and high IPC (instructions per cycle), and are particularly suited for handling heavy single-threaded workloads. In some embodiments, the P cores are also capable of hyperthreading (i.e., running multiple software threads simultaneously).

[0146] Embodiments of the present disclosure may include the various steps described above. These steps may be embodied in machine executable instructions, which may be used to cause a general or special processor to perform these steps. Alternatively, these steps may be performed by specific hardware components containing hardwired logic for performing these steps, or by any combination of programmed computer components and custom hardware components.

[0147] Example

[0148] The following are example implementations of different embodiments of the present disclosure.

[0149] Example 1. An apparatus comprising: three processing elements capable of operating in a first redundant mode, the three processing elements being configured to execute the same sequence of instructions to produce three corresponding results; a detection circuit configured to detect when any one of the three processing elements produces a result that is different from the other two of the three processing elements; and a tracking circuit configured to associate an error with the one processing element when the one processing element produces a result that is different from the other two processing elements, wherein if an error threshold is reached for the one processing element, the other two processing elements will operate in a second redundant mode that does not include the one processing element.

[0150] Example 2. The apparatus of Example 1, wherein the tracking circuit is to accumulate errors associated with each of the three processing elements and determine when the error threshold is reached for any of the three processing elements.

[0151] Example 3. The apparatus of Example 1 or 2, further comprising: monitoring circuitry for monitoring memory transactions performed by the three processing elements and detecting differences in memory transactions associated with any one of the three processing elements; and wherein the tracking circuitry is for responsively associating additional errors with the one processing element.

[0152] Example 4. The apparatus of any of Examples 1-3, wherein monitoring memory transactions comprises comparing addresses used by each processing element to fetch instructions, and detecting when the address used by the one processing element to fetch instructions differs from addresses used by the other two processing elements to fetch instructions.

[0153] Example 5. An apparatus of any one of Examples 1-4, wherein the second redundancy mode of the other two processing elements includes a lockstep mode, in which an error is generated in response to detecting a difference between a first result generated by a first processing element of the two processing elements and a second result generated by a second processing element of the two processing elements.

[0154] Example 6. The apparatus of any of Examples 1-5, wherein if error correction is used to produce one of the first result or the second result, the tracking circuit is to associate an error with the result using the error correction.

[0155] Example 7. The apparatus of any one of Examples 1-6, wherein the error threshold comprises a first error threshold, wherein if a second error threshold associated with the first processing element or the second processing element is reached, a corresponding one of the first processing element and the second processing element is removed from participating in the lockstep mode, and the other of the first processing element and the second processing element continues to operate.

[0156] Example 8. The apparatus of any of Examples 1-7, wherein each of the three processing elements comprises a core of a processor of a system on a chip (SoC).

[0157] Example 9. The apparatus of any of Examples 1-8, wherein each of the three processing elements comprises a separate processor of a computing system or a system on a chip (SoC).

[0158] Example 10. A method comprising: operating three processing elements in a first redundant mode, the three processing elements being configured to execute an identical sequence of instructions to produce three corresponding results; detecting when any one of the three processing elements produces a result that is different from the other two of the three processing elements; associating an error with the one processing element when the one processing element produces a result that is different from the other two processing elements; and operating the other two processing elements in a second redundant mode that does not include the one processing element if an error threshold is reached for the one processing element.

[0159] Example 11. The method of Example 10, further comprising: accumulating errors associated with each of the three processing elements; and determining when the error threshold is reached for any of the three processing elements.

[0160] Example 12. The method of Example 10 or 11, further comprising: monitoring memory transactions performed by the three processing elements; detecting differences in memory transactions associated with any one of the three processing elements; and responsively associating additional errors with the one processing element.

[0161] Example 13. The method of any of Examples 10-12, wherein monitoring memory transactions comprises comparing addresses used by each processing element to fetch instructions, and detecting when the address used by the one processing element to fetch instructions differs from addresses used by the other two processing elements to fetch instructions.

[0162] Example 14. The method of any of Examples 10-13, wherein the second redundancy mode of the other two processing elements comprises a lockstep mode in which an error is generated in response to detecting a difference between a first result produced by a first processing element of the two processing elements and a second result produced by a second processing element of the two processing elements.

[0163] Example 15. The method of any of Examples 10-14, wherein if error correction was used to produce one of the first result or the second result, an error is associated with the result in which the error correction was used.

[0164] Example 16. The method of any of Examples 10-15, wherein the error threshold comprises a first error threshold, wherein if a second error threshold associated with the first processing element or the second processing element is reached, a corresponding one of the first processing element and the second processing element is removed from participating in the lockstep mode, and the other of the first processing element and the second processing element continues to operate.

[0165] Example 17. A machine-readable medium having program code stored thereon, the program code, when executed by a processor or a processor component, causing the processor or the processor component to perform operations, the operations comprising: operating three processing elements in a first redundant mode, the three processing elements being used to execute the same sequence of instructions to produce three corresponding results; detecting when any one of the three processing elements produces a result different from the other two of the three processing elements; associating an error with the one processing element when the one processing element produces a result different from the other two processing elements; and operating the other two processing elements in a second redundant mode that does not include the one processing element if an error threshold is reached for the one processing element.

[0166] Example 18. The machine-readable medium of Example 17, the operations further comprising: accumulating errors associated with each of the three processing elements; and determining when the error threshold is reached for any of the three processing elements.

[0167] Example 19. The machine-readable medium of Example 17 or 18, the operations further comprising: monitoring memory transactions performed by the three processing elements; detecting differences in memory transactions associated with any one of the three processing elements; and responsively associating additional errors with the one processing element.

[0168] Example 20. The machine-readable medium of any of Examples 18-19, wherein monitoring memory transactions comprises comparing addresses used by each processing element to fetch instructions, and detecting when the address used by the one processing element to fetch instructions differs from addresses used by the other two processing elements to fetch instructions.

[0169] As described herein, instructions may refer to a specific configuration of hardware (e.g., an application-specific integrated circuit (ASIC) configured to perform certain operations or have predetermined functions), or may refer to software instructions stored in a memory embodied in a non-transitory computer-readable medium. Therefore, the techniques shown in the figure can be implemented using code and data stored and executed on one or more electronic devices (e.g., terminal stations, network elements, etc.). Such electronic devices use computer machine-readable media to store and transmit (internally and / or with other electronic devices through a network) code and data, such as non-transitory computer machine-readable storage media (e.g., disks; optical disks; random access memory; read-only memory; flash memory devices; phase change memory) and transient computer machine-readable communication media (e.g., electrical, optical, acoustic or other forms of propagation signals - such as carrier waves, infrared signals, digital signals, etc.). In addition, such electronic devices typically include a group of one or more processors coupled to one or more other components, such as one or more storage devices (non-transitory machine-readable storage media), user input / output devices (e.g., keyboards, touch screens and / or displays), and network connections. The coupling of the group of processors and other components is typically through one or more buses and bridges (also known as bus controllers). The storage device and the signal carrying the network business represent one or more machine-readable storage media and machine-readable communication media, respectively. Therefore, the storage device of a given electronic device generally stores code and / or data for execution on a set of one or more processors of the electronic device. Of course, one or more parts of the embodiments of the present disclosure can be implemented using different combinations of software, firmware and / or hardware. Throughout this specific implementation, for the purpose of explanation, many specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be practiced without some of these specific details. In some cases, well-known structures and functions are not described in detail to avoid blurring the subject matter of the present disclosure. Therefore, the scope and spirit of the present disclosure should be judged according to the appended claims.

Claims

1. A device comprising: three processing elements operable in a first redundant mode, the three processing elements for executing the same sequence of instructions to produce three corresponding results; a detection circuit for detecting when any one of the three processing elements produces a result that is different from the other two of the three processing elements; a tracking circuit for associating an error with the one processing element when the one processing element produces a different result than the other two processing elements, If the error threshold is reached for the one processing element, the other two processing elements will operate in a second redundant mode that does not include the one processing element.

2. The device according to claim 1, wherein: The tracking circuit is to accumulate errors associated with each of the three processing elements and determine when the error threshold is reached for any of the three processing elements.

3. The device according to claim 1 or 2, further comprising: monitoring circuitry for monitoring memory transactions executed by the three processing elements and detecting discrepancies in memory transactions associated with any of the three processing elements; and Wherein the tracking circuit is used to responsively associate additional errors with the one processing element.

4. The device according to claim 3, wherein: Monitoring memory transactions includes comparing addresses used by each processing element to fetch instructions and detecting when the address used by the one processing element to fetch instructions differs from addresses used by the other two processing elements to fetch instructions.

5. The device according to any one of claims 1 to 4, wherein: The second redundancy mode of the other two processing elements comprises a lockstep mode in which an error is generated in response to detecting a difference between a first result produced by a first processing element of the two processing elements and a second result produced by a second processing element of the two processing elements.

6. The device according to claim 5, wherein: If error correction was used to produce one of the first result or the second result, the tracking circuit is used to associate an error with the result in which the error correction was used.

7. The device according to claim 6, wherein: The error threshold includes a first error threshold, wherein if a second error threshold associated with the first processing element or the second processing element is reached, the corresponding one of the first processing element and the second processing element is removed from participating in the lockstep mode and the other of the first processing element and the second processing element continues to operate.

8. The device according to any one of claims 1 to 7, wherein: Each of the three processing elements comprises a core of a processor of a system on a chip (SoC).

9. The device according to any one of claims 1 to 8, wherein: Each of the three processing elements comprises a separate processor of a computing system or system on a chip (SoC).

10. A method comprising: operating three processing elements in a first redundant mode, the three processing elements being operable to execute the same sequence of instructions to produce three corresponding results; detecting when any one of the three processing elements produces a result that is different from another two of the three processing elements; associating an error with the one processing element when the one processing element produces a different result than the other two processing elements; as well as If the error threshold is reached for the one processing element, the other two processing elements are operated in a second redundant mode that does not include the one processing element.

11. The method of claim 10, further comprising: accumulating errors associated with each of the three processing elements; as well as A determination is made as to when the error threshold is reached for any of the three processing elements.

12. The method according to claim 10 or 11, further comprising: monitoring memory transactions performed by the three processing elements; detecting a difference in memory transactions associated with any of the three processing elements; as well as An additional error is responsively associated with the one processing element.

13. The method of claim 12, wherein: Monitoring memory transactions includes comparing addresses used by each processing element to fetch instructions and detecting when the address used by the one processing element to fetch instructions differs from addresses used by the other two processing elements to fetch instructions.

14. The method according to any one of claims 10 to 13, wherein: The second redundancy mode of the other two processing elements comprises a lockstep mode in which an error is generated in response to detecting a difference between a first result produced by a first processing element of the two processing elements and a second result produced by a second processing element of the two processing elements.

15. The method of claim 14, wherein: If error correction was used to produce one of the first result or the second result, an error is associated with the result in which the error correction was used.

16. The method of claim 15, wherein: The error threshold includes a first error threshold, wherein if a second error threshold associated with the first processing element or the second processing element is reached, the corresponding one of the first processing element and the second processing element is removed from participating in the lockstep mode and the other of the first processing element and the second processing element continues to operate.

17. A machine-readable medium having program code stored thereon, the program code, when executed by a processor or a processor component, causing the processor or processor component to perform operations comprising: operating three processing elements in a first redundant mode, the three processing elements being operable to execute the same sequence of instructions to produce three corresponding results; detecting when any one of the three processing elements produces a result that is different from another two of the three processing elements; associating an error with the one processing element when the one processing element produces a different result than the other two processing elements; as well as If the error threshold is reached for the one processing element, the other two processing elements are operated in a second redundant mode that does not include the one processing element.

18. The machine-readable medium of claim 17, the operations further comprising: accumulating errors associated with each of the three processing elements; as well as A determination is made as to when the error threshold is reached for any of the three processing elements.

19. The machine-readable medium of claim 17 or 18, the operations further comprising: monitoring memory transactions performed by the three processing elements; detecting a difference in memory transactions associated with any of the three processing elements; as well as An additional error is responsively associated with the one processing element.

20. The machine-readable medium of claim 19, wherein: Monitoring memory transactions includes comparing addresses used by each processing element to fetch instructions and detecting when the address used by the one processing element to fetch instructions differs from addresses used by the other two processing elements to fetch instructions.

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