Chip reset function verification method and system
By configuring the event pool to be triggered and the reset operation task manager in the chip verification environment, the problem of the inability to independently control individual components in the complex verification environment in the existing technology is solved, and the flexibility and efficiency improvement of chip reset function verification is achieved. .
Patent Information
- Application Number
- CN202411250884.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-06
- Publication Date
- 2024-12-31
AI Technical Summary
The existing chip reset testing methods cannot independently control individual components in complex verification environments, resulting in wasted testing resources and reduced simulation efficiency.
Pre-configure the event pool to be triggered in the chip verification environment, create reset events and associated reset operation task managers, and trigger the monitor to monitor and control the reset of environment components in real time, allowing new test cases to flexibly configure reset points in time to Triggers the reset event.
It realizes selective reset control of individual components in complex verification environments, reduces waste of test resources, and improves the flexibility and efficiency of chip reset function verification.
Smart Images
Figure CN119226067A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of chip reset verification, and in particular to a chip reset function verification method and system. Background Art
[0002] Large-scale integrated circuit technology has been developing rapidly in recent years. As the number of gates in integrated circuits continues to increase, the logic scale of the corresponding chips is becoming more and more complex. Therefore, verification work for large-scale integrated circuits is becoming more and more important.
[0003] In the process of verifying the design to be tested, it is essential to test the reset scenario of the chip. The specific process usually includes: during the normal simulation operation of the chip or when the chip is idle for a period of time, the reset signal of the chip is set to the valid state to reset the chip. After a certain period of reset, the reset signal is released to restart the chip, and then the chip is called to work to observe whether the chip works normally after reset. However, operating the reset signal during the normal operation of the chip will often disrupt the operation of the testbench (verification platform), resulting in some unpredictable problems.
[0004] At present, a commonly used reset test method is to call the phase jump method in the UVM test environment to directly jump the verification environment running phase to the reset_phase phase, reset the entire verification environment, and then send normal stimulus to check whether the chip can work normally after reset.
[0005] However, the above reset test method has the following shortcomings:
[0006] Using phase jump will reset the entire verification environment. In a more complex verification environment, there is no way to control the jump of individual components. It is impossible to control different components separately in the reset scenario. At the same time, resetting the entire verification environment will also lead to a large waste of test resources and reduce simulation efficiency. Summary of the invention
[0007] In view of the problems existing in the prior art, the present invention provides a chip reset function verification method, which pre-configures a to-be-triggered event pool in a chip verification environment; the chip reset function verification method comprises:
[0008] Step S1, creating a reset event and an associated reset operation task manager in a test case base class in the chip verification environment, and configuring a reset event trigger monitor in an environment component that needs to perform a reset operation, and placing the reset event into the event pool to be triggered;
[0009] Step S2, when the new test case inheriting the test case base class in the chip verification environment needs to verify the chip reset function, the corresponding reset operation task manager is called according to the preset reset time point to perform the reset operation, and after the reset operation is completed, the event trigger function is called to trigger the corresponding reset event in the event pool to be triggered;
[0010] Step S3, the reset event triggering monitor continuously monitors the event pool to be triggered, and performs a post-reset operation on the corresponding environment component when detecting that the corresponding reset event is triggered;
[0011] Step S4, after the post-reset operation is completed, the new test case generates a corresponding stimulus input into the chip to complete the chip reset function verification.
[0012] Preferably, the reset operation task manager is configured with three parameters, namely, reset mode, minimum reset duration period and maximum reset duration period;
[0013] Then in step S2, the process of the reset operation task manager performing the reset operation includes:
[0014] Step S21, generating a reset effective duration according to the minimum reset duration period and the maximum reset duration period;
[0015] Step S22, applying a corresponding effective reset signal to the chip according to the reset mode, and maintaining the reset effective time, and then calling an event triggering function to trigger the corresponding reset event in the event pool to be triggered.
[0016] Preferably, in step S22, the corresponding valid reset signal is applied to the chip through a backdoor HDL path.
[0017] Preferably, in step S21, the reset effective time length is randomly generated with the minimum value of the reset duration period as the lower limit and the maximum value of the reset duration period as the upper limit.
[0018] Preferably, the environment component includes an agent component, a scoreboard component and a general verification component; then in step S3, the post-reset operation includes:
[0019] The queue in the monitoring module encapsulated in the proxy component is cleared, and / or the queue in the scoreboard component is cleared, and / or the transaction generator in the universal verification component is remounted.
[0020] The present invention also provides a chip reset function verification system, which applies the above chip reset function verification method, and the chip reset function verification system comprises:
[0021] A chip verification environment, wherein the chip verification environment includes a pre-configured event pool to be triggered, a test case base class, at least one new test case that inherits the test case base class, and a plurality of environment components;
[0022] A first configuration module, connected to the chip verification environment, is used for a chip verification personnel to create a reset event and an associated reset operation task manager in the test case base class, and to configure a reset event trigger monitor in an environment component that needs to perform a reset operation, and to place the reset event into the event pool to be triggered;
[0023] A second configuration module is connected to the chip verification environment, and is used for the chip verification personnel to add a corresponding reset time point in the new test case when the new test case needs to verify the chip reset function, so that the new test case calls the corresponding reset operation task manager to perform a reset operation at the reset time point, and calls the event trigger function to trigger the corresponding reset event in the event pool to be triggered after the reset operation is completed;
[0024] The reset event trigger monitor is used to continuously monitor the event pool to be triggered, and when it is detected that the corresponding reset event is triggered, perform a post-reset operation on the corresponding environment component;
[0025] After the post-reset operation is completed, the new test case generates a corresponding stimulus input into the chip to complete the chip reset function verification.
[0026] Preferably, the reset operation task manager is configured with three parameters, namely, reset mode, minimum reset duration period and maximum reset duration period;
[0027] Then the reset operation task manager includes:
[0028] A duration generation module, used to generate a reset effective duration according to the minimum reset duration period and the maximum reset duration period;
[0029] A reset control module, connected to the duration generation module, is used to apply a corresponding effective reset signal to the chip according to the reset method and maintain the reset effective duration, and then call an event trigger function to trigger the corresponding reset event in the event pool to be triggered.
[0030] Preferably, in the reset control module, the corresponding valid reset signal is applied to the chip through a backdoor HDL path.
[0031] Preferably, in the duration generation module, the reset effective duration is randomly generated with the minimum value of the reset duration period as the lower limit and the maximum value of the reset duration period as the upper limit.
[0032] Preferably, the environment component includes an agent component, a scoreboard component and a general verification component; then the post-reset operation includes:
[0033] The queue in the monitoring module encapsulated in the proxy component is cleared, and / or the queue in the scoreboard component is cleared, and / or the transaction generator in the universal verification component is remounted.
[0034] The above technical solution has the following advantages or beneficial effects:
[0035] 1) By configuring a pool of events to be triggered in the verification environment, the environment components that need to be reset in the verification environment can selectively configure corresponding reset event trigger monitors to observe the state changes of reset events in the pool of events to be triggered in real time. Environment components that do not need to be reset do not need to add reset event trigger monitors, thereby achieving that each environment component can independently and selectively perform post-reset operations without resetting the entire verification environment, making the chip reset function verification process more flexible and efficient;
[0036] 2) By creating a reset event and an associated reset operation task manager in the test case base class, it is convenient for new test cases that inherit the test case base class to call without repeated configuration. When an update is required, only the reset event and the associated reset operation task manager in the test case base class need to be updated accordingly, further improving the chip reset function verification efficiency;
[0037] 3) By configuring a preset reset time point in a new test case, the time when the reset scenario occurs can be flexibly controlled. BRIEF DESCRIPTION OF THE DRAWINGS
[0038] Figure 1 A schematic flow chart of a chip reset function verification method in a preferred embodiment of the present invention;
[0039] Figure 2 It is a structural schematic diagram of a chip verification environment in a preferred embodiment of the present invention;
[0040] Figure 3 It is a flowchart of the process of the reset operation task manager performing the reset operation in a preferred embodiment of the present invention;
[0041] Figure 4 The figure is a schematic diagram of the structure of a chip reset function verification system in a preferred embodiment of the present invention. DETAILED DESCRIPTION
[0042] The present invention is described in detail below in conjunction with the accompanying drawings and specific embodiments. The present invention is not limited to this embodiment, and other embodiments may also fall within the scope of the present invention as long as they conform to the gist of the present invention.
[0043] In a preferred embodiment of the present invention, based on the above problems existing in the prior art, a chip reset function verification method is provided, in which a pool of events to be triggered is pre-configured in a chip verification environment; Figure 1 and Figure 2 As shown, the chip reset function verification method includes:
[0044] Step S1, creating a reset event and an associated reset operation task manager in a test case base class in a chip verification environment, and configuring a reset event trigger monitor in an environment component that needs to perform a reset operation, and placing the reset event into a to-be-triggered event pool;
[0045] Step S2, when a new test case inheriting the test case base class in the chip verification environment needs to verify the chip reset function, the new test case calls the corresponding reset operation task manager to perform a reset operation according to a preset reset time point, and after the reset operation is completed, calls the event trigger function to trigger the corresponding reset event in the event pool to be triggered;
[0046] Step S3, the reset event trigger monitor continuously monitors the event pool to be triggered, and when the corresponding reset event is detected to be triggered, performs a post-reset operation on the corresponding environment component;
[0047] Step S4: After the new test case completes the post-reset operation, a corresponding stimulus is generated and input into the chip to complete the chip reset function verification.
[0048] Specifically, Figure 2 The figure shows a complete chip verification environment 1, which includes a test case base class TC_BASE, at least one new test case TC_NO1 corresponding to the chip to be tested, and multiple environment components ENV. Figure 2 Only two environment components ENV are shown, namely environment component ENV1 and environment component ENV2, but the number of environment components ENV is not limited thereto.
[0049] In this embodiment, before the chip reset function verification is required for the chip to be tested, it is preferred to configure the reset event EVENT and the reset operation task manager 12 in the test case base class TC_BASE inherited by the new test case TC_NO1 corresponding to the test chip, and configure the to-be-triggered event pool 11 in the chip verification environment 1. The to-be-triggered event pool 11 is used to store the reset event EVENT as a publicly monitorable event, so that each environment component ENV can monitor the trigger status of each reset event EVENT. In order to realize the trigger status monitoring of each reset event EVENT by each environment component ENV, it is also necessary to configure the reset event trigger monitor 13 in the environment component ENV that needs to perform the reset operation. It can be seen that Figure 2 The environment component ENV1 and the environment component ENV2 are both configured with a reset event trigger monitor 13, but this is not limiting. Whether to configure the reset event trigger monitor 13 in a single environment component ENV is optional and can be flexibly adjusted according to actual reset verification requirements.
[0050] After the above configuration is completed, when the chip reset function needs to be verified for the chip under test, a preset reset time point can be configured in the new test case according to the verification requirements to control the time when the reset occurs. The preset reset time point can be the time when the chip is idle or the time when the chip is working, such as Figure 2 In the example, the preset reset time point can be configured between function one and function two executed by the new test case. Then, after function one is executed, the new test case will call the reset operation task manager 12 configured in the inherited test case base class TC_BASE to perform the reset operation, and after the reset operation is completed, call the event trigger function TRIGGER to trigger the corresponding reset event in the event pool to be triggered: EVENT.TRIGGER.
[0051] For the environment component ENV, if a reset operation needs to be performed, it is only necessary to create a corresponding reset event trigger monitor 13, which can be implemented by waiting for the reset event trigger function: RESET_EVENT.WAIT_TRIGGER(), so that the environment component ENV can monitor the occurrence of the reset event EVENT in the public event pool 11 to be triggered. Once the reset event trigger monitor 13 monitors the occurrence of the corresponding reset event EVENT, the corresponding post-reset operation can be performed. Each environment component ENV can selectively add a reset event trigger monitor 13 according to actual needs. If it is not added, no operation will be performed in the reset new test case.
[0052] After that, in the new test case TC_NO1, after waiting for the reset event to end, that is, after the reset operation is completed, a new stimulus is generated and input to the chip again to observe whether the chip can work normally. In this way, the verification test of the entire chip reset scenario is completed.
[0053] It can be seen that by configuring the event pool to be triggered in the verification environment, the environment components that need to be reset in the verification environment can selectively configure the corresponding reset event trigger monitor to observe the state changes of the reset events in the event pool to be triggered in real time. The environment components that do not need to be reset can not add the reset event trigger monitor, thereby achieving that each environment component can independently and selectively perform post-reset operations without resetting the entire verification environment, making the chip reset function verification process more flexible and efficient. In addition, by creating a reset event and an associated reset operation task manager in the test case base class, it is convenient to call new test cases that inherit the test case base class without repeated configuration, and when an update is needed, it is only necessary to update the reset event and the associated reset operation task manager in the test case base class accordingly, further improving the chip reset function verification efficiency;
[0054] In a preferred embodiment of the present invention, the reset operation task manager is configured with three parameters, namely, the reset mode, the minimum reset duration period, and the maximum reset duration period;
[0055] Then in step S2, if Figure 3 As shown, the process of the reset operation task manager performing the reset operation includes:
[0056] Step S21, generating a reset effective duration according to a minimum reset duration period and a maximum reset duration period;
[0057] Step S22, applying a corresponding effective reset signal to the chip according to the reset mode, and maintaining the reset effective time. After the reset signal is released, the event trigger function is then called to trigger the corresponding reset event in the event pool to be triggered.
[0058] Specifically, in this embodiment, the above reset modes are classified according to the design code, including but not limited to hot reset, cold reset and soft reset. Preferably, the above three parameters can be adjusted by inputting parameters to control the desired reset mode and the effective duration of the reset.
[0059] Further, in step S21, the reset effective duration is randomly generated with the minimum value of the reset duration period as the lower limit and the maximum value of the reset duration period as the upper limit. By configuring the minimum value of the reset duration period and the maximum value of the reset duration period, and correspondingly randomly generating the reset effective duration, more reset scenarios can be covered to ensure the completeness of the reset scenario verification. For example, the actual reset time required for the chip to be tested is T, and the corresponding minimum value of the reset duration period and the maximum value of the reset duration period can be configured based on T. During the actual reset test verification, the reset function of the chip to be tested can be verified based on the randomly generated reset effective duration, so as to correspond to the test such as when the reset effective duration is less than T, whether the chip can work normally after reset, or when the reset effective duration is greater than T, whether the chip can work normally after reset, etc.
[0060] In a preferred embodiment of the present invention, in step S22, a corresponding valid reset signal is applied to the chip through a backdoor HDL path.
[0061] Specifically, in this embodiment, different reset modes require different reset signals to cooperate and implement. For example, if the reset signal is valid at a low level, the corresponding reset signal is pulled down through the backdoor HDL path, and the same applies to other situations. Compared with the existing method of operating the reset signal of the design to be tested through the stimulus sequence and the driver, applying the corresponding valid reset signal to the chip through the backdoor HDL path does not require adding any other components, reduces the amount of code, and effectively improves the verification efficiency.
[0062] In a preferred embodiment of the present invention, the environment component ENV includes an agent component Agent, a scoreboard component scoreboard and a universal verification component UVC; then in step S3, the post-reset operation includes:
[0063] Clean up the queue in the monitoring module monitor encapsulated in the agent component Agent, and / or clean up the queue in the scoreboard component scoreboard, and / or re-mount the transaction generator sequence in the universal verification component UVC. These processing processes can be packaged into a complete function for easy reuse.
[0064] The present invention also provides a chip reset function verification system, which applies the above chip reset function verification method, such as Figure 2 and Figure 4 As shown, the chip reset function verification system includes:
[0065] A chip verification environment 1, wherein the chip verification environment 1 includes a pre-configured to-be-triggered event pool 11, a test case base class TC_BASE, at least one new test case TC_NO1 that inherits the test case base class TC_BASE, and multiple environment components ENV;
[0066] The first configuration module 2 is connected to the chip verification environment 1, and is used for the chip verification personnel to create a reset event EVENT and an associated reset operation task manager 12 in the test case base class TC_BASE, and to configure a reset event trigger monitor 13 in the environment component ENV that needs to perform the reset operation, and put the reset event EVENT into the event pool to be triggered 11;
[0067] The second configuration module 3 is connected to the chip verification environment 1, and is used for the chip verification personnel to add a corresponding reset time point in the new test case TC_NO1 when the chip reset function verification is required, so that the new test case calls the corresponding reset operation task manager 12 to perform the reset operation at the reset time point, and calls the event trigger function to trigger the corresponding reset event EVENT in the to-be-triggered event pool 11 after the reset operation is completed;
[0068] The reset event trigger monitor 13 is used to continuously monitor the event pool to be triggered 11, and when it is detected that the corresponding reset event EVENT is triggered, it performs a post-reset operation on the corresponding environment component ENV;
[0069] After the post-reset operation is completed, the new test case TC_NO1 generates the corresponding stimulus input to the chip to complete the chip reset function verification.
[0070] In a preferred embodiment of the present invention, the reset operation task manager 12 is configured with three parameters, namely, the reset mode, the minimum reset duration period, and the maximum reset duration period;
[0071] The reset operation task manager 12 includes:
[0072] The duration generating module 121 is used to generate the reset effective duration according to the minimum value of the reset duration period and the maximum value of the reset duration period;
[0073] The reset control module 122 is connected to the duration generation module 121, and is used to apply a corresponding effective reset signal to the chip according to the reset mode and maintain the reset effective duration, and then call the event trigger function to trigger the corresponding reset event EVENT in the event pool 11 to be triggered.
[0074] In a preferred embodiment of the present invention, in the reset control module 122, a corresponding valid reset signal is applied to the chip through a backdoor HDL path.
[0075] In a preferred embodiment of the present invention, in the duration generation module 121, the reset effective duration is randomly generated with the minimum value of the reset duration period as the lower limit and the maximum value of the reset duration period as the upper limit.
[0076] In a preferred embodiment of the present invention, the environment component ENV includes an agent component Agent, a scoreboard component scoreboard and a universal verification component UVC; then in step S3, the post-reset operation includes:
[0077] Clean up the queue in the monitoring module monitor encapsulated in the agent component Agent, and / or clean up the queue in the scoreboard component scoreboard, and / or re-mount the transaction generator sequence in the universal verification component UVC. These processing processes can be packaged into a complete function for easy reuse.
[0078] The above description is only a preferred embodiment of the present invention, and does not limit the implementation mode and protection scope of the present invention. For those skilled in the art, it should be aware that all solutions obtained by equivalent substitutions and obvious changes made using the contents of this specification and illustrations should be included in the protection scope of the present invention.
Claims
1. A chip reset function verification method, characterized in that: A pool of events to be triggered is preconfigured in a chip verification environment; the chip reset function verification method includes: Step S1, creating a reset event and an associated reset operation task manager in a test case base class in the chip verification environment, and configuring a reset event trigger monitor in an environment component that needs to perform a reset operation, and placing the reset event into the event pool to be triggered; Step S2, when the new test case inheriting the test case base class in the chip verification environment needs to verify the chip reset function, the corresponding reset operation task manager is called according to the preset reset time point to perform the reset operation, and after the reset operation is completed, the event trigger function is called to trigger the corresponding reset event in the event pool to be triggered; Step S3, the reset event triggering monitor continuously monitors the event pool to be triggered, and performs a post-reset operation on the corresponding environment component when detecting that the corresponding reset event is triggered; Step S4, after the post-reset operation is completed, the new test case generates a corresponding stimulus input into the chip to complete the chip reset function verification.
2. The chip reset function verification method according to claim 1, characterized in that: The reset operation task manager is configured with three parameters, namely, reset mode, minimum reset duration period and maximum reset duration period; Then in step S2, the process of the reset operation task manager performing the reset operation includes: Step S21, generating a reset effective duration according to the minimum reset duration period and the maximum reset duration period; Step S22, applying a corresponding effective reset signal to the chip according to the reset mode, and maintaining the reset effective time, and then calling an event triggering function to trigger the corresponding reset event in the event pool to be triggered.
3. The chip reset function verification method according to claim 2, characterized in that: In the step S22, the corresponding valid reset signal is applied to the chip through a backdoor HDL path.
4. The chip reset function verification method according to claim 2, characterized in that: In the step S21, the reset effective time length is randomly generated with the minimum value of the reset duration period as the lower limit and the maximum value of the reset duration period as the upper limit.
5. The chip reset function verification method according to claim 1, characterized in that: The environment component includes an agent component, a scoreboard component and a general verification component; then in step S3, the post-reset operation includes: The queue in the monitoring module encapsulated in the proxy component is cleared, and / or the queue in the scoreboard component is cleared, and / or the transaction generator in the universal verification component is remounted.
6. A chip reset function verification system, characterized in that: The chip reset function verification method according to any one of claims 1 to 5 is applied, and the chip reset function verification system comprises: A chip verification environment, wherein the chip verification environment includes a pre-configured event pool to be triggered, a test case base class, at least one new test case that inherits the test case base class, and a plurality of environment components; A first configuration module, connected to the chip verification environment, is used for a chip verification personnel to create a reset event and an associated reset operation task manager in the test case base class, and to configure a reset event trigger monitor in an environment component that needs to perform a reset operation, and to place the reset event into the event pool to be triggered; A second configuration module is connected to the chip verification environment, and is used for the chip verification personnel to add a corresponding reset time point in the new test case when the new test case needs to verify the chip reset function, so that the new test case calls the corresponding reset operation task manager to perform a reset operation at the reset time point, and calls the event trigger function to trigger the corresponding reset event in the event pool to be triggered after the reset operation is completed; The reset event trigger monitor is used to continuously monitor the event pool to be triggered, and when it is detected that the corresponding reset event is triggered, perform a post-reset operation on the corresponding environment component; After the post-reset operation is completed, the new test case generates a corresponding stimulus input into the chip to complete the chip reset function verification.
7. The chip reset function verification system according to claim 6, characterized in that: The reset operation task manager is configured with three parameters, namely, reset mode, minimum reset duration period and maximum reset duration period; Then the reset operation task manager includes: A duration generation module, used to generate a reset effective duration according to the minimum reset duration period and the maximum reset duration period; A reset control module, connected to the duration generation module, is used to apply a corresponding effective reset signal to the chip according to the reset method and maintain the reset effective duration, and then call an event trigger function to trigger the corresponding reset event in the event pool to be triggered.
8. The chip reset function verification system according to claim 7, characterized in that: In the reset control module, the corresponding valid reset signal is applied to the chip through a backdoor HDL path.
9. The chip reset function verification system according to claim 7, characterized in that: In the duration generation module, the reset effective duration is randomly generated with the minimum value of the reset duration period as the lower limit and the maximum value of the reset duration period as the upper limit.
10. The chip reset function verification system according to claim 6, characterized in that: The environment component includes an agent component, a scoreboard component and a general verification component; the post-reset operation includes: The queue in the monitoring module encapsulated in the proxy component is cleared, and / or the queue in the scoreboard component is cleared, and / or the transaction generator in the universal verification component is remounted.
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