Model generation method, simulation method, device, electronic device and storage medium

Abstract

The present application discloses a model generation method, simulation method, device, electronic device and storage medium, belonging to the field of simulation technology, including: obtaining first sample data of a high electron mobility transistor, and a drain current label corresponding to the first sample data; wherein the first sample data includes a sample gate-source voltage value, a sample drain-source voltage value, a sample junction temperature value, a sample first trap time value and a sample second trap time value; determining a current loss value based on a predicted drain current and a drain current label output by a first neural network according to the first sample data; adjusting the parameters of the first neural network based on the current loss value to obtain a target simulation model. The ability to construct training samples based on measured data of high electron mobility transistors at multiple junction temperatures and trap time values ​​to train a dynamic field effect transistor model containing a neural network is helpful to improve the accuracy of the target simulation model established for high electron mobility transistors.

Description

Technical Field

[0001] The present application belongs to the field of simulation technology, and specifically relates to a model generation method, a simulation method, a device, an electronic device and a storage medium. Background Art

[0002] With the rapid development of applications such as radio frequency (RF / mm) and millimeter wave (mm-wave), the demand for high-performance power amplifiers is growing. High electron mobility transistors (HEMTs) have become the preferred technology for these applications due to their excellent power handling capabilities and frequency response characteristics. Accurate modeling of HEMTs is critical to ensuring the performance of power amplifier designs.

[0003] In the related art, the high electron mobility transistor model is mainly based on the empirical method of physical formulas and empirical formulas, which describes the component characteristics of the high electron mobility transistor through physical formulas and empirical formulas to obtain a formula model that can describe the output of the high electron mobility transistor according to its input.

[0004] However, the high electron mobility transistor model established in the above manner has limitations in predicting the performance of the device under extreme conditions. For example, it cannot accurately describe the output performance of the device under the influence of thermal effects, resulting in poor accuracy of the established high electron mobility transistor model. Summary of the invention

[0005] The purpose of the embodiments of the present application is to provide a model generation method, a simulation method, an apparatus, an electronic device and a storage medium, which can solve the problem of poor accuracy of the high electron mobility transistor model established in the related art.

[0006] In a first aspect, an embodiment of the present application provides a model generation method, the method comprising:

[0007] Acquire first sample data of a high electron mobility transistor and a drain current label corresponding to the first sample data; wherein the first sample data includes a sample gate-source voltage value, a sample drain-source voltage value, a sample junction temperature value, a sample first trap time value, and a sample second trap time value;

[0008] Inputting the first sample data into a first neural network of an initial dynamic field effect transistor model to obtain a predicted drain current output by the first neural network;

[0009] determining a current loss value based on the predicted drain current and the drain current signature;

[0010] The parameters of the first neural network are adjusted based on the current loss value to obtain a second neural network, and then a target simulation model including the second neural network is obtained; wherein the target simulation model is used to simulate the target junction temperature value, the target first trap time value and the target second trap time value of the high electron mobility transistor according to the input target gate-source voltage value and the target drain-source voltage value, and simulate the target drain current of the high electron mobility transistor based on the target gate-source voltage value, the target drain-source voltage value, the target junction temperature value, the target first trap time value and the target second trap time value.

[0011] Optionally, the target simulation model also includes a first capture emission module for outputting a target first trap time value according to the target gate-source voltage value, and a second capture emission module for outputting a target second trap time value according to the target drain-source voltage value, and the second neural network is used to output the target drain current according to the input target gate-source voltage value, target drain-source voltage value, target junction temperature value, target first trap time value and target second trap time value.

[0012] Optionally, the first sample data also includes a sample gate-source voltage average and a sample drain-source voltage average, the target simulation model also includes a first average module for outputting a target gate-source voltage average according to the target gate-source voltage value, and a second average module for outputting a target drain-source voltage average according to the target drain-source voltage value, and the second neural network is also used to output a target drain current based on the input target gate-source voltage value, target drain-source voltage value, target junction temperature value, target gate-source voltage average and target drain-source voltage average.

[0013] Optionally, the drain current label includes a first drain current sequence determined based on nonlinear characteristics of actual measurement data of the high electron mobility transistor, a second drain current sequence determined based on a static current-voltage relationship of the actual measurement data, and a third drain current sequence determined based on a scattering parameter of the actual measurement data, and determining the current loss value based on the predicted drain current and the drain current label includes:

[0014] calculating a first loss value based on the first drain current sequence and a predicted drain current corresponding to the first drain current sequence;

[0015] calculating a second loss value based on the second drain current sequence and a predicted drain current corresponding to the second drain current sequence;

[0016] Calculating a third loss value based on the third drain current sequence and a predicted drain current corresponding to the third drain current sequence;

[0017] The current loss value is determined based on the first loss value, the second loss value, and the third loss value.

[0018] Optionally, the method further comprises:

[0019] Acquire second sample data and a gate charge label corresponding to the second sample data; wherein the second sample data includes a sample gate-source voltage value and a sample drain-source bias voltage value;

[0020] Inputting the second sample data into a third neural network of the initial dynamic field effect transistor model to obtain a first gate charge value output by the third neural network;

[0021] determining a charge loss value based on the first gate charge value and the gate charge signature;

[0022] The parameters of the third neural network are adjusted based on the charge loss value to obtain a fourth neural network, and then a target simulation model including the second neural network and the fourth neural network model is obtained; wherein the target simulation model is also used to simulate the target gate charge value of the high electron mobility transistor according to the input target gate-source voltage value and target drain-source voltage value.

[0023] Optionally, the gate charge tag includes a first parasitic capacitance value and a second parasitic capacitance value, and determining the charge loss value based on the first gate charge value and the gate charge tag includes:

[0024] Obtaining a first partial derivative of the first gate charge value with respect to a sample gate-source voltage value in the second sample data, and a second partial derivative of the first gate charge value with respect to a sample drain-source bias voltage value in the second sample data;

[0025] The charge loss value is calculated according to a first difference between the first partial derivative and the first parasitic capacitance value, and a second difference between the second partial derivative and the second parasitic capacitance value.

[0026] Optionally, the third neural network includes a charge prediction network and a companion neural network corresponding to the charge prediction network, and obtaining a first partial derivative of the first gate charge value with respect to a sample gate-source voltage value in the second sample data, and a second partial derivative of the first gate charge value with respect to a sample drain-source bias voltage value in the second sample data includes:

[0027] The second sample data is input into the charge prediction network to obtain a first gate charge value output by the charge prediction network, a first partial derivative of the first gate charge value output by the accompanying neural network with respect to a sample gate-source voltage value in the second sample data, and a second partial derivative of the first gate charge value with respect to a sample drain-source bias voltage value in the second sample data.

[0028] In a second aspect, an embodiment of the present application provides a simulation method, the method comprising:

[0029] Obtaining a target gate-source voltage value and a target drain-source voltage value;

[0030] The target gate-source voltage value and the target drain-source voltage value are input into a target simulation model to obtain a target drain current output by the target simulation model to simulate a high electron mobility transistor; wherein the target simulation model is obtained based on the model generation method of the first aspect.

[0031] In a third aspect, an embodiment of the present application provides a model generation device, the device comprising:

[0032] A first acquisition module, used to acquire first sample data of a high electron mobility transistor and a drain current label corresponding to the first sample data; wherein the first sample data includes a sample gate-source voltage value, a sample drain-source voltage value, a sample junction temperature value, a sample first trap time value, and a sample second trap time value;

[0033] A first input module, used for inputting the first sample data into a first neural network of an initial dynamic field effect transistor model to obtain a predicted drain current output by the first neural network;

[0034] a current loss module, configured to determine a current loss value based on the predicted drain current and the drain current tag;

[0035] A first training module is used to adjust the parameters of the first neural network based on the current loss value to obtain a second neural network, and then obtain a target simulation model including the second neural network; wherein the target simulation model is used to simulate the target junction temperature value, the target first trap time value and the target second trap time value of the high electron mobility transistor according to the input target gate-source voltage value and the target drain-source voltage value, and simulate the target drain current of the high electron mobility transistor based on the target gate-source voltage value, the target drain-source voltage value, the target junction temperature value, the target first trap time value and the target second trap time value.

[0036] Optionally, the target simulation model also includes a first capture emission module for outputting a target first trap time value according to the target gate-source voltage value, and a second capture emission module for outputting a target second trap time value according to the target drain-source voltage value, and the second neural network is used to output the target drain current according to the input target gate-source voltage value, target drain-source voltage value, target junction temperature value, target first trap time value and target second trap time value.

[0037] Optionally, the first sample data also includes a sample gate-source voltage average and a sample drain-source voltage average, the target simulation model also includes a first average module for outputting a target gate-source voltage average according to the target gate-source voltage value, and a second average module for outputting a target drain-source voltage average according to the target drain-source voltage value, and the second neural network is also used to output a target drain current based on the input target gate-source voltage value, target drain-source voltage value, target junction temperature value, target gate-source voltage average and target drain-source voltage average.

[0038] Optionally, the drain current label includes a first drain current sequence determined based on nonlinear characteristics of actual measurement data of the high electron mobility transistor, a second drain current sequence determined based on a static current-voltage relationship of the actual measurement data, and a third drain current sequence determined based on a scattering parameter of the actual measurement data, and the current loss module includes:

[0039] A first loss calculation submodule, configured to calculate a first loss value based on the first drain current sequence and a predicted drain current corresponding to the first drain current sequence;

[0040] A first loss calculation submodule, configured to calculate a second loss value based on the second drain current sequence and a predicted drain current corresponding to the second drain current sequence;

[0041] A first loss calculation submodule, configured to calculate a third loss value based on the third drain current sequence and a predicted drain current corresponding to the third drain current sequence;

[0042] The current loss value calculation submodule is used to determine the current loss value based on the first loss value, the second loss value and the third loss value.

[0043] Optionally, the device further comprises:

[0044] A second acquisition module, used to acquire second sample data and a gate charge label corresponding to the second sample data; wherein the second sample data includes a sample gate-source voltage value and a sample drain-source bias voltage value;

[0045] A second input module, used for inputting the second sample data into a third neural network of the initial dynamic field effect transistor model to obtain a first gate charge value output by the third neural network;

[0046] a charge loss module, configured to determine a charge loss value based on the first gate charge value and the gate charge tag;

[0047] The second training module is used to adjust the parameters of the third neural network based on the charge loss value to obtain a fourth neural network, and then obtain a target simulation model including the second neural network and the fourth neural network model; wherein the target simulation model is also used to simulate the target gate charge value of the high electron mobility transistor according to the input target gate-source voltage value and target drain-source voltage value.

[0048] Optionally, the gate charge tag includes a first parasitic capacitance value and a second parasitic capacitance value, and the charge loss module includes:

[0049] A partial derivative submodule, configured to obtain a first partial derivative of the first gate charge value with respect to a sample gate-source voltage value in the second sample data, and a second partial derivative of the first gate charge value with respect to a sample drain-source bias voltage value in the second sample data;

[0050] The charge loss value calculation submodule is used to calculate the charge loss value according to a first difference between the first partial derivative and the first parasitic capacitance value, and a second difference between the second partial derivative and the second parasitic capacitance value.

[0051] Optionally, the third neural network includes a charge prediction network and a companion neural network corresponding to the charge prediction network, and the partial derivative submodule is further used to input the second sample data into the charge prediction network to obtain a first gate charge value output by the charge prediction network, as well as a first partial derivative of the first gate charge value output by the companion neural network with respect to a sample gate-source voltage value in the second sample data, and a second partial derivative of the first gate charge value with respect to a sample drain-source bias voltage value in the second sample data.

[0052] In a fourth aspect, an embodiment of the present application provides a simulation device, the device comprising:

[0053] A target acquisition module, used to acquire a target gate-source voltage value and a target drain-source voltage value;

[0054] A target input module is used to input the target gate-source voltage value and the target drain-source voltage value into a target simulation model to obtain a target drain current output by the target simulation model to simulate a high electron mobility transistor; wherein the target simulation model is obtained based on the model generation method of the first aspect.

[0055] In a fifth aspect, an embodiment of the present application provides an electronic device, comprising a model generation device or a simulation device as described above, for implementing the method of the first aspect or the second aspect as described above.

[0056] In a sixth aspect, an embodiment of the present application provides a readable storage medium, on which a program or instruction is stored, and when the program or instruction is executed by a processor, the method of the first aspect or the second aspect above is implemented.

[0057] In an embodiment of the present application, a model generation method is provided, including: obtaining first sample data of a high electron mobility transistor, and a drain current label corresponding to the first sample data; wherein the first sample data includes a sample gate-source voltage value, a sample drain-source voltage value, a sample junction temperature value, a sample first trap time value, and a sample second trap time value; inputting the first sample data into a first neural network of an initial dynamic field effect transistor model to obtain a predicted drain current output by the first neural network; determining a current loss value based on the predicted drain current and the drain current label; adjusting the parameters of the first neural network based on the current loss value to obtain a second neural network, and then obtaining a target simulation model including the second neural network; wherein the target simulation model is used to simulate a target junction temperature value, a target first trap time value, and a target second trap time value of the high electron mobility transistor according to the input target gate-source voltage value and target drain-source voltage value, and simulate a target drain current of the high electron mobility transistor based on the target gate-source voltage value, the target drain-source voltage value, the target junction temperature value, the target first trap time value, and the target second trap time value. It is possible to construct training samples based on measured data of high electron mobility transistors at various junction temperatures and trap time values, and to train a dynamic field effect transistor model including a neural network based on these training samples, thereby obtaining a target simulation model that can accurately describe the dynamic output characteristics of the high electron mobility transistor at different temperatures, which helps to improve the accuracy of the target simulation model established for the high electron mobility transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] Figure 1 is a flowchart of the steps of a model generation method provided in an embodiment of the present application;

[0059] Figure 2 is an internal model equivalent circuit diagram provided in an embodiment of the present application;

[0060] Figure 3 is a thermal model equivalent circuit diagram provided in an embodiment of the present application;

[0061] Figure 4 is a flowchart of another model generation method provided in an embodiment of the present application;

[0062] Figure 5 is an equivalent circuit diagram of a first capture and transmit module provided in an embodiment of the present application;

[0063] Figure 6 is an equivalent circuit diagram of a second capture and transmit module provided in an embodiment of the present application;

[0064] Figure 7 is an equivalent circuit diagram of a first averaging module provided in an embodiment of the present application;

[0065] Figure 8 is an equivalent circuit diagram of a second averaging module provided in an embodiment of the present application;

[0066] Fig. 9 is a schematic diagram of a measurement system provided in an embodiment of the present application;

[0067] Fig.10 is a first neural network training schematic diagram provided in an embodiment of the present application;

[0068] Fig.11 is a third neural network training schematic diagram provided in an embodiment of the present application;

[0069] Fig.12 is a flowchart of a simulation method provided by an embodiment of the present application;

[0070] Fig.13 It is a logic block diagram of a model generation device provided in an embodiment of the present application;

[0071] Fig.14 It is a logic block diagram of a simulation device provided in an embodiment of the present application;

[0072] Fig.15 It is a structural schematic diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0073] The following will be combined with the drawings in the embodiments of the present application to clearly describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments in the present application belong to the scope of protection of this application.

[0074] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0075] The model generation method provided in the embodiment of the present application is described in detail below through specific embodiments and their application scenarios in conjunction with the accompanying drawings.

[0076] Reference Figure 1 , Figure 1 A flow chart of the steps of a model generation method provided in an embodiment of the present application is shown as follows: Figure 1 As shown, the specific steps include:

[0077] Step 101, obtaining first sample data of a high electron mobility transistor and a drain current label corresponding to the first sample data; wherein the first sample data includes a sample gate-source voltage value, a sample drain-source voltage value, a sample junction temperature value, a sample first trap time value and a sample second trap time value.

[0078] A high electron mobility transistor (HEMT) is a special type of field effect transistor that has the characteristics of high electron mobility and is usually used in high-frequency and high-power scenarios. In the embodiments of the present application, the high electron mobility transistor may specifically include but is not limited to a gallium nitride high electron mobility transistor (GaN HEMT), a gallium arsenide high electron mobility transistor (GaAs HEMT), a silicon-based gallium nitride high electron mobility transistor (GaN-on-SiC HEMT), and the like.

[0079] In an embodiment of the present application, in order to establish a dynamic field-effect transistor model (Dynamic Field-Effect Transistor Model, DynaFET model) corresponding to a high electron mobility transistor to simulate the high electron mobility transistor, the actual characteristics of the high electron mobility transistor can be measured at different junction temperatures to obtain actual measurement data, and then the first sample data for training the model and the drain current label corresponding to the first sample data are generated according to the actual measurement data. The first sample data may include a sample gate-source voltage value, a sample drain-source voltage value, a sample junction temperature value, a sample first trap time value, and a sample second trap time value. Among them, the first trap time value and the second trap time value can be used to characterize the time variable related to the trap mechanism. Specifically, the first trap time value can represent the influence time of the gate voltage change on the trap state, and the second trap time value can represent the influence time of the drain-source voltage change on the trap state.

[0080] The measurement methods of the above actual measurement data may include but are not limited to DC (dc-IV) and RF (S-parameters) characteristic measurements, large signal measurements using a nonlinear vector network analyzer (NVNA), etc., to fully capture the steady-state, transient, and dynamic characteristics of the high electron mobility transistor.

[0081] Among them, the sample gate-source voltage value (Gate-Source Voltage, Vgs) represents the voltage applied to the gate (Gate, G) of the high electron mobility transistor, the sample drain-source voltage value (Drain-Source Voltage, Vds) represents the voltage of the drain (Drain, D) of the high electron mobility transistor, and the sample junction temperature value (Tj) represents the temperature inside the high electron mobility transistor, for example, it may refer to the temperature at the junction of the transistor (PN junction or hot spot of the device).

[0082] Step 102: input the first sample data into a first neural network of an initial dynamic field effect transistor model to obtain a predicted drain current output by the first neural network.

[0083] The dynamic field effect transistor model is a mathematical model used to describe and predict the behavior of field effect transistors in dynamic working state. The model is designed to capture the nonlinear characteristics and dynamic response of field effect transistors under different voltage, frequency and temperature conditions. The dynamic field effect transistor model can contain models that simulate various characteristics of field effect transistors.

[0084] In an embodiment of the present application, an initial dynamic field effect transistor model to be trained can be constructed, and in the initial dynamic field effect transistor model, an internal model (Internal Model) describing the relationship between drain current, gate-source voltage, drain-source voltage, and transistor junction temperature can be included. In the internal model, a first neural network can be set, or the first neural network can be used as the above internal model, and the drain current is predicted through the output of the first neural network. The input of the first neural network can be the first sample data, that is, the sample gate-source voltage value, sample drain-source voltage value, sample junction temperature value, sample first trap time value, and sample second trap time value of the high electron mobility transistor at a certain moment, so as to predict the drain current of the high electron mobility transistor under the current conditions through the first neural network.

[0085] The first neural network may include but is not limited to a Multi-Layer Perceptron (MLP), a Convolutional Neural Network (CNN), a Long Short-Term Memory Network (LSTM), a Radial Basis Function Network (RBF), etc., and is not specifically limited in the embodiments of the present application.

[0086] Step 103: determining a current loss value based on the predicted drain current and the drain current label.

[0087] In an embodiment of the present application, the current loss value corresponding to the first neural network can be determined based on the predicted drain current output by the first neural network based on the first sample data, and the drain current label corresponding to the first sample data, that is, the actual measured value of the drain current.

[0088] Specifically, the loss function that can be used to determine the above-mentioned current loss value includes but is not limited to mean square error (MSE), root mean square error (RMSE), mean absolute error (MAE), etc., and the embodiments of the present application do not make specific limitations.

[0089] Step 104, adjusting the parameters of the first neural network based on the current loss value to obtain a second neural network, and further obtaining a target simulation model including the second neural network; wherein the target simulation model is used to simulate the target junction temperature value, the target first trap time value and the target second trap time value of the high electron mobility transistor according to the input target gate-source voltage value and the target drain-source voltage value, and simulate the target drain current of the high electron mobility transistor based on the target gate-source voltage value, the target drain-source voltage value, the target junction temperature value, the target first trap time value and the target second trap time value.

[0090] In the embodiment of the present application, the parameters of the first neural network can be adjusted according to the current loss value until the training cutoff condition is reached to obtain the second neural network, and then obtain the target simulation model composed of the second neural network.

[0091] Specifically, the back propagation algorithm can be used to calculate the gradient of the current loss value relative to the parameters (such as weights and biases) of the first neural network, and then the calculated gradient is used to update the parameters of the first neural network. The specific update method may include but is not limited to Stochastic Gradient Descent (SGD), Adam Optimizer, etc., and the embodiments of the present application are not specifically limited.

[0092] It should be noted that, in addition to including a second neural network that can simulate the target drain current of the high electron mobility transistor based on the target gate-source voltage value, the target drain-source voltage value, the target junction temperature value, the target first trap time value and the target second trap time value, the target simulation model can also include a thermal equivalent circuit model that can simulate the target junction temperature value of the high electron mobility transistor according to the input target gate-source voltage value and the target drain-source voltage value, and a capture emission module that can simulate the target first trap time value and the target second trap time value of the high electron mobility transistor according to the input target gate-source voltage value and the target drain-source voltage value.

[0093] In addition, the target simulation model may also include other models that simulate the circuit characteristics of high electron mobility transistors, such as sub-circuit models for simulating dynamic charge capture and emission, parasitic inductance models (Lg, Ld, Ls) for simulating gate, drain and source, parasitic capacitance models (Cgsman, Cgdman, Cdsman), etc., which are not specifically limited in the embodiments of the present application.

[0094] Exemplarily, an equivalent circuit diagram of a target simulation model may include an internal model and a thermal model.

[0095] Reference Figure 2 , Figure 2 An internal model equivalent circuit diagram provided by an embodiment of the present application is shown. Figure 2 As shown, the internal model equivalent circuit can simulate the relationship between the gate (Gate), source (Source), drain (Drain), gate-source voltage (Vgs), gate current (IG), gate charge (QG), source-drain voltage (Vds), drain current (ID), and drain charge (QD) in a high electron mobility transistor. In the target simulation model of the embodiment of the present application, the drain current is simulated and output by the second neural network.

[0096] Reference Figure 3 , Figure 3 A thermal model equivalent circuit diagram provided by an embodiment of the present application is shown. Figure 3 As shown in FIG. 1 , the thermal model equivalent circuit diagram is used to simulate the relationship between the junction temperature (Tj), ambient temperature (T0), thermal resistance (Rth), thermal capacitance (Cth), and electrothermal power (I(t)V(t)) in a high electron mobility transistor. The electrothermal power can be determined based on the target gate-source voltage value, the target drain-source voltage value, and the target drain current.

[0097] In summary, an embodiment of the present application provides a model generation method, including obtaining first sample data of a high electron mobility transistor, and a drain current label, a sample first trap time value, and a sample second trap time value corresponding to the first sample data; wherein the first sample data includes a sample gate-source voltage value, a sample drain-source voltage value, and a sample junction temperature value; inputting the first sample data into a first neural network of an initial dynamic field effect transistor model to obtain a predicted drain current output by the first neural network; determining a current loss value based on the predicted drain current and the drain current label; adjusting the parameters of the first neural network based on the current loss value to obtain a second neural network, and then obtaining a target simulation model including the second neural network; wherein the target simulation model is used to simulate a target junction temperature value, a target first trap time value, and a target second trap time value of a high electron mobility transistor according to the input target gate-source voltage value and a target drain-source voltage value, and to simulate a target drain current of the high electron mobility transistor based on the target gate-source voltage value, the target drain-source voltage value, the target junction temperature value, the target first trap time value, and the target second trap time value. It is possible to construct training samples based on measured data of high electron mobility transistors at various junction temperatures and trap time values, and to train a dynamic field effect transistor model including a neural network based on these training samples, thereby obtaining a target simulation model that can accurately describe the dynamic output characteristics of the high electron mobility transistor at different temperatures, which helps to improve the accuracy of the target simulation model established for the high electron mobility transistor.

[0098] like Figure 4 As shown, Figure 4A flowchart of another model generation method provided in an embodiment of the present application, the method may include:

[0099] Step 201, obtaining first sample data of a high electron mobility transistor and a drain current label corresponding to the first sample data; wherein the first sample data includes a sample gate-source voltage value, a sample drain-source voltage value, a sample junction temperature value, a sample first trap time value and a sample second trap time value.

[0100] This step can refer to step 101 and will not be described in detail in this embodiment of the present application.

[0101] Optionally, the target simulation model also includes a first capture emission module for outputting a target first trap time value according to the target gate-source voltage value, and a second capture emission module for outputting a target second trap time value according to the target drain-source voltage value, and the second neural network is used to output the target drain current according to the input target gate-source voltage value, target drain-source voltage value, target junction temperature value, target first trap time value and target second trap time value.

[0102] The first trap time value and the second trap time value can be used to characterize time variables related to the trap mechanism. Specifically, the first trap time value can represent the influence time of gate voltage change on the trap state, and the second trap time value can represent the influence time of drain-source voltage change on the trap state.

[0103] In an embodiment of the present application, the actual measurement data may include the first trap time value and the second trap time value of the measured high electron mobility transistor at multiple junction temperatures, so that the first sample data may include not only the sample gate-source voltage value, the sample drain-source voltage value, and the sample junction temperature value, but also the sample gate-source voltage value, the sample drain-source voltage value, and the sample junction temperature value, and the corresponding sample first trap time value and sample second trap time value.

[0104] Thus, the second neural network trained with the first sample data can output the corresponding target drain current according to the target gate-source voltage value, the target drain-source voltage value, the target junction temperature value, the target first trap time value and the target second trap time value. In order to enable the second neural network in the target simulation model to run smoothly, a first capture emission module for outputting the target first trap time value according to the target gate-source voltage value and a second capture emission module for outputting the target second trap time value according to the target drain-source voltage value can also be provided in the target simulation model.

[0105] Reference Figure 5 , Figure 5 FIG. 4 shows an equivalent circuit diagram of a first capture and transmit module provided in an embodiment of the present application. Figure 5As shown, Vgs represents the gate-source voltage, and the resistors R1_capt and R1_emit cooperate with the capacitor C1_emit to simulate the dynamic process of charge capture (capt) and release (emit) under the influence of the gate-source voltage. Φ1 describes the time variable related to the trap mechanism of this capture-emission process, that is, when the target gate-source voltage value is input, the corresponding target first trap time value can be output through Φ1.

[0106] Reference Figure 6 , Figure 6 FIG. 4 shows an equivalent circuit diagram of a second capture and transmit module provided in an embodiment of the present application. Figure 6 As shown, Vds represents the drain-source voltage, and the resistors R2_capt and R2_emit cooperate with the capacitor C2_emit to simulate the dynamic process of charge capture (capt) and release (emit) under the influence of the drain-source voltage. Φ2 describes the time variable related to the trap mechanism of this capture-emission process, that is, when the target drain-source voltage value is input, the corresponding target second trap time value can be output through Φ2.

[0107] By including in the first sample data a sample first trap time value and a sample second trap time value obtained by actually measuring a high electron mobility transistor and training the first neural network, the accuracy of the trained second neural network model in simulating the drain current of the high electron mobility transistor can be improved. By setting a first capture emission module and a second capture emission module in the target simulation model, a target first trap time value and a target second trap time value are provided to the second neural network therein, which helps to improve the accuracy of simulating the high electron mobility transistor through the target simulation model.

[0108] Optionally, the first sample data also includes a sample gate-source voltage average and a sample drain-source voltage average, the target simulation model also includes a first average module for outputting a target gate-source voltage average according to the target gate-source voltage value, and a second average module for outputting a target drain-source voltage average according to the target drain-source voltage value, and the second neural network is also used to output a target drain current based on the input target gate-source voltage value, target drain-source voltage value, target junction temperature value, target gate-source voltage average and target drain-source voltage average.

[0109] The sample gate-source voltage average value represents the average value of the gate-source voltage of the high electron mobility transistor in a period of time, and the sample drain-source voltage average value represents the average value of the drain-source voltage of the high electron mobility transistor in a period of time. Since the actual measurement data may include the actual measurement data of the high electron mobility transistor at multiple consecutive times, for the time Tm, the average values ​​of the sample gate-source voltage and the average value of the sample drain-source voltage at the time Tm, Tm-1…Tm-n may be calculated to obtain the sample gate-source voltage average value and the sample drain-source voltage average value at the time Tm.

[0110] Thus, the first sample data including the sample gate-source voltage value, the sample drain-source voltage value, the sample junction temperature value, the sample gate-source voltage average value and the sample drain-source voltage average value can be used to train the first neural network to obtain the second neural network, so that the second neural network can output the corresponding target drain current according to the target gate-source voltage value, the target drain-source voltage value, the target junction temperature value, the target gate-source voltage average value and the target drain-source voltage average value. In order to enable the second neural network in the target simulation model to run smoothly, a first average module for outputting the target gate-source voltage average value according to the target gate-source voltage value, and a second average module for outputting the target drain-source voltage average value according to the target drain-source voltage value can also be provided in the target simulation model.

[0111] Reference Figure 7 , Figure 7 An equivalent circuit diagram of a first average module provided in an embodiment of the present application is shown, such as Figure 7 As shown, R1_LPF represents the first low-pass filter resistor, C1_LPFC represents the first filter capacitor, and the circuit can simulate the average value of the gate-source voltage according to the input gate-source voltage (Vgs), that is, according to the input target gate-source voltage, simulate the corresponding target gate-source voltage average value.

[0112] Reference Figure 8 , Figure 8 An equivalent circuit diagram of a second average module provided in an embodiment of the present application is shown, such as Figure 8 As shown, R2_LPF represents the second low-pass filter resistor, C2_LPFC represents the second filter capacitor, and the circuit can simulate the average value of the drain-source voltage according to the input drain-source voltage (Vds), that is, according to the input target drain-source voltage, simulate the corresponding target drain-source voltage average.

[0113] It should be noted that the above-mentioned first sample data may also include sample gate-source voltage value, sample drain-source voltage value, sample junction temperature value, sample first trap time value, sample second trap time value, sample gate-source voltage mean value and sample drain-source voltage mean value, so that the trained second neural network model can output the target drain current according to the input target gate-source voltage value, target drain-source voltage value, target junction temperature value, target first trap time value, target second trap time value, target gate-source voltage mean value and target drain-source voltage mean value. In this case, the target simulation model can be provided with a first capture-and-transmit module, a second capture-and-transmit module, a first mean value module and a second mean value module at the same time. Among them, the target first trap time value, the target second trap time value, the target gate-source voltage mean value and the target drain-source voltage mean value are auxiliary variables, which can provide additional information about the operating state of the device. These auxiliary variables can help the model to more accurately predict the large signal behavior of the device under different load and temperature conditions.

[0114] By including in the first sample data the sample gate-source voltage average and the sample drain-source voltage average obtained by actual measurement of the high electron mobility transistor and training the first neural network, the accuracy of the trained second neural network model in simulating the drain current of the high electron mobility transistor can be improved, and by setting the first average module and the second average module in the target simulation model, the target gate-source voltage average and the target drain-source voltage average are provided to the second neural network therein, which helps to improve the accuracy of simulating the high electron mobility transistor through the target simulation model.

[0115] Step 202: input the first sample data into a first neural network of an initial dynamic field effect transistor model to obtain a predicted drain current output by the first neural network.

[0116] This step can be referred to as step 102, and will not be described in detail in this embodiment of the present application.

[0117] Step 203: determining a current loss value based on the predicted drain current and the drain current label.

[0118] This step can refer to step 103, and will not be described in detail in this embodiment of the present application.

[0119] Optionally, the drain current label includes a first drain current sequence determined based on the nonlinear characteristics of actual measurement data of the high electron mobility transistor, a second drain current sequence determined based on a static current-voltage relationship of the actual measurement data, and a third drain current sequence determined based on scattering parameters of the actual measurement data.

[0120] In the embodiments of the present application, the high electron mobility transistor can be actually measured by various methods or devices to obtain rich actual measurement data. The actual measurement data may include but are not limited to the nonlinear characteristics, static current-voltage relationship, scattering parameters, large signal NVNA characteristics, etc. of the high electron mobility transistor, which are not specifically limited in the embodiments of the present application.

[0121] For example, comprehensive DC (dc-IV) and RF (S-parameters) characteristic measurements can be performed on the target high electron mobility transistor. Among them, the DC characteristics include the static current-voltage (IV) characteristics of the transistor, which can be expressed as a curve graph showing the drain current at different gate-source voltages and drain-source voltages. These data can be used to extract the threshold voltage, maximum drain current, and static characteristics of the transistor under different bias conditions; RF S characteristics measure the S parameters of the transistor, that is, scattering parameters, which describe the input and output behavior of the transistor under RF signals. S parameters can include S11 (reflection coefficient), S21 (gain or transmission coefficient), S12 (reverse isolation) and S22 (output reflection coefficient). These parameters can be measured at different frequencies, usually expressed in complex form, and can be plotted on a Smith chart to clarify the matching network design and frequency response of the transistor.

[0122] It should be noted that the above-mentioned target high electron mobility transistor can be flexibly set according to actual simulation requirements. For example, the target high electron mobility transistor can be a silicon-based gallium nitride high electron mobility transistor with a gate length of 150nm and a gate width of 8×50µm.

[0123] For example, a nonlinear vector network analyzer can be used to perform large signal measurements on a target high electron mobility transistor at a frequency of 100MHz to capture the transient response and dynamic effects of the transistor, and measure the response under different input power levels (e.g., from -17dBm to 18.5dBm) and different load impedance conditions. The above measurement process can be achieved through active load traction technology. The measured data can be used to analyze the nonlinear behavior of the transistor under large signal stimulation, such as thermal effects and charge capture effects.

[0124] Reference Fig. 9 , Fig. 9 A schematic diagram of a measurement system provided in an embodiment of the present application is shown. Fig. 9As shown, the measurement system can be composed of a network analyzer (PNA-X), a 26.5 GHz comb generator (Comb Gen), a splitter (Splitter), a power amplifier (PA), a coupler (Coupler), a 40V / 0.5A bias device, a 100V / 3A bias device, a synchronous bias power supply and a device under test (DUT). Among them, the network analyzer can be used to measure network parameters and provide test signals. The network analyzer can output a 10MHz reference signal (Ref) through the rear panel (Rear Panel) and perform actual measurement operations through the device under test plane (DUT Plane); the comb generator can generate a 26.5GHz signal frequency to test the high-frequency response of the device under test; the distributor is used to distribute the reference signal. The device under test can be a high electron mobility transistor. The above measurement system can achieve high-precision measurement of high electron mobility transistors.

[0125] This scheme introduces neural network technology into the dynamic field effect transistor model, and uses NVNA data that can accurately reflect the large signal characteristics of the transistor during the neural network training process, so that the obtained target simulation model can improve the simulation accuracy under large signal conditions to a certain extent.

[0126] Step 203 may include:

[0127] Sub-step 2031: calculating a first loss value based on the first drain current sequence and a predicted drain current corresponding to the first drain current sequence.

[0128] In an embodiment of the present application, a high electron mobility transistor can be measured by a variety of measurement methods, so that the drain current label corresponding to the first sample data can have data of multiple measurement methods. Specifically, a nonlinear vector network analyzer can be used to measure the nonlinear characteristics to obtain the first drain current of the first sample data, measure the static current-voltage relationship to obtain the second drain current of the first sample data, and measure the scattering parameters to obtain the third drain current of the first sample data. The first drain current corresponding to multiple first sample data can constitute a first drain current sequence, the second drain current corresponding to multiple first sample data can constitute a second drain current sequence, and the third drain current corresponding to multiple first sample data can constitute a third drain current sequence. It should be noted that a first sample data can have only one measurement method label, or can have multiple measurement method labels at the same time, which is not specifically limited in the embodiment of the present application.

[0129] Inputting a continuous first sample data (for example, a plurality of first sample data collected from the high electron mobility transistor from power-on to 10 seconds of operation) into the first neural network can obtain a predicted drain current sequence output by the first neural network. The data at the same point in the predicted drain current sequence, the first drain current sequence, the second drain current sequence, and the third drain current sequence can correspond to the same first sample data. Thus, the first loss value can be calculated based on the first drain current sequence and the predicted drain current corresponding to the first drain current sequence; the second loss value can be calculated based on the second drain current sequence and the predicted drain current corresponding to the second drain current sequence; the third loss value can be calculated based on the third drain current sequence and the predicted drain current corresponding to the third drain current sequence; and then the current loss value can be determined based on the first loss value, the second loss value, and the third loss value.

[0130] Exemplarily, the first loss value L1 can be calculated using the following formula 1:

[0131] Formula 1

[0132] in, is the predicted drain current of the ith data point predicted by the first neural network, is the first drain current corresponding to the ith data point, and N is the total number of data points corresponding to the first drain current during this round of prediction.

[0133] Sub-step 2032: calculating a second loss value based on the second drain current sequence and a predicted drain current corresponding to the second drain current sequence.

[0134] Exemplarily, the second loss value L2 may be calculated using the following formula 2:

[0135] Formula 2

[0136] in, is the predicted drain current of the jth data point predicted by the first neural network, is the second drain current corresponding to the jth data point, and M is the total number of data points corresponding to the second drain current during this round of prediction.

[0137] Sub-step 2033: calculating a third loss value based on the third drain current sequence and a predicted drain current corresponding to the third drain current sequence.

[0138] Exemplarily, the third loss value L3 may be calculated using the following formula 3:

[0139] Formula 3

[0140] in, is the predicted drain current of the kth data point predicted by the first neural network, is the third drain current corresponding to the kth data point, and P is the total number of data points corresponding to the third drain current during this prediction period.

[0141] It should be noted that the above-mentioned first loss value, second loss value, and third loss value can also be calculated using other loss functions, and are not limited to the above-mentioned mean square error loss function, and the embodiments of the present application do not make specific limitations.

[0142] Sub-step 2034, determining the current loss value based on the first loss value, the second loss value and the third loss value.

[0143] In an embodiment of the present application, the current loss value can be calculated based on the first loss value, the second loss value and the third loss value. The calculation method may include but is not limited to average, weighted average, summation, weighted summation, etc., which is not specifically limited in the embodiment of the present application.

[0144] In addition, the weight parameters W1, W2 and W3 corresponding to the first loss value, the second loss value and the third loss value can be adjusted during the training process, so as to balance the loss functions of different types of data and improve the training effect of the model.

[0145] By calculating the first loss value based on the first drain current sequence and the predicted drain current corresponding to the first drain current sequence; calculating the second loss value based on the second drain current sequence and the predicted drain current corresponding to the second drain current sequence; calculating the third loss value based on the third drain current sequence and the predicted drain current corresponding to the third drain current sequence; determining the current loss value based on the first loss value, the second loss value and the third loss value, it is possible to refer to the drain current labels of different transistor characteristics obtained by different measurement methods during the training process, so that the trained target simulation model can accurately simulate the thermal effect and the capture effect, so that the target simulation model can better evaluate the reliability and life of the high electron mobility transistor, and can be applicable to a variety of application scenarios from small signal amplifiers to high power amplifiers, thereby providing the applicability of the model.

[0146] Step 204: Adjust the parameters of the first neural network based on the current loss value to obtain a second neural network.

[0147] This step can be referred to as step 104, and will not be described in detail in this embodiment of the present application.

[0148] Reference Fig.10 , Fig.10 A first neural network training schematic diagram provided in an embodiment of the present application is shown. Fig.10As shown, the input parameters of the first neural network may include a sample gate-source voltage value (Vgs), a sample drain-source voltage value (Vds), a sample junction temperature value Tj, a sample first trap time value Φ1, a sample second trap time value Φ2, a sample gate-source voltage average value and the sample drain-source voltage mean , according to the output predicted drain current Id(t) and the corresponding drain current label The first loss value L1, the second loss value L2 and the third loss value L3 are calculated, and then the weight parameters W1, W2 and W3 corresponding to each loss value are used to perform weighted summation on the first loss value L1, the second loss value L2 and the third loss value L3 to obtain the current loss value (W1L1+W1L1+W1L1), and then the parameters of the first neural network are adjusted according to the current loss value to obtain the second neural network.

[0149] Step 205 , obtaining second sample data and a gate charge label corresponding to the second sample data; wherein the second sample data includes a sample gate-source voltage value and a sample drain-source bias voltage value.

[0150] In the embodiment of the present application, the second sample data and the gate charge label corresponding to the second sample data can also be obtained according to the actual measurement data of the high electron mobility transistor, wherein the second sample data can include a sample gate-source voltage value and a sample drain-source bias voltage value. It should be noted that there can be a one-to-one correspondence between the first sample data and the second sample data, and the sample gate-source voltage values ​​in the corresponding first sample data and the second sample data are the same.

[0151] Step 206: input the second sample data into the third neural network of the initial dynamic field effect transistor model to obtain a first gate charge value output by the third neural network.

[0152] In the internal model of the initial dynamic field effect transistor model, a third neural network can be set to output the first gate charge value through the third neural network. The input of the third neural network can be the second sample data, that is, the sample gate-source voltage value and the sample drain-source bias voltage value of the high electron mobility transistor at a certain moment, so as to predict the gate charge value (QG) of the high electron mobility transistor under the current conditions through the third neural network. Among them, the third neural network can include but is not limited to a multilayer perceptron, a convolutional neural network, a long short-term memory network, a radial basis function network, etc., and the embodiments of the present application are not specifically limited.

[0153] Step 207 : determining a charge loss value based on the first gate charge value and the gate charge tag.

[0154] In the embodiment of the present application, the charge loss value corresponding to the third neural network can be calculated based on the first gate charge value output by the third neural network based on the second sample data and the gate charge label corresponding to the second sample data. Specifically, the loss function that can be used to determine the above charge loss value includes but is not limited to mean square error, root mean square error, mean absolute error, etc., which is not specifically limited in the embodiment of the present application.

[0155] Optionally, the gate charge tag includes a first parasitic capacitance value and a second parasitic capacitance value. Exemplarily, the first parasitic capacitance value can be expressed as ; The second parasitic capacitance value can be expressed as ;in, represents the input admittance under specific bias conditions, represents the reverse output admittance under a specific bias condition, Im represents the imaginary part, and ω represents the oscillation angular frequency. Thus, step 207 may include:

[0156] Sub-step 2071 , obtaining a first partial derivative of the first gate charge value with respect to a sample gate-source voltage value in the second sample data, and a second partial derivative of the first gate charge value with respect to a sample drain-source bias voltage value in the second sample data.

[0157] In the embodiment of the present application, after obtaining the first gate charge value output by the third neural network, the first partial derivative of the first gate charge value with respect to the sample gate-source voltage value in the second sample data can be determined. The first partial derivative can be expressed as:

[0158] ;

[0159] A second partial derivative of the first gate charge value with respect to the sample drain-source bias voltage value in the second sample data may also be determined, and the second partial derivative may be expressed as:

[0160] ;

[0161] Wherein, QG represents the first gate charge value output by the third neural network, Vgs represents the sample gate-source voltage value, Vds represents the sample drain-source bias voltage value, and bias represents the bias condition. The first partial derivative may indicate the sensitivity of the model output to the input gate-source voltage value, and the second partial derivative may indicate the sensitivity of the model output to the input drain-source voltage value.

[0162] Optionally, the third neural network includes a charge prediction network and an adjoint neural network corresponding to the charge prediction network, and sub-step 2071 may be implemented in the following manner:

[0163] The second sample data is input into the charge prediction network to obtain a first gate charge value output by the charge prediction network, a first partial derivative of the first gate charge value output by the accompanying neural network with respect to a sample gate-source voltage value in the second sample data, and a second partial derivative of the first gate charge value with respect to a sample drain-source bias voltage value in the second sample data.

[0164] Reference Fig.11 , Fig.11 A third neural network training schematic diagram provided in an embodiment of the present application is shown. Fig.11 As shown, the third neural network can be composed of a charge prediction network ( Fig.11 The left network) and the accompanying neural network for outputting the first partial derivative and the second partial derivative ( Fig.11 The network on the right side), the companion neural network can directly output the corresponding first partial derivative and second partial derivative according to the input sample gate-source voltage value (Vgs) and sample drain-source bias voltage value (Vds(bias)) of the third neural network.

[0165] By setting up an adjoint neural network, a relatively concise method for calculating partial derivatives is provided, which avoids the computational overhead of global solution and can obtain the required loss value calculation information with only one forward propagation, which helps to improve the efficiency of model training.

[0166] Sub-step 2072, calculating the charge loss value according to a first difference between the first partial derivative and the first parasitic capacitance value, and a second difference between the second partial derivative and the second parasitic capacitance value.

[0167] In an embodiment of the present application, a first difference between a first partial derivative and a first parasitic capacitance value can be calculated, a second difference between a second partial derivative and a second parasitic capacitance value can be calculated, and the first difference and the second difference can be summed, averaged, etc. to obtain a charge loss value.

[0168] For example, Fig.11 As shown, the first partial derivative of the third neural network output and the first parasitic capacitance value in the gate charge label are The difference result, as well as the first partial derivative of the third neural network output and the second parasitic capacitance value in the gate charge label The difference results are summed to obtain the charge loss value EQG, and the parameter W of the third neural network is adjusted according to the charge loss value.

[0169] By obtaining a first partial derivative of a first gate charge value with respect to a sample gate-source voltage value in second sample data, and a second partial derivative of a first gate charge value with respect to a sample drain-source bias voltage value in second sample data; calculating a charge loss value based on a first difference between the first partial derivative and a first parasitic capacitance value, and a second difference between the second partial derivative and a second parasitic capacitance value, the model can calculate the charge loss value using the difference between the partial derivative and the parasitic capacitance as a constraint term, which can more accurately and finely reflect the deviation between the model output and the true value, and help to enhance the training accuracy of the model.

[0170] Step 208, adjusting the parameters of the third neural network based on the charge loss value to obtain a fourth neural network, and then obtaining a target simulation model including the second neural network and the fourth neural network model; wherein the target simulation model is also used to simulate the target gate charge value of the high electron mobility transistor according to the input target gate-source voltage value and target drain-source voltage value.

[0171] In the embodiment of the present application, the parameters of the third neural network can be adjusted according to the charge loss value until the training cutoff condition is reached to obtain the fourth neural network, and then the target simulation model composed of the second neural network and the fourth neural network is obtained, so that the target simulation model can not only accurately simulate the drain current of the high electron mobility transistor, but also accurately simulate the gate charge value of the high electron mobility transistor, which helps to improve the simulation accuracy of the target simulation model for the high electron mobility transistor.

[0172] Specifically, a back propagation algorithm can be used to calculate the gradient of the charge loss value relative to the parameters (such as weights and biases) of the third neural network, and then the calculated gradient is used to update the parameters of the third neural network. The specific update method may include but is not limited to stochastic gradient descent, Adam optimizer, etc., and the embodiments of the present application are not specifically limited.

[0173] It should be noted that during the training process, the model can be verified using independent validation sets, which may include data under different temperatures and bias conditions to evaluate the model's ability to simulate thermal and capture effects. An independent test set can also be used to further evaluate the generalization ability of the model to ensure that the model can accurately predict unseen data. In addition, the model can be further fine-tuned and optimized based on the validation and test results. The fine-tuning optimization may include but is not limited to optimizing at least one of the model's network architecture and the hyperparameters in the model, thereby further improving the target simulation model's ability to simulate the thermal and capture effects of high electron mobility transistors.

[0174] In summary, another model generation method provided by an embodiment of the present application includes obtaining first sample data of a high electron mobility transistor, and a drain current label, a sample first trap time value, and a sample second trap time value corresponding to the first sample data; wherein the first sample data includes a sample gate-source voltage value, a sample drain-source voltage value, and a sample junction temperature value; inputting the first sample data into a first neural network of an initial dynamic field effect transistor model to obtain a predicted drain current output by the first neural network; determining a current loss value based on the predicted drain current and the drain current label; adjusting the parameters of the first neural network based on the current loss value to obtain a second neural network, and then obtaining a target simulation model including the second neural network; wherein the target simulation model is used to simulate a target junction temperature value, a target first trap time value, and a target second trap time value of a high electron mobility transistor according to the input target gate-source voltage value and a target drain-source voltage value, and simulate the target drain current of the high electron mobility transistor based on the target gate-source voltage value, the target drain-source voltage value, the target junction temperature value, the target first trap time value, and the target second trap time value. It is possible to construct training samples based on measured data of high electron mobility transistors at various junction temperatures and trap time values, and to train a dynamic field effect transistor model including a neural network based on these training samples, thereby obtaining a target simulation model that can accurately describe the dynamic output characteristics of the high electron mobility transistor at different temperatures, which helps to improve the accuracy of the target simulation model established for the high electron mobility transistor.

[0175] Reference Fig.12 , Fig.12 A flow chart of the steps of a simulation method provided by an embodiment of the present application is shown as follows: Fig.12 As shown, the specific steps include:

[0176] Step 301, obtaining a target gate-source voltage value and a target drain-source voltage value.

[0177] Step 302, inputting the target gate-source voltage value and the target drain-source voltage value into a target simulation model to obtain a target drain current output by the target simulation model to simulate a high electron mobility transistor; wherein the target simulation model is obtained based on the above-mentioned model generation method.

[0178] Optionally, the parameters input into the target simulation model may further include the ambient temperature, so that the temperature module in the target simulation model outputs a junction temperature value based on the ambient temperature, and inputs the junction temperature value into the second neural network of the target simulation model.

[0179] It should be noted that before using the target simulation model, the companion network in the third neural network can be deleted or retained, which is not specifically limited in the embodiments of the present application.

[0180] In summary, a simulation method provided in an embodiment of the present application can construct training samples based on measured data of a high electron mobility transistor at a variety of junction temperatures and trap time values, and train a dynamic field effect transistor model including a neural network based on these training samples to obtain a target simulation model that can accurately describe the dynamic output characteristics of the high electron mobility transistor at different temperatures. Simulating the high electron mobility transistor through the target simulation model helps to improve the simulation accuracy of the high electron mobility transistor.

[0181] like Fig.13 As shown, Fig.13 A logic block diagram of a model generation device provided in an embodiment of the present application, the model generation device 40 may include:

[0182] A first acquisition module 41 is used to acquire first sample data of a high electron mobility transistor and a drain current label corresponding to the first sample data; wherein the first sample data includes a sample gate-source voltage value, a sample drain-source voltage value, a sample junction temperature value, a sample first trap time value, and a sample second trap time value;

[0183] A first input module 42, configured to input the first sample data into a first neural network of an initial dynamic field effect transistor model to obtain a predicted drain current output by the first neural network;

[0184] A current loss module 43, configured to determine a current loss value based on the predicted drain current and the drain current label;

[0185] The first training module 44 is used to adjust the parameters of the first neural network based on the current loss value to obtain the second neural network, and then obtain a target simulation model including the second neural network; wherein the target simulation model is used to simulate the target junction temperature value, the target first trap time value and the target second trap time value of the high electron mobility transistor according to the input target gate-source voltage value and the target drain-source voltage value, and simulate the target drain current of the high electron mobility transistor based on the target gate-source voltage value, the target drain-source voltage value, the target junction temperature value, the target first trap time value and the target second trap time value.

[0186] Optionally, the target simulation model also includes a first capture emission module for outputting a target first trap time value according to the target gate-source voltage value, and a second capture emission module for outputting a target second trap time value according to the target drain-source voltage value, and the second neural network is used to output the target drain current according to the input target gate-source voltage value, target drain-source voltage value, target junction temperature value, target first trap time value and target second trap time value.

[0187] Optionally, the first sample data also includes a sample gate-source voltage average and a sample drain-source voltage average, the target simulation model also includes a first average module for outputting a target gate-source voltage average according to the target gate-source voltage value, and a second average module for outputting a target drain-source voltage average according to the target drain-source voltage value, and the second neural network is also used to output a target drain current based on the input target gate-source voltage value, target drain-source voltage value, target junction temperature value, target gate-source voltage average and target drain-source voltage average.

[0188] Optionally, the drain current label includes a first drain current sequence determined based on nonlinear characteristics of actual measurement data of the high electron mobility transistor, a second drain current sequence determined based on a static current-voltage relationship of the actual measurement data, and a third drain current sequence determined based on a scattering parameter of the actual measurement data, and the current loss module includes:

[0189] A first loss calculation submodule, configured to calculate a first loss value based on the first drain current sequence and a predicted drain current corresponding to the first drain current sequence;

[0190] A first loss calculation submodule, configured to calculate a second loss value based on the second drain current sequence and a predicted drain current corresponding to the second drain current sequence;

[0191] A first loss calculation submodule, configured to calculate a third loss value based on the third drain current sequence and a predicted drain current corresponding to the third drain current sequence;

[0192] The current loss value calculation submodule is used to determine the current loss value based on the first loss value, the second loss value and the third loss value.

[0193] Optionally, the device further comprises:

[0194] A second acquisition module, used to acquire second sample data and a gate charge label corresponding to the second sample data; wherein the second sample data includes a sample gate-source voltage value and a sample drain-source bias voltage value;

[0195] A second input module, used for inputting the second sample data into a third neural network of the initial dynamic field effect transistor model to obtain a first gate charge value output by the third neural network;

[0196] a charge loss module, configured to determine a charge loss value based on the first gate charge value and the gate charge tag;

[0197] The second training module is used to adjust the parameters of the third neural network based on the charge loss value to obtain a fourth neural network, and then obtain a target simulation model including the second neural network and the fourth neural network model; wherein the target simulation model is also used to simulate the target gate charge value of the high electron mobility transistor according to the input target gate-source voltage value and target drain-source voltage value.

[0198] Optionally, the gate charge tag includes a first parasitic capacitance value and a second parasitic capacitance value, and the charge loss module includes:

[0199] A partial derivative submodule, configured to obtain a first partial derivative of the first gate charge value with respect to a sample gate-source voltage value in the second sample data, and a second partial derivative of the first gate charge value with respect to a sample drain-source bias voltage value in the second sample data;

[0200] The charge loss value calculation submodule is used to calculate the charge loss value according to a first difference between the first partial derivative and the first parasitic capacitance value, and a second difference between the second partial derivative and the second parasitic capacitance value.

[0201] Optionally, the third neural network includes a charge prediction network and a companion neural network corresponding to the charge prediction network, and the partial derivative submodule is further used to input the second sample data into the charge prediction network to obtain a first gate charge value output by the charge prediction network, as well as a first partial derivative of the first gate charge value output by the companion neural network with respect to a sample gate-source voltage value in the second sample data, and a second partial derivative of the first gate charge value with respect to a sample drain-source bias voltage value in the second sample data.

[0202] In summary, a model generation device provided in an embodiment of the present application can construct training samples based on the measured data of high electron mobility transistors at various junction temperatures and trap time values, and train a dynamic field effect transistor model including a neural network based on these training samples to obtain a target simulation model that can accurately describe the dynamic output characteristics of the high electron mobility transistor at different temperatures, which helps to improve the accuracy of the target simulation model established for the high electron mobility transistor.

[0203] like Fig.14 As shown, Fig.14 A logic block diagram of a simulation device provided in an embodiment of the present application, the simulation device 50 may include:

[0204] A target acquisition module 51 is used to acquire a target gate-source voltage value and a target drain-source voltage value;

[0205] The target input module 52 is used to input the target gate-source voltage value and the target drain-source voltage value into a target simulation model to obtain a target drain current output by the target simulation model to simulate a high electron mobility transistor; wherein the target simulation model is obtained based on the above-mentioned model generation method.

[0206] In summary, a simulation device provided in an embodiment of the present application can construct training samples based on measured data of a high electron mobility transistor at a variety of junction temperatures and trap time values, and train a dynamic field effect transistor model including a neural network based on these training samples to obtain a target simulation model that can accurately describe the dynamic output characteristics of the high electron mobility transistor at different temperatures. Simulating the high electron mobility transistor through the target simulation model helps to improve the simulation accuracy of the high electron mobility transistor.

[0207] The model generation device and the simulation device in the embodiment of the present application can be an electronic device, or a component in the electronic device, such as an integrated circuit or a chip. The electronic device can be a terminal, or it can be other devices other than a terminal. Exemplarily, the electronic device can be a GPU BOX, a mobile phone, a tablet computer, a laptop computer, a PDA, a vehicle-mounted electronic device, a mobile Internet device (Mobile Internet Device, MID), an augmented reality (augmented reality, AR) / virtual reality (virtual reality, VR) device, a robot, a wearable device, an ultra-mobile personal computer (ultra-mobile personal computer, UMPC), a netbook or a personal digital assistant (personal digital assistant, PDA), etc., and can also be a server, a network attached storage (Network Attached Storage, NAS), a personal computer (personal computer, PC), a television (television, TV), a teller machine or a self-service machine, etc., which is not specifically limited in the embodiment of the present application.

[0208] The model generation device and the simulation device in the embodiment of the present application may be a device having an operating system. The operating system may be an Android operating system, a Linux operating system, a Windows operating system, etc., or other possible operating systems, which are not specifically limited in the embodiment of the present application.

[0209] The model generation device provided in the embodiment of the present application can achieve Figures 1 to 11 The simulation device provided in the embodiment of the present application can realize each process implemented by the method embodiment of Fig.12To avoid repetition, the various processes implemented by the method embodiment are not described here.

[0210] Alternatively, if Fig.15 As shown, an embodiment of the present application also provides an electronic device M00, including a processor M01 and a memory M02, wherein the memory M02 stores programs or instructions that can be executed on the processor M01, and when the program or instructions are executed by the processor M01, the various steps of the above-mentioned model generation method embodiment or simulation method embodiment are implemented, and the same technical effect can be achieved. To avoid repetition, they are not described here.

[0211] In an embodiment of the present application, the memory M02 can be used to store software programs and various data. The memory M02 may mainly include a first storage area for storing programs or instructions and a second storage area for storing data, wherein the first storage area may store an operating system, an application program or instructions required for at least one function (such as a sound playback function, an image playback function, etc.), etc. In addition, the memory M02 may include a volatile memory or a non-volatile memory, or the memory x09 may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), a static random access memory (SRAM), a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a double data rate synchronous dynamic random access memory (DDRSDRAM), an enhanced synchronous dynamic random access memory (ESDRAM), a synchronous link dynamic random access memory (SLDRAM) and a direct memory bus random access memory (DRRAM). The memory M02 in the embodiment of the present application includes but is not limited to these and any other suitable types of memories.

[0212] The processor M01 may include one or more processing units; optionally, the processor M01 integrates an application processor and a modem processor, wherein the application processor mainly processes operations related to an operating system, a user interface, and application programs, and the modem processor mainly processes wireless communication signals, such as a baseband processor. It is understandable that the modem processor may not be integrated into the processor M01.

[0213] An embodiment of the present application also provides an electronic device, including the model generation device or simulation device as described above, which is used to implement the various processes of the above-mentioned model generation method or simulation method embodiment, and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0214] An embodiment of the present application also provides a readable storage medium, on which a program or instruction is stored. When the program or instruction is executed by a processor, each process of the above-mentioned model generation method embodiment or simulation method embodiment is implemented, and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

[0215] The processor is the processor in the electronic device described in the above embodiment. The readable storage medium includes a computer readable storage medium, such as a computer read-only memory ROM, a random access memory RAM, a magnetic disk or an optical disk.

[0216] An embodiment of the present application further provides a chip, which includes a processor and a communication interface, wherein the communication interface is coupled to the processor, and the processor is used to run programs or instructions to implement the various processes of the above-mentioned model generation method embodiment or simulation method embodiment, and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0217] It should be understood that the chip involved in the embodiments of the present application can also be called a system-level chip, a system chip, a chip system or a system-on-chip chip, etc.

[0218] An embodiment of the present application provides a computer program product, which is stored in a storage medium. The program product is executed by at least one processor to implement the various processes of the above-mentioned model generation method embodiment or simulation method embodiment, and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0219] It should be noted that, in this article, the terms "comprise", "include" or any other variant thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise one..." do not exclude the presence of other identical elements in the process, method, article or device including the element. In addition, it should be pointed out that the scope of the methods and devices in the embodiments of the present application is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in reverse order according to the functions involved, for example, the described method may be performed in an order different from that described, and various steps may also be added, omitted, or combined. In addition, the features described with reference to certain examples may be combined in other examples.

[0220] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present application, or the part that contributes to the relevant technology, can be embodied in the form of a computer software product, which is stored in a storage medium (such as ROM / RAM, disk, CD), and includes a number of instructions for a terminal (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in each embodiment of the present application.

[0221] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.

Claims

1. A model generation method, characterized in that: The method comprises: Acquire first sample data of a high electron mobility transistor and a drain current label corresponding to the first sample data; wherein the first sample data includes a sample gate-source voltage value, a sample drain-source voltage value, a sample junction temperature value, a sample first trap time value, and a sample second trap time value; Inputting the first sample data into a first neural network of an initial dynamic field effect transistor model to obtain a predicted drain current output by the first neural network; determining a current loss value based on the predicted drain current and the drain current signature; Adjusting the parameters of the first neural network based on the current loss value to obtain a second neural network, and then obtaining a target simulation model including the second neural network; wherein the target simulation model is used to simulate the target junction temperature value, the target first trap time value, and the target second trap time value of the high electron mobility transistor according to the input target gate-source voltage value and the target drain-source voltage value, and simulate the target drain current of the high electron mobility transistor based on the target gate-source voltage value, the target drain-source voltage value, the target junction temperature value, the target first trap time value, and the target second trap time value; The target simulation model also includes a first capture emission module for outputting a target first trap time value according to the target gate-source voltage value, and a second capture emission module for outputting a target second trap time value according to the target drain-source voltage value. The second neural network is used to output a target drain current according to the input target gate-source voltage value, target drain-source voltage value, target junction temperature value, target first trap time value and target second trap time value.

2. The method according to claim 1, characterized in that The first sample data also includes a sample gate-source voltage average and a sample drain-source voltage average. The target simulation model also includes a first average module for outputting a target gate-source voltage average according to the target gate-source voltage value, and a second average module for outputting a target drain-source voltage average according to the target drain-source voltage value. The second neural network is also used to output a target drain current based on the input target first trap time value, target second trap time value, target gate-source voltage value, target drain-source voltage value, target junction temperature value, target gate-source voltage average and target drain-source voltage average.

3. The method according to claim 1, characterized in that The drain current label includes a first drain current sequence determined based on the nonlinear characteristics of actual measurement data of the high electron mobility transistor, a second drain current sequence determined based on a static current-voltage relationship of the actual measurement data, and a third drain current sequence determined based on a scattering parameter of the actual measurement data, and determining a current loss value based on the predicted drain current and the drain current label includes: calculating a first loss value based on the first drain current sequence and a predicted drain current corresponding to the first drain current sequence; calculating a second loss value based on the second drain current sequence and a predicted drain current corresponding to the second drain current sequence; Calculating a third loss value based on the third drain current sequence and a predicted drain current corresponding to the third drain current sequence; The current loss value is determined based on the first loss value, the second loss value, and the third loss value.

4. The method according to claim 1, characterized in that: The method further comprises: Acquire second sample data and a gate charge label corresponding to the second sample data; wherein the second sample data includes a sample gate-source voltage value and a sample drain-source bias voltage value; Inputting the second sample data into a third neural network of the initial dynamic field effect transistor model to obtain a first gate charge value output by the third neural network; determining a charge loss value based on the first gate charge value and the gate charge signature; The parameters of the third neural network are adjusted based on the charge loss value to obtain a fourth neural network, and then a target simulation model including the second neural network and the fourth neural network model is obtained; wherein the target simulation model is also used to simulate the target gate charge value of the high electron mobility transistor according to the input target gate-source voltage value and target drain-source voltage value.

5. The method according to claim 4, characterized in that The gate charge tag includes a first parasitic capacitance value and a second parasitic capacitance value, and determining the charge loss value based on the first gate charge value and the gate charge tag includes: Obtaining a first partial derivative of the first gate charge value with respect to a sample gate-source voltage value in the second sample data, and a second partial derivative of the first gate charge value with respect to a sample drain-source bias voltage value in the second sample data; The charge loss value is calculated according to a first difference between the first partial derivative and the first parasitic capacitance value, and a second difference between the second partial derivative and the second parasitic capacitance value.

6. The method according to claim 5, characterized in that The third neural network includes a charge prediction network and a companion neural network corresponding to the charge prediction network, and the obtaining of a first partial derivative of the first gate charge value with respect to a sample gate-source voltage value in the second sample data, and a second partial derivative of the first gate charge value with respect to a sample drain-source bias voltage value in the second sample data includes: The second sample data is input into the charge prediction network to obtain a first gate charge value output by the charge prediction network, a first partial derivative of the first gate charge value output by the accompanying neural network with respect to a sample gate-source voltage value in the second sample data, and a second partial derivative of the first gate charge value with respect to a sample drain-source bias voltage value in the second sample data.

7. A simulation method, characterized in that: The method comprises: Obtaining a target gate-source voltage value and a target drain-source voltage value; The target gate-source voltage value and the target drain-source voltage value are input into a target simulation model to obtain a target drain current output by the target simulation model to simulate a high electron mobility transistor; wherein the target simulation model is obtained based on the model generation method described in any one of claims 1 to 6.

8. A model generation device, characterized in that: The device comprises: A first acquisition module, used to acquire first sample data of a high electron mobility transistor and a drain current label corresponding to the first sample data; wherein the first sample data includes a sample gate-source voltage value, a sample drain-source voltage value, a sample junction temperature value, a sample first trap time value, and a sample second trap time value; A first input module, used for inputting the first sample data into a first neural network of an initial dynamic field effect transistor model to obtain a predicted drain current output by the first neural network; a current loss module, configured to determine a current loss value based on the predicted drain current and the drain current tag; A first training module is used to adjust the parameters of the first neural network based on the current loss value to obtain a second neural network, and then obtain a target simulation model including the second neural network; wherein the target simulation model is used to simulate the target junction temperature value, the target first trap time value and the target second trap time value of the high electron mobility transistor according to the input target gate-source voltage value and the target drain-source voltage value, and simulate the target drain current of the high electron mobility transistor based on the target gate-source voltage value, the target drain-source voltage value, the target junction temperature value, the target first trap time value and the target second trap time value; The target simulation model also includes a first capture emission module for outputting a target first trap time value according to the target gate-source voltage value, and a second capture emission module for outputting a target second trap time value according to the target drain-source voltage value. The second neural network is used to output a target drain current according to the input target gate-source voltage value, target drain-source voltage value, target junction temperature value, target first trap time value and target second trap time value.

9. A simulation device, characterized in that: The device comprises: A target acquisition module, used to acquire a target gate-source voltage value and a target drain-source voltage value; A target input module, used to input the target gate-source voltage value and the target drain-source voltage value into a target simulation model to obtain a target drain current output by the target simulation model to simulate a high electron mobility transistor; wherein the target simulation model is obtained based on the model generation method described in any one of claims 1 to 6.

10. An electronic device, characterized in that: The method comprises a processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the processor implements the method according to any one of claims 1 to 7 when executing the program.

11. A readable storage medium, characterized in that: The readable storage medium stores a program or instruction, and when the program or instruction is executed by a processor, the method according to any one of claims 1 to 7 is implemented.

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