A low power consumption and high precision LED row drive blanking circuit

Abstract

The present invention belongs to the technical field of integrated circuits, and particularly relates to a low-power, high-precision LED row drive blanking circuit. The circuit comprises: a row drive module; a blanking voltage control module, which is composed of a PMOS tube P1; the gate end of the PMOS tube P1 is connected to a bias voltage Vbias1, and the source end of the PMOS tube P1 is connected to the resistance end of the row drive module; an AND gate module; a blanking time control module, the input end D of which is connected to the input end of the row drive module, the input end of the blanking time control module and the input end 1 of the AND gate module, and the output end of the blanking time control module is connected to the input end 2 of the AND gate module. The circuit structure achieves the advantages of low static power consumption, low design and production cost, high blanking voltage control accuracy and controllable blanking time.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a low-power consumption high-precision LED row drive blanking circuit. Background Art

[0002] As a common lighting and display device, LED is widely used in various fields. The common LED driving mode is the line scanning driving mode, but due to the parasitic capacitance on the line line, it is easy to have the problem of display smearing, which affects the display effect. At this time, it is necessary to design a blanking circuit in the line driver chip. For example, the patent publication number is CN105810146A, the blanking circuit and its control method, the line driving circuit and the display screen; in order to improve the accuracy of the blanking voltage, the design of the technical solution uses an operational amplifier for error amplification, so that the blanking voltage is controlled. However, since each port needs to design an operational amplifier, a large static power consumption is introduced. Due to the current driving characteristics of the LED itself, the LED display system has a large power consumption as a whole, so the low power consumption design of the driving circuit itself is particularly important. At the same time, the design of the operational amplifier needs to occupy a large layout area in the IC design, which affects the overall design cost. Moreover, since the switch of the blanking circuit is completely controlled by the DN signal in the above design, the anode of the LED will always have a fixed potential during the effective period of DN. If the overall solution is not designed properly, a long-term reverse electromotive force will be generated at both ends of the LED, affecting the service life of the LED. Summary of the invention

[0003] The object of the present invention is to provide a low-power, high-precision LED row drive blanking circuit, the circuit structure has the advantages of low power consumption, low design and production cost, high blanking voltage control accuracy and controllable blanking time.

[0004] In order to solve the above technical problems, the present invention provides a low-power consumption high-precision LED row drive blanking circuit, comprising:

[0005] Row driver module;

[0006] The blanking voltage control module is composed of a PMOS tube P1; the gate end of the PMOS tube P1 is connected to the bias voltage Vbias1, and the source end of the PMOS tube P1 is connected to the resistance end of the row driving module;

[0007] AND gate module;

[0008] A blanking time control module, wherein the input terminal D is connected to the input terminal of the row driving module, the input terminal of the blanking time control module and the input terminal 1 of the AND gate module, the output terminal of the blanking time control module is connected to the input terminal 2 of the AND gate module, and the output terminal of the AND gate module is connected to the drain terminal of the PMOS tube P1; wherein the blanking time control module is composed of a PMOS tube P2, an NMOS tube N2, a Buffer circuit and a capacitor Cap; the gate terminal of the PMOS tube P2 is connected to the input terminal D, the source terminal of the PMOS tube P2 is connected to the power supply VDD, the drain terminal of the PMOS tube P2 is connected to the input terminal of the Buffer circuit, the upper end of the capacitor Cap and the drain terminal of the NMOS tube N2; the gate terminal of the NMOS tube N2 is connected to the bias voltage Vbias2, the source terminal of the NMOS tube N2 is connected to the lower end of the capacitor Cap and is grounded; the output terminal of the Buffer circuit is connected to the input terminal 2 of the AND gate module.

[0009] Preferably, the row driving module is composed of inverters INV1~INV2, a row driving tube Q and a resistor R; the input end of the inverter INV1 is connected to the input end D, the output end of the inverter INV1 is connected to the input end of the inverter INV2, the output end of the inverter INV2 is connected to the gate end of the row driving tube Q, the source end of the row driving tube Q is connected to the power supply VDD, the drain end of the row driving tube Q is connected to the row driving port R_OUT and the upper end of the resistor R, and the lower end of the resistor R is connected to the source end of the PMOS tube P1.

[0010] Preferably, the AND gate module is composed of an AND gate AND and an NMOS tube N1; the two input ends of the AND gate AND are respectively connected to the input end D and the output end of the Buffer circuit, the output end of the AND gate AND is connected to the gate end of the NMOS tube N1, the source end of the NMOS tube N1 is grounded, and the drain end of the NMOS tube N1 is connected to the drain end of the PMOS tube P1.

[0011] Preferably, it also includes a bias generating circuit 1 for generating the bias voltage Vbias1; the bias generating circuit 1 includes: n+1 voltage-dividing resistors connected in series between the power supply VDD and the ground, n CMOS transmission gates connected in parallel and control signals C1~Cn; the input ends of the n CMOS transmission gates are sequentially connected between each two adjacent voltage-dividing resistors, the output ends of the n CMOS transmission gates output the bias voltage Vbias1, and the control ends of the n CMOS transmission gates are sequentially connected to the control signals C1~Cn.

[0012] Preferably, it further includes a bias generating circuit 2 for generating the bias voltage Vbias2; the bias generating circuit 2 includes: PMOS tubes Q1~Q2, PMOS tubes M1~Mn, switch tubes T1~Tn, a current source I and control signals D1~Dn; the source ends of the PMOS tubes Q1 and the PMOS tubes M1~Mn are both connected to the power supply VDD, the drain end and the gate end of the PMOS tube Q1, and the gate ends of the PMOS tubes M1~Mn are connected to the grounded current source I, the drain ends of the PMOS tubes M1~Mn are sequentially connected to the source ends of the switch tubes T1~Tn, the gate ends of the switch tubes T1~Tn are sequentially connected to the control signals D1~Dn, the drain ends of the switch tubes T1~Tn are connected to the drain end and the gate end of the PMOS tube Q2, the source end of the PMOS tube Q2 is grounded, and the gate end of the PMOS tube Q2 outputs the bias voltage Vbias2.

[0013] Preferably, the PMOS transistor Q1 and the PMOS transistors M1 to Mn form n cascode current mirror structures.

[0014] Preferably, the buffer circuit is composed of two stages of cascaded inverters, and each stage of the inverter is composed of a PMOS tube and an NMOS tube.

[0015] Preferably, the inverter INV1 and the inverter INV2 have the same structure, both consisting of a PMOS tube and an NMOS tube.

[0016] Preferably, the gate ends of the PMOS tube and the NMOS tube are input ends, the source end of the PMOS tube is connected to the power supply VDD, the source end of the NMOS tube is grounded, and the drain ends of the PMOS tube and the NMOS tube are output ends.

[0017] Compared with the prior art, the present invention has the following beneficial effects:

[0018] 1. The present invention utilizes the source follower principle of the PMOS tube P1 to control the blanking voltage of the output port. The gate voltage Vbias1 of the PMOS tube P1 is configurable to achieve the adaptation of the blanking voltage control part to different LEDs, thereby achieving high precision without requiring a large number of device design op amps, and only requiring a small number of MOS devices, thereby reducing the design and production costs and achieving the advantage of static low power consumption, that is, when the PMOS row driver tube Q is turned off, the blanking logic has no static current, thereby achieving static low power consumption.

[0019] 2. The present invention uses a delay unit composed of a current source of the NMOS tube N2 and a capacitor Cap to control the blanking time. The gate voltage Vbias2 of the NMOS tube N2 is configurable, which can control the effective time of the blanking process, avoid reverse electromotive force, protect the LED, and have a higher fault tolerance rate in the overall solution design. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 The present invention is a circuit schematic diagram of a low-power, high-precision LED row drive blanking circuit.

[0021] Figure 2 FIG. 4 is a circuit schematic diagram of a bias generating circuit 1 of the present invention.

[0022] Figure 3 This is a circuit schematic diagram of the bias generating circuit 2 of the present invention.

[0023] Figure 4 It is a circuit schematic diagram of the buffer circuit and inverters INV1-INV2 of the present invention. DETAILED DESCRIPTION

[0024] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are in very simplified form and in non-precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0025] like Figure 1 As shown, the embodiment of the present invention provides a low-power consumption high-precision LED row drive blanking circuit, comprising:

[0026] Row driver module;

[0027] The blanking voltage control module is composed of a PMOS tube P1; the gate end of the PMOS tube P1 is connected to the bias voltage Vbias1, and the source end of the PMOS tube P1 is connected to the resistance end of the row driving module;

[0028] AND gate module;

[0029] A blanking time control module, wherein the input terminal D is connected to the input terminal of the row driving module, the input terminal of the blanking time control module and the input terminal 1 of the AND gate module, the output terminal of the blanking time control module is connected to the input terminal 2 of the AND gate module, and the output terminal of the AND gate module is connected to the drain terminal of the PMOS tube P1; wherein the blanking time control module is composed of a PMOS tube P2, an NMOS tube N2, a Buffer circuit and a capacitor Cap; the gate terminal of the PMOS tube P2 is connected to the input terminal D, the source terminal of the PMOS tube P2 is connected to the power supply VDD, the drain terminal of the PMOS tube P2 is connected to the input terminal of the Buffer circuit, the upper end of the capacitor Cap and the drain terminal of the NMOS tube N2; the gate terminal of the NMOS tube N2 is connected to the bias voltage Vbias2, the source terminal of the NMOS tube N2 is connected to the lower end of the capacitor Cap and is grounded; the output terminal of the Buffer circuit is connected to the input terminal 2 of the AND gate module.

[0030] Continue reading Figure 1The row driving module is composed of inverters INV1~INV2, a row driving tube Q and a resistor R; the input end of the inverter INV1 is connected to the input end D, the output end of the inverter INV1 is connected to the input end of the inverter INV2, the output end of the inverter INV2 is connected to the gate end of the row driving tube Q, the source end of the row driving tube Q is connected to the power supply VDD, the drain end of the row driving tube Q is connected to the row driving port R_OUT and the upper end of the resistor R, and the lower end of the resistor R is connected to the source end of the PMOS tube P1.

[0031] Continue reading Figure 1 The AND gate module is composed of an AND gate AND and an NMOS tube N1; the two input ends of the AND gate AND are respectively connected to the input end D and the output end of the Buffer circuit, the output end of the AND gate AND is connected to the gate end of the NMOS tube N1, the source end of the NMOS tube N1 is grounded, and the drain end of the NMOS tube N1 is connected to the drain end of the PMOS tube P1.

[0032] In the embodiment of the present invention, when the row drive port R_OUT is turned on (the input signal at the input terminal D is logic 0, hereinafter abbreviated as 0), the PMOS tube P2 is turned on, Vbias2 controls the NMOS tube N2 to turn on and generate nA level current, and at this time, the upper node of the capacitor Cap is charged to logic 1 (hereinafter abbreviated as 1). The buffer circuit outputs 1, the AND gate AND outputs 0, the NMOS tube N1 is turned off, the blanking path is closed, and the row drive port R_OUT normally outputs a high level to drive the external LED.

[0033] When the row drive port R_OUT changes from on to off (the signal at the input terminal D just changes to 1), the PMOS row drive tube Q is turned off. Since the NMOS tube N2 only has nA-level current, the voltage of the node on the upper side of the capacitor Cap will slowly drop, that is, the NMOS tube N2 and the capacitor Cap form a delay unit. In a short time, the buffer circuit still outputs 1, so that the AND gate AND outputs 1 and turns on the NMOS tube N1. At this time, the blanking path is turned on and enters the blanking function state.

[0034] The voltage of the row drive port R_OUT will drop due to the opening state of the PMOS tube P1 and the NMOS tube N1. Due to the source follower principle of the PMOS tube P1, the voltage of the row drive port R_OUT will stop dropping when it drops to the potential of Vbias1+Vth_PMOS tube P1 (Vth_PMOS tube P1 represents the threshold voltage of the PMOS tube P1). This design can effectively control the blanking voltage of the row drive port R_OUT, and obtain the same high-precision effect as the existing technical solution in the background technology.

[0035] like Figure 2As shown, it also includes a bias generating circuit 1 for generating the bias voltage Vbias1; the bias generating circuit 1 includes: n+1 voltage-dividing resistors connected in series between the power supply VDD and the ground, n CMOS transmission gates connected in parallel and control signals C1~Cn; the input ends of the n CMOS transmission gates are sequentially connected between each two adjacent voltage-dividing resistors, the output ends of the n CMOS transmission gates output the bias voltage Vbias1, and the control ends of the n CMOS transmission gates are sequentially connected to the control signals C1~Cn.

[0036] The bias voltage Vbias1 can be generated by a simple resistor voltage divider and can be set in any range according to different situations. That is, the bias voltage Vbias1 is generated by using the power supply VDD through a resistor voltage divider, so that the bias voltage Vbias1 changes with the power supply voltage VDD, and has good adaptability in different power supply systems. At the same time, different branch voltages can be selected to supply the bias voltage Vbias1 through the control signals C1~Cn as needed. Different bias voltages Vbias1 can be selected according to the characteristics of the LEDs used in different systems, which can better achieve the effect of blanking and preventing reverse bias.

[0037] like Figure 3 As shown, it also includes a bias generating circuit 2 for generating the bias voltage Vbias2; the bias generating circuit 2 includes: PMOS tubes Q1~Q2, PMOS tubes M1~Mn, switch tubes T1~Tn, a current source I and control signals D1~Dn; the source ends of the PMOS tubes Q1 and the PMOS tubes M1~Mn are both connected to the power supply VDD, the drain end and the gate end of the PMOS tube Q1, and the gate ends of the PMOS tubes M1~Mn are connected to the grounded current source I, the drain ends of the PMOS tubes M1~Mn are sequentially connected to the source ends of the switch tubes T1~Tn, the gate ends of the switch tubes T1~Tn are sequentially connected to the control signals D1~Dn, the drain ends of the switch tubes T1~Tn are connected to the drain end and the gate end of the PMOS tube Q2, the source end of the PMOS tube Q2 is grounded, and the gate end of the PMOS tube Q2 outputs the bias voltage Vbias2. The PMOS transistor Q1 and the PMOS transistors M1 -Mn form n common-source and common-gate current mirror structures.

[0038] like Figure 4 As shown, the buffer circuit is composed of two stages of cascaded inverters, and each stage of the inverter is composed of a PMOS tube and an NMOS tube. The structures of the inverter INV1 and the inverter INV2 are the same, and both are composed of a PMOS tube and an NMOS tube. The gate ends of the PMOS tube and the NMOS tube are input ends, the source end of the PMOS tube is connected to the power supply VDD, the source end of the NMOS tube is grounded, and the drain ends of the PMOS tube and the NMOS tube are output ends.

[0039] In the embodiment of the present invention, the bias voltage Vbias2 is generated by the above mirror current source structure, and the control signal D1~Dn controls the discharge current of the NMOS tube N2 to the capacitor Cap within a certain range, which can be any required value between 1nA~1μA. Since the current is set to be small, the required delay can be obtained when the capacitor Cap with a smaller capacitance is matched, which effectively saves area and reduces costs; at the same time, the constant current source design is used, and the current accuracy is high, and the required delay can be set more accurately. When the voltage of the node on the upper side of the capacitor Cap drops below the flip threshold of the buffer circuit, the buffer circuit outputs 0, and the AND gate AND outputs 0, turning off the NMOS tube N1, so that the effective level of the row drive port R_OUT only exists for a limited time, which can ensure that the reverse electromotive force will not be applied to the external LED, thereby protecting the LED and avoiding damage.

[0040] At the same time, when the input terminal D is input 1, since the PMOS tube P2 is turned off, the module has no current path from the power supply to the ground, achieving static low power consumption.

[0041] In the above structure, Vbias1 and Vbias2 can be designed to set specific values ​​through software. The advantages of this design are: since different colors of LEDs require different blanking voltages, when Vbias1 has a configuration range, the blanking voltage can be modified to adapt to more usage scenarios. At the same time, according to the principle of smear generation, since the parasitic capacitance values ​​of the row lines are different in different overall solutions, the required blanking time is different. Therefore, when Vbias2 has a configuration range, the blanking time can be modified, which can further improve the fault tolerance of the overall solution design.

[0042] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A low power consumption high precision LED row drive blanking circuit, characterized in that: include: Row driver module; The blanking voltage control module is composed of a PMOS tube P1; the gate end of the PMOS tube P1 is connected to the bias voltage Vbias1, and the source end of the PMOS tube P1 is connected to the resistance end of the row driving module; AND gate module; A blanking time control module, wherein the input terminal D is connected to the input terminal of the row driving module, the input terminal of the blanking time control module and the input terminal 1 of the AND gate module, the output terminal of the blanking time control module is connected to the input terminal 2 of the AND gate module, and the output terminal of the AND gate module is connected to the drain terminal of the PMOS tube P1; wherein the blanking time control module is composed of a PMOS tube P2, an NMOS tube N2, a Buffer circuit and a capacitor Cap; the gate terminal of the PMOS tube P2 is connected to the input terminal D, the source terminal of the PMOS tube P2 is connected to the power supply VDD, the drain terminal of the PMOS tube P2 is connected to the input terminal of the Buffer circuit, the upper end of the capacitor Cap and the drain terminal of the NMOS tube N2; the gate terminal of the NMOS tube N2 is connected to the bias voltage Vbias2, the source terminal of the NMOS tube N2 is connected to the lower end of the capacitor Cap and is grounded; the output terminal of the Buffer circuit is connected to the input terminal 2 of the AND gate module.

2. A low power consumption high precision LED row drive blanking circuit as claimed in claim 1, characterized in that: The row driving module is composed of an inverter INV1, an inverter INV2, a row driving tube Q and a resistor R; the input end of the inverter INV1 is connected to the input end D, the output end of the inverter INV1 is connected to the input end of the inverter INV2, the output end of the inverter INV2 is connected to the gate end of the row driving tube Q, the source end of the row driving tube Q is connected to the power supply VDD, the drain end of the row driving tube Q is connected to the row driving port R_OUT and the upper end of the resistor R, and the lower end of the resistor R is connected to the source end of the PMOS tube P1.

3. A low power consumption high precision LED row drive blanking circuit as claimed in claim 1, characterized in that: The AND gate module is composed of an AND gate AND and an NMOS tube N1; the two input ends of the AND gate AND are respectively connected to the input end D and the output end of the Buffer circuit, the output end of the AND gate AND is connected to the gate end of the NMOS tube N1, the source end of the NMOS tube N1 is grounded, and the drain end of the NMOS tube N1 is connected to the drain end of the PMOS tube P1.

4. A low power consumption high precision LED row drive blanking circuit as claimed in claim 1, characterized in that: It also includes a bias generating circuit 1 for generating the bias voltage Vbias1; the bias generating circuit 1 includes: n+1 voltage-dividing resistors connected in series between the power supply VDD and the ground, n CMOS transmission gates connected in parallel and control signals C1~Cn; the input ends of the n CMOS transmission gates are sequentially connected between each two adjacent voltage-dividing resistors, the output ends of the n CMOS transmission gates output the bias voltage Vbias1, and the control ends of the n CMOS transmission gates are sequentially connected to the control signals C1~Cn.

5. A low power consumption high precision LED row drive blanking circuit as claimed in claim 1, characterized in that: The invention also includes a bias generating circuit 2 for generating the bias voltage Vbias2; the bias generating circuit 2 includes: PMOS tubes Q1-Q2, PMOS tubes M1-Mn, switch tubes T1-Tn, a current source I and control signals D1-Dn; the source ends of the PMOS tubes Q1 and M1-Mn are both connected to the power supply VDD, the drain end and the gate end of the PMOS tube Q1, and the gate ends of the PMOS tubes M1-Mn are connected to the grounded current source I, the drain ends of the PMOS tubes M1-Mn are sequentially connected to the source ends of the switch tubes T1-Tn, the gate ends of the switch tubes T1-Tn are sequentially connected to the control signals D1-Dn, the drain ends of the switch tubes T1-Tn are connected to the drain end and the gate end of the PMOS tube Q2, the source end of the PMOS tube Q2 is grounded, and the gate end of the PMOS tube Q2 outputs the bias voltage Vbias2.

6. A low power consumption high precision LED row drive blanking circuit as claimed in claim 5, characterized in that: The PMOS transistor Q1 and the PMOS transistors M1 -Mn form n common-source and common-gate current mirror structures.

7. A low power consumption high precision LED row drive blanking circuit as claimed in claim 1, characterized in that: The buffer circuit is composed of two stages of cascaded inverters, and each stage of the inverter is composed of a PMOS tube and an NMOS tube.

8. A low power consumption high precision LED row drive blanking circuit as claimed in claim 2, characterized in that: The inverter INV1 and the inverter INV2 have the same structure, and both are composed of a PMOS tube and an NMOS tube.

9. A low power consumption high precision LED row drive blanking circuit as claimed in claim 7 or 8, characterized in that: The gate ends of the PMOS tube and the NMOS tube are input ends, the source end of the PMOS tube is connected to the power supply VDD, the source end of the NMOS tube is grounded, and the drain ends of the PMOS tube and the NMOS tube are output ends.

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