Display panel and driving method thereof

Abstract

A method for driving a display panel includes (a) inputting a waveform to a data line at a target time, wherein the longer the target time, the lower the reflectivity of a plurality of liquid crystal molecules in the display panel; (b) inputting a voltage to a first gate line at a time interval; (c) inputting the voltage to a second gate line at the time interval, wherein the first gate line has no input voltage; (d) inputting the voltage to a third gate line at the time interval, wherein the first gate line and the second gate line have no input voltage; and (e) repeating steps (b) to (d) to the target time, wherein the target time is at least forty milliseconds.

Description

Technical Field

[0001] This disclosure relates to a display panel and a method for driving the display panel. Background Technology

[0002] In the field of liquid crystal displays (LCDs), cholesteric liquid crystals are widely used due to their bistable properties. There are two main applications of bistable cholesteric liquid crystals: passive and active. Passive applications require calculating the resistance multiplied by the capacitance of all pixels on the data lines, resulting in a very large resistance-capacitance delay (RC-Delay).

[0003] Furthermore, while active-matrix applications can improve resistive-capacitive delay by about two orders of magnitude, the voltage required for switching cholesteric liquid crystals is very large, thus necessitating new display driving methods. Summary of the Invention

[0004] The technical specification disclosed herein is a driving method for a display panel.

[0005] According to one embodiment of this disclosure, a method for driving a display panel includes (a) inputting a waveform to a data line at a target time, wherein the longer the target time, the lower the reflectivity of a plurality of liquid crystal molecules in the display panel; (b) inputting a voltage to a first gate line at time intervals; (c) inputting a voltage to a second gate line at time intervals, wherein the first gate line has no input voltage; (d) inputting a voltage to a third gate line at time intervals, wherein the first gate line and the second gate line have no input voltage; and (e) repeating steps (b) to (d) until the target time, wherein the target time is at least forty milliseconds.

[0006] In one embodiment of this disclosure, the driving method for the display panel further includes changing the reflectivity of a plurality of liquid crystal molecules in the display panel by using a waveform that is symmetrical to the positive and negative frequencies of the data line input.

[0007] In one embodiment of this disclosure, the driving method for the display panel further includes resetting the data line with a fixed frequency signal before step (a).

[0008] In one embodiment of this disclosure, step (e) includes storing voltage with a plurality of thin-film transistors.

[0009] In one embodiment of this disclosure, the driving method for the display panel further includes changing the reflectivity of a plurality of liquid crystal molecules in the display panel by inputting a waveform with positive and negative symmetry to the data line at a frequency, wherein the voltage in the positive direction of the waveform varies with time between at least two voltages.

[0010] Another technical aspect disclosed herein is a display panel.

[0011] According to one embodiment of this disclosure, a display panel includes a voltage control unit, a first gate line, a second gate line, a third gate line, a data line, and a plurality of thin-film transistors. The voltage control unit is configured to control an input voltage. The first gate line is electrically connected to the voltage control unit and configured to input voltage through the voltage control unit at time intervals. The second gate line is electrically connected to the voltage control unit and configured to input voltage through the voltage control unit at time intervals, wherein when the second gate line receives a voltage, the first gate line receives no input voltage. The third gate line is electrically connected to the voltage control unit and configured to input voltage through the voltage control unit at time intervals, wherein when the third gate line receives a voltage, the first and second gate lines receive no input voltage. The data line is electrically connected to the voltage control unit and configured to adjust the grayscale of the display panel via the voltage control unit. The thin-film transistors are electrically connected to the data line and configured to store the voltage of the data line.

[0012] In one embodiment of this disclosure, the voltage control unit is configured to input a positive and negative symmetrical waveform to the data line, thereby changing the reflectivity of a plurality of liquid crystal molecules in the display panel.

[0013] In one embodiment of this disclosure, the thin-film transistor stores voltage when the voltage control unit adjusts the grayscale of the display panel via a data line.

[0014] In one embodiment of this disclosure, a voltage control unit is configured to input a positive and negative symmetrical waveform to a data line, causing a change in the reflectivity of a plurality of liquid crystal molecules in the display panel, wherein the voltage in the positive direction of the waveform varies with time between at least two voltages.

[0015] In one embodiment of this disclosure, the voltage control unit is configured to reset the data line by inputting a fixed-frequency signal to the data line.

[0016] In the above-described embodiments disclosed herein, by repeatedly inputting voltages to the first gate line, the second gate line, and the third gate line for a target time, and inputting voltage waveforms to the data line within the target time, the reflectivity of the liquid crystal molecules is changed, thereby adjusting the grayscale of the liquid crystal display in a shorter time and achieving the effect of adjusting the brightness of the display. Attached Figure Description

[0017] The nature of this disclosure can be best understood by reading it in conjunction with the accompanying illustrations and by the embodiments described below. Note that, according to standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be increased or decreased arbitrarily for clarity of explanation.

[0018] Figure 1 A flowchart illustrating a driving method for a display panel according to an embodiment of this disclosure is shown.

[0019] Figure 2 A block diagram illustrating a display panel according to one embodiment of the present disclosure.

[0020] Figure 3 A schematic diagram illustrating the voltage variation over time of each of the first gate line, second gate line, third gate line, and data line according to an embodiment of the present disclosure.

[0021] Figure 4 and Figure 5 A schematic diagram illustrating the voltage of a data line changing over time according to another embodiment of this disclosure is shown.

[0022] Figure 6 A graph illustrating the relationship between reflectivity and scanning time of a display panel under different voltages according to an embodiment of the present disclosure is shown.

[0023] Figure 7 A schematic diagram illustrating the voltage of a data line changing over time according to yet another embodiment of this disclosure is shown.

[0024] Figure 8 A schematic diagram illustrating the voltage change of a data line over time according to another embodiment of this disclosure is shown.

[0025] In the attached figures, the following labels are used:

[0026] 100: Display panel

[0027] 110: Voltage Control Unit

[0028] 120: Thin-film transistor

[0029] G1: First gate line

[0030] G2: Second gate line

[0031] G3: Third gate line

[0032] D: Data cable

[0033] S1, S2, S3, S4, S5: Steps

[0034] t: time interval, time

[0035] t1, t2: Scan time

[0036] V: Voltage

[0037] V1: Voltage Detailed Implementation

[0038] The following description of embodiments provides many different implementations, or examples, for carrying out various features of the provided object. Specific examples of elements and arrangements are described below to simplify the subject matter. Of course, these examples are merely illustrative and are not intended to be limiting. Furthermore, element symbols and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself specify the relationship between the various embodiments and / or configurations discussed.

[0039] Spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” are used herein for descriptive purposes to describe the relationship between one element or feature and another, as shown in the accompanying drawings. Spatial relative terms are intended to cover different orientations of the device in use or operation other than those shown in the accompanying drawings. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptors used herein shall be interpreted accordingly.

[0040] As used herein, “about,” “approximately,” or “substantially” includes the value and the average value within an acceptable range of deviations from a particular value as determined by one of ordinary skill in the art, taking into account the measurement in question and a particular number of errors associated with the measurement (i.e., limitations of the measurement system). For example, “about” may mean within one or more standard deviations of the value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, the use of “about,” “approximately,” or “substantially” herein may be chosen based on optical, etched, or other properties to select a more acceptable range of deviations or standard deviations, and may not require a single standard deviation to apply to all properties.

[0041] Figure 1 A flowchart illustrating a driving method for a display panel according to an embodiment of this disclosure is shown. (Refer to...) Figure 1 A method for driving a display panel includes the following steps. First, in step S1, a waveform is input to a data line at a target time; the longer the target time, the lower the reflectivity of the multiple liquid crystal molecules in the display panel. Next, in step S2, a voltage is input to a first gate line at time intervals. Next, in step S3, a voltage is input to a second gate line at time intervals, wherein there is no input voltage to the first gate line. Next, in step S4, a voltage is input to a third gate line at time intervals, wherein there is no input voltage to the first and second gate lines. Finally, in step S5, steps S2 to S4 are repeated until the target time, wherein the target time is at least forty milliseconds.

[0042] In some embodiments, the driving method for the display panel is not limited to steps S1 to S5 described above. For example, in some embodiments, other steps may be included between steps S1 and S5, or other steps may be included before step S1 and after step S5. In the following description, at least the above steps will be explained.

[0043] Figure 2 A block diagram illustrating a display panel 100 according to an embodiment of the present disclosure is shown. Figure 3 A schematic diagram illustrating the voltage variation of each of the first gate line G1, the second gate line G2, the third gate line G3, and the data line D as a function of time t according to an embodiment of this disclosure is shown. (See also...) Figure 2 and Figure 3 The display panel 100 includes a voltage control unit 110, a first gate line G1, a second gate line G2, a third gate line G3, a plurality of thin-film transistors 120, and a data line D. The voltage control unit 110 is configured to control the input voltage. The first gate line G1 is electrically connected to the voltage control unit 110 and configured to input voltage V1 through the voltage control unit 110 at time intervals t. The second gate line G2 is electrically connected to the voltage control unit 110 and configured to input voltage V1 through the voltage control unit 110 at time intervals t, wherein when the second gate line G2 inputs voltage V1, the first gate line G1 has no input voltage V1. The third gate line G3 is electrically connected to the voltage control unit 110 and configured to input voltage V1 through the voltage control unit 110 at time intervals t, wherein when the third gate line G3 inputs voltage V1, the first gate line G1 and the second gate line G2 have no input voltage V1. The data line D is electrically connected to the voltage control unit 110 and configured to adjust the grayscale of the display panel 100 through the voltage control unit 110. Thin-film transistor 120 is electrically connected to data line D and configured to store the voltage of data line D.

[0044] Specifically, when applying voltage V1 to the first gate line G1, the second gate line G2, and the third gate line G3, to significantly reduce the time required for the entire process, a voltage V1 is applied to the first gate line G1 at a time interval t, then to the second gate line G2 at the same time interval t, and then to the third gate line G3 at the same time interval t. After each of the first, second, and third gate lines G1 and G2 has been applied voltage V1 in sequence, this cycle continues until the target time is reached. The target time can be as short as 41.6 milliseconds and as long as 30 seconds. During this process, the thin-film transistors 120 in the display panel 100 store the voltage of the data lines.

[0045] Figure 4 and Figure 5A schematic diagram illustrating the change of voltage V of data line D with time t according to another embodiment of this disclosure is shown. (Refer to...) Figure 4 and Figure 5 The driving method for the display panel further includes resetting the data line D with a fixed-frequency signal S before step S1. The fixed-frequency signal S can be, for example, a 60 Hz, 40 volt signal, but this disclosure is not limited to this. Subsequently, the data line enters a "wait" state before "scanning" begins. "Scanning" involves inputting a set of positive and negative symmetrical waveforms. Figure 4 and Figure 5 The difference is that, Figure 4 The scan time t1 is compared to Figure 5 The scan time t2 is shorter. Even under the same voltage, different scan times will result in different reflectivity results, which will... Figure 6 Detailed explanation.

[0046] Figure 6 A graph illustrating the relationship between reflectivity and scanning time of a display panel according to an embodiment of this disclosure under different voltages is shown. (Refer to...) Figure 6 At the same voltage, the longer the scan time (e.g., ... Figure 5 The longer the scan time (t2), the lower the reflectivity of the display panel. Therefore, the scan time of the data line alters the reflectivity of multiple liquid crystal molecules in the display panel. Furthermore, the higher the input voltage, the more pronounced the change in the display panel's reflectivity with scan time becomes within the range of 0 to 50 milliseconds.

[0047] Reference Figure 3 , Figure 3 The waveform input to data line D when the first gate line G1, the second gate line G2, and the third gate line G3 begin charging is also the aforementioned "scan," therefore, it also controls the display panel 100 (see...). Figure 2 The function of grayscale (i.e. reflectivity).

[0048] The following description details the scanning methods of data lines in different implementations.

[0049] Figure 7 A schematic diagram illustrating the voltage change of a data line over time according to yet another embodiment of this disclosure is shown. This embodiment is similar to... Figure 4 or Figure 5 The difference in implementation is that, in this implementation, during the scanning step, the data lines no longer have only one positive and one negative voltage and zero bias voltage, but rather two positive and two negative voltages. Since the page-turning time of the display panel equals the frame time multiplied by the number of frames, and the number of frames is positively correlated with color depth, as shown in the following formula:

[0050]

[0051] For example Therefore, multiple voltage sets can be used to reduce the number of frames, thereby shortening the page change time.

[0052] Figure 8 A schematic diagram illustrating the voltage change of a data line over time according to another embodiment of this disclosure is shown. This embodiment is similar to... Figure 7 The difference in implementation is that, in this embodiment, during the scanning step, the data lines no longer have only two positive and two negative voltages and zero bias, but rather three positive and three negative voltages. As mentioned above, more voltage combinations can significantly shorten page-turning time, thereby improving the performance of the display panel.

[0053] In summary, by repeatedly inputting voltages to the first, second, and third gate lines for a target time, and inputting voltage waveforms to the data lines within the target time, the reflectivity of the liquid crystal molecules is changed, thus allowing the grayscale of the liquid crystal display to be adjusted in a shorter time, thereby achieving the effect of adjusting the brightness of the display.

[0054] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made to them without departing from the spirit and scope of this disclosure.

Claims

1. A driving method of a display panel applied to a cholesteric liquid crystal display, characterized by, Comprising: (a) inputting a waveform to a data line for a target time, wherein the longer the target time, the lower the reflectivity of liquid crystal molecules in the display panel; (b) inputting a voltage to a first gate line for a time interval; (c) inputting the voltage to a second gate line for the time interval, wherein the first gate line is free of inputting the voltage; (d) inputting the voltage to a third gate line for the time interval, wherein the first gate line and the second gate line are free of inputting the voltage; and (e) repeating steps (b) to (d) to the target time, wherein the target time is at least forty milliseconds.

2. The driving method of a display panel according to claim 1, wherein Further comprising: inputting the waveform to the data line with a frequency such that the reflectivity of the liquid crystal molecules in the display panel changes.

3. The driving method of a display panel according to claim 2, wherein Further comprising: resetting the data line with a frequency signal before step (a).

4. The driving method of a display panel according to claim 1, wherein Wherein step (e) comprises storing the voltage with a plurality of thin film transistors.

5. The driving method of a display panel according to claim 1, wherein Further comprising: inputting a waveform to a data line with a frequency such that the reflectivity of the liquid crystal molecules in the display panel changes, wherein a positive direction of the voltage of the waveform varies between at least two voltages over time.

6. A cholesteric liquid crystal display panel, characterized by comprising: Comprising: a voltage control unit configured to control input voltage; a first gate line electrically connected to the voltage control unit configured to input a voltage through the voltage control unit for a time interval; a second gate line electrically connected to the voltage control unit configured to input the voltage through the voltage control unit for the time interval, wherein the first gate line is free of inputting the voltage when the second gate line inputs the voltage; a third gate line electrically connected to the voltage control unit configured to input the voltage through the voltage control unit for the time interval, wherein the first gate line and the second gate line are free of inputting the voltage when the third gate line inputs the voltage; a data line electrically connected to the voltage control unit configured to adjust a gray scale of the display panel through the voltage control unit, configured to input a waveform for a target time, wherein the longer the target time, the lower the reflectivity of liquid crystal molecules in the display panel, the target time being at least forty milliseconds; and a plurality of thin film transistors electrically connected to the data line configured to store the voltage of the data line. Wherein the voltage control unit is configured to input a waveform to the data line with a frequency such that the reflectivity of the liquid crystal molecules in the display panel changes.

7. The display panel of claim 6, wherein, Wherein the thin film transistors store the voltage when the voltage control unit adjusts the gray scale of the display panel through the data line.

8. The display panel of claim 6, wherein, Wherein the voltage control unit is configured to input a waveform to the data line with a frequency such that the reflectivity of the liquid crystal molecules in the display panel changes, and a positive direction of the voltage of the waveform varies between at least two voltages over time.

9. The display panel of claim 6, wherein, Wherein the voltage control unit is configured to reset the data line with a frequency signal.

10. The display panel of claim 6, wherein, ​

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