Semiconductor structure and memory

Abstract

The embodiment of the invention provides a semiconductor structure and a memory, a first memory block comprises N first memory groups arranged along a first direction, and a second memory block comprises N second memory groups arranged along the first direction; the row decoding circuit comprises 2N selection control units, N row redundancy units, N-1 pre-decoding units and 2 * (N-1) amplification control units, so that access delay is reduced, and the performance of the row decoding circuit is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a memory. Background Art

[0002] With the continuous development of semiconductor technology, people have put forward higher and higher requirements for data transmission speed when manufacturing and using computers and other equipment. In order to obtain faster data transmission speed, a series of devices such as memory that can transmit data at double data rate (DDR) have emerged.

[0003] Among them, for the row decoding circuit (Row Decoder), the row decoding circuit is composed of multiple functional units, including a row redundancy unit and a pre-decoding unit. The row redundancy unit and the pre-decoding unit are located on one side of the storage block, and the storage block includes multiple storage groups, so that the row redundancy unit and the pre-decoding unit are far away from the storage group finally accessed, resulting in a large access delay. Summary of the invention

[0004] Embodiments of the present disclosure provide a semiconductor structure and a memory.

[0005] In a first aspect, an embodiment of the present disclosure provides a semiconductor structure, the semiconductor structure comprising a first storage block, a second storage block and a row decoding circuit, wherein the first storage block, the row decoding circuit and the second storage block are arranged along a second direction;

[0006] The first storage block includes N first storage groups arranged along a first direction, and the second storage block includes N second storage groups arranged along the first direction;

[0007] The row decoding circuit includes 2N selection control units, N row redundancy units, N-1 pre-decoding units and 2×(N-1) amplification control units;

[0008] Wherein, a first storage group, a selection control unit, a row redundancy unit, another selection control unit and a second storage group are arranged in sequence along the second direction; an amplification control unit is arranged between every two selection control units, and a pre-decoding unit is arranged between every two row redundancy units;

[0009] Wherein, N is an integer greater than 0, and the first direction and the second direction are perpendicular to each other.

[0010] In some embodiments, each selection control unit includes a word line driving unit and a block decoding unit, wherein:

[0011] A first storage group, a word line driving unit, a block decoding unit, a row redundancy unit, another block decoding unit, another word line driving unit and a second storage group are arranged in sequence along the second direction.

[0012] In some embodiments, in the first direction, a portion of each amplifying control unit is located between two adjacent word line driving units, and the remaining portion of the amplifying control unit is located between two adjacent block decoding units.

[0013] In some embodiments, the length of the first storage group along the first direction is greater than the length of the row redundancy unit along the first direction, and the length of the second storage group along the first direction is greater than the length of the row redundancy unit along the first direction;

[0014] The length of the row redundancy unit along the second direction is greater than the length of the block decoding unit along the second direction, and the length of the row redundancy unit along the second direction is greater than the length of the word line driving unit along the second direction.

[0015] In some embodiments, a length of the amplification control unit along the first direction is greater than a length of the pre-decoding unit along the first direction.

[0016] In some embodiments, a projection of one amplification control unit along the second direction and projections of two first storage groups along the second direction have overlapping parts, so that the two first storage groups share adjacent amplification control units;

[0017] Furthermore, there are overlapping parts between the projection of one amplification control unit along the second direction and the projections of the two second storage groups along the second direction, so that the two second storage groups share adjacent amplification control units.

[0018] In some embodiments, the row decoding circuit further includes 2N main word line driving units, wherein:

[0019] A first storage group, a main word line driving unit, a word line driving unit, a block decoding unit, a row redundancy unit, another block decoding unit, another word line driving unit, another main word line driving unit and a second storage group are arranged in sequence along the second direction.

[0020] In some embodiments, the row decoding circuit further includes two buffer driving units;

[0021] In the first direction, the first buffer driving unit is located at a side of the first row redundant unit away from the pre-decoding unit, and the second buffer driving unit is located at a side of the Nth row redundant unit away from the pre-decoding unit;

[0022] The row decoding circuit is used to decode the row address signal, and the buffer driving unit is used to drive and enhance the row address signal.

[0023] In some embodiments, the row redundancy unit includes a redundant matching unit and a redundant address encoding unit arranged along the second direction, wherein:

[0024] The redundant matching unit is located at a side of the redundant address encoding unit away from the first storage group.

[0025] In some embodiments, the first storage block is a storage unit, and the second storage block is another storage unit; or,

[0026] The first storage block is 1 / 2 of the storage unit, the second storage block is 1 / 2 of the storage unit, and the first storage block and the second storage block together constitute one storage unit.

[0027] In some embodiments, the redundant matching unit is configured to receive an initial address signal and determine whether the initial address signal has been subjected to a redundant repair process; if the initial address signal has not been subjected to a redundant repair process, output the initial address signal as a row address signal; if the initial address signal has been subjected to a redundant repair process, output the repair address signal as a row address signal;

[0028] The repair address signal indicates a redundant storage row used to repair the storage row corresponding to the initial address signal.

[0029] In some embodiments, the pre-decoding unit is connected to the redundant matching unit, and is configured to receive and perform a first decoding process on the row address signal, and output a decoding signal.

[0030] In some embodiments, the main word line driving unit is connected to the pre-decoding unit, configured to receive and perform a second decoding process on the decoding signal, and output a plurality of control signals;

[0031] Wherein, a plurality of control signals respectively enter the word line driving unit, the block decoding unit and the amplification control unit.

[0032] In a second aspect, an embodiment of the present disclosure provides a memory, which includes a semiconductor structure as described in any one of the first aspects.

[0033] In some embodiments, the memory is a synchronous dynamic random access memory SDRAM chip, or a dynamic random access memory DRAM chip.

[0034] The disclosed embodiment provides a semiconductor structure and a memory, the semiconductor structure includes a first storage block, a second storage block and a row decoding circuit, and the first storage block, the row decoding circuit and the second storage block are arranged along the second direction; the first storage block includes N first storage groups arranged along the first direction, and the second storage block includes N second storage groups arranged along the first direction; the row decoding circuit includes 2N selection control units, N row redundancy units, N-1 pre-decoding units and 2×(N-1) amplification control units; wherein, 1 first storage group, 1 selection control unit, 1 row redundancy unit, another selection control unit and 1 second storage group are arranged in sequence along the second direction; 1 amplification control unit is arranged between every 2 selection control units, and 1 pre-decoding unit is arranged between every 2 row redundancy units; wherein N is an integer greater than 0, and the first direction and the second direction are perpendicular to each other. In this way, the row decoding circuit architecture is fully functional, and the row redundancy unit and the pre-decoding unit are arranged on the side close to the first storage group or the second storage group that is finally accessed, thereby reducing access delay and improving the performance of the row decoding circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 A schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure Figure 1 ;

[0036] Figure 2 A schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure Figure 2 ;

[0037] Figure 3 A schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure Figure 3 ;

[0038] Figure 4 A schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure Figure 4 ;

[0039] Figure 5 A schematic diagram of a decoding process of a row decoding circuit provided in an embodiment of the present disclosure;

[0040] Figure 6 A schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure Figure 5 ;

[0041] Figure 7 A schematic diagram of the composition structure of a memory provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0042] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. It is understood that the specific embodiments described herein are only used to explain the relevant applications, rather than to limit the present disclosure. It should also be noted that, for the convenience of description, only the parts related to the relevant applications are shown in the drawings.

[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0044] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0045] It should be pointed out that the terms "first\second\third" involved in the embodiments of the present disclosure are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that "first\second\third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of the present disclosure described here can be implemented in an order other than that illustrated or described here.

[0046] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0047] In the memory, for a memory array sheet (Memory Mat) containing 512×512 memory cells (Memory Cell), it may include a memory array (Memory Array), a sense amplifier (Sense Amplifier, SA) unit, a sub wordline control (Sub Wordline Control, SWC) unit and a sub wordline driver (Sub Wordline Driver, SWD) unit. Here, the row decoding circuit decodes the address signal input by the memory controller (Memory Controller, MC) and provides the corresponding timing signal, so as to activate the sub wordline driver unit, sub wordline control unit and sense amplifier unit corresponding to a certain area (Section) in the memory array, and then activate the specific wordline (Wordline, WL) in the selected area, and amplify the bitline (BitLine, BL) signal of charge sharing (Charge Sharing) after the wordline is activated.

[0048] The row decoding circuit can be composed of many units with different functions, such as a section decoder (SectionDecoder) unit, which is used to select a certain area in the storage array; a sense amplifier timing control (BLSA_Control) unit, which is used to control the timing of the sense amplifier; a main wordline driver (Main Wordline Driver, MWD) unit, which is used to decode and drive the main word line; an address driver (Physical WL Driver) unit, which is used to decode and select the lower 8-bit address.

[0049] The row decoding circuit may also include other functional units. In one embodiment of the present disclosure, see Figure 1 , which shows a schematic diagram of the composition structure of a semiconductor structure provided by an embodiment of the present disclosure Figure 1 .like Figure 1 As shown, the semiconductor structure 20 may include a first storage block 21, a second storage block 22 and a row decoding circuit 23, and the first storage block 21, the row decoding circuit 23 and the second storage block 22 are arranged along the second direction;

[0050] The first storage block 21 includes N first storage groups 211 arranged along a first direction, and the second storage block 22 includes N second storage groups 221 arranged along the first direction. Figure 1 In the figure, only one first storage group 211 and one second storage group 221 are exemplarily numbered;

[0051] The row decoding circuit 23 includes 2N selection control units 231, N row redundancy units 232, N-1 pre-decoding units 233 and 2×(N-1) amplification control units 234 ( Figure 1 In the figure, only one selection control unit 231, one row redundancy unit 232, one pre-decoding unit 233 and one amplification control unit 234 are exemplarily labeled);

[0052] Among them, a first storage group 211, a selection control unit 231, a row redundant unit 232, another selection control unit 231 and a second storage group 221 are arranged in sequence along the second direction; an amplification control unit 234 is set between every two selection control units 231, and a pre-decoding unit 233 is set between every two row redundant units 232.

[0053] It should be noted that N is an integer greater than 0, and the first direction and the second direction are perpendicular to each other.

[0054] It should also be noted that, in the embodiment of the present disclosure, for the semiconductor structure 20, it can specifically be a new type of row decoding circuit architecture, in which functional units such as the selection control unit, the amplification control unit, the row redundancy unit and the pre-decoding unit are placed in the same row decoding circuit, so that the row decoding circuit architecture is fully functional; and the row redundancy unit and the pre-decoding unit are close to the storage group that is finally accessed, which brings extremely small access delay, which is beneficial to improving circuit performance.

[0055] It should also be noted that in the embodiments of the present disclosure, the first direction and the second direction may be any two intersecting directions, for example: the angle between the first direction and the second direction may be 60°, 90° or other suitable angles, which is not specifically limited, and this embodiment is described by taking the first direction being perpendicular to the second direction as an example. In addition, the first direction refers to the horizontal direction, i.e. the horizontal direction; the second direction refers to the vertical direction, i.e. the longitudinal direction; or the first direction refers to the vertical direction, i.e. the longitudinal direction; the second direction refers to the horizontal direction, i.e. the horizontal direction, which is not specifically limited, and this embodiment is described by taking the first direction referring to the horizontal direction and the second direction referring to the vertical direction as an example.

[0056] It should also be noted that Figure 1 Only any three first storage groups 211 and second storage groups 221 of the N first storage groups 211 and the N second storage groups 221 and their corresponding row decoding circuits 23 are shown exemplarily, where n is an integer greater than 1 and less than N.

[0057] It should also be noted that in Figure 1 And subsequent Figures 2 to 4 In the figure, all structures with the same filler correspond to the same functional units.

[0058] It should also be noted that, in the embodiment of the present disclosure, the first storage group 211 and the second storage group 221 can be represented by BK (block), the pre-decoding unit 233 can be represented by PreDec, and the amplification control unit 234 can be represented by SACtrl (SenseAmplifier Control). In addition, the amplification control unit 234 is used to control the sense amplifier, and the sense amplifier is used to read and amplify the signal of the bit line.

[0059] It should also be noted that, in the embodiment of the present disclosure, since one amplification control unit 234 is provided between every two selection control units 231, for N selection control units 231 close to the first storage group 211 or the second storage group 221, there is one less amplification control unit 234 than the selection control unit 231, so there are a total of 2×(N-1) amplification control units 234. Similarly, since one pre-decoding unit 233 is provided between every two row redundant units 232, for N row redundant units 232, there is one less pre-decoding unit 233 than the row redundant unit 232, so there are a total of N-1 pre-decoding units 233.

[0060] It should also be noted that, in the embodiment of the present disclosure, the first storage block 21 and the second storage block 22 share a row redundancy unit 232 and a pre-decoding unit 233, and the first storage block 21 and the second storage block 22 respectively include N storage groups (the first storage group 211 or the second storage group 221), so the row decoding circuit 23 includes N row redundancy units 232 and N-1 pre-decoding units 233. In addition, the first storage block 21 and the second storage block 22 each use a selection control unit 231 and an amplification control unit 234, so the row decoding circuit 23 includes 2N selection control units 231 and 2×(N-1) amplification control units 234.

[0061] In some embodiments, the semiconductor structure 20 may be distributed in an axisymmetric manner along a symmetry axis parallel to the first direction, so that the layout structure of the semiconductor structure 20 is neatly arranged, which is beneficial to process implementation.

[0062] It should be noted that in the embodiment of the present disclosure, among the 2N selection control units 231, N selection control units 231 are close to the first storage group 211, and N selection control units 231 are close to the second storage group 221, and each selection control unit 231 implements a function for the first storage group 211 or the second storage group 221 that is close to it. Similarly, among the 2×(N-1) amplification control units 234, N-1 amplification control units 234 are close to the first storage group 211, and N-1 amplification control units 234 are close to the second storage group 221, and each amplification control unit 234 implements a function for the first storage group 211 or the second storage group 221 that is close to it. It can be understood that the internal specific structures of the selection control unit 231 close to the first storage group 211 and the selection control unit 231 close to the second storage group 221 can be arranged in a mirror distribution along the symmetry axis parallel to the first direction, and the internal specific structures of the amplification control unit 234 close to the first storage group 211 and the amplification control unit 234 close to the second storage group 221 can also be arranged in a mirror distribution along the symmetry axis parallel to the first direction, and no specific limitation is made to this.

[0063] Further, in some embodiments, the first storage block 21 is a storage unit, and the second storage block 22 is another storage unit; or,

[0064] The first storage block 21 is a 1 / 2 storage unit, the second storage block 22 is a 1 / 2 storage unit, and the first storage block 21 and the second storage block 22 together constitute a storage unit.

[0065] That is, the first storage block 21 and the second storage block 22 may be two independent storage units, or two 1 / 2 storage units (i.e., 1 / 2 storage units) may together constitute one storage unit, and no specific limitation is given to this. It is understandable that in different semiconductor projects, the design may be performed according to actual needs, and the two sides of the row decoding circuit 23 arranged along the second direction may be two storage units or two 1 / 2 storage units.

[0066] It should be noted that, in the embodiment of the present disclosure, the storage unit can be represented by Bank, and 1 / 2 of the storage unit can be represented by Half Bank.

[0067] In some embodiments, the relative positions of the amplification control unit 234 and the pre-decoding unit 233 are as follows: Figure 1 As shown, the length of the amplification control unit 234 along the first direction is greater than the length of the pre-decoding unit 233 along the first direction.

[0068] It should be noted that, in the embodiment of the present disclosure, when the functions of the pre-decoding unit 233 are different, the number of pre-decoding units 233 included in the row decoding circuit 23 may be different. Specifically, when the pre-decoding unit 233 decodes the information of the storage group (the first storage group 211 or the second storage group 221), one storage group corresponds to one pre-decoding unit 233; when the pre-decoding unit 233 decodes the specific word line information, multiple storage groups share one pre-decoding unit 233. This embodiment is described by taking the row decoding circuit 23 including N first storage groups 211, N second storage groups 221 and N-1 pre-decoding units 233 as an example.

[0069] Furthermore, in some embodiments, Figure 1 As shown, the projection of one amplification control unit 234 along the second direction and the projection of two first storage groups 211 along the second direction have overlapping parts, so that the two first storage groups 211 share the adjacent amplification control unit 234;

[0070] Furthermore, there are overlapped portions between the projection of one amplification control unit 234 along the second direction and the projections of two second storage groups 221 along the second direction, so that the two second storage groups 221 share the adjacent amplification control unit 234 .

[0071] That is, each first storage group 211 needs to use two amplification control units 234, and the two amplification control units 234 are used to read and amplify signals from odd bit lines and even bit lines, respectively. Similarly, each second storage group 221 needs to use two amplification control units 234, and the two amplification control units 234 are used to read and amplify signals from odd bit lines and even bit lines, respectively.

[0072] Furthermore, in some embodiments, for the selection control unit 231, Figure 1 Based on the semiconductor structure 20 shown, see Figure 2 Each selection control unit may include a word line driving unit 2311 and a block decoding unit 2312, wherein:

[0073] A first storage group 211, a word line driving unit 2311, a block decoding unit 2312, a row redundancy unit 232, another block decoding unit 2312, another word line driving unit 2311 and a second storage group 221 are arranged in sequence along the second direction.

[0074] It can be understood that the selection control unit includes a word line driving unit 2311 and a block decoding unit 2312 arranged along the second direction, and the word line driving unit 2311 is located on a side of the block decoding unit 2312 close to the storage group (the first storage group 211 or the second storage group 221). That is, for the first storage group 211, one first storage group 211, one word line driving unit 2311 and one block decoding unit 2312 are arranged in sequence along the second direction; for the second storage group 221, another block decoding unit 2312, another word line driving unit 2311 and one second storage group 221 are arranged in sequence along the second direction.

[0075] It should be noted that, in the embodiment of the present disclosure, the word line driver unit 2311 can be represented by FXT (Wordline Driver), and the block decoding unit 2312 can be represented by RMS (Block Decoder).

[0076] In some embodiments, Figure 2 As shown, in the first direction, a portion of each amplifying control unit 234 is located between two adjacent word line driving units 2311 , and the remaining portion of the amplifying control unit 234 is located between two adjacent block decoding units 2312 .

[0077] That is, the length of the amplification control unit 234 along the second direction is equal to the sum of the lengths of the word line driving unit 2311 and the block decoding unit 2312 along the second direction, that is, the length of the amplification control unit 234 along the second direction is equal to the length of the selection control unit along the second direction.

[0078] Furthermore, in some embodiments, Figure 2 As shown, the length of the first storage group 211 along the first direction is greater than the length of the row redundant unit 232 along the first direction, and the length of the second storage group 221 along the first direction is greater than the length of the row redundant unit 232 along the first direction;

[0079] The length of the row redundancy unit 232 along the second direction is greater than the length of the block decoding unit 2312 along the second direction, and the length of the row redundancy unit 232 along the second direction is greater than the length of the word line driving unit 2311 along the second direction.

[0080] It should be noted that in the embodiment of the present disclosure, the length of the first storage group 211 along the first direction may be equal to or unequal to the length of the second storage group 221 along the first direction, and there is no specific limitation on this, but both are greater than the length of the row redundancy unit 232 along the first direction.

[0081] It should also be noted that, in the embodiment of the present disclosure, the length of the row redundant unit 232 along the second direction may be greater than the length of the selection control unit along the second direction, or may be less than the length of the selection control unit along the second direction, and no specific limitation is made to this. However, the length of the row redundant unit 232 along the second direction is respectively greater than the length of the word line driving unit 2311 and the block decoding unit 2312 constituting the selection control unit along the second direction.

[0082] Furthermore, in some embodiments, Figure 2 As shown, the row decoding circuit 23 may further include 2N main word line driving units 235, wherein:

[0083] A first storage group 211, a main word line driver unit 235, a word line driver unit 2311, a block decoding unit 2312, a row redundancy unit 232, another block decoding unit 2312, another word line driver unit 2311, another main word line driver unit 235 and a second storage group 221 are arranged in sequence along the second direction.

[0084] It should be noted that, in the embodiment of the present disclosure, the main wordline driver unit 235 can be represented by XDEC (Main Wordline Driver).

[0085] It should be noted that, in the embodiment of the present disclosure, among the 2N main word line driving units 235, N main word line driving units 235 are close to the first storage group 211, and N main word line driving units 235 are close to the second storage group 221, and each main word line driving unit 235 respectively implements a function for the first storage group 211 or the second storage group 221 close to it. It can be understood that the specific internal structures of the main word line driving units 235 close to the first storage group 211 and the main word line driving units 235 close to the second storage group 221 can be arranged in a mirror distribution along a symmetry axis parallel to the first direction, and no specific limitation is made to this.

[0086] It should also be noted that in the embodiments of the present disclosure, Figure 2 As shown, the main word line driving unit 235 may be close to the first storage group 211 or the second storage group 221, or may be at a certain distance from the first storage group 211 or the second storage group 221 along the second direction, which is not specifically limited. In addition, the length of the main word line driving unit 235 along the first direction may be consistent with the length of the first storage group 211 along the first direction or the length of the second storage group 221 along the first direction, which is not specifically limited.

[0087] In some embodiments, see Figure 3 , the row decoding circuit 23 may further include two buffer driving units 236;

[0088] In the first direction, the first buffer driving unit 236 is located at a side of the first row redundant unit 232 away from the pre-decoding unit 233, and the second buffer driving unit 236 is located at a side of the Nth row redundant unit 232 away from the pre-decoding unit 233;

[0089] The row decoding circuit 23 is used to decode the row address signal, and the buffer driving unit 236 is used to drive and enhance the row address signal.

[0090] It should be noted that in Figure 3 , i represents any one of the N first storage groups 211 and any one of the N second storage groups 221, and i is an integer greater than 0 and less than or equal to N. It can be understood that the first row redundancy unit 232 corresponds to the first first storage group 211 and the first second storage group 221, and the Nth row redundancy unit 232 corresponds to the Nth first storage group 211 and the Nth second storage group 221.

[0091] It should also be noted that, in the embodiment of the present disclosure, the buffer driving unit 236 can be represented by a Repeater.

[0092] It should also be noted that in the embodiment of the present disclosure, the buffer driving unit 236 is located on both sides of the row decoding circuit 23. Since the row address signal needs to be transmitted to each pre-decoding unit 233 and the transmission distance is very far, the buffer driving unit 236 is required to drive and enhance the row address signal.

[0093] It should also be noted that when data is to be written into a storage cell in the storage array, or when data is to be read from a storage cell, the addressing of the storage cell must be completed first. The addressing process first inputs the corresponding row address signal and column address signal of the storage cell to be operated into the row address buffer and the column address buffer, and then selects a specific row address line through the row decoding circuit to activate a specific row address; wherein each row address line is connected to multiple column address lines and multiple storage cells, and in order to detect the weak activation signal on the column address line, a sensitive amplifier is required to amplify the signal; when the row is activated, the column address signal in the column address buffer determines the column address through the column decoding circuit, and is amplified by the corresponding sensitive amplifier and connected to the local data line, so that the storage cell is activated and can be used for read and write operations, and the addressing is completed. In this way, because the row decoding circuit 23 includes a buffer driver unit 236, the signal integrity can be guaranteed, thereby improving the performance of the row decoding circuit 23.

[0094] Furthermore, in some embodiments, for the row redundancy unit 232, Figure 3 Based on the semiconductor structure 20 shown, see Figure 4 , the row redundancy unit may include a redundancy matching unit 2321 and a redundancy address encoding unit 2322 arranged along the second direction, wherein:

[0095] The redundant matching unit 2321 is located at a side of the redundant address encoding unit 2322 away from the first storage group 211 .

[0096] It should be noted that, in the embodiment of the present disclosure, the redundant matching unit 2321 can be represented by RRED (Row Redundancy), and the redundant address encoding unit 2322 can be represented by R_REDOR (Redundancy Encoder).

[0097] It is understandable that there are usually redundant memory cells on the memory chip, and these redundant memory cells can replace the defective memory cells when the memory chip generates defective memory cells to achieve the purpose of repairing the memory chip. Here, the redundant matching unit 2321 has multiple redundant tables that can be used to repair the damaged storage rows. When one of the redundant rows successfully matches the current address signal, it is necessary to provide the information of the repaired new row address (i.e., the repair address signal). In this way, it is necessary to set the redundant address encoding unit 2322 to determine which redundant row the damaged storage row is relocated to and provide the information of the repair address signal.

[0098] Regarding the functions of each functional unit in the row decoding circuit 23, in some embodiments, the redundant matching unit is configured to receive an initial address signal and determine whether the initial address signal has been processed for redundant repair; if the initial address signal has not been processed for redundant repair, the initial address signal is output as a row address signal; if the initial address signal has been processed for redundant repair, the repaired address signal is output as a row address signal.

[0099] It should be noted that the repair address signal indicates a redundant storage row used to repair the storage row corresponding to the initial address signal.

[0100] It should also be noted that, in the embodiment of the present disclosure, the redundant address encoding unit can be used to provide information of a repair address signal after the initial address signal has been subjected to a redundant repair process.

[0101] Furthermore, in some embodiments, the pre-decoding unit is connected to the redundant matching unit, and is configured to receive and perform a first decoding process on the row address signal, and output a decoding signal.

[0102] It should be noted that, in the embodiment of the present disclosure, after the redundant matching unit outputs the row address signal, the pre-decoding unit receives the row address signal and outputs a decoding signal to the main word line driving unit.

[0103] Further, in some embodiments, the main word line driving unit is connected to the pre-decoding unit, configured to receive and perform a second decoding process on the decoding signal, and output a plurality of control signals;

[0104] Wherein, a plurality of control signals respectively enter the word line driving unit, the block decoding unit and the amplification control unit.

[0105] It should be noted that in the embodiment of the present disclosure, after the pre-decoding unit outputs the decoding signal, the main word line driving unit receives the decoding signal and outputs multiple control signals to the word line driving unit, the block decoding unit and the amplification control unit respectively, to control these functional units respectively.

[0106] An embodiment of the present disclosure provides a semiconductor structure, which includes a first storage block, a second storage block and a row decoding circuit. The row decoding circuit architecture is fully functional, and the row redundancy unit and the pre-decoding unit in the row decoding circuit are arranged on the side close to the first storage group or the second storage group that is finally accessed, thereby reducing access delay and improving the performance of the row decoding circuit.

[0107] In another embodiment of the present disclosure, see Figure 5 , which shows a schematic diagram of a decoding process of a row decoding circuit provided by an embodiment of the present disclosure. Figure 5 As shown, the row address strobe (RAS) address is transmitted to the row decoding circuit, and the row decoding circuit may include a pre-decoding unit (PRE-DECODER), a subarray selection unit (For choose49Subarray), a sense amplifier selection unit (For SA Block), a main word line driver unit (For MWD Block) and a word line driver unit (For FXT / FXB Block). The subarray selection unit is used to output a subarray selection signal, and transmit the subarray selection signal to the sense amplifier selection unit, the main word line driver unit and the word line driver unit; the sense amplifier selection unit is used to output a sense amplifier selection signal; the main word line driver unit is used to output a main word line driver selection signal; and the word line driver unit is used to output a word line driver selection signal.

[0108] Here, the sense amplifier selection signal, the main word line drive selection signal and the word line drive selection signal respectively represent the signals output by the sense amplifier selection unit, the main word line drive unit and the word line drive unit after receiving the sub-array selection signal. Figure 5 Only the signals are shown, and the arrow directions of the signal transmission paths are not marked.

[0109] It should be noted that Figure 5 The decoding process of the row decoding circuit in the conventional memory size of 512 megabytes (Mbit, Mb) / 49 regions. It can be understood that Figure 5 The description is about the row address decoding process, specifically the pre-decoding unit and other functional units in the row decoding circuit and the address correspondence.

[0110] Furthermore, if Figure 6 As shown, the 512Mb memory is divided into two sub-memories, each sub-memory has a memory size of 256Mb, and a row decoding circuit is located between the two sub-memories. The row decoding circuit is used to control the entire memory.

[0111] It should be noted that the 512Mb memory may be a storage unit (Bank) in the aforementioned embodiment, and the two sub-memories are 1 / 2 storage units (Half Bank) respectively, and the two sub-memories together constitute a storage unit.

[0112] It should also be noted that the row decoding circuit here is the row decoding circuit 23 in the aforementioned embodiment.

[0113] In another embodiment of the present disclosure, see Figure 7 , which shows a schematic diagram of the composition structure of a memory provided by an embodiment of the present disclosure. Figure 7 As shown, the memory 30 includes the semiconductor structure 20 described in any one of the aforementioned embodiments.

[0114] In some embodiments, the semiconductor structure 20 can be applied to a semiconductor memory 30. The semiconductor memory 30 can be a synchronous dynamic random access memory (SDRAM) chip or a dynamic random access memory (DRAM) chip.

[0115] Furthermore, in some embodiments, for DRAM chips, not only can they comply with memory specifications such as DDR, DDR2, DDR3, DDR4, DDR5, DDR6, etc., but they can also comply with memory specifications such as LPDDR, LPDDR2, LPDDR3, LPDDR4, LPDDR5, LPDDR6, etc., and no specific limitation is made here.

[0116] It should be noted that the embodiments of the present disclosure relate to a memory, and in particular to an SDRAM chip. For the memory, a row decoding circuit with complete functions is provided by refining the design of the row decoding circuit.

[0117] In the embodiment of the present disclosure, for the memory 30, since it includes the semiconductor structure 20 described in the above embodiment, the row decoding circuit architecture is fully functional, and the access delay is reduced, thereby improving the performance of the row decoding circuit.

[0118] Details not disclosed in the embodiments of the present disclosure may be understood by referring to the description of the aforementioned embodiments.

[0119] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure.

[0120] It should be noted that in the present disclosure, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0121] The serial numbers of the above-mentioned embodiments of the present disclosure are only for description and do not represent the advantages or disadvantages of the embodiments.

[0122] The methods disclosed in several method embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0123] The features disclosed in several product embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments.

[0124] The features disclosed in several method or device embodiments provided in the present disclosure may be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0125] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A semiconductor structure, characterized in that: The semiconductor structure includes a first storage block, a second storage block and a row decoding circuit, and the first storage block, the row decoding circuit and the second storage block are arranged along a second direction; The first storage block includes N first storage groups arranged along a first direction, and the second storage block includes N second storage groups arranged along the first direction; The row decoding circuit includes 2N selection control units, N row redundancy units, N-1 pre-decoding units and 2×(N-1) amplification control units; Wherein, one of the first storage groups, one of the selection control units, one of the row redundant units, another of the selection control units and one of the second storage groups are arranged in sequence along the second direction; one of the amplification control units is arranged between every two of the selection control units, and one of the pre-decoding units is arranged between every two of the row redundant units; Wherein, N is an integer greater than 0, and the first direction and the second direction are perpendicular to each other.

2. The semiconductor structure according to claim 1, characterized in that: Each of the selection control units comprises a word line driving unit and a block decoding unit, wherein: One of the first storage groups, one of the word line driving units, one of the block decoding units, one of the row redundancy units, another of the block decoding units, another of the word line driving units and one of the second storage groups are arranged in sequence along the second direction.

3. The semiconductor structure according to claim 2, characterized in that: In the first direction, a portion of each of the amplifying control units is located between two adjacent word line driving units, and the remaining portion of the amplifying control unit is located between two adjacent block decoding units.

4. The semiconductor structure according to claim 3, characterized in that: The length of the first storage group along the first direction is greater than the length of the row redundancy unit along the first direction, and the length of the second storage group along the first direction is greater than the length of the row redundancy unit along the first direction; The length of the row redundancy unit along the second direction is greater than the length of the block decoding unit along the second direction, and the length of the row redundancy unit along the second direction is greater than the length of the word line driving unit along the second direction.

5. The semiconductor structure according to claim 1, characterized in that: The length of the amplification control unit along the first direction is greater than the length of the pre-decoding unit along the first direction.

6. The semiconductor structure according to claim 1, characterized in that A projection of one of the amplification control units along the second direction overlaps with projections of two of the first storage groups along the second direction, so that the two first storage groups share the adjacent amplification control unit; Furthermore, there are overlapping parts between the projection of one amplification control unit along the second direction and the projections of two second storage groups along the second direction, so that the two second storage groups share the adjacent amplification control unit.

7. The semiconductor structure according to claim 2, characterized in that: The row decoding circuit further includes 2N main word line driving units, wherein: One of the first storage groups, one of the main word line driving units, one of the word line driving units, one of the block decoding units, one of the row redundancy units, another of the block decoding units, another of the word line driving units, another of the main word line driving units and one of the second storage groups are arranged in sequence along the second direction.

8. The semiconductor structure according to claim 7, characterized in that: The row decoding circuit also includes two buffer driving units; In the first direction, the first buffer driving unit is located at a side of the first row redundant unit away from the pre-decoding unit, and the second buffer driving unit is located at a side of the Nth row redundant unit away from the pre-decoding unit; The row decoding circuit is used to decode the row address signal, and the buffer driving unit is used to drive and enhance the row address signal.

9. The semiconductor structure according to claim 8, characterized in that: The row redundancy unit comprises a redundancy matching unit and a redundancy address encoding unit arranged along the second direction, wherein: The redundant matching unit is located at a side of the redundant address encoding unit away from the first storage group.

10. The semiconductor structure according to claim 1, characterized in that The first storage block is a storage unit, and the second storage block is another storage unit; or, The first storage block is a 1 / 2 storage unit, the second storage block is a 1 / 2 storage unit, and the first storage block and the second storage block together constitute a storage unit.

11. The semiconductor structure according to claim 9, characterized in that: The redundant matching unit is configured to receive an initial address signal and determine whether the initial address signal has been subjected to redundant repair processing; if the initial address signal has not been subjected to redundant repair processing, output the initial address signal as the row address signal; if the initial address signal has been subjected to redundant repair processing, output the repair address signal as the row address signal; The repair address signal indicates a redundant storage row used to repair the storage row corresponding to the initial address signal.

12. The semiconductor structure according to claim 11, characterized in that: The pre-decoding unit is connected to the redundant matching unit, and is configured to receive and perform a first decoding process on the row address signal, and output a decoding signal.

13. The semiconductor structure according to claim 12, characterized in that: The main word line driving unit is connected to the pre-decoding unit and is configured to receive and perform a second decoding process on the decoding signal and output a plurality of control signals; The plurality of control signals respectively and correspondingly enter the word line driving unit, the block decoding unit and the amplification control unit.

14. A memory, characterized in that: The memory comprises the semiconductor structure according to any one of claims 1 to 13.

15. The memory according to claim 14, characterized in that: The memory is a synchronous dynamic random access memory SDRAM chip or a dynamic random access memory DRAM chip.

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