Dual-port storage and calculation integrated unit circuit and dual-port storage and calculation integrated array circuit

Abstract

The embodiment of the invention discloses a dual-port storage and calculation integrated unit circuit, a dual-port storage and calculation integrated array circuit, a chip and electronic equipment, and the dual-port storage and calculation integrated unit circuit comprises two storage units, a write selection unit, a calculation selection unit and a calculation unit. The write selection unit selects an input data storage unit from the two storage units according to an input write selection signal, and stores the weight data into the input data storage unit; the calculation selection unit selects a calculation data storage unit from the two storage units according to an input calculation selection signal; and the calculation unit receives the weight data output from the calculation data storage unit, calculates the weight data with the to-be-calculated data, and outputs a calculation result. According to the embodiment of the invention, when the weight data is written into one part of the storage units in the storage and calculation array, the stored weight data is extracted from the other part of the storage units and is calculated with the input to-be-calculated data, so that the calculation efficiency is greatly improved.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuit design, and in particular to a dual-port storage-computing integrated unit circuit, a dual-port storage-computing integrated array circuit, a chip and an electronic device. Background Art

[0002] Computing-in-Memory (CIM) refers to the technology of combining computing with storage and directly embedding algorithms inside the memory. Simply put, it is to operate the data input into the neural network with the weight parameters pre-stored in the memory unit to realize the weighted accumulation of the input data, which is the convolution operation. The convolution operation is the core component unit of the deep learning algorithm and accounts for more than 90% of the operations in most current artificial intelligence (AI) chips. This means that through the new architecture of computing-in-memory, 90% or even more of the operations can be completed and output directly by the memory.

[0003] The integration of storage and computing solves the long-standing problems of "storage wall" and "power consumption wall", completely eliminates memory access delays, and greatly reduces data transfer power consumption, resulting in ultra-high computing power and energy efficiency. It is an architecture that is more suitable for AI computing than the von Neumann architecture.

[0004] The common storage-computing-in-memory is generally a single-port computing-computing-in-memory (SP-CIM), that is, one port is provided to access the memory. This architecture provides a clock and a set of address signal lines. When writing is enabled and calculation is disabled, CIM enters write mode, and controls the order of writing weight data and determines the address of writing weight data through the clock and the above set of address signal lines, so as to perform regular write operations; when calculation is enabled and writing is disabled, CIM enters calculation mode, and controls the order of calculation and determines the address of weight data involved in the calculation through the clock and the above set of address signal lines, and controls the order of data input into the neural network through the clock, so that the data input into the neural network is calculated with the weight data pre-stored in the CIM and the result is output.

[0005] In the calculation of neural networks, data processing is mainly performed in the form of a matrix rather than a single row or column. Each write operation can only write one row of weight data, which means that before the calculation, at least Y write operations are required to ensure that the storage cell array in the CIM is filled with weight data, where Y is the total number of rows in the storage cell array.

[0006] However, SP-CIM has only one port and cannot support simultaneous writing and computing operations. Writing a large amount of data to SP-CIM takes a long time, and the long writing time will interrupt the computing process. Therefore, SP-CIM cannot maintain peak computing power for a long time, which in turn affects the final computing efficiency. Summary of the invention

[0007] An embodiment of the present disclosure provides a dual-port storage and computing unit circuit, which includes: two storage units, a write selection unit, a calculation selection unit and a calculation unit; the write selection unit is used to select a storage unit from the two storage units as an input data storage unit according to an input write selection signal, and store the currently input weight data into the input data storage unit; the calculation selection unit is used to select a storage unit from the two storage units as a calculation data storage unit according to an input calculation selection signal; the calculation unit is used to calculate the weight data stored in the calculation data storage unit and the input data to be calculated, obtain the calculation result and output the calculation result.

[0008] In some embodiments, the calculation selection unit includes a first control switch and a second control switch; the first control switch is used to receive a calculation selection signal, and when the calculation selection signal is a first signal, the first weight data in the calculation data storage unit corresponding to the first signal is input into the calculation unit; the second control switch is used to receive a calculation selection signal, and when the calculation selection signal is a second signal, the second weight data in the calculation data storage unit corresponding to the first signal is input into the calculation unit.

[0009] In some embodiments, the calculation unit includes a multiplier for receiving input data to be calculated, and performing multiplication calculation on the data to be calculated using the first weight data or the second weight data and outputting the result.

[0010] In some embodiments, the first inverter is used to invert the first weight data when the calculation selection signal is the first signal, obtain the first inverted weight data, and input the first inverted weight data into the NOR gate; the second inverter is used to invert the second weight data when the calculation selection signal is the second signal, obtain the second inverted weight data, and input the second inverted weight data into the NOR gate; the third inverter is used to invert the data to be calculated to obtain the inverted data to be calculated; the NOR gate is used to perform an NOR operation on the inverted data to be calculated and the input first inverted weight data when the calculation selection signal is the first signal, and output the multiplication result of the data to be calculated and the first weight data; when the calculation selection signal is the second signal, perform an NOR operation on the inverted data to be calculated and the input second inverted weight data, and output the multiplication result of the data to be calculated and the second weight data.

[0011] In some embodiments, the first control switch includes a first switch element and a second switch element, the first switch element is used to connect the first inverter to the level representing the first data when the calculation selection signal is the first signal, and the second switch element is used to connect the first inverter to the level representing the second data when the calculation selection signal is the first signal; the second control switch includes a third switch element and a fourth switch element, the third switch element is used to connect the second inverter to the level representing the first data when the calculation selection signal is the second signal, and the fourth switch element is used to connect the second inverter to the level representing the second data when the calculation selection signal is the second signal.

[0012] In some embodiments, the calculation unit is further used to: generate a read control signal in response to receiving a read data mode selection signal; and output the weight data stored in the storage unit currently selected by the calculation selection unit based on the read control signal.

[0013] According to another aspect of the embodiments of the present disclosure, a dual-port storage and computing integrated array circuit is provided, which includes: a controller and a dual-port storage and computing module array; the dual-port storage and computing module array includes a first preset number of dual-port storage and computing module groups, each dual-port storage and computing module group includes a second preset number of dual-port storage and computing modules, and each dual-port storage and computing module includes the above-mentioned dual-port storage and computing integrated unit circuit; the controller is used to send a write selection signal to the write selection unit included in each dual-port storage and computing module, and the write selection unit stores the input weight data into the input data storage unit corresponding to the write selection signal; the controller is also used to send a calculation selection signal to the calculation selection unit included in each dual-port storage and computing module, and the calculation selection unit selects the calculation data storage unit for calculation with the input data to be calculated, and the corresponding calculation unit calculates the data to be calculated and the weight data output by the calculation data storage unit to obtain a calculation result.

[0014] In some embodiments, the circuit also includes an addition tree and a shift accumulator; the addition tree is used to accumulate the calculation results output by the dual-port storage and computing modules located at the same position in each dual-port storage and computing module group to obtain a first accumulation result; the shift accumulator is used to shift and accumulate each first accumulation result to obtain a second accumulation result.

[0015] In some embodiments, the circuit also includes a first preset number of word line groups, each of the first preset number of word line groups corresponds to a dual-port storage and computing module group, and each word line group includes a first word line and a second word line; for each dual-port storage and computing module group in the first preset number of dual-port storage and computing module groups, the word line group corresponding to the dual-port storage and computing module group includes a first word line and a second word line, and the first word line and the second word line respectively correspond to a first storage unit and a second storage unit included in each dual-port storage and computing module in the dual-port storage and computing module group; the write selection unit included in each dual-port storage and computing module in the dual-port storage and computing module group is further used to: select a target word line from the first word line and the second word line included in the word line group corresponding to the dual-port storage and computing module group according to the received write selection signal, and store the input weight data in the storage unit corresponding to the target word line.

[0016] According to another aspect of the embodiments of the present disclosure, a chip is provided, which includes the above-mentioned dual-port storage-computation-in-one unit circuit or dual-port storage-computation-in-one array circuit.

[0017] According to another aspect of an embodiment of the present disclosure, an electronic device is provided, the electronic device comprising the above chip.

[0018] The dual-port storage and calculation integrated unit circuit and dual-port storage and calculation integrated array circuit, chip and electronic device provided by the above embodiments of the present disclosure are provided with two storage units, a write selection unit, a calculation selection unit and a calculation unit in the basic dual-port storage and calculation module. The write selection unit selects the input data storage unit from the two storage units according to the input write selection signal, and stores the weight data in the input data storage unit. The calculation selection unit selects the calculation data storage unit from the two storage units according to the input calculation selection signal. The calculation unit calculates the weight data in the calculation data storage unit and the input data to be calculated, and outputs the calculation result. The circuit provided by the embodiment of the present disclosure can simultaneously perform data writing operation and data calculation operation on two storage units respectively. Compared with the existing single-port storage and calculation integrated memory, while writing weight data to a part of the storage units in the storage and calculation array, the stored weight data can be extracted from another part of the storage units and the input data to be calculated for calculation, so that the writing of weight data and the calculation using weight data are independent and do not interfere with each other, and the calculation efficiency is greatly improved. The circuit has a longer peak computing power retention time, a higher effective computing power, a more flexible design space and a wider range of applications.

[0019] The technical solution of the present disclosure is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The above and other purposes, features and advantages of the present disclosure will become more apparent by describing the embodiments of the present disclosure in more detail in conjunction with the accompanying drawings. The accompanying drawings are used to provide a further understanding of the embodiments of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the present disclosure and do not constitute a limitation of the present disclosure. In the drawings, the same reference numerals generally represent the same components or steps;

[0021] Figure 1 is a structural schematic diagram of a dual-port storage-computation-in-one unit circuit provided by an exemplary embodiment of the present disclosure;

[0022] Figure 2 is another structural schematic diagram of a dual-port storage-computation-in-one unit circuit provided by an exemplary embodiment of the present disclosure;

[0023] Figure 3 is an exemplary structural diagram of a calculation selection unit and a calculation unit provided by an exemplary embodiment of the present disclosure;

[0024] Figure 4 is another exemplary structural diagram of a calculation selection unit and a calculation unit provided by an exemplary embodiment of the present disclosure;

[0025] Figure 5 It is a structural diagram of a dual-port storage-computation-in-one array circuit provided by an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0026] Below, the exemplary embodiments according to the present disclosure will be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments of the present disclosure, and it should be understood that the present disclosure is not limited to the exemplary embodiments described here.

[0027] It should be noted that the relative arrangement of components and steps, the numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present disclosure unless specifically stated otherwise.

[0028] Those skilled in the art can understand that the terms "first" and "second" in the embodiments of the present disclosure are only used to distinguish different steps, devices or modules, etc., and neither represent any specific technical meaning nor indicate the necessary logical order between them.

[0029] It should also be understood that in the embodiments of the present disclosure, “plurality” may refer to two or more than two, and “at least one” may refer to one, two, or more than two.

[0030] It should also be understood that any component, data or structure mentioned in the embodiments of the present disclosure can generally be understood as one or more, unless explicitly limited or otherwise indicated in the context.

[0031] In addition, the term "and / or" in the present disclosure is only a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in the present disclosure generally indicates that the associated objects before and after are in an "or" relationship.

[0032] It should also be understood that the description of the various embodiments in the present disclosure focuses on the differences between the various embodiments, and the same or similar aspects thereof can be referenced to each other, and for the sake of brevity, they will not be described one by one.

[0033] At the same time, it should be understood that for the convenience of description, the sizes of the various parts shown in the drawings are not drawn according to the actual proportional relationship.

[0034] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the present disclosure, its application, or uses.

[0035] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered as part of the specification.

[0036] It should be noted that like reference numerals and letters refer to similar items in the following figures, and therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0037] Application Overview

[0038] In order to solve the problem of computing efficiency bottleneck in the current single-port storage and computing integrated memory, the embodiments of the present invention provide a dual-port storage and computing integrated unit circuit and a dual-port storage and computing integrated array circuit. The dual-port storage and computing integrated unit circuit is the basic storage and computing module of the dual-port storage and computing integrated array circuit. The basic storage and computing module is composed of two storage units, a write selection unit, a calculation selection unit, and a calculation unit. Through the write selection unit and the calculation selection unit, the two storage units can perform data writing operations and data calculation operations at the same time. Compared with the existing single-port storage and computing integrated memory, the circuit provided by the embodiments of the present invention can write weight data to a part of the storage units in the storage and computing array while extracting the stored weight data from another part of the storage units to perform operations on the input data to be calculated, thereby achieving the writing and calculation of weight data independently and without interfering with each other. The circuit has a longer peak computing power retention time, higher effective computing power, more flexible design space and a wider range of applications.

[0039] Exemplary Structure

[0040] Figure 1The schematic diagram is a schematic diagram of a dual-port storage-computation-in-one unit circuit provided by an exemplary embodiment of the present disclosure. The various components included in the circuit can be integrated into one chip, or can be set in different chips or circuit boards, and data communication links are established between these chips or circuit boards.

[0041] like Figure 1 As shown, the circuit includes: two storage units 101 , a write selection unit 102 , a calculation selection unit 103 , and a calculation unit 104 .

[0042] In this embodiment, the write selection unit 102 is used to select a storage unit from the two storage units 101 as an input data storage unit according to the input write selection signal, and store the weight data in the input data storage unit. Generally, the circuit provided in this embodiment can be applied in a neural network accelerator, so the weight data can be a weight parameter involved in the calculation in the neural network.

[0043] The two storage units 101 are usually used to store single bits included in the input multi-bit weight data, and the single bits are the weight data described above. The dual-port storage-computation-integrated unit circuit provided in this embodiment can usually constitute a storage-computation-integrated module in a storage-computation-integrated array. Figure 1 As shown, WD ij is the input single-bit weight data, i and j represent the position of the storage-computation-integrated module formed by the dual-port storage-computation-integrated unit circuit in the storage-computation-integrated array, i is the row number, and j is the column number. Figure 1 When the first storage unit 1011 in is an input data storage unit, the single-bit weight data input to the first storage unit 1011 is represented as WD ij [0], when the write selection unit 102 selects Figure 1 When the second storage unit 1012 in FIG. 1 is an input data storage unit, the single-bit weight data input to the second storage unit 1012 is represented as WD ij [1].

[0044] The write selection unit 102 may be implemented by using a device such as a transistor, for example, an analog switch device, and the state of the analog switch device may be changed by changing the write selection signal. Figure 1 As shown, the write selection signal is represented by WRT_MUX_SEL, and WRT_MUX_SELB is the inversion of WRT_MUX_SEL. When WRT_MUX_SEL is 1 and WRT_MUX_SELB is 0, the write selection signal will be WD ij When the first storage unit 1011 is input, WRT_MUX_SEL is 0 and WRT_MUX_SELB is 1, the write selection signal WD ijInput second storage unit 1012.

[0045] In this embodiment, the calculation selection unit 103 is used to select one storage unit from the two storage units 101 as a calculation data storage unit according to an input calculation selection signal.

[0046] Specifically, the calculation selection unit 103 can realize its function by a device such as a transistor. For example, the calculation selection unit 103 can be a switch simulating a single-pole double-throw, and the storage unit connected to the input end of the calculation unit 104 is switched by changing the calculation selection signal. Figure 1 As shown, the calculation selection signal is represented by CIM_MUX_SEL, and CIM_MUX_SELB is the inversion of CIM_MUX_SEL. When CIM_MUX_SEL is 1 and CIM_MUX_SELB is 0, the first storage unit 1011 is a calculation data storage unit, and the calculation selection unit 103 inputs the weight data Bit0 stored in the first storage unit 1011 into the calculation unit 104. When CIM_MUX_SEL is 0 and CIM_MUX_SELB is 1, the calculation selection signal inputs the weight data Bit1 stored in the second storage unit 1012 into the calculation unit 104.

[0047] The data to be calculated can be data to be used in the neural network to be used for calculation with the weight data, for example, text data, image data, audio data, video data, and feature data obtained by extracting features from the above data. Usually, the data to be calculated is single-bit data, for example, the data to be calculated can be a bit included in the multi-bit feature data in the neural network. Figure 1 As shown, NN j The data to be calculated is currently being calculated.

[0048] In this embodiment, the calculation unit 104 is used to calculate the weight data stored in the calculation data storage unit and the input data to be calculated, obtain the calculation result and output the calculation result.

[0049] like Figure 1 As shown, the calculation unit 104 calculates the input data NN to be calculated. j The weight data Bit output by the storage unit selected for calculation by the calculation selection unit 103 is calculated and the calculation result is output.

[0050] The calculation unit 104 can be set according to the application scenario of the dual-port storage-calculation unit circuit. For example, the calculation unit 104 can be a multiplier, a NOR gate, etc. Generally, when the dual-port storage-calculation unit circuit provided in this embodiment is used for the operation of a neural network, the calculation result output by the calculation unit 104 is the product of the data to be calculated and the weight data.

[0051] The circuit provided by the above-mentioned embodiment of the present disclosure sets two storage units, a write selection unit, a calculation selection unit, and a calculation unit in a basic dual-port storage and calculation module. The write selection unit selects the input data storage unit from the two storage units according to the input write selection signal, and stores the weight data in the input data storage unit. The calculation selection unit selects the calculation data storage unit from the two storage units according to the input calculation selection signal. The calculation unit calculates the weight data in the calculation data storage unit and the input data to be calculated, and outputs the calculation result. The circuit provided by the embodiment of the present disclosure can simultaneously perform data writing operations and data calculation operations on two storage units respectively. Compared with the existing single-port storage and calculation integrated memory, while writing weight data to a part of the storage units in the storage and calculation array, the stored weight data can be extracted from another part of the storage units and the input data to be calculated for calculation, and the writing of weight data and the calculation using weight data are realized independently and do not interfere with each other, and the calculation efficiency is greatly improved. The circuit has a longer peak computing power retention time, a higher effective computing power, a more flexible design space and a wider range of applications.

[0052] In some optional implementations, such as Figure 2 As shown, the calculation selection unit 103 includes a first control switch 1031 and a second control switch 1032 .

[0053] The first control switch 1031 is used to receive a calculation selection signal, and when the calculation selection signal is a first signal, input the first weight data in the calculation data storage unit corresponding to the first signal into the calculation unit 104 .

[0054] The second control switch 1032 is used to receive a calculation selection signal, and when the calculation selection signal is a second signal, input the second weight data in the calculation data storage unit corresponding to the second signal into the calculation unit 104 .

[0055] like Figure 2 As shown, Bit0 is the first weight data output by the first storage unit 1011, and Bit1 is the second weight data output by the second storage unit 1012. When the calculation selection signal is the first signal (e.g., "1"), the first control switch 1031 can input Bit0 into the calculation unit 104. When the calculation selection signal is the second signal (e.g., "0"), the second control switch 1032 can input Bit1 into the calculation unit 104.

[0056] The first control switch 1031 and the second control switch 1032 can be implemented by using devices such as transistors, and the first control switch 1031 and the second control switch 1032 can be turned on or off according to the calculation selection signal. Generally, the first control switch 1031 and the second control switch 1032 perform opposite operations under the same calculation selection signal. For example, when the calculation selection signal is the first signal (e.g., "1"), the first control switch 1031 inputs Bit0 into the calculation unit 104, and the second control switch 1032 is turned off; when the calculation selection signal is the second signal (e.g., "0"), the second control switch 1032 inputs Bit1 into the calculation unit 104, and the first control switch 1031 is turned off. In this way, only one storage unit can be selected to participate in the calculation at the same time, and the storage unit that does not participate in the calculation can receive the weight data stored therein.

[0057] This embodiment achieves simple and efficient switching of the data to be calculated by setting the first control switch and the second control switch in the calculation selection unit, and flexibly selects the storage unit participating in the calculation from multiple storage units, which helps to efficiently calculate the weight data in a part of the storage units in the storage and calculation array while writing data to another part of the storage units, thereby improving the flexibility of circuit configuration and operating efficiency.

[0058] In some optional implementations, the calculation unit 104 includes a multiplier for receiving input data to be calculated, performing multiplication calculation on the data to be calculated using the input first weight data or second weight data, and outputting the multiplication result.

[0059] This embodiment does not limit the implementation method of the multiplier. For example, the multiplication calculation can be implemented by an AND gate, or by a combination of a NOT gate and a NOR gate. By setting the computing unit as a multiplier, the circuit can be applied to processes such as convolution operations of a neural network, which helps to improve the computing efficiency of the neural network accelerator.

[0060] In some optional implementations, such as Figure 2 As shown, the calculation unit 104 includes a first inverter 1041 , a second inverter 1042 , a third inverter 1043 , and a NOR gate 1044 .

[0061] The first inverter 1041 is used for performing an inversion operation on the first weight data to obtain first inverted weight data when the calculation selection signal is the first signal, and inputting the first weight data into the NOR gate 1044 .

[0062] The second inverter 1042 is used for performing an inversion operation on the second weight data to obtain second inverted weight data when the calculation selection signal is the second signal, and inputting the second weight data into the NOR gate 1044 .

[0063] The third inverter 1043 is used to perform an inversion operation on the data to be calculated to obtain inverted data to be calculated.

[0064] The NOR gate 1044 is used to perform a NOR operation on the inverted data to be calculated and the input first inverted weight data when the calculation selection signal is the first signal, and output the multiplication result of the data to be calculated and the first weight data; when the calculation selection signal is the second signal, perform a NOR operation on the inverted data to be calculated and the input second inverted weight data, and output the multiplication result of the data to be calculated and the second weight data.

[0065] like Figure 2 As shown, the first control switch 1031 can control the first inverter 1041 to output the data Bitb inverted for Bit0 when the calculation selection signal CIM_MUX_SEL is the first signal (e.g., "1"). The second control switch 1032 can control the second inverter 1042 to output the data Bitb inverted for Bit1 when the calculation selection signal CIM_MUX_SEL is the second signal (e.g., "0").

[0066] Generally, the first control switch 1031 and the second control switch 1032 perform opposite operations under the same calculation selection signal. For example, when the calculation selection signal is "1", the first control switch 1031 enables the first inverter 1041, and the second control switch 1032 disables the second inverter 1042. When the calculation selection signal is "0", the first control switch 1031 disables the first inverter 1041, and the first inverter 1041 is disabled.

[0067] like Figure 2 As shown, the third inverter 1043 receives the input data NN to be calculated. j Take the inverse and get NN j b, NOR gate 1044 to NN j b and Bitb are OR-not operated, and the output data is NN j The product of Bit0 or Bit1.

[0068] Optionally, the third inverter 1043 can be in the same preset space as the first inverter 1041, the second inverter 1042, and the NOR gate 1044 included in the computing unit 104, or can be outside the preset space, that is, the third inverter 1043 can maintain a certain distance from other components of the dual-port storage and computing unit circuit of this embodiment, thereby facilitating the arrangement of components.

[0069] This embodiment realizes multiplication of the weight data stored in the currently selected storage unit participating in the operation with the data to be calculated under the control of the first control switch and the second control switch by setting the first inverter, the second inverter, the third inverter, and the NOR gate in the calculation unit. The circuit structure and function implementation are simpler, which helps to improve the efficiency of circuit configuration, reduce the cost of circuit implementation, and reduce the complexity of circuit operation. At the same time, multiplication calculation is performed by inverters and NOR gates, which can increase the swing of the level of weight data and data to be calculated, and improve the accuracy of calculation.

[0070] In some optional implementations, the first control switch 1031 includes a first switch element and a second switch element, the first switch element is used to connect the first inverter 1041 to the level representing the first data when the calculation selection signal is the first signal, and the second switch element is used to connect the first inverter 1041 to the level representing the second data when the calculation selection signal is the first signal.

[0071] The second control switch 1032 includes a third switch element and a fourth switch element. The third switch element is used to connect the second inverter 1042 to the level representing the first data when the calculation selection signal is the second signal, and the fourth switch element is used to connect the second inverter 1042 to the level representing the second data when the calculation selection signal is the second signal.

[0072] like Figure 3As shown, it shows an exemplary structural diagram of a calculation selection unit 103 and a calculation unit 104, the first inverter 1041 includes P2 and N1, the second inverter 1042 includes P4 and N3, the first control switch 1031 includes a first switch element and a second switch element, respectively, P1 and N2, and the second control switch 1032 includes a third switch element and a fourth switch element, respectively, P3 and N4. P1, P2, P3, and P4 are P-type MOS tubes, and N1, N2, N3, and N4 are N-type MOS tubes. Assume that the first signal is "1" (corresponding to the high level VDD), the first data is "1" (corresponding to the high level), and the second data is "0" (corresponding to the low level GND), that is, when CIM_MUX_SEL is 1, CIM_MUX_SELB is 0, at this time P1 and N2 are both turned on, P3 and N4 are both turned off, that is, P2 and N1 included in the first inverter 1041 are enabled, and P4 and N3 included in the second inverter 1042 are prohibited from outputting data, and the output Bitb is the inverted data of Bit0 (the first inverted weight data). Similarly, let the second signal be "0" (corresponding to a low level), that is, when CIM_MUX_SEL is 0, CIM_MUX_SELB is 1. At this time, P3 and N4 are both turned on, and P1 and N2 are both turned off. This enables P4 and N3 included in the second inverter 1042, and prohibits P2 and N1 included in the first inverter 1041 from outputting data. The output Bitb is the inverted data of Bit1 (the second inverted weight data). Bitb is connected to NN output by the third inverter (not shown in the figure). j b input NOR gate 1044.

[0073] It should be understood that Figure 3 The types and positions of the first switch element, the second switch element, the third switch element and the fourth switch element shown, as well as the types and positions of the devices constituting the first inverter 1041 and the second inverter 1042 can be arbitrarily set as needed, as long as the circuit architecture can realize the functions of the above-mentioned first inverter 1041, the second inverter 1042, the first control switch 1031 and the second control switch 1032, they are all within the scope defined by the embodiments of the present disclosure.

[0074] like Figure 4 As shown, it shows another exemplary structure diagram of the calculation selection unit 103 and the calculation unit 104, wherein the first inverter 1041 includes P1 and N2, the second inverter 1042 includes P3 and N4, the first switch element and the second switch element are P2 and N1, and the third switch element and the fourth switch element are P4 and N3. This circuit structure can be implemented with Figure 3 The circuit structure shown has the same function.

[0075] Above Figure 3 , Figure 4P1, P2, N1, N2, and P3, P4, N3, N4 shown constitute a three-state buffer gate, which can effectively isolate the weight data involved in the calculation from the weight data not involved in the calculation, thereby improving the accuracy of circuit storage and calculation.

[0076] This embodiment realizes the function of realizing the calculation selection signal with fewer components by setting the first switch element, the second switch element, the third switch element, and the fourth switch element in cooperation with the first inverter and the second inverter. Moreover, it is only necessary to switch the calculation selection signal between the first signal and the second signal to realize the selection of the storage unit participating in the calculation between the two storage units, thereby simplifying the circuit structure and reducing the complexity of the circuit operation.

[0077] In some optional implementations, the computing unit 104 is further configured to:

[0078] In response to receiving a read data mode selection signal, a read control signal is generated; based on the read control signal, the weight data stored in the storage unit currently selected by the calculation selection unit is output.

[0079] like Figure 1 and Figure 2 As shown, BIST_MODE represents the input mode selection signal. As an example, when BIST_MODE=0, it indicates that the read data mode selection signal is received. Correspondingly, when BIST_MODE=1, it indicates that the calculation mode selection signal is received. It should be understood that the schemes described in the above embodiments are all operating processes in the calculation mode.

[0080] The above-mentioned read control signal is used to control whether the weight data input by the calculation selection unit 103 to the calculation unit 104 participates in the calculation. As an example, the calculation unit 104 may include a data selection switch. When a read data mode selection signal is received, the read data mode selection signal can be used as a read control signal, and the data selection switch is controlled by the read control signal to connect the calculation selection unit 103 with the data output end of the calculation unit 104, thereby outputting the weight data stored in the storage unit currently selected by the calculation selection unit 103. Correspondingly, when a calculation data mode selection signal is received, the calculation data mode selection signal can be used as a calculation control signal, and the data selection switch is controlled by the calculation control signal to connect the weight data input by the calculation selection unit 103 with the data NN to be calculated input to the calculation unit 104. j Perform calculations and output the results.

[0081] As another example, Figure 2 As shown, when receiving the read data mode selection signal, the third inverter 1043 outputs NN jb is set to 0, and the NOR gate 1044 inverts Bitb after Bit0 or Bit1 is inverted again, and outputs Bit0 or Bit1, thereby realizing reading the weight data from the currently selected storage unit. Correspondingly, when receiving the calculation data mode selection signal, the third inverter 1043 receives the input data NN to be calculated j , output NN j The inverted data NN j b, NN j b and Bitb are OR-not operated, and the output data is NN j The product of Bit0 or Bit1.

[0082] This embodiment realizes switching between the data reading mode and the calculation mode by using the calculation unit, and can flexibly control the function of the circuit without changing the circuit structure, thereby further expanding the application scope of the circuit.

[0083] Figure 5 The schematic diagram of the structure of a dual-port storage-computation integrated array circuit provided by an exemplary embodiment of the present disclosure is shown in FIG. The various components included in the circuit can be integrated into one chip, or can be set in different chips or circuit boards, and data communication links are established between these chips or circuit boards.

[0084] like Figure 5 As shown, the circuit includes: a controller 501 and a dual-port storage and computing module array 502.

[0085] In this embodiment, the dual-port storage and computing module array 502 includes a first preset number of dual-port storage and computing module groups, each of which includes a second preset number of dual-port storage and computing modules, and each dual-port storage and computing module includes the above Figure 1-Figure 4 A dual-port storage-computation-in-one unit circuit described in any corresponding embodiment.

[0086] like Figure 5 As shown, the first preset number may be the number of rows of the dual-port storage and computing module array 502, and the second preset number may be the number of columns of the dual-port storage and computing module array 502. The number of rows and the number of columns of the dual-port storage and computing module array 502 in the figure are Y and X, respectively. 0,0 、2P-CIM C 0,1 ……2P-CIM C Y-1,X-1 They respectively represent a dual-port storage and computing module.

[0087] Each row of the dual-port storage and calculation module array 502 can simultaneously input multi-bit weight data, and each bit of the multi-bit weight data is correspondingly stored in a storage unit of a dual-port storage and calculation module. Figure 5As shown, the single-bit weight data included in the L multi-bit weight data corresponding to the input in row 0 is represented as WD 0,0 -WD 0,X-1 The single-bit weight data included in the L multi-bit weight data corresponding to the input in the Y-1th row is represented as WD Y-1,0 -WD Y-1,X-1 WD 0,0 -WD 0,X-1 is divided into L groups, each group includes K single bits, and K single bits constitute a multi-bit weight data. Similarly, WD Y-1,0 -WD Y-1,X-1 It is divided into L groups, each group includes K single bits, and K single bits constitute a multi-bit weight data. For example, X is 32, and one row can store 4 8-bit weight data.

[0088] The data to be calculated in each row of input can usually be a single bit contained in a multi-bit data (for example, N-bit data), that is, the single bit contained in the multi-bit data is represented as NN0-NN N-1 The multi-bit data may be, for example, multi-bit feature data to be calculated in a neural network. During calculation, based on the calculation clock, multiple groups of data to be calculated are calculated in sequence. For example, in the first calculation clock cycle, NN0-NN1 of the first multi-bit data is calculated. N-1 The corresponding rows are input respectively, and each calculation unit included in the corresponding row calculates the input data to be calculated and the stored weight data; in the second calculation clock cycle, NN0-NN of the second multi-bit data is calculated. N-1 The corresponding rows are input respectively, and the calculation units included in the corresponding rows calculate the input data to be calculated and the stored weight data. This process is repeated until the calculation of multiple multi-bit data is completed.

[0089] It should be noted that the number of bits N of the input multi-bit data may be the same as or different from the number of rows Y of the dual-port storage and computing module array 502. For the convenience of description in the drawings, the number of bits N and Y of the multi-bit data shown in 5 are the same, that is, the data to be calculated input in each calculation cycle includes NN0-NN Y-1 In order to make the dual-port storage and computing module array 502 more versatile, the number of rows Y of the dual-port storage and computing module array 502 is usually set to a larger value, and the number of bits N of the input multi-bit data is less than Y. Therefore, one or more multi-bit data can be input in one calculation cycle. For example, when N is 8 and Y is 16, one multi-bit data can be input in one calculation cycle, that is, NN0-NN7 is input to 8 rows respectively, or 2 multi-bit data can be input in one calculation cycle, that is, NN0-NN7 of the first multi-bit data is input to the first 8 rows respectively, and NN0-NN7 of the second multi-bit data is input to the second 8 rows respectively.

[0090] In this embodiment, the controller 501 is used to send a write selection signal to the write selection unit included in each dual-port storage and calculation module, and the write selection unit stores the input weight data into the input data storage unit corresponding to the write selection signal.

[0091] like Figure 5 As shown, the write selection signals corresponding to each row are all WRT_MUX_SEL, that is, weight data can be written to each row at the same time.

[0092] In this embodiment, the controller 501 is also used to send a calculation selection signal to the calculation selection unit included in each dual-port storage and calculation module, and the calculation selection unit selects the calculation data storage unit for calculation with the input data to be calculated, and the corresponding calculation unit calculates the data to be calculated and the weight data output by the calculation data storage unit to obtain the calculation result. The above-mentioned data to be calculated can be data in the neural network to be used for calculation with the weight data. Usually, the data to be calculated is single-bit data, for example, the data to be calculated can be a bit included in the multi-bit feature data in the neural network.

[0093] like Figure 5 As shown, the calculation selection signals corresponding to each row are all CIM_MUX_SEL, that is, each row can be controlled to perform calculation at the same time.

[0094] Typically, the write selection signal and the calculation selection signal sent at the same time correspond to different storage units in each dual-port storage and calculation module. In the current calculation operation, the controller 501 can send a calculation selection signal for selecting a first storage unit from the corresponding two storage units for calculation to the calculation selection unit included in each dual-port storage and calculation module. At the same time, when it is necessary to write weight data to the second storage unit of the two storage units, the controller 501 can send a write selection signal for selecting the second storage unit from the corresponding two storage units for data writing to the write selection unit included in each dual-port storage and calculation module. The write selection unit can store the received weight data in the second storage unit according to the write selection signal.

[0095] After at least one calculation operation is completed using the first storage unit included in each dual-port storage and calculation module, if it is necessary to use the weight data stored in the second storage unit included in each dual-port storage and calculation module to perform a calculation operation, the controller 501 can send a calculation selection signal for selecting the second storage unit from the corresponding two storage units to the calculation selection unit included in each dual-port storage and calculation module. At the same time, when it is necessary to write weight data to the first storage unit of the two storage units, the controller 501 can also send a write selection signal for selecting the first storage unit from the corresponding two storage units to write data to the write selection unit included in each dual-port storage and calculation module, and the write selection unit can store the received weight data in the first storage unit according to the write selection signal.

[0096] Through the above process, in the process of using a storage unit included in each dual-port storage and calculation module to perform a calculation operation, another storage unit included in each dual-port storage and calculation module can store the currently input weight data. When the calculation operation is completed, if it is necessary to switch the weight data and the input data to be calculated for calculation, the storage unit participating in the calculation can be switched between the two storage units included in each dual-port storage and calculation module, and new weight data can be input to the other storage unit at the same time, thereby realizing the independence of the write operation and the calculation operation of the dual-port storage and calculation module array 502.

[0097] The dual-port storage-and-computing integrated array circuit provided in the above-mentioned embodiment of the present disclosure, by using the above-mentioned dual-port storage-and-computing integrated unit circuit, constructs a dual-port storage-and-computing integrated module array including a dual-port storage-and-computing integrated module. While writing weight data to a part of the storage units in the dual-port storage-and-computing integrated module array, it can extract the stored weight data from another part of the storage units to perform calculations on the input data to be calculated, thereby greatly improving the calculation efficiency, and achieving the independent writing and calculation of the weight data without interfering with each other. The circuit has a longer peak computing power retention time, a higher effective computing power, a more flexible design space and a wider range of applications.

[0098] In some optional implementations, such as Figure 5 As shown, the circuit further includes an addition tree 503 and a shift accumulator 504 .

[0099] The addition tree 503 is used to accumulate the calculation results output by the dual-port storage and calculation modules located at the same position in each dual-port storage and calculation module group to obtain a first accumulation result. Figure 5 As shown in the figure, when each row of the dual-port storage and calculation modules is used as a dual-port storage and calculation module group, when each dual-port storage and calculation module finishes calculating, the addition tree 503 can accumulate the calculation results respectively output by the dual-port storage and calculation modules included in each column of the array to obtain the first accumulation result corresponding to each column (s0-s1 in the figure). X-1). It should be noted that s0-s X-1 are the results of multiplying and adding Y single-bit weight data and the data to be calculated, that is, s0-s X-1 are all multi-bit data. For example, if the number of rows Y is 32, then s0-s X-1 It is the result of multiplication and addition of 32 pairs of single-bit data, and the number of bits can be 6.

[0100] The shift accumulator 504 is used to perform shift accumulation on each first accumulation result to obtain a second accumulation result (SUM0-SUM L-1 ). Generally, when the shift accumulator 504 performs a shift-accumulate operation, it targets s0-s X-1 For example, if the number of columns X involved in the operation is 32, and each row stores 4 (i.e. L is 4) 8-bit weight data, then s0-s X-1 It can be divided into 4 groups, and each group of data performs shift accumulation respectively, and the obtained SUM contains 4 second accumulation results, and each second accumulation result is the result of multiplying and adding Y 8-bit weight data and Y data to be calculated.

[0101] Optionally, since the neural network usually performs multiplication and addition calculations on a one-to-one correspondence of a plurality of multi-bit input data (such as feature data) and a plurality of multi-bit weight data. Therefore, after performing multiplication and accumulation calculations on a plurality of single-bit data to be calculated and a plurality of single-bit weight data input each time, the second accumulation results obtained each time can be shifted and accumulated multiple times to obtain the multiplication and addition results of the plurality of multi-bit input data and the plurality of multi-bit weight data. For example, the SUM0 obtained by multiple calculations is shifted and accumulated one by one to obtain the multiplication and addition results of the Y multi-bit weight data contained in the 0th group and the Y multi-bit input data input.

[0102] This embodiment realizes the calculation and shift accumulation of multiple multi-bit feature data and multiple multi-bit weight data by setting an addition tree and a shift accumulator. Therefore, when the dual-port storage and computing module array is applied to a neural network computing scenario, the neural network calculation and the weight data are written to the dual-port storage and computing module array efficiently at the same time, thereby improving the efficiency of the neural network calculation.

[0103] In some optional implementations, the circuit further includes a first preset number of word line groups, each of the first preset number of word line groups corresponds to a dual-port storage and computing module group, and each word line group includes a first word line and a second word line.

[0104] For each dual-port storage and computing module group in the first preset number of dual-port storage and computing module groups, the word line group corresponding to the dual-port storage and computing module group includes a first word line and a second word line, and the first word line and the second word line respectively correspond to the first storage unit and the second storage unit included in each dual-port storage and computing module in the dual-port storage and computing module group.

[0105] like Figure 5 As shown, each row of the dual-port memory module array 502 corresponds to two word lines, WWL i [0] (first word line) and WWL i [1] (second word line), where i is the row number. i [0] corresponds to the first storage unit of each dual-port storage and computing module in the i-th row, WWL i [1] The second storage unit included in each dual-port storage and computing module corresponding to the i-th row.

[0106] The write selection unit included in each dual-port storage and computing module in the dual-port storage and computing module group is further used to: select a target word line from the first word line and the second word line included in the word line group corresponding to the dual-port storage and computing module group according to the received write selection signal, and store the input weight data into the storage unit corresponding to the target word line.

[0107] As an example, Figure 5 As shown, for the i-th row of the array, if the write selection signal input to the row is "1", the write selection unit selects WWL i [0] is the target word line, and the first storage unit included in each dual-port storage module in the i-th row is connected to WWL i [0] is turned on, and each first storage unit receives and stores the corresponding input single-bit weight data.

[0108] This embodiment sets two word lines in each row of the dual-port storage and computing module array, thereby achieving unified selection of the two storage cells included in each dual-port storage and computing module, thereby facilitating efficient writing of weight data to the two storage cells included in each dual-port storage and computing module in sequence, thereby improving the efficiency of data storage and in-memory operations of the dual-port storage and computing module array.

[0109] The embodiment of the present disclosure further provides a chip, on which a dual-port storage-computing integrated unit circuit or a dual-port storage-computing integrated array circuit is integrated. The technical details of the dual-port storage-computing integrated unit circuit are as follows: Figure 1-Figure 4 As shown in the relevant description, the technical details of the dual-port storage and computing array circuit are as follows Figure 5 As shown in the relevant description, no further description is given here.

[0110] The embodiments of the present disclosure also provide an electronic device, which includes the chip described in the above embodiments. In addition, the electronic device may also include an input device, an output device, and necessary memory, etc. Among them, the input device may include such as a mouse, a keyboard, a touch screen, a communication network connector, etc., for inputting weight data, feature data, etc. The output device may include such as a display, a printer, and a communication network and its connected remote output device, etc., for outputting calculation results, etc. The memory is used to store the data input by the above input device, as well as the data generated during the operation of the dual-port storage and calculation unit circuit or the dual-port storage and calculation array circuit. The memory may include volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory (cache), etc. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc.

[0111] The basic principles of the present disclosure are described above in conjunction with specific embodiments. However, it should be noted that the advantages, strengths, effects, etc. mentioned in the present disclosure are only examples and not limitations, and it cannot be considered that these advantages, strengths, effects, etc. are required by each embodiment of the present disclosure. In addition, the specific details disclosed above are only for the purpose of illustration and ease of understanding, and are not limitations. The above details do not limit the present disclosure to the necessity of adopting the above specific details to be implemented.

[0112] Each embodiment in this specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referenced to each other.

[0113] The block diagrams of the devices, apparatuses, equipment, and systems involved in this disclosure are only illustrative examples and are not intended to require or imply that they must be connected, arranged, and configured in the manner shown in the block diagrams. As will be appreciated by those skilled in the art, these devices, apparatuses, equipment, and systems can be connected, arranged, and configured in any manner. Words such as "including," "comprising," "having," and the like are open words, referring to "including but not limited to," and can be used interchangeably therewith. The words "or" and "and" used herein refer to the words "and / or," and can be used interchangeably therewith, unless the context clearly indicates otherwise. The word "such as" used herein refers to the phrase "such as but not limited to," and can be used interchangeably therewith.

[0114] The circuits of the present disclosure may be implemented in many ways. For example, the circuits of the present disclosure may be implemented by software, hardware, firmware, or any combination of software, hardware, and firmware. The above order of steps of the method used in the circuit is for illustration only, and the steps of the method of the present disclosure are not limited to the order specifically described above unless otherwise specifically stated. In addition, in some embodiments, the present disclosure may also be implemented as programs recorded in a recording medium, which include machine-readable instructions for implementing the functions of the circuits of the present disclosure. Thus, the present disclosure also covers recording media storing programs for executing the functions of the circuits of the present disclosure.

[0115] It should also be noted that in the circuit of the present disclosure, each component or each step can be decomposed and / or recombined. Such decomposition and / or recombination should be regarded as an equivalent solution of the present disclosure.

[0116] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of the present disclosure. Therefore, the present disclosure is not intended to be limited to the aspects shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

[0117] The above description has been given for the purpose of illustration and description. In addition, this description is not intended to limit the embodiments of the present disclosure to the forms disclosed herein. Although multiple example aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, changes, additions and sub-combinations thereof.

Claims

1. A dual-port storage and computing integrated unit circuit, comprising: two storage units, a write selection unit, a calculation selection unit and a calculation unit; The write selection unit is used to select a storage unit from the two storage units as an input data storage unit according to an input write selection signal, and store the currently input weight data into the input data storage unit; The calculation selection unit is used to select one storage unit from the two storage units as a calculation data storage unit according to an input calculation selection signal; The calculation unit is used to calculate the weight data stored in the calculation data storage unit and the input data to be calculated, obtain a calculation result, and output the calculation result.

2. The circuit according to claim 1, wherein The calculation selection unit includes a first control switch and a second control switch; The first control switch is used to receive the calculation selection signal, and when the calculation selection signal is a first signal, input the first weight data in the calculation data storage unit corresponding to the first signal into the calculation unit; The second control switch is used to receive the calculation selection signal, and when the calculation selection signal is a second signal, input the second weight data in the calculation data storage unit corresponding to the second signal into the calculation unit.

3. The circuit according to claim 2, wherein: The calculation unit includes a multiplier, which is used to receive input data to be calculated, and use the first weight data or the second weight data to perform multiplication calculation on the data to be calculated and output the result.

4. The circuit according to claim 3, wherein: The calculation unit includes a first inverter, a second inverter, a third inverter, and a NOR gate; The first inverter is used for performing an inversion operation on the first weight data to obtain first inverted weight data when the calculation selection signal is the first signal, and inputting the first inverted weight data into the NOR gate; The second inverter is used for performing an inversion operation on the second weight data to obtain second inverted weight data when the calculation selection signal is the second signal, and inputting the second inverted weight data into the NOR gate; The third inverter is used to perform an inversion operation on the data to be calculated to obtain inverted data to be calculated; The NOR gate is used for performing a NOR operation on the inverted data to be calculated and the input first inverted weight data when the calculation selection signal is the first signal, and outputting a multiplication result of the data to be calculated and the first weight data; When the calculation selection signal is the second signal, a negation operation is performed on the inverted data to be calculated and the input second inverted weight data, and a multiplication result of the data to be calculated and the second weight data is output.

5. The circuit according to claim 4, wherein: The first control switch includes a first switch element and a second switch element, the first switch element is used to connect the first inverter to a level representing first data when the calculation selection signal is the first signal, and the second switch element is used to connect the first inverter to a level representing second data when the calculation selection signal is the first signal; The second control switch includes a third switch element and a fourth switch element, the third switch element is used to connect the second inverter to the level representing the first data when the calculation selection signal is the second signal, and the fourth switch element is used to connect the second inverter to the level representing the second data when the calculation selection signal is the second signal.

6. The circuit according to any one of claims 1 to 5, wherein: The computing unit is further configured to: generating a read control signal in response to receiving a read data mode selection signal; Based on the read control signal, the weight data stored in the storage unit currently selected by the calculation selection unit is output.

7. A dual-port storage and computing integrated array circuit, comprising: Controller and dual-port storage and computing module array; The dual-port storage and computing module array includes a first preset number of dual-port storage and computing module groups, each dual-port storage and computing module group includes a second preset number of dual-port storage and computing modules, and each dual-port storage and computing module includes the dual-port storage and computing integrated unit circuit according to any one of claims 1 to 5; The controller is used to send a write selection signal to a write selection unit included in each dual-port storage and calculation module, and the write selection unit stores the input weight data into the input data storage unit corresponding to the write selection signal; The controller is also used to send a calculation selection signal to the calculation selection unit included in each dual-port storage and calculation module, and the calculation selection unit selects the calculation data storage unit to calculate the input data to be calculated, and the corresponding calculation unit calculates the data to be calculated and the weight data output by the calculation data storage unit to obtain a calculation result.

8. The circuit according to claim 7, wherein: It also includes a first preset number of word line groups, each of which corresponds to a dual-port storage and computing module group, and each word line group includes a first word line and a second word line; For each dual-port storage and computing module group in the first preset number of dual-port storage and computing module groups, the word line group corresponding to the dual-port storage and computing module group includes a first word line and a second word line, and the first word line and the second word line respectively correspond to a first storage unit and a second storage unit included in each dual-port storage and computing module in the dual-port storage and computing module group; The write selection unit included in each dual-port storage and computing module in the dual-port storage and computing module group is further used for: According to the received write selection signal, a target word line is selected from the first word line and the second word line included in the word line group corresponding to the dual-port storage and computing module group, and the input weight data is stored in the storage unit corresponding to the target word line.

9. A chip, comprising the dual-port storage-computation-in-one unit circuit according to any one of claims 1-5 or the dual-port storage-computation-in-one array circuit according to any one of claims 6-8.

10. An electronic device comprising the chip according to claim 9.

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