Memory, storage system, and operating method of memory

Abstract

The application discloses a memory, a storage system and an operating method of the memory, and belongs to the technical field of storage. The memory is characterized in that when each memory string in a storage block is subjected to an erasing operation, if there is a first memory string that has completed erasing and a second memory string that has not completed erasing in the memory string, a selection line coupled with a first selection tube of the first memory string is floated in advance before a selection line coupled with a first selection tube of the second memory string is floated, so as to reduce the erasing speed of the first memory string, avoid the first memory string from being excessively erased in the process of erasing the second memory string, reduce the possibility that a storage unit in the first memory string is laterally diffused after programming, and weaken the drift of the threshold voltage of the storage unit in the first memory string.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular to a memory, a storage system, and a method of operating the memory. Background Technology

[0002] With the development of semiconductor technology, memory is widely used in various types of electronic devices. During operation, electronic devices inevitably perform erase operations on the memory blocks. Due to differences in process parameters, the erase speed of each memory string within a block varies, resulting in different erase depths. The erase depth can be represented by the threshold voltage of the memory cells in the erase state within the memory string. A lower threshold voltage results in a deeper erase depth, while a higher threshold voltage results in a shallower erase depth.

[0003] After being programmed, memory cells in memory strings with deep erase depths are prone to lateral spread, which causes the threshold voltage of the memory cells to drift. Summary of the Invention

[0004] This application provides a memory, a memory system, and a method for operating the memory, which can reduce the lateral diffusion of memory strings and mitigate the drift of threshold voltages in memory cells within the memory string. The technical solution is as follows:

[0005] In a first aspect, a memory is provided, the memory including a memory array and peripheral circuitry, the memory array including a memory block and a first select line, the memory block including a plurality of memory strings, each memory string including a first select transistor, the first select line being coupled to the first select transistor, and the peripheral circuitry being coupled to the first select line.

[0006] The peripheral circuit is configured to perform an erase operation on the plurality of memory strings in the memory block. To perform the erase operation, the peripheral circuit is configured as follows:

[0007] At the first moment, the first selection line coupled to the first selection tube of the first memory string is floated, and the first memory string is the memory string that has been erased among the plurality of memory strings;

[0008] At a second time after the first time, the first selection line coupled to the first selection tube of the second memory string is floated, and the second memory string is the memory string that has not been erased among the plurality of memory strings.

[0009] In one possible implementation, the memory array further includes a first doped semiconductor layer and a plurality of word lines, the first doped semiconductor layer being coupled to one end of each memory string near the first select transistor, each memory string further including a plurality of memory cells, the plurality of word lines being coupled to the plurality of memory cells of each memory string respectively, and the peripheral circuitry being coupled to the plurality of word lines;

[0010] The peripheral circuit is also configured to:

[0011] At a third time prior to the first time, a first voltage is applied to the first doped semiconductor layer coupled to each memory string in the memory block;

[0012] From the third time point to the first time point, a second voltage is applied to the first select line coupled to the first select transistor of the first memory string, the second voltage being less than the first voltage;

[0013] From the third time point to the second time point, the second voltage is applied to the first select line coupled to the first select transistor of the second memory string;

[0014] At the third moment, a third voltage, which is less than the first voltage, is applied to the word lines coupled to each memory cell of each memory string in the memory block.

[0015] In one possible implementation, each memory string in the memory block further includes a second select transistor, the memory array further includes a second doped semiconductor layer and a second select line, the second doped semiconductor layer being coupled to one end of each memory string near the second select transistor, the second select line being coupled to the second select transistor, and the peripheral circuitry being coupled to the second select line.

[0016] The peripheral circuit is also configured to:

[0017] At the third moment, a fourth voltage is applied to the second doped semiconductor layer coupled to each memory string in the memory block;

[0018] At the third moment, the second selection line coupled to the second selection tube of each memory string in the memory block is floated.

[0019] In one possible implementation, the first doped semiconductor layer is coupled to a bitline, and the first doped semiconductor layer is an N-type doped semiconductor layer.

[0020] In one possible implementation, the first doped semiconductor layer is coupled to the source line, and the first doped semiconductor layer is an N-type doped semiconductor layer or a P-type doped semiconductor layer.

[0021] In one possible implementation, each memory string in the memory block further includes a second select transistor, the memory array further includes a second doped semiconductor layer and a second select line, the second doped semiconductor layer being coupled to one end of each memory string near the second select transistor, the second select line being coupled to the second select transistor, and the peripheral circuitry being coupled to the second select line.

[0022] The peripheral circuit is also configured to:

[0023] At the third moment, a fifth voltage is applied to the second doped semiconductor layer coupled to each memory string in the memory block.

[0024] In one possible implementation, the peripheral circuit is further configured as follows:

[0025] From the third time point to the second time point, a sixth voltage is applied to the second selection line coupled to the second selection transistor of each memory string in the memory block, the sixth voltage being less than the fifth voltage;

[0026] At the second moment, the second selection line coupled to the second selection tube of each memory string in the memory block is floated.

[0027] In one possible implementation, the peripheral circuit is further configured as follows:

[0028] From the third time point to the fourth time point, a seventh voltage is applied to the second selection line coupled to the second selection transistor of the first memory string. At the fourth time point, the second selection line coupled to the second selection transistor of the first memory string is floated. The seventh voltage is less than the fifth voltage.

[0029] From the third time point to the fifth time point after the fourth time point, the seventh voltage is applied to the second selection line coupled to the second selection transistor of the second memory string, and at the fifth time point, the second selection line coupled to the second selection transistor of the second memory string is floated.

[0030] In one possible implementation, the first doped semiconductor layer is coupled to a bitline, and the first doped semiconductor layer is an N-type doped semiconductor layer;

[0031] The second doped semiconductor layer is coupled to the source line, and the second doped semiconductor layer is an N-type doped semiconductor layer or a P-type doped semiconductor layer.

[0032] In one possible implementation, the first doped semiconductor layer is coupled to the source line, and the first doped semiconductor layer is an N-type doped semiconductor layer or a P-type doped semiconductor layer.

[0033] The second doped semiconductor layer is coupled to the bit line, and the second doped semiconductor layer is an N-type doped semiconductor layer.

[0034] In one possible implementation, the storage string includes multiple substrings, each substring including a first selection transistor and multiple storage units, each first selection transistor in the same storage string is coupled to the same first selection line, and the first selection transistors in different storage strings are coupled to different first selection lines.

[0035] In one possible implementation, the peripheral circuit is further configured as follows:

[0036] At the sixth time after the second time, an erase verification operation is performed on each storage string in the storage block;

[0037] If a second storage string that fails the erase verification exists in the storage block, the step of erasing the plurality of storage strings in the storage block is performed.

[0038] In a second aspect, a storage system is provided, the storage system including a memory configured to store data and a controller coupled to the memory and configured to control the memory, wherein the memory includes a storage array and peripheral circuitry, the storage array includes storage blocks and a first select line, the storage block includes a plurality of storage strings, each storage string includes a first select transistor, the first select line is coupled to the first select transistor, and the peripheral circuitry is coupled to the first select line; the peripheral circuitry is configured to perform an erase operation on the plurality of storage strings in the storage block, and to perform the erase operation, the peripheral circuitry is configured to:

[0039] At the first moment, the first selection line coupled to the first selection tube of the first memory string is floated, and the first memory string is the memory string that has been erased among the plurality of memory strings;

[0040] At a second time after the first time, the first selection line coupled to the first selection tube of the second memory string is floated, and the second memory string is the memory string that has not been erased among the plurality of memory strings.

[0041] In one possible implementation, the memory array further includes a first doped semiconductor layer and a plurality of word lines, the first doped semiconductor layer being coupled to one end of each memory string near the first select transistor, each memory string further including a plurality of memory cells, the plurality of word lines being coupled to the plurality of memory cells of each memory string respectively, and the peripheral circuitry being coupled to the plurality of word lines;

[0042] The peripheral circuit is also configured to:

[0043] At a third time prior to the first time, a first voltage is applied to the first doped semiconductor layer coupled to each memory string in the memory block;

[0044] From the third time point to the first time point, a second voltage is applied to the first select line coupled to the first select transistor of the first memory string, the second voltage being less than the first voltage;

[0045] From the third time point to the second time point, the second voltage is applied to the first select line coupled to the first select transistor of the second memory string;

[0046] At the third moment, a third voltage, which is less than the first voltage, is applied to the word lines coupled to each memory cell of each memory string in the memory block.

[0047] In one possible implementation, each memory string in the memory block further includes a second select transistor, the memory array further includes a second doped semiconductor layer and a second select line, the second doped semiconductor layer being coupled to one end of each memory string near the second select transistor, the second select line being coupled to the second select transistor, and the peripheral circuitry being coupled to the second select line.

[0048] The peripheral circuit is also configured to:

[0049] At the third moment, a fourth voltage is applied to the second doped semiconductor layer coupled to each memory string in the memory block;

[0050] At the third moment, the second selection line coupled to the second selection tube of each memory string in the memory block is floated.

[0051] In one possible implementation, the first doped semiconductor layer is coupled to a bitline, and the first doped semiconductor layer is an N-type doped semiconductor layer.

[0052] In one possible implementation, the first doped semiconductor layer is coupled to the source line, and the first doped semiconductor layer is an N-type doped semiconductor layer or a P-type doped semiconductor layer.

[0053] In one possible implementation, each memory string in the memory block further includes a second select transistor, the memory array further includes a second doped semiconductor layer and a second select line, the second doped semiconductor layer being coupled to one end of each memory string near the second select transistor, the second select line being coupled to the second select transistor, and the peripheral circuitry being coupled to the second select line.

[0054] The peripheral circuit is also configured to:

[0055] At the third moment, a fifth voltage is applied to the second doped semiconductor layer coupled to each memory string in the memory block.

[0056] In one possible implementation, the peripheral circuit is further configured as follows:

[0057] From the third time point to the second time point, a sixth voltage is applied to the second selection line coupled to the second selection transistor of each memory string in the memory block, the sixth voltage being less than the fifth voltage;

[0058] At the second moment, the second selection line coupled to the second selection tube of each memory string in the memory block is floated.

[0059] In one possible implementation, the peripheral circuit is further configured as follows:

[0060] From the third time point to the fourth time point, a seventh voltage is applied to the second selection line coupled to the second selection transistor of the first memory string. At the fourth time point, the second selection line coupled to the second selection transistor of the first memory string is floated. The seventh voltage is less than the fifth voltage.

[0061] From the third time point to the fifth time point after the fourth time point, the seventh voltage is applied to the second selection line coupled to the second selection transistor of the second memory string, and at the fifth time point, the second selection line coupled to the second selection transistor of the second memory string is floated.

[0062] In one possible implementation, the first doped semiconductor layer is coupled to a bitline, and the first doped semiconductor layer is an N-type doped semiconductor layer;

[0063] The second doped semiconductor layer is coupled to the source line, and the second doped semiconductor layer is an N-type doped semiconductor layer or a P-type doped semiconductor layer.

[0064] In one possible implementation, the first doped semiconductor layer is coupled to the source line, and the first doped semiconductor layer is an N-type doped semiconductor layer or a P-type doped semiconductor layer.

[0065] The second doped semiconductor layer is coupled to the bit line, and the second doped semiconductor layer is an N-type doped semiconductor layer.

[0066] In one possible implementation, the storage string includes multiple substrings, each substring including a first selection transistor and multiple storage units, each first selection transistor in the same storage string is coupled to the same first selection line, and the first selection transistors in different storage strings are coupled to different first selection lines.

[0067] In one possible implementation, the peripheral circuit is further configured as follows:

[0068] At the sixth time after the second time, an erase verification operation is performed on each storage string in the storage block;

[0069] If a second storage string that fails the erase verification exists in the storage block, the step of erasing the plurality of storage strings in the storage block is performed.

[0070] In one possible implementation, the storage system further includes a host coupled to the controller, the host being configured to send data to or receive data from the memory via the controller.

[0071] Thirdly, a method for operating a memory is provided, the memory including a memory array and peripheral circuitry, the memory array including a memory block and a first select line, the memory block including a plurality of memory strings, each memory string including a first select transistor, the first select line coupled to the first select transistor, and the peripheral circuitry coupled to the first select line; the method includes performing an erasure operation on the plurality of memory strings in the memory block, the erasure operation including:

[0072] At the first moment, the first selection line coupled to the first selection tube of the first memory string is floated, and the first memory string is the memory string that has been erased among the plurality of memory strings;

[0073] At a second time after the first time, the first selection line coupled to the first selection tube of the second memory string is floated, and the second memory string is the memory string that has not been erased among the plurality of memory strings.

[0074] In one possible implementation, the memory array further includes a first doped semiconductor layer and a plurality of word lines, the first doped semiconductor layer being coupled to one end of each memory string near the first select transistor, each memory string further including a plurality of memory cells, the plurality of word lines being coupled to the plurality of memory cells of each memory string respectively;

[0075] The erasure operation also includes:

[0076] At a third time prior to the first time, a first voltage is applied to the first doped semiconductor layer coupled to each memory string in the memory block;

[0077] From the third time point to the first time point, a second voltage is applied to the first select line coupled to the first select transistor of the first memory string, the second voltage being less than the first voltage;

[0078] From the third time point to the second time point, the second voltage is applied to the first select line coupled to the first select transistor of the second memory string;

[0079] At the third moment, a third voltage, which is less than the first voltage, is applied to the word lines coupled to each memory cell of each memory string in the memory block.

[0080] In one possible implementation, each memory string in the memory block further includes a second select transistor, and the memory array further includes a second doped semiconductor layer and a second select line, the second doped semiconductor layer being coupled to one end of each memory string near the second select transistor, and the second select line being coupled to the second select transistor;

[0081] The erasure operation also includes:

[0082] At the third moment, a fourth voltage is applied to the second doped semiconductor layer coupled to each memory string in the memory block;

[0083] At the third moment, the second selection line coupled to the second selection tube of each memory string in the memory block is floated.

[0084] In one possible implementation, the first doped semiconductor layer is coupled to a bitline, and the first doped semiconductor layer is an N-type doped semiconductor layer.

[0085] In one possible implementation, the first doped semiconductor layer is coupled to the source line, and the first doped semiconductor layer is an N-type doped semiconductor layer or a P-type doped semiconductor layer.

[0086] In one possible implementation, each memory string in the memory block further includes a second select transistor, and the memory array further includes a second doped semiconductor layer and a second select line, the second doped semiconductor layer being coupled to one end of each memory string near the second select transistor, and the second select line being coupled to the second select transistor;

[0087] The erasure operation also includes:

[0088] At the third moment, a fifth voltage is applied to the second doped semiconductor layer coupled to each memory string in the memory block.

[0089] In one possible implementation, the erasure operation further includes:

[0090] From the third time point to the second time point, a sixth voltage is applied to the second selection line coupled to the second selection transistor of each memory string in the memory block, the sixth voltage being less than the fifth voltage;

[0091] At the second moment, the second selection line coupled to the second selection tube of each memory string in the memory block is floated.

[0092] In one possible implementation, the erasure operation further includes:

[0093] From the third time point to the fourth time point, a seventh voltage is applied to the second selection line coupled to the second selection transistor of the first memory string. At the fourth time point, the second selection line coupled to the second selection transistor of the first memory string is floated. The seventh voltage is less than the fifth voltage.

[0094] From the third time point to the fifth time point after the fourth time point, the seventh voltage is applied to the second selection line coupled to the second selection transistor of the second memory string, and at the fifth time point, the second selection line coupled to the second selection transistor of the second memory string is floated.

[0095] In one possible implementation, the first doped semiconductor layer is coupled to a bitline, and the first doped semiconductor layer is an N-type doped semiconductor layer;

[0096] The second doped semiconductor layer is coupled to the source line, and the second doped semiconductor layer is an N-type doped semiconductor layer or a P-type doped semiconductor layer.

[0097] In one possible implementation, the first doped semiconductor layer is coupled to the source line, and the first doped semiconductor layer is an N-type doped semiconductor layer or a P-type doped semiconductor layer.

[0098] The second doped semiconductor layer is coupled to the bit line, and the second doped semiconductor layer is an N-type doped semiconductor layer.

[0099] In one possible implementation, the storage string includes multiple substrings, each substring including a first selection transistor and multiple storage units, each first selection transistor in the same storage string is coupled to the same first selection line, and the first selection transistors in different storage strings are coupled to different first selection lines.

[0100] In one possible implementation, after the first select line coupled to the first select tube of the floating second memory string, the method further includes:

[0101] At the sixth time after the second time, an erase verification operation is performed on each storage string in the storage block;

[0102] If a second storage string that fails the erase verification exists in the storage block, the step of erasing the plurality of storage strings in the storage block is performed.

[0103] The technical solution provided in this application embodiment reduces the erasure speed of the first storage string by, when performing an erasure operation on each storage string in the storage block, if there is a first storage string that has been erased and a second storage string that has not been erased, floating the selection line coupled to the first selection transistor of the first storage string before floating the selection line coupled to the first selection transistor of the second storage string. This avoids the first storage string being over-erased during the erasure of the second storage string, reduces the possibility of lateral diffusion of the storage cells in the first storage string after programming, and weakens the drift of the threshold voltage of the storage cells in the first storage string. Attached Figure Description

[0104] Figure 1 This is a schematic diagram illustrating a memory according to an exemplary embodiment;

[0105] Figure 2 This is a schematic diagram of the electrical structure of a memory array according to an exemplary embodiment;

[0106] Figure 3 This is a cross-sectional side view of a substring according to an exemplary embodiment;

[0107] Figure 4 This is a schematic diagram of the structure of a peripheral circuit according to an exemplary embodiment;

[0108] Figure 5 This is a schematic diagram illustrating the principle of lateral diffusion according to an exemplary embodiment;

[0109] Figure 6 This is a schematic diagram illustrating a threshold voltage drift caused by lateral diffusion according to an exemplary embodiment;

[0110] Figure 7 This is a flowchart illustrating a method of operating a memory according to an exemplary embodiment;

[0111] Figure 8 This is a voltage waveform diagram of a memory block during single-ended erasure, according to an exemplary embodiment.

[0112] Figure 9 This is a voltage waveform diagram of a memory block during double-ended erasure, according to an exemplary embodiment.

[0113] Figure 10 This is a voltage waveform diagram of a memory block during a double-ended erase, according to an exemplary embodiment.

[0114] Figure 11 This is a flowchart illustrating a block erase operation method for a memory according to an exemplary embodiment;

[0115] Figure 12This is a schematic diagram illustrating a storage system according to an exemplary embodiment;

[0116] Figure 13 This is a schematic diagram illustrating a memory card according to an exemplary embodiment;

[0117] Figure 14 This is a schematic diagram illustrating a solid-state drive according to an exemplary embodiment. Detailed Implementation

[0118] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0119] In this application, the terms "first," "second," etc., are used to distinguish identical or similar items that have essentially the same function. It should be understood that there is no logical or temporal dependency between "first," "second," and "nth," nor does it limit the quantity or execution order. It should also be understood that although the following description uses the terms "first," "second," etc., to describe various elements, these elements should not be limited by the terms.

[0120] These terms are simply used to distinguish one element from another. For example, without departing from the various examples, the first element can be referred to as the second element, and similarly, the second element can be referred to as the first element. Both the first and second elements can be elements, and in some cases, they can be separate and distinct elements.

[0121] "At least one" means one or more elements. For example, at least one element can be one element, two elements, three elements, or any integer number of elements greater than or equal to one. "At least two" means two or more elements. For example, at least two elements can be two elements, three elements, or any integer number of elements greater than or equal to two.

[0122] Figure 1 This is a schematic diagram of a memory according to an exemplary embodiment, such as... Figure 1 As shown, the memory 100 includes a memory array 110, multiple bit lines (BL) 120, multiple word lines (WL) 130, and peripheral circuitry 140.

[0123] The storage array 110 includes a plurality of sub-strings 111 arranged in an array above a substrate (not shown), with each sub-string 111 extending vertically above the substrate.

[0124] Each substring 111 includes multiple storage cells 112, which are vertically stacked above the substrate of the storage array 110. Each storage cell 112 stores data, the amount of data stored determined by the number of electrons stored in the cell. The number of electrons stored in a cell determines its threshold voltage, thus indicating the stored data. The storage cell 112 is a floating-gate field-effect transistor (FET) or a charge-trap FET. In some embodiments, the storage cell 112 may have two possible storage states. For example, the storage cell 112 may be a single-level cell (SLC) storing one bit of data. For instance, the first storage state "0" of the SLC corresponds to a threshold voltage in a first voltage range, and the first storage state "1" corresponds to a threshold voltage in a second voltage range. In other embodiments, storage unit 112 may store at least two bits of data. For example, storage unit 112 may be a multi-level cell (MLC), where each storage unit may store two bits, or three bits (also known as a triple-level cell (TLC)), or four bits (also known as a quad-level cell (QLC)). Each MLC may be programmed to take a range of possible nominal stored values.

[0125] Each substring 111 also includes an upper select gate 113 and a lower select gate 114, which are used to activate the selected substring when erasing, programming, or erasing memory cells. The upper select gate 113 is also called the top select gate (TSG), and the lower select gate 114 is also called the bottom select gate (BSG).

[0126] The memory 100 also includes a plurality of drain select lines (DSLs) 150, each DSL 150 being coupled to an upper select transistor 113 in at least one substring 111, such as Figure 1 As shown, the upper selection tubes 113 in multiple substrings 111 are coupled to the same DSL 150 at the same or similar height from the substrate bearing surface. The substrings 111 coupled to different DSLs are different, for example... Figure 2The diagram illustrates the electrical structure of a storage array according to an exemplary embodiment. DSL0 is coupled to the TSGs of multiple substrings 111 represented by thin solid lines, and DSL1 is coupled to the TSGs of multiple substrings 111 represented by thick solid lines. All substrings 111 coupled to the same DSL can be considered as a single storage string; that is, a storage string includes at least one substring 111. In the case where a storage string includes only one substring 111, this single substring 111 can also be called a storage string. The TSGs of different storage strings are coupled to different DSLs. In the case where a storage string includes multiple substrings 111, the TSGs in the multiple substrings 111 are coupled to the same DSL, and the TSGs of different storage strings are coupled to different DSLs. (Continuing with...) Figure 2 Taking DSL0 and DSL1 as examples, all substrings 111 coupled to DSL0 are organized into a storage string by DSL0, and all substrings 111 coupled to DSL1 are organized into another storage string by DSL1. At this time, the DSL coupled to the storage string is also coupled to the peripheral circuit 140, so that the peripheral circuit 140 can control the switching state of each TSG on the storage string through the DSL.

[0127] The memory 100 also includes a plurality of source select lines (SSLs) 160, each SSL 160 being coupled to a lower select transistor 114 in at least one substring 111, such as Figure 1 As shown, multiple substrings 111 with the same or similar height from the substrate bearing surface are coupled to the same SSL 160. The substrings 111 coupled to different SSLs are different. Figure 2 Taking SSL0 and SSL1 as examples, SSL0 is coupled to the BSG of multiple substrings 111 represented by thin solid lines, and SSL1 is coupled to the BSG of multiple substrings 111 represented by thick solid lines. In other embodiments, storage strings are not divided according to SSL, but according to DSL. For example, all substrings 111 coupled to the same SSL are considered as one storage string, that is, a storage string includes at least one substring 111, and the BSGs of different storage strings are coupled to different SSLs. When a storage string includes multiple substrings 111, the BSGs in the multiple substrings 111 are coupled to the same SSL. Still using... Figure 2 Taking SSL0 and SSL1 as examples, all substrings 111 coupled to SSL0 are organized into a storage string by SSL0, and all substrings 111 coupled to SSL1 are organized into another storage string by SSL1. At this time, the SSL coupled to the storage string is also coupled to the peripheral circuit 140, so that the peripheral circuit 140 can control the switching state of each BSG on the storage string through the SSL.

[0128] One end of each substring 111 is coupled to a bit line 120. For example, one end of the substring is coupled to a bit line contact, and the bit line 120 is also coupled to a bit line contact. The other end of the substring 111 is coupled to a source line (SL) 170. For example, the other end of the substring is coupled to a substrate, and the source line 170 is also coupled to a substrate.

[0129] like Figure 2 As shown, a bit line (BL) can be coupled to multiple substrings 11. For example... Figure 1 and Figure 2 As shown, multiple substrings 111 can be coupled to the same SL170.

[0130] like Figure 1 As shown, memory cells 112 in different substrings 111 that are at the same or similar height from the substrate bearing surface are located on the same layer. Multiple memory cells 112 on the same layer form a memory cell row 11a, that is, the memory array 110 includes multiple memory cell rows, and multiple word lines 130 are coupled to multiple memory cell rows respectively. All substrings 111 in the memory array 110 that share the same set of word lines form a memory block 11b, and each substring 111 in the same memory block 31b is coupled to the same source line 170.

[0131] As the number of storage cell layers increases, multiple etches are needed to form multiple stacked substrings 111. For example, Figure 3 A cross-sectional side view of a substring is shown according to an exemplary embodiment. See also Figure 3 Substring 111 can extend vertically through the memory cell stack layer 320 above the doped semiconductor layer 310. The doped semiconductor layer 310 is coupled to the source line. In some embodiments, the doped semiconductor layer 310 is an N-type doped semiconductor layer, in which case the doped semiconductor layer 310 can serve as a substrate, i.e., an N-type substrate. In other embodiments, the doped semiconductor layer 310 is a P-type doped semiconductor layer, in which case the doped semiconductor layer 310 is a P-well in the substrate, i.e., a P-type substrate.

[0132] The memory cell stack 320 includes alternating gate conductive layers 330 and gate-to-gate dielectric layers 340. The number of logarithms of the gate conductive layers 330 and gate-to-gate dielectric layers 340 in the memory cell stack 320 determines the number of memory cells 112 in the memory array 110. The gate conductive layers 330 may include conductive materials, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicides, or any combination thereof. In one possible implementation, each gate conductive layer 330 includes a metal layer, such as a tungsten layer. In some implementations, each gate conductive layer 330 includes a doped polysilicon layer. Each gate conductive layer 330 may include a gate surrounding the memory cell 112 and may extend laterally at the top of the memory cell stack 320 as DSL 150, at the bottom of the memory cell stack 320 as SSL 160, or between DSL and SSL as WL 130.

[0133] like Figure 3 As shown, substring 111 also includes a channel structure 350 extending vertically through the memory cell stack layer 320, the channel structure 350 including channel vias filled with at least one semiconductor material (such as a semiconductor channel) and at least one dielectric material (such as a memory film). In some embodiments, the semiconductor channel includes silicon (such as a memory film). In some embodiments, the memory film is a composite dielectric layer including a tunnel layer, a trap layer, and a barrier layer. The channel structure 350 may have a cylindrical shape (such as a pillar shape). According to some embodiments, the semiconductor channel, the trap layer (also referred to as the memory layer), and the barrier layer are arranged radially from the center of the pillar toward the outer surface of the pillar in this order. The tunnel layer may include silicon oxide, silicon oxynitride, or any combination thereof. The trap layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0134] like Figure 3 As shown, a doped semiconductor layer 360 is stacked on top of the memory cell stacking layer 320 in substring 111. The doped semiconductor layer 360 is also called a bit line contact. The doped semiconductor layer 360 is coupled to the bit line and connected. The doped semiconductor layer 360 is an N-type doped semiconductor layer.

[0135] When the doped semiconductor layer 360 is an N-type doped semiconductor layer, the substring 111 can be erased using gate-induced drain leakage (GIDL) erasure via the bit lines coupled to the doped semiconductor layer 360 and the DSL coupled to the TSG in the substring 111. For example, an erase voltage is applied to the bit lines coupled to the doped semiconductor layer 360, so that the erase voltage acts on the doped semiconductor layer 360. A voltage smaller than the erase voltage is applied to the DSL coupled to the TSG in the substring 111, creating a voltage difference between the gate of the TSG and the doped semiconductor layer 360. This voltage difference causes band-to-band tunneling at the location between the gate of the TSG and the doped semiconductor layer 360, generating GIDL. Holes in the GIDL move from this location into the channel of the substring 111, thereby injecting holes into the channel of the substring 111 from this location, increasing the channel potential. A voltage less than the erase voltage (called low voltage, such as 0V) is applied to the word line coupled to each memory cell in substring 111 to apply the low voltage to the gate of the memory cell. As the channel potential of the memory cell increases, the voltage difference between the gate and the channel of the memory cell increases. When the voltage difference is greater than the tunneling voltage of the memory cell, the voltage difference causes a tunneling effect between the channel and the gate of the memory cell. As a result, the holes in the channel of the memory cell tunnel to the memory layer of the memory cell to eliminate the electrons in the memory layer, thereby erasing the memory cell.

[0136] In some embodiments, when the doped semiconductor layer 310 is an N-type doped semiconductor layer, the sub-string block can be erased using a GIDL erasure method via the source line coupled to the doped semiconductor layer 310 and the SSL coupled to the BSG in the sub-string 111. For example, an erase voltage is applied to the source line, and a voltage lower than the erase voltage (called a low voltage) is applied to the SSL coupled to the BSG, causing a GIDL to be generated at the position between the gate of the BSG and the doped semiconductor layer 310. Holes in the GIDL move towards the channel, thereby injecting holes into the channel of the sub-string 111 from this position, increasing the potential of the channel. A low voltage is applied to the word line coupled to each memory cell in the sub-string 111. As the channel potential of the memory cell increases, when the voltage difference between the gate of the memory cell and the channel of the memory cell is greater than the tunneling voltage of the memory cell, the holes in the channel tunnel to the memory layer of the memory cell to eliminate electrons in the memory layer, thereby erasing the memory cell.

[0137] Based on this, when both the doped semiconductor layer 310 and the doped semiconductor layer 310 are N-type doped semiconductor layers, the peripheral circuit can erase the substring 111 at either end using the GIDL erasure method (i.e., single-ended GIDL erasure method), or it can erase the substring 111 at both ends using the GIDL erasure method (i.e., double-ended GIDL erasure method).

[0138] In other embodiments, when the doped semiconductor layer 310 is a P-type doped semiconductor layer, the substring 111 is erased based on the erasure method of the P-type doped semiconductor layer. For example, an erase voltage is applied to the source line to apply the erase voltage to the P-type doped semiconductor layer, causing holes to be generated in the P-type doped semiconductor layer. A low voltage is applied to the BSG of the substring 111 and the word lines coupled to each memory cell, so that the low voltage applies to the gate of the BSG and the gate of each memory cell. Since the low voltage is less than the erase voltage, holes move from the P-type doped semiconductor layer to the channel of the substring 111 to inject holes from the P-type doped semiconductor layer into the channel, causing the channel potential to rise. As the channel potential of the memory cell increases, when the voltage difference between the gate of the memory cell and the channel of the memory cell is greater than the tunneling voltage of the memory cell, the holes in the channel tunnel to the memory layer of the memory cell to eliminate electrons in the memory layer, thereby erasing the memory cell.

[0139] Based on this, when the doped semiconductor layer 360 is an N-type doped semiconductor layer and the doped semiconductor layer 310 is a P-type doped semiconductor layer, double-end erasure can be performed on substring 111. For example, a single-end GIDL erasure can be performed at the end of substring 111 closest to the N-type doped semiconductor layer, and an erasure based on the P-type doped semiconductor layer can be performed at the other end of substring 111. Alternatively, single-end erasure can be performed on substring 111, for example, a single-end GIDL erasure can be performed at the end of substring 111 closest to the P-type doped semiconductor layer, without erasing based on the P-type doped semiconductor layer at the other end of substring 111, or a single-end GIDL erasure can be performed at the end of substring 111 closest to the P-type doped semiconductor layer, and an erasure based on the P-type doped semiconductor layer can be performed at the other end of substring 111.

[0140] The storage unit 112 described above can be in an erase state or a programming state, and there can be multiple programming states. The erase state represents the original state of the storage unit before programming, or the state where no data is stored; it can also be understood as storing data as "0". The programming state represents the state where different data is stored. For example, for the SLC storage unit described above, which can store 1 bit of data, only one binary data "0" is needed to represent the erase state, and one binary data "1" is needed to represent the programming state. For the MLC storage unit described above, which can store 2 bits of data, one erase state is needed to represent data "00", and three programming states are needed to represent data "01", "10", and "11".

[0141] The erase and program states described above are essentially represented by the threshold voltage of the memory cell. Since the memory cell can trap electrons, by applying a voltage between the gate electrode and the channel, electrons can be tunneled through the tunneling layer to reach the memory layer, i.e., the electron trapping layer, thus confining the electrons within the memory layer. Changes in the amount of electrons in the memory layer cause changes in the threshold voltage of that memory cell. Therefore, to store data in the memory cell, corresponding electrons can be injected into the memory layer. This electron injection process can be called "programming," that is, adjusting the state of the memory cell from the erase state to different program states through programming.

[0142] Return to reference Figure 1 The peripheral circuit 140 is coupled to multiple word lines 130. The peripheral circuit 140 controls the voltage V of the word lines 130 coupled to the selected memory string. WL and the voltage V of the bit line coupled to the selected memory string. BL The following operation method is implemented by controlling the storage cells in the selected storage string.

[0143] Peripheral circuitry 140 includes various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 4 A schematic diagram of a peripheral circuit is shown according to an exemplary embodiment. For example... Figure 3 The peripheral circuitry 140 shown includes a page buffer / sensor amplifier 402, a column decoder / bit line (BL) driver 404, a row decoder / word line (WL) driver 406, a voltage generator 408, a control logic unit 410, a register 412, an interface (I / F) 414, and a data bus 316. In some examples, it also includes... Figure 3Additional peripheral circuitry is not shown. The page buffer / sensor amplifier 402 can be configured to read data from and program (write) data to the memory array 110 according to control signals from the control logic unit 410. In one example, the page buffer / sensor amplifier 402 can store a page of programming data (write data) to be programmed into a page of the memory array 110. In another example, the page buffer / sensor amplifier 402 can perform a programming verification operation to ensure that data has been correctly programmed into the memory cell 112 coupled to the selected word line. In yet another example, the page buffer / sensor amplifier 402 can also sense a low-power signal from the bit line representing a data bit stored in the memory cell 112 and amplify a small voltage swing to a recognizable logic level during a read operation. The column decoder / bit line driver 404 can be configured to be controlled by the control logic unit 410 and to select one or more substrings 111 by applying a bit line voltage generated from the voltage generator 408.

[0144] The line decoder / word line driver 406 can be configured to be controlled by the control logic unit 410 and to select / deselect word lines 130 of memory blocks 31b of the memory array 110. The line decoder / word line driver 406 can also be configured to drive word lines using word line voltages generated from the voltage generator 408. In some embodiments, the line decoder / word line driver 406 can also select / deselect and drive DSL and SSL. As described in detail below, the line decoder / word line driver 406 is configured to perform erase operations on memory cells 112 coupled to one or more selected word lines. The voltage generator 408 can be configured to be controlled by the control logic unit 410 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory array 110.

[0145] Control logic unit 410 can be coupled to each of the peripheral circuits 140 described above and is configured to control the operation of each peripheral circuit 140. Register 412 can be coupled to control logic unit 410 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit 140. Interface 414 can be coupled to control logic unit 410 and acts as a control buffer to buffer control commands received from a host (not shown) and relay them to control logic unit 410, as well as to buffer status information received from control logic unit 410 and relay it to the host. Interface 414 can also be coupled to column decoder / bit line driver 404 via data bus 316 and acts as a data I / O interface and data buffer to buffer data and relay it to or from memory array 110.

[0146] The peripheral circuitry is configured to erase memory strings within a memory block, on a block-by-block basis. As the number of erase cycles increases, the erase depth of each memory string becomes inconsistent. The erase depth of a memory string refers to the erase depth of its substrings. All substrings within the same memory string have the same erase depth, indicated by the threshold voltage of the memory cells within that substring. For example, a lower threshold voltage results in a shallower erase depth, and vice versa. However, memory cells in substrings with deeper erase depths are prone to lateral diffusion after programming, causing the threshold voltage of the memory cells to drift. The following section will discuss this further. Figure 5 and Figure 6 Taking examples, the principles of lateral diffusion and threshold voltage drift are introduced below.

[0147] Figure 5 This is a schematic diagram illustrating the principle of lateral diffusion according to an exemplary embodiment, assuming... Figure 5 The diagram shows a substring with a relatively deep erase depth, illustrating some of the memory cells within the substring: memory cells n-1 to n+1, which are coupled to word lines WLn-1 to WLn+1, respectively. Each memory cell includes a channel, a tunnel layer, a capture layer, and a blocking layer. Figure 5As shown, after the substring undergoes an erase operation and then full-block random programming, assuming that memory cell n is in the programming state P, and the two adjacent memory cells (memory cells n+1 and n-1) are in the erase state E. Since memory cells n+1 and n-1 are in the erase state E, the capture layers of memory cells n-1 and n+1 contain a small number of electrons or no electrons, resulting in relatively low threshold voltages for memory cells n-1 and n+1. However, since memory cell n is in the programming state P, and the higher the programming state P, the higher the threshold voltage of memory cell n, leading to a larger threshold voltage difference between memory cells n and n-1. This triggers electrons in the capture layer of memory cell n to move towards the capture layers of memory cells n-1 and n+1, i.e., lateral diffusion occurs.

[0148] Electrons in the trapping layer of memory cell n move to both sides, reducing the number of electrons in the trapping layer and causing a decrease in the threshold voltage of memory cell n, i.e., causing the threshold voltage of memory cell n to drift. Figure 6 A schematic diagram illustrating a threshold voltage drift caused by lateral diffusion is shown in an exemplary embodiment. Assuming that the threshold voltage VT of the memory cell n is in the programming state P as curve 601, after the electrons in the trapping layer of the memory cell n undergo lateral diffusion, the threshold voltage VT curve 601 drifts to the left, resulting in curve 602.

[0149] The threshold voltage of memory cells in the erased state on substrings with deeper erase depths is lower than that on substrings with shallower erase depths. Especially in substrings with deeper erase depths, once a memory cell in the programming state is adjacent to a memory cell in the erased state, the lower threshold voltage of the adjacent memory cells causes the electrons stored in the programming memory cell to diffuse more severely to the adjacent memory cells. This leads to a more severe drift in the threshold voltage of the programming memory cell. When the threshold voltage drift is severe, the data stored in the memory cell may change, thus reducing the data retention characteristic of the memory cell.

[0150] Based on this, this application provides a memory operation method to avoid excessive erasure of memory strings in a memory block and to prevent the occurrence of memory strings with excessively deep erasures. For example, Figure 7A flowchart illustrating an operation method of a memory according to an exemplary embodiment is provided, wherein the memory includes a memory array and peripheral circuitry. Taking the memory 100 described above as an example, the memory array is a memory array 110. The memory array has at least one memory block, each memory block includes multiple memory strings, and each memory string includes at least one substring. First select transistors of each substring within the same memory string are coupled to the same first select line. The first select transistor can be either a BSG or a TSG of the substring. For example, if each TSG of the same memory string is coupled to the same DSL, and each BSG of the same memory string is not coupled to the same SSL, then the first select transistor is a TSG. If each TSG of the same memory string is coupled to the same DSL, and each BSG of the same memory string is not coupled to the same SSL, then the first select transistor can be either a TSG or a BSG.

[0151] For ease of description, the selection line coupled to the first selection transistor of the substring is called the first selection line, the doped semiconductor layer closest to the first selection transistor among the doped semiconductor layers coupled at both ends of the substring is called the first doped semiconductor layer, and the contact line (such as BL or SL) coupled to the first doped semiconductor layer is called the first contact line. For example, if the first selection transistor is BSG, then the first doped semiconductor layer is a P-well or N-type substrate in the substrate, and the first contact line is SL; if the first selection transistor is TSG, then the first doped semiconductor layer is an N-type doped semiconductor layer, and the first contact line is BL.

[0152] For ease of description, the selector at the other end of the substring is referred to as the second selector, the doped semiconductor layer closest to the second selector among the doped semiconductor layers coupled at both ends of the substring is referred to as the second doped semiconductor layer, and the contact line (such as BL or SL) coupled to the second doped semiconductor layer is referred to as the second contact line. For example, if the first selector is TSG, then the second selector is BSG, the second doped semiconductor layer is a P-well or an N-type substrate, and the second contact line is SL; if the first selector is BSG, then the second selector is TSG, the second doped semiconductor layer is an N-type doped semiconductor layer, and the second contact line is BL.

[0153] The peripheral circuit is configured to execute a memory operation method, which includes erasing multiple memory strings in a memory block. The memory block is any memory block in a memory array awaiting data erasure. The memory block contains at least one memory string that has not been erased; this at least one memory string may be a portion of the memory strings in the memory block or all the memory strings in the memory block. To distinguish between erased and incompletely erased memory strings in the memory block, the erased memory strings are referred to as the first memory string, and the incompletely erased memory strings are referred to as the second memory string. It should be understood that the first and second memory strings are different memory strings within the memory block. The first select transistor in the first memory string is different from the first select transistor in the second memory string; the first select line coupled to the first select transistor in the first memory string is different from the first select line coupled to the first select transistor in the second memory string; the second select transistor in the first memory string is different from the second select transistor in the second memory string; and the first select line coupled to the second select transistor in the first memory string is different from the first select line coupled to the second select transistor in the second memory string.

[0154] For example, if all memory strings in the memory block are second memory strings, the erase operation is described as follows:

[0155] Starting from the third time point, a first voltage is applied to the first contact line coupled to the first doped semiconductor layer of each memory string in the memory block, and this application continues until the seventh time point, ensuring that the first voltage acts on the first doped semiconductor layer of each memory string from the third to the seventh time point. From the third time point to the second time point, a second voltage is continuously applied to the first select line coupled to the first select transistor of each memory string in the memory block, ensuring that the gate voltage (i.e., gate voltage) of the first select transistor of each memory string remains at the second voltage from the third to the second time point. From the second time point to the seventh time point, the first select line coupled to the first select transistor of each memory string is floated, ensuring that the gate of the first select transistor of each memory string is in a floating state. From the third time point to the seventh time point, a third voltage is continuously applied to the word line coupled to each memory cell of each memory string in the memory block.

[0156] The third time point is the start time of the erase operation on multiple memory strings in the memory block, the seventh time point is the end time of the erase operation, and the second time point is any time between the third and seventh time points. The second time point is the time during which the first select transistor is floating during the erase process of the memory block if all memory strings in the memory block have not been erased. The value of the second time point may be the same or different in different application scenarios; therefore, this application embodiment does not limit the second time point. The first voltage, also called the erase voltage or erase pulse, is greater than the second voltage. The second voltage is used to turn on the memory strings and is greater than or equal to 0V and less than the threshold voltage of the first select transistor. The first voltage is greater than the third voltage, and the voltage difference between the first and third voltages is greater than the tunneling voltage of the memory cell. The third voltage is greater than or equal to 0V. Here, this application embodiment does not limit the value range of the first, second, and third voltages.

[0157] For the erase operation described above, if the first doped semiconductor layer is a P-type doped semiconductor layer, from the third time point to the seventh time point, the first voltage causes the P-type doped semiconductor layer to continuously generate holes. From the third time point to the second time point, since the gate voltage (i.e., the second voltage) of the first select transistor in the memory string and the gate voltage (i.e., the third voltage) of each memory cell are both less than the first voltage, the holes move towards the channel of the memory string where the first select transistor is located (i.e., the channel of each substring in the memory string) to raise the channel potential. From the second time point to the seventh time point, the gate of each first select transistor is in a floating state, so that the gate of the first select transistor and the first doped semiconductor layer coupled to the substring where the first select transistor is located are coupled into a capacitor. The voltage jump principle across the capacitor causes the gate voltage of the first select transistor to change with the change of the first voltage on the first doped semiconductor layer, thereby reducing the voltage difference between the gate of the first select transistor and the first doped semiconductor layer. This reduction in voltage difference reduces the number of holes transported to the channel of the memory string, slowing down the rate of increase in channel potential.

[0158] For the erase operation described above, if the first doped semiconductor layer is an N-type doped semiconductor layer, from the third time point to the second time point, because the gate voltage (i.e., the second voltage) of the first select transistor is less than the first voltage on the first doped semiconductor layer, a GIDL (Gate-to-Dip) is generated between the gate of the first select transistor and the first doped semiconductor layer. Holes in the GIDL move towards the channel of the memory string to raise the channel potential. From the third time point to the second time point, the gate of the first select transistor is in a floating state, which reduces the voltage difference between the gate of the first select transistor and the first doped semiconductor layer. This reduction in voltage difference decreases the number of holes in the GIDL, thereby reducing the number of holes transported to the channel of the memory string and slowing down the rate of increase in channel potential.

[0159] For the erase operation described above, from the third time point to the seventh time point, as the channel potential of the memory string increases, when the voltage difference (i.e., voltage drop) between the channel and gate of any memory cell in the memory string is greater than the tunneling voltage of the memory cell, the data stored in that memory cell can be erased. From the second time point to the seventh time point, as the number of holes transported to the channel of the memory string decreases, the rate of electron elimination within the storage layer of the memory cell decreases, thus preventing over-erasure of incompletely erased memory strings during this erase operation.

[0160] If a first memory string and a second memory string exist in the memory block, and the first select transistors of each memory string are floated at the second time according to the above-mentioned erase operation, then the electrons in the storage layer of the storage cell of the first memory string that has been erased after the second time will continue to be eliminated, increasing the erase depth of the first memory string. This makes it easy for the first memory string to be over-erased. Especially after multiple erase operations are performed on the memory block, after the first memory string is erased, as the number of subsequent erase operations increases, the electrons in the storage layer of the storage cell of the first memory string will continue to be eliminated, thereby further increasing the possibility of the first memory string being over-erased.

[0161] Based on this, when there is a first storage string and a second storage string in the storage block, during the erase operation of the storage block, the first selection transistor of the first storage string is floated in advance before the first selection transistor of the second storage string is floated, and then the second storage string is floated normally. For ease of description, the time when the first selection transistor of the first storage string is floated is called the first moment. The first moment is any moment between the third moment and the second moment, that is, the third moment is before the first moment and the second moment is after the first moment. The first moment can be obtained according to the specific product test. Here, the embodiments of this application do not limit the first moment.

[0162] For example, when a first memory string and a second memory string exist in a memory block, the erase operation performed on the multiple memory strings in the memory block includes: applying a first voltage to the first doped semiconductor layer coupled to each memory string in the memory block at a third time before the first time; applying a second voltage to the first select line coupled to the first select transistor of the first memory string from the third time to the first time; applying a second voltage to the first select line coupled to the first select transistor of the second memory string from the third time to the second time; and applying a third voltage to the word line coupled to each memory cell of each memory string in the memory block at the third time.

[0163] For example, Figure 7A voltage waveform diagram of a memory block during single-ended erasure is shown according to an exemplary embodiment. Assuming T0 is the third time point, T1 is the first time point, T2 is the second time point, and T3 is the seventh time point, starting from the third time point T0, a first voltage is applied to the first contact line coupled to the first doped semiconductor layer of each memory string in the memory block, until the application of the first voltage ends at the seventh time point T3, such that the first voltage acts on the first doped semiconductor layer coupled to each memory string from the third time point to the seventh time point. From the third time point T0 to the seventh time point T3, a third voltage (not applied during single-ended erasure) is applied to the word line coupled to the memory cell of each memory string. Figure 7 (as shown in the image).

[0164] From the third time T0 to the first time T1, the applied voltage to the first select line coupled to the first select transistor of the first memory string in the memory block is the second voltage, so that the gate of the first select transistor of the first memory string is maintained at the second voltage from the third time T0 to the first time T1. Under the action of the first voltage and the second voltage, holes generated by the first doped semiconductor layer coupled to the first memory string, or holes generated at the position between the first doped semiconductor layer and the first select transistor, move towards the channel of the first memory string (i.e., the channel of each sub-string of the first memory string) to raise the potential of the channel. From the third time T0 to the first time T3, the applied voltage to the word line coupled to the memory cell of the first memory string is the third voltage (not in the third time T0). Figure 7 As shown in the figure, the voltage (i.e., gate voltage) of the gate of the memory cell of the first memory string is maintained at a third voltage. During this period, as the channel potential of the first memory string increases, when the voltage difference between the channel and the gate of any memory cell of the first memory string is greater than the tunneling voltage of the memory cell, electrons in the storage layer of the memory cell of the first memory string are eliminated.

[0165] From the third time T0 to the second time T2, the applied voltage to the first select line coupled to the first select transistor of the second memory string in the memory block is the second voltage. This causes the gate of the first select transistor of the second memory string to remain at the second voltage from the third time T0 to the second time T2. Under the influence of the first and second voltages, holes generated by the first doped semiconductor layer coupled to the second memory string, or holes generated at the position between the first doped semiconductor layer and the first select transistor, move towards the channel of the second memory string (i.e., the channel of each sub-string of the second memory string) to raise the channel potential. From the third time T0 to the second time T2, a third voltage (not applied during the second time string) is applied to the word line coupled to the memory cell of the second memory string. Figure 7 As shown in the figure, the gate voltage of the gate of the memory cell of the second memory string is maintained at a third voltage. During this period, as the channel potential of the second memory string increases, when the voltage difference between the channel and the gate of any memory cell of the second memory string is greater than the tunneling voltage of the memory cell, electrons in the storage layer of the memory cell of the second memory string are eliminated.

[0166] In the case where a first storage string and a second storage string exist in the storage block, the erase operation for multiple storage strings in the storage block also includes... Figure 8 It should be understood that the step numbers shown in steps 801 and 802 are used to distinguish different operations. The step numbers do not represent the actual order of operations and can be changed.

[0167] 801. At the first moment, the first selection line coupled to the first selection tube of the first memory string is floated, and the first memory string is the memory string that has been erased among the multiple memory strings of the memory block.

[0168] Still with Figure 7 For example, starting from the third time T0, after a first duration, the first time T1 is reached. From the first time T1, the first selection line coupled to the gate of the first selection transistor of the first memory string is floated until the seventh time T3. During this period, the gate of the first selection transistor of the first memory string is in a floating state, so that the gate of the first selection transistor of the first memory string is coupled to the corresponding first doped semiconductor layer (i.e., the first doped semiconductor layer coupled to the substring where the first selection transistor is located) to form a capacitor. The voltage jump principle across the capacitor causes the gate voltage of the first selection transistor of the first memory string to change with the change of the first voltage, thereby reducing the voltage difference between the gate of the first selection transistor of the first memory string and the corresponding first doped semiconductor layer. This results in a reduction of holes transported to the channel of the first memory string, which reduces the rate at which electrons in the storage layer of the storage cell of the first memory string are eliminated from the first time T1 to the seventh time T3. This can prevent the first memory string from being over-erased, and thus reduce the increase in the erase depth of the first memory string during this erase operation.

[0169] It should be understood that, since different memory cells within a memory block may be in different programming states, the higher the programming state of the memory cell, the higher the threshold voltage. Multiple erase processes may be required to complete the erasure of all memory strings within the memory block. This application, by reasonably setting the first and second time points, can mitigate over-erasure caused by the continued erasure of already erased memory strings in subsequent erase processes. Thus, after all memory strings in the memory block have been erased, the erase depth of each memory string is approximately uniform, and the memory cells within each memory string are not over-erased. This reduces the threshold voltage of each memory cell in the erased state within the memory block. The threshold voltage will not shift significantly to the left, meaning it will not decrease significantly. Even after subsequent programming, if two adjacent memory cells in the programmed state are in the erased state, the threshold voltage difference between the programmed and erased memory cells will not be as large because the threshold voltage of the erased memory cells has not decreased significantly. Consequently, the number of electrons moving from the programmed memory cells to the erased memory cells will be reduced, thus weakening lateral diffusion and reducing the threshold voltage drift of the programmed memory cells. Consequently, the data retention characteristics of the memory cells are improved.

[0170] 802. At the second moment after the first moment, the first selection line coupled to the first selection tube of the floating second memory string is set, and the second memory string is the memory string that has not been erased among multiple memory strings in the memory block.

[0171] Still with Figure 7 For example, starting from the first time T1, after a second time period, the second time T2 is reached. From the second time T2, the first selection line coupled to the first selection transistor of the second memory string is floated until the seventh time T3. During this period, the gate of the first selection transistor of the second memory string is in a floating state, so that the gate of the first selection transistor of the second memory string is coupled with the corresponding first doped semiconductor layer (i.e., the first doped semiconductor layer coupled to the substring where the first selection transistor is located) to form a capacitor. The voltage jump principle across the capacitor causes the gate voltage of the first selection transistor of the second memory string to change with the change of the first voltage, thereby reducing the voltage difference between the gate of the first selection transistor of the second memory string and the corresponding first doped semiconductor layer. This results in a reduction of holes transported to the channel of the second memory string, which reduces the rate at which electrons in the storage layer of the storage cell of the second memory string are eliminated from the second time T2 to the seventh time T3, thereby preventing the second memory string from being over-erased.

[0172] The erase operation performed on multiple memory strings in the memory block further includes: at a third time moment, applying a fourth voltage to the second doped semiconductor layer coupled to each memory string in the memory block; and at the same third time moment, floating the second select line coupled to the second select transistor of each memory string in the memory block to prevent the injection of holes from the second select transistor of the memory string into the channel. The fourth voltage is greater than 0V, and may be the same as or different from the first voltage.

[0173] Still with Figure 7 For example, starting from the third time T0, a fourth voltage is applied to the second contact line coupled to the second doped semiconductor layer of each memory string in the memory block until the application of the fourth voltage ends at the seventh time T3, so that the fourth voltage acts on the second doped semiconductor layer. Starting from the third time T0, the second selection line coupled to the second selection transistor of each memory string in the memory block is floated until the floatation ends at the seventh time T3. During this period, the gate of the second selection transistor is in a floating state, so that the gate of the second selection transistor is coupled to the corresponding second doped semiconductor layer (i.e., the second doped semiconductor layer coupled to the substring where the second selection transistor is located) to form a capacitor. The voltage jump principle across the capacitor causes the gate voltage of the second selection transistor to change with the fourth voltage, so as to maintain the voltage difference between the gate of the second selection transistor and the second doped semiconductor layer basically constant. This voltage difference is greater than 0V. When the second doped semiconductor layer is an N-type doped semiconductor layer, this voltage difference is insufficient to generate GIDL, or the GIDL generated by this voltage difference is relatively small, and the holes in the GIDL are insufficient to erase the data in the memory cell. When the second doped semiconductor layer is a P-type doped semiconductor layer, the voltage difference is relatively small and insufficient to allow a large number of holes in the second doped semiconductor layer to enter the channel, thus insufficient to erase the data in the memory cell. This completes the injection of holes from one end of the memory string in the memory block into the channel to erase the data stored in the memory cell of the memory string, realizing single-end erasure.

[0174] The method provided in this application embodiment reduces the erasure speed of the first storage string by, when performing an erase operation on multiple storage strings in a storage block, if there is a first storage string that has been erased and a second storage string that has not been erased, floating the selection line coupled to the first selection transistor of the first storage string before floating the selection line coupled to the first selection transistor of the second storage string. This avoids the first storage string being over-erased during the erasure of the second storage string, reduces the possibility of lateral diffusion of the storage cells in the first storage string after programming, and weakens the drift of the threshold voltage of the storage cells in the first storage string.

[0175] The method provided in this application embodiment reduces the erasure speed of the first storage string by, when performing an erase operation on multiple storage strings in a storage block, if there is a first storage string that has been erased and a second storage string that has not been erased, floating the selection line coupled to the first selection transistor of the first storage string before floating the selection line coupled to the first selection transistor of the second storage string. This avoids the first storage string being over-erased during the erasure of the second storage string, reduces the possibility of lateral diffusion of the storage cells in the first storage string after programming, and weakens the drift of the threshold voltage of the storage cells in the first storage string.

[0176] In other embodiments, if the first doped semiconductor layer coupled to each memory string of the memory block is coupled to BL, and the first doped semiconductor layer is an N-type doped semiconductor layer, and the second doped semiconductor layer coupled to each memory string of the memory block is coupled to SL, and the second doped semiconductor layer is an N-type or P-type doped semiconductor layer, then double-ended erasure of the memory strings in the memory block is also possible. Alternatively, if the first doped semiconductor layer coupled to each memory string of the memory block is coupled to SL, and the first doped semiconductor layer is an N-type or P-type doped semiconductor layer, and the second doped semiconductor layer coupled to each memory string of the memory block is coupled to BL, and the second doped semiconductor layer is an N-type doped semiconductor layer, then double-ended erasure of the memory strings in the memory block is also possible.

[0177] In the case of double-ended erasure, in some embodiments, during the erasure operation on multiple memory strings of a memory block, the selection line coupled to the first or second selection transistor of the first memory string is pre-floated. This pre-floating scheme will be described below:

[0178] The process of pre-floating the first selection transistor of the first memory string is similar to the process of pre-floating the second selection transistor of the first memory string. Here, we will take the pre-floating first selection transistor of the first memory string as an example. The process of pre-floating the second selection transistor of the first memory string can be referred to the process of pre-floating the first selection transistor of the first memory string.

[0179] For example, the erase operation performed on multiple memory strings of a memory block includes: at a third time, applying a fifth voltage to the second doped semiconductor layer coupled to each memory string in the memory block; at a first time, floating the first select line coupled to the first select transistor of the first memory string (as described in step 801 above); at a second time after the first time, floating the first select line coupled to the first select transistor of the second memory string (as described in step 802 above); from the third time to the second time, applying a sixth voltage to the second select line coupled to the second select transistor of each memory string in the memory block; at the second time, floating the second select line coupled to the second select transistor of each memory string in the memory block. Since the first time is before the second time, the first select transistor of the first memory string is floated in advance.

[0180] Wherein, the fifth voltage is greater than 0, and the fifth voltage may be the same as or different from the first voltage. The sixth voltage is less than the fifth voltage. For example, the sixth voltage is greater than or equal to 0 and less than the fifth voltage. The sixth voltage may be the same as or different from the second voltage. Here, the embodiments of this application do not limit the range of values ​​for the fifth voltage and the sixth voltage.

[0181] For any memory string in the memory block, holes are injected into the channel of the memory string by applying a fifth voltage to the second doped semiconductor layer coupled to the memory string and a sixth voltage to the second select line coupled to the second select transistor of the memory string. The method of injecting holes is similar to the method of injecting holes into the channel by applying a first voltage and a second voltage to the memory string. The difference is that the direction of injecting holes into the channel of the memory string is different. For example, applying a fifth voltage and a sixth voltage to the memory string injects holes from the second select transistor of the memory string into the channel of the memory string, while applying a first voltage and a second voltage to the memory string injects holes from the first select transistor of the memory string into the channel of the memory string.

[0182] The following is combined Figure 9 The control process of pre-floating the first select transistor of the first memory string during double-ended erasure is described below.

[0183] Figure 9 This is a voltage waveform diagram of a memory block during double-ended erasure, according to an exemplary embodiment, wherein the process of applying voltage to the first contact line, the gate of the first select transistor of the first memory string, and the gate of the second select transistor of the second memory string is... Figure 7 Similarly, I will not go into details here.

[0184] like Figure 9As shown, starting from the third time T0, a fifth voltage is applied to the second contact line coupled to the second doped semiconductor layer of each memory string in the memory block, until the application of the fifth voltage ends at the seventh time T3, so that the fifth voltage acts on the second doped semiconductor layer. From the third time T0 to the seventh time T3, a third voltage is continuously applied to the word line coupled to each memory cell of each memory string (without...). Figure 9 (as shown in the image).

[0185] From the third time T0 to the second time T2, a sixth voltage is continuously applied to the second selection line coupled to the second selection transistor of each memory string in the memory block, so that the gate voltage of the second selection transistor is maintained at the sixth voltage. Under the action of the fifth and sixth voltages, holes generated by the second doped semiconductor layer coupled to the memory string or holes generated at the position between the second doped semiconductor layer and the second selection transistor move into the channel of the memory string to raise the channel potential. As the channel potential of each memory string increases, when the voltage difference between the channel and the gate of any memory cell is greater than the tunneling voltage of the memory cell, electrons in the memory layer of the memory cell are eliminated.

[0186] Starting from the second time T2, the second selection line coupled to the second selection transistor of each memory string is floated until the seventh time T3. During this period, the gate of the second selection transistor of each memory string is in a floating state, so that the gate of the second selection transistor of the memory string is coupled to the corresponding second doped semiconductor layer (i.e., the second doped semiconductor layer coupled to the substring where the second selection transistor is located) to form a capacitor. The voltage jump principle across the capacitor causes the gate voltage of the second selection transistor of each memory string to change with the change of the fifth voltage, thereby reducing the voltage difference between the gate of the second selection transistor of each memory string and the corresponding second doped semiconductor layer. This results in a reduction of holes transported to the channel of each memory string, which slows down the rate at which electrons in the storage layer of the memory cell of each memory string are eliminated from the second time T2 to the seventh time T3, thereby preventing each memory string from being over-erased.

[0187] In the case of double-ended erasure, in some embodiments, during the erasure operation on multiple memory strings of a memory block, the first select transistor of the first memory string and the second select line coupled to the second select transistor are advanced. This advanced floating scheme will be described below.

[0188] For ease of description, the time when the second selector of the first memory string is floating is referred to as the fourth time, and the time when the second selector of the second memory string is floating is referred to as the fifth time. The fourth time is any time between the third and fifth times, and may be the same as or different from the first time. The fifth time is any time between the third and seventh times, and may be the same as or different from the second time. In this embodiment, the fourth and fifth times are not limited.

[0189] For example, the erase operation performed on multiple memory strings of a memory block includes: at a third time, applying a fifth voltage to the second doped semiconductor layer coupled to each memory string in the memory block; at a first time, floating the first select line coupled to the first select transistor of the first memory string (as described in step 801 above); at a second time after the first time, floating the first select line coupled to the first select transistor of the second memory string (as described in step 802 above); from the third time to the fourth time, applying a seventh voltage to the second select line coupled to the second select transistor of the first memory string, and at the fourth time, floating the second select line coupled to the second select transistor of the first memory string; from the third time to the fifth time after the fourth time, applying a seventh voltage to the second select line coupled to the second select transistor of the second memory string, and at the fifth time, floating the second select line coupled to the second select transistor of the second memory string. Since the first time is before the second time and the fourth time is before the fifth time, the first select transistor and the second select transistor of the first memory string are floated in advance.

[0190] Wherein, the seventh voltage is less than the fifth voltage. For example, the seventh voltage is greater than or equal to 0 and less than the fifth voltage. The seventh voltage may be the same as or different from the second voltage. In this embodiment of the application, the range of the seventh voltage is not limited.

[0191] For any memory string, holes are injected into the channel of the memory string by applying a fifth voltage to the second doped semiconductor layer coupled to the memory string and a seventh voltage to the second select line coupled to the second select transistor of the memory string. The method of injecting holes is similar to the method of injecting holes into the channel by applying a first voltage and a second voltage to the memory string. The difference is that the direction of injecting holes into the channel of the memory string is different. For example, applying a fifth voltage and a seventh voltage to the memory string injects holes from the second select transistor of the memory string into the channel of the memory string, while applying a first voltage and a second voltage to the memory string injects holes from the first select transistor of the memory string into the channel of the memory string.

[0192] The following is combined Figure 10 The control process of pre-floating the selectors at both ends of the first memory string during double-ended erasure is described below.

[0193] Figure 10 This is a voltage waveform diagram of a memory block during a double-ended erase, illustrated according to an exemplary embodiment. The process of applying voltage to the first contact line, the first select line coupled to the first select transistor of the first memory string, and the first select line coupled to the first select transistor of the second memory string is... Figure 7 Similarly, I will not go into details here.

[0194] like Figure 10 As shown, starting from the third time T0, a fifth voltage is applied to the second contact line coupled to the second doped semiconductor layer of each memory string in the memory block, until the application of the fifth voltage ends at the seventh time T3, so that the fifth voltage acts on the second doped semiconductor layer. From the third time T0 to the seventh time T3, a third voltage is continuously applied to the word line coupled to each memory cell of each memory string (without...). Figure 10 (as shown in the image).

[0195] From the third time T0 to the fourth time T4, a seventh voltage is continuously applied to the second selection line coupled to the second selection transistor of each memory string in the memory block, so that the gate voltage of the second selection transistor of each memory string is maintained at the seventh voltage. Under the action of the fifth voltage and the seventh voltage, holes generated by the second doped semiconductor layer coupled to the memory string or holes generated at the position between the second doped semiconductor layer and the second selection transistor move into the channel of the memory string to raise the channel potential. As the channel potential of each memory string increases, when the voltage difference between the channel and the gate of any memory cell is greater than the tunneling voltage of the memory cell, electrons in the memory layer of the memory cell of the memory string are eliminated.

[0196] Starting from time T4, the second selection line coupled to the second selection transistor of the first memory string is floated until time T3, during which time the floating ends. During this period, the gate of the second selection transistor of the first memory string is in a floating state. The gate of the second selection transistor of the first memory string is coupled to the corresponding second doped semiconductor layer (i.e., the second doped semiconductor layer coupled to the substring where the second selection transistor is located) to form a capacitor. The voltage jump principle across the capacitor causes the gate voltage of the second selection transistor of the first memory string to change with the change of the fifth voltage, thereby reducing the voltage difference between the gate of the second selection transistor of the first memory string and the corresponding second doped semiconductor layer. This results in a reduction of holes transported to the channel of the first memory string, which slows down the rate at which electrons in the storage layer of the memory cell of the first memory string are eliminated from time T4 to time T3, thus preventing the first memory string from being over-erased.

[0197] From the fourth time T4 to the fifth time T5, a seventh voltage is continuously applied to the second selection line coupled to the second selection transistor of the second memory string, so that the gate voltage of the second selection transistor of the second memory string is maintained at the seventh voltage. Under the action of the fifth voltage and the seventh voltage, holes generated in the second doped semiconductor layer coupled to the second memory string, or holes generated at the position between the second doped semiconductor layer and the second selection transistor, move into the channel of the second memory string to raise the potential of the channel. When the voltage difference between the channel and the gate of any memory cell in the second memory string is greater than the tunneling voltage of the memory cell, electrons in the memory layer of the memory cell of the memory string are eliminated. Starting from the fifth time point, the second selection line coupled to the second selection transistor of the second memory string is floated. During this period, the gate of the second selection transistor of the second memory string is in a floating state, so that the gate of the second selection transistor of the second memory string is coupled to the corresponding second doped semiconductor layer (i.e., the second doped semiconductor layer coupled to the substring where the second selection transistor is located) to form a capacitor. The voltage jump principle across the capacitor causes the gate voltage of the second selection transistor of the second memory string to change with the fifth voltage, thereby reducing the voltage difference between the gate of the second selection transistor of the second memory string and the corresponding second doped semiconductor layer. This results in a reduction of holes transported to the channel of the second memory string, which slows down the rate at which electrons in the storage layer of the storage cell of the second memory string are eliminated from the fifth time point T5 to the seventh time point T3, thereby preventing the second memory string from being over-erased.

[0198] Regarding the erase operation performed on multiple storage cells in the storage block, the erase operation ends at the seventh time. Assuming that at the sixth time after the seventh time, the voltages of all control lines (such as BL, SL, DSL, SSL, and BL) coupled to the peripheral circuit of the storage block have returned to their initial voltages, the single erase process of the storage block ends. At the sixth time, an erase verification operation is performed on each storage string in the storage block to verify whether there are any unerased storage strings. For example, if it is verified that any storage string contains unerased storage cells, then the storage string is an incomplete erased storage string, and the verification fails; this storage string becomes the second storage string. If it is verified that all storage cells in any storage string have been successfully erased (i.e., there are no unerased storage cells), then the storage string is a completed erased storage string, and the verification passes; this storage string becomes the first storage string.

[0199] If a second storage string that fails the erase verification exists in the storage block, it means that the second storage string was not erased after the erase process of the storage block described above. Then, the erase operation on multiple storage strings in the storage block is performed again. The steps are: at the first moment, float the first selection line coupled to the first selection transistor of the first storage string; at the second moment, float the first selection line coupled to the first selection transistor of the second storage string.

[0200] For example, Figure 11 According to a flowchart of a block erasure operation method for a memory according to an exemplary embodiment, an erasure pulse (such as a first voltage) is applied to a memory block in the memory to perform an erasure operation on the memory block. An erasure verification operation is performed on each memory string in the memory block to determine whether all memory strings in the memory block have passed the erasure verification. If so, it means that all memory strings in the memory block have been erased, and no further erasure verification operation is performed on the memory block. If not, it is necessary to further determine whether all memory strings in the memory block have failed the erasure verification. If all memory strings in the memory block have failed the erasure verification, an erasure pulse is applied to the memory block again to perform the next erasure operation on the memory block. During this period, the first selection transistors of each memory string in the memory block are simultaneously floated. If not all memory strings in a memory block fail the erase verification, then some memory strings in the block fail the erase verification while others pass. An erase pulse is then applied to the memory block again to perform the next erase operation. During this process, the duration of the voltage applied to the first selection transistor of the memory strings that passed the erase verification is reduced, thus enabling the first selection transistors of the passed-verification memory strings to be floated in advance, and then the first selection transistors of the memory strings that failed the erase verification to be floated. The memory strings that passed the erase verification are the first memory strings, and the memory strings that failed the erase verification are the second memory strings. After performing multiple erase operations on the memory block, all memory strings in the block will pass the erase verification.

[0201] It should be understood that if some memory strings in a memory block fail the erase verification while others pass, during the process of applying an erase pulse to the memory block again, the duration of applying voltage to the first selection transistor of the memory strings that passed the erase verification can be reduced by one time, without needing to be reduced multiple times. For example, the duration between the third time and the second time can be reduced to the duration between the third time and the first time. In the case where the first memory string and the second memory string are stored in the memory block at the same time, the first selection transistor of the first memory string can be floated at the first time during each erase operation of the memory block.

[0202] The memory 100 described above can be used in a storage system to provide data storage services to the host in the storage system. The architecture of the storage system will be described below.

[0203] Figure 12 This is a schematic diagram illustrating a storage system according to an exemplary embodiment, such as... Figure 12As shown, the storage system 400 can be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein.

[0204] like Figure 12 As shown, the storage system 400 includes a host 401 and a storage subsystem 402. The host 401 can be a processor (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). The host 401 can be configured to send data to the memory 100 in the storage subsystem 402. Alternatively, the host 401 can be configured to receive data from the memory 100.

[0205] The storage subsystem 402 includes one or more memories 100 and a controller 200. The memories 100 are coupled to the controller 200. The memories 100 can be any memory disclosed in this application. Optionally, the memories 100 are NAND flash memory devices. NAND flash memory devices, such as 3D NAND flash memory devices, are also possible.

[0206] According to some implementations, controller 200 is also coupled to host 401. Controller 200 can manage data stored in memory 100 and communicate with host 401.

[0207] In one possible implementation, the controller 200 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc.

[0208] In one possible implementation, the controller 200 is designed to operate in a high duty cycle environment, in a solid-state drive (SSD) or an embedded multimedia card (eMMC), which serves as data storage for mobile devices such as smartphones, tablets, laptops, etc., as well as enterprise storage arrays.

[0209] Controller 200 can be configured to control operations of memory 100, such as read, erase, and program operations. Controller 200 can also be configured to manage various functions relating to data stored or to be stored in memory 100, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In one possible implementation, controller 200 is also configured to handle error correction codes (ECC) relating to data read from or written to memory 100.

[0210] Controller 200 may also perform any other suitable functions, such as formatting memory 100. Controller 200 may communicate with external devices (e.g., host 401) according to a specific communication protocol. For example, controller 200 may communicate with external devices through at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Firewire, etc.

[0211] The controller 200 and one or more memories 100 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the storage system 400 can be implemented and packaged into different types of end electronic products.

[0212] Figure 13 This is a schematic diagram of a memory card according to an exemplary embodiment, such as... Figure 13 As shown, controller 200 and a single memory 100 can be integrated into memory card 500. Memory card 500 may include PC cards (PCMCIA, Personal Computer Memory Card International Association), CF cards, Smart Media (SM) cards, memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), UFS, etc. Memory card 500 may also include a connector for connecting memory card 500 to a host computer (e.g., Figure 12 The memory card connector 501 is coupled to the host 401.

[0213] Figure 14 This is a schematic diagram illustrating a solid-state drive according to an exemplary embodiment, such as... Figure 14As shown, the controller 200 and multiple memories 100 can be integrated into a solid-state drive (SSD) 600. The solid-state drive 600 may also include a connection between the solid-state drive 600 and a host (e.g., ...). Figure 12 The solid-state drive connector 601 is coupled to the host 401. In one possible implementation, the storage capacity and / or operating speed of the solid-state drive 600 is greater than the storage capacity and / or operating speed of the memory card 500.

[0214] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A memory, characterized in that, The memory includes a memory array and peripheral circuitry. The memory array includes a memory block, a first doped semiconductor layer, a first select line, and multiple word lines. The memory block includes multiple memory strings, each memory string including a first select transistor and multiple memory cells. The first doped semiconductor layer is coupled to one end of each memory string near the first select transistor. The first select line is coupled to the first select transistor. The multiple word lines are respectively coupled to the multiple memory cells of each memory string. The peripheral circuitry is coupled to the first select line and the multiple word lines. The peripheral circuit is configured to perform an erase operation on the plurality of memory strings in the memory block. To perform the erase operation, the peripheral circuit is configured as follows: At a third time point prior to the first time point, a first voltage is applied to the first doped semiconductor layer coupled to each memory string in the memory block, and a third voltage is applied to the word line coupled to each memory cell of each memory string in the memory block, wherein the third voltage is less than the first voltage. From the third time point to the second time point after the first time point, a second voltage is applied to the first selection line coupled to the first selection transistor of the second memory string, wherein the second memory string is the memory string among the plurality of memory strings that has not been erased, and the second voltage is less than the first voltage; From the third time point to the first time point, the second voltage is applied to the first selection line coupled to the first selection transistor of the first memory string, wherein the first memory string is the memory string that has been erased among the plurality of memory strings; At the first moment, the first selection line coupled to the first selection tube of the first memory string is floating; At a second time after the first time, the first selection line coupled to the first selection tube of the second memory string is floated.

2. The memory according to claim 1, characterized in that, Each memory string in the memory block further includes a second select transistor, the memory array further includes a second doped semiconductor layer and a second select line, the second doped semiconductor layer is coupled to one end of each memory string near the second select transistor, the second select line is coupled to the second select transistor, and the peripheral circuit is also coupled to the second select line; The peripheral circuit is also configured to: At the third moment, a fourth voltage is applied to the second doped semiconductor layer coupled to each memory string in the memory block; At the third moment, the second selection line coupled to the second selection tube of each memory string in the memory block is floated.

3. The memory according to claim 2, characterized in that, The first doped semiconductor layer is coupled to the bit line, and the first doped semiconductor layer is an N-type doped semiconductor layer.

4. The memory according to claim 2, characterized in that, The first doped semiconductor layer is coupled to the source line, and the first doped semiconductor layer is an N-type doped semiconductor layer or a P-type doped semiconductor layer.

5. The memory according to claim 1, characterized in that, Each memory string in the memory block further includes a second select transistor, the memory array further includes a second doped semiconductor layer and a second select line, the second doped semiconductor layer is coupled to one end of each memory string near the second select transistor, the second select line is coupled to the second select transistor, and the peripheral circuit is also coupled to the second select line; The peripheral circuit is also configured to: At the third moment, a fifth voltage is applied to the second doped semiconductor layer coupled to each memory string in the memory block.

6. The memory according to claim 5, characterized in that, The peripheral circuit is also configured to: From the third time point to the second time point, a sixth voltage is applied to the second selection line coupled to the second selection transistor of each memory string in the memory block, the sixth voltage being less than the fifth voltage; At the second moment, the second selection line coupled to the second selection tube of each memory string in the memory block is floated.

7. The memory according to claim 5, characterized in that, The peripheral circuit is also configured to: From the third time point to the fourth time point, a seventh voltage is applied to the second selection line coupled to the second selection transistor of the first memory string. At the fourth time point, the second selection line coupled to the second selection transistor of the first memory string is floated. The seventh voltage is less than the fifth voltage. From the third time point to the fifth time point after the fourth time point, the seventh voltage is applied to the second selection line coupled to the second selection transistor of the second memory string, and at the fifth time point, the second selection line coupled to the second selection transistor of the second memory string is floated.

8. The memory according to any one of claims 5-7, characterized in that, The first doped semiconductor layer is coupled to the bit line, and the first doped semiconductor layer is an N-type doped semiconductor layer; The second doped semiconductor layer is coupled to the source line, and the second doped semiconductor layer is an N-type doped semiconductor layer or a P-type doped semiconductor layer.

9. The memory according to any one of claims 5-7, characterized in that, The first doped semiconductor layer is coupled to the source line, and the first doped semiconductor layer is an N-type doped semiconductor layer or a P-type doped semiconductor layer. The second doped semiconductor layer is coupled to the bit line, and the second doped semiconductor layer is an N-type doped semiconductor layer.

10. The memory according to any one of claims 1-7, characterized in that, The storage string includes multiple substrings, each substring includes a first selection transistor and multiple storage units. Each first selection transistor in the same storage string is coupled to the same first selection line, and the first selection transistors in different storage strings are coupled to different first selection lines.

11. The memory according to any one of claims 1-7, characterized in that, The peripheral circuit is also configured to: At the sixth time after the second time, an erase verification operation is performed on each storage string in the storage block; If a second storage string that fails the erase verification exists in the storage block, the step of erasing the plurality of storage strings in the storage block is performed.

12. A storage system, characterized in that, The storage system includes a memory configured to store data and a controller coupled to the memory and configured to control the memory. The memory includes a storage array and peripheral circuitry. The storage array includes a storage block, a first doped semiconductor layer, a first select line, and multiple word lines. The storage block includes multiple storage strings, each storage string including a first select transistor and multiple storage cells. The first doped semiconductor layer is coupled to one end of each storage string near the first select transistor. The first select line is coupled to the first select transistor. The multiple word lines are respectively coupled to the multiple storage cells of each storage string. The peripheral circuitry is coupled to the first select line and the multiple word lines. The peripheral circuitry is configured to perform an erase operation on the multiple storage strings in the storage block. To perform the erase operation, the peripheral circuitry is configured to: At a third time point prior to the first time point, a first voltage is applied to the first doped semiconductor layer coupled to each memory string in the memory block, and a third voltage is applied to the word line coupled to each memory cell of each memory string in the memory block, wherein the third voltage is less than the first voltage. From the third time point to the second time point after the first time point, a second voltage is applied to the first selection line coupled to the first selection transistor of the second memory string, wherein the second memory string is the memory string among the plurality of memory strings that has not been erased, and the second voltage is less than the first voltage; From the third time point to the first time point, the second voltage is applied to the first selection line coupled to the first selection transistor of the first memory string, wherein the first memory string is the memory string that has been erased among the plurality of memory strings; At the first moment, the first selection line coupled to the first selection tube of the first memory string is floating; At a second time after the first time, the first selection line coupled to the first selection tube of the second memory string is floated.

13. The storage system according to claim 12, characterized in that, The storage system also includes a host computer coupled to the controller, the host computer being configured to send data to or receive data from the memory via the controller.

14. A method for operating a memory, characterized in that, The memory includes a memory array, which includes a memory block, a first doped semiconductor layer, a first select line, and a plurality of word lines. The memory block includes a plurality of memory strings, each memory string including a first select transistor and a plurality of memory cells. The first doped semiconductor layer is coupled to one end of each memory string near the first select transistor. The first select line is coupled to the first select transistor. The plurality of word lines are respectively coupled to the plurality of memory cells of each memory string. The method includes performing an erase operation on the plurality of storage strings in the storage block, the erase operation including: At a third time point prior to the first time point, a first voltage is applied to the first doped semiconductor layer coupled to each memory string in the memory block, and a third voltage is applied to the word line coupled to each memory cell of each memory string in the memory block, wherein the third voltage is less than the first voltage. From the third time point to the second time point after the first time point, a second voltage is applied to the first selection line coupled to the first selection transistor of the second memory string, wherein the second memory string is the memory string among the plurality of memory strings that has not been erased, and the second voltage is less than the first voltage; From the third time point to the first time point, the second voltage is applied to the first selection line coupled to the first selection transistor of the first memory string, wherein the first memory string is the memory string that has been erased among the plurality of memory strings; At the first moment, the first selection line coupled to the first selection tube of the first memory string is floating; At a second time after the first time, the first selection line coupled to the first selection tube of the second memory string is floated.

15. The method according to claim 14, characterized in that, Each memory string in the memory block further includes a second select transistor, and the memory array further includes a second doped semiconductor layer and a second select line, the second doped semiconductor layer being coupled to one end of each memory string near the second select transistor, and the second select line being coupled to the second select transistor; The erasure operation also includes: At the third moment, a fourth voltage is applied to the second doped semiconductor layer coupled to each memory string in the memory block; At the third moment, the second selection line coupled to the second selection tube of each memory string in the memory block is floated.

16. The method according to claim 15, characterized in that, The first doped semiconductor layer is coupled to the bit line, and the first doped semiconductor layer is an N-type doped semiconductor layer.

17. The method according to claim 15, characterized in that, The first doped semiconductor layer is coupled to the source line, and the first doped semiconductor layer is an N-type doped semiconductor layer or a P-type doped semiconductor layer.

18. The method according to claim 14, characterized in that, Each memory string in the memory block further includes a second select transistor, and the memory array further includes a second doped semiconductor layer and a second select line, the second doped semiconductor layer being coupled to one end of each memory string near the second select transistor, and the second select line being coupled to the second select transistor; The erasure operation also includes: At the third moment, a fifth voltage is applied to the second doped semiconductor layer coupled to each memory string in the memory block.

19. The method according to claim 18, characterized in that, The erasure operation also includes: From the third time point to the second time point, a sixth voltage is applied to the second selection line coupled to the second selection transistor of each memory string in the memory block, the sixth voltage being less than the fifth voltage; At the second moment, the second selection line coupled to the second selection tube of each memory string in the memory block is floated.

20. The method according to claim 18, characterized in that, The erasure operation also includes: From the third time point to the fourth time point, a seventh voltage is applied to the second selection line coupled to the second selection transistor of the first memory string. At the fourth time point, the second selection line coupled to the second selection transistor of the first memory string is floated. The seventh voltage is less than the fifth voltage. From the third time point to the fifth time point after the fourth time point, the seventh voltage is applied to the second selection line coupled to the second selection transistor of the second memory string, and at the fifth time point, the second selection line coupled to the second selection transistor of the second memory string is floated.

21. The method according to any one of claims 18-20, characterized in that, The first doped semiconductor layer is coupled to the bit line, and the first doped semiconductor layer is an N-type doped semiconductor layer; The second doped semiconductor layer is coupled to the source line, and the second doped semiconductor layer is an N-type doped semiconductor layer or a P-type doped semiconductor layer.

22. The method according to any one of claims 18-20, characterized in that, The first doped semiconductor layer is coupled to the source line, and the first doped semiconductor layer is an N-type doped semiconductor layer or a P-type doped semiconductor layer. The second doped semiconductor layer is coupled to the bit line, and the second doped semiconductor layer is an N-type doped semiconductor layer.

23. The method according to any one of claims 14-20, characterized in that, The storage string includes multiple substrings, each substring includes a first selection transistor and multiple storage units. Each first selection transistor in the same storage string is coupled to the same first selection line, and the first selection transistors in different storage strings are coupled to different first selection lines.

24. The method according to any one of claims 14-20, characterized in that, Following the first select line coupled to the first select transistor of the floating second memory string, the method further includes: At the sixth time after the second time, an erase verification operation is performed on each storage string in the storage block; If a second storage string that fails the erase verification exists in the storage block, the step of erasing the plurality of storage strings in the storage block is performed.

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