Operation method of memory, memory and memory system

Abstract

The invention provides an operation method of a memory, the memory and a memory system, relates to the technical field of memories, and aims to solve the problem of how to shorten programming time. The method comprises the following steps: executing a first programming verification operation on a plurality of memory cells of the memory for multiple times to obtain a plurality of memory cells from a first programming state to an ith programming state, i being a positive integer, judging whether to execute a first programming verification operation of a next programming state or not based on whether a first verification result reaches a first preset value or not in the first programming verification operation, the first verification result comprises the number of the storage units in the current programming state. And executing a second programming verification operation on the storage unit in the nth programming state to obtain a second verification result of the storage unit in the nth programming state, n being a positive integer. If the second verification result of the storage unit in the nth programming state is larger than or equal to a second preset value, second programming verification operation is executed on the storage unit in the (n + 1) th programming state, and the second preset value is different from the first preset value.

Description

Technical Field

[0001] The present disclosure relates to the field of memory technology, and in particular to a memory operation method, a memory, and a memory system. Background Art

[0002] NAND flash memory is a non-volatile storage technology that can store data even after power failure. It has the advantages of low storage cost and high storage capacity. Existing NAND flash memory chips are usually programmed using the incremental step pulse programming (ISPP) method, which uses a gradually increasing programming voltage to program the storage cell. Each programming pulse is followed by a corresponding verification pulse to check whether the storage cell threshold voltage reaches the target value.

[0003] As the number of bits stored in a memory cell increases, the time required for programming also increases. Among them, the number of times programming pulses are applied and the number of times programming verification operations are performed are important factors that determine the programming time. Therefore, how to shorten the programming time while ensuring programming quality has become an urgent problem to be solved. Summary of the invention

[0004] The embodiments of the present disclosure provide a memory operation method, a memory, and a memory system, aiming to solve the problem of how to shorten the programming time.

[0005] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions.

[0006] In a first aspect, a method for operating a memory is provided, the method comprising: performing a first programming verification operation multiple times on a plurality of memory cells of the memory to obtain a plurality of memory cells in a 1st programming state to an i-th programming state, i being a positive integer, judging whether to perform a first programming verification operation of a next programming state based on whether a first verification result reaches a first preset value in the first programming verification operation, the first verification result including the number of memory cells in the current programming state. Performing a second programming verification operation on a memory cell in an n-th programming state to obtain a second verification result of the memory cell in the n-th programming state, n being a positive integer. If the second verification result of the memory cell in the n-th programming state is greater than or equal to a second preset value, performing a second programming verification operation on a memory cell in an n+1-th programming state, the second preset value being different from the first preset value.

[0007] The operating method of the memory provided by the above-mentioned embodiment of the present disclosure adopts a two-step programming method, including rough programming and fine programming. In the rough programming, whether to perform the first programming verification operation of the next programming state is determined based on the first preset value, and whether to perform the second programming verification operation of the next programming state is determined based on the second preset value in the fine programming. Compared with the rough programming and fine programming using the same preset value, the operating method of the memory provided by the embodiment of the present application uses different preset values ​​in the rough programming and fine programming, which can reduce the impact of the rough programming on the fine programming, thereby reducing the number of verifications of the fine programming and reducing the programming time.

[0008] In some embodiments, before performing a second programming verification operation on the storage cell in the nth programming state and obtaining a second verification result of the storage cell in the nth programming state, the method further includes: obtaining a pre-verification result of the storage cell in the nth programming state based on a verification voltage of the second programming verification operation.

[0009] In these embodiments, the pre-verification result is the number of storage cells that have reached the nth programming state after the coarse programming is completed. The pre-verification result can be understood as the impact of the coarse programming on the fine programming. Based on the pre-verification result, the value of the second preset value in the fine programming can be adjusted, thereby reducing the verification operations of the fine programming and reducing the programming time.

[0010] In some embodiments, the second verification result includes the number of memory cells in the nth programming state, and the second preset value is greater than the first preset value.

[0011] In these embodiments, if the second verification result includes the number of storage cells in the nth programming state, it is equivalent to that the second verification result includes the impact of coarse programming on fine programming. At this time, the second preset value is greater than the first preset value, which can reduce the impact of coarse programming on fine programming, thereby reducing the verification operations of fine programming and reducing programming time.

[0012] In some embodiments, the second verification result includes the number of memory cells in the nth programming state except the number of memory cells corresponding to the pre-verification result, and the second preset value is less than the first preset value.

[0013] In these embodiments, if the second verification result does not include the number of storage cells in the nth programming state, it is equivalent to that the influence of coarse programming on fine programming has been proposed in the second verification result. At this time, the second preset value is less than the first preset value, which can reduce the influence of coarse programming on fine programming, thereby reducing the verification operations of fine programming and reducing programming time.

[0014] In some embodiments, performing a first programming verification operation multiple times on a plurality of memory cells of a memory to obtain a plurality of memory cells in the 1st programming state to the i-th programming state includes: performing a first programming verification operation on a memory cell in the m-th programming state to obtain a first verification result of the memory cell in the m-th programming state, where m is a positive integer. If the first verification result of the memory cell in the m-th programming state is greater than or equal to a first preset value, performing a first programming verification operation on a memory cell in the m+1-th programming state. If the first verification result of the memory cell in the m-th programming state is less than the first preset value, performing a first programming verification operation on the memory cell in the m-th programming state. If the first verification result obtained by performing a first programming verification operation on a memory cell in the highest programming state is greater than or equal to the first preset value, a plurality of memory cells in the 1st programming state to the i-th programming state are obtained.

[0015] In these embodiments, based on the comparison result of the first verification result of the storage unit in the mth programming state with the first preset value, it is determined whether to continue the first programming verification operation of the current programming state or to perform the first programming verification operation of the next programming state. The starting time of each programming state to be verified can be dynamically determined, the accuracy of the determined starting time of each programming state to be verified can be improved, and the number of verifications can be reduced to shorten the programming time.

[0016] In some embodiments, a step size of the plurality of programming pulses of the first program verification operation is greater than a step size of the plurality of programming pulses of the second program verification operation.

[0017] In these embodiments, the multiple first programming verification operations can be understood as rough programming, and the multiple second programming verification operations can be understood as fine programming. The memory operation method provided in the embodiment of the present application first performs rough programming to quickly reach different programming states and improve the programming speed, and then performs fine programming to obtain better programming quality and shorten the programming time.

[0018] In some embodiments, if the second verification result of the memory cell in the nth programming state is less than a second preset value, a second program verification operation is performed on the memory cell in the nth programming state.

[0019] In these embodiments, if the second verification result is less than the second preset value, it indicates that only a few memory cells have reached the nth programming state, and it can be predicted that after applying the next programming pulse, almost no memory cells whose target programming state is the n+1th programming state can reach the n+1th programming state, and at this time, there is no need to perform the second programming verification operation on the memory cells in the n+1th programming state. In this way, the number of second programming verification operations can be reduced, which is conducive to shortening the programming time, reducing the number of second verification results to be processed, and improving programming efficiency.

[0020] In some embodiments, the method further includes: obtaining a first number of the first program verification operation, and determining a first preset value according to the first number; obtaining a second number of the second program verification operation, and determining a second preset value according to the second number.

[0021] In these embodiments, by obtaining the number of programming verification operations and determining a preset value based on the number, the programming characteristics that change with the number of cycles can be tracked during the programming verification operation, and the range of the preset value can be flexibly adjusted to reduce the slow programming speed caused by improper determination of the preset value, which is beneficial to improving the programming speed and ensuring the programming quality.

[0022] In a second aspect, a memory is provided, the memory comprising: a memory cell array, the memory cell array comprising a plurality of memory cells. A peripheral circuit, the peripheral circuit is coupled to the memory cell array, and the peripheral circuit is configured to: perform a plurality of first programming verification operations on a plurality of memory cells of the memory to obtain a plurality of memory cells in a 1st programming state to an i-th programming state, i being a positive integer, and in the first programming verification operation, determine whether to perform a first programming verification operation for a next programming state based on whether a first verification result reaches a first preset value, the first verification result including the number of memory cells in a current programming state. Perform a second programming verification operation on a memory cell in an n-th programming state to obtain a second verification result for a memory cell in an n-th programming state, n being a positive integer. If the second verification result for a memory cell in an n-th programming state is greater than or equal to a second preset value, perform a second programming verification operation on a memory cell in an n+1-th programming state, the second preset value being different from the first preset value.

[0023] The beneficial effects of the second aspect can refer to the description of the first aspect.

[0024] In some embodiments, the peripheral circuit is further configured to: obtain a pre-verification result of the memory cell in the nth program state based on a verification voltage of the second program verification operation.

[0025] In some embodiments, the second verification result includes the number of memory cells in the nth programming state, and the second preset value is greater than the first preset value.

[0026] In some embodiments, the second verification result includes the number of memory cells in the nth programming state except the number of memory cells corresponding to the pre-verification result, and the second preset value is less than the first preset value.

[0027] In some embodiments, the peripheral circuit is further configured to: perform a first programming verification operation on the storage cell in the mth programming state to obtain a first verification result of the storage cell in the mth programming state, where m is a positive integer. If the first verification result of the storage cell in the mth programming state is greater than or equal to the first preset value, perform a first programming verification operation on the storage cell in the m+1th programming state. If the first verification result of the storage cell in the mth programming state is less than the first preset value, perform a first programming verification operation on the storage cell in the mth programming state. If the first verification result obtained by performing the first programming verification operation on the storage cell in the highest programming state is greater than or equal to the first preset value, multiple storage cells from the 1st programming state to the i-th programming state are obtained.

[0028] In some embodiments, a step size of the plurality of programming pulses of the first program verification operation is greater than a step size of the plurality of programming pulses of the second program verification operation.

[0029] In some embodiments, the peripheral circuit is further configured to: if the second verification result of the memory cell in the nth programming state is less than a second preset value, perform a second program verification operation on the memory cell in the nth programming state.

[0030] In some embodiments, the peripheral circuit is further configured to: obtain a first number of first program verification operations, and determine a first preset value according to the first number; obtain a second number of second program verification operations, and determine a second preset value according to the second number.

[0031] According to a third aspect, a memory system is provided. The memory system comprises: one or more memories according to the second aspect, and a memory controller coupled to the memories and configured to control the memories.

[0032] It can be understood that the beneficial effects that can be achieved by the memory operation method, memory and memory system provided by the above embodiments of the present disclosure can refer to the beneficial effects of the semiconductor structure described above, which will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.

[0034] Figure 1 A threshold voltage distribution diagram of a current programming state provided in an embodiment of the present application;

[0035] Figure 2 A schematic diagram of the structure of an exemplary system S1 having a storage system 10 provided in an embodiment of the present application;

[0036] Figure 3 A schematic diagram of a memory card provided in an embodiment of the present application;

[0037] Figure 4 A schematic diagram of another memory card provided in an embodiment of the present application;

[0038] Figure 5 A schematic diagram of the structure of a memory provided in an embodiment of the present application;

[0039] Figure 6 A flowchart of a method for operating a memory provided by an embodiment of the present application;

[0040] Figure 7 A threshold voltage distribution diagram of an n-th programming state provided in an embodiment of the present application;

[0041] Figure 8 A threshold voltage distribution diagram of another n-th programming state provided in an embodiment of the present application;

[0042] Fig. 9 A flowchart for roughly programming a memory provided in an embodiment of the present application. DETAILED DESCRIPTION

[0043] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0044] In the description of the present disclosure, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.

[0045] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0046] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "multiple" means two or more. "At least one of A, B and C" has the same meaning as "at least one of A, B or C", and both include the following combinations of A, B and C: only A, only B, only C, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B and C. "A and / or B" includes the following three combinations: only A, only B, and a combination of A and B.

[0047] The use of "adapted to" or "configured to" herein is meant to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0048] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0049] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of variation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0050] In the context of the present disclosure, the meanings of “on,” “over,” and “over” should be interpreted in the broadest manner, so that “on” means not only “directly on something,” but also includes the meaning of “on something” with intervening features or layers therebetween, and “over” or “above” means not only “above” or “over” something, but also includes the meaning of “above” or “over” something without intervening features or layers therebetween (i.e., directly on something).

[0051] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0052] As used herein, the term "substrate" refers to a material on which subsequent material layers may be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0053] The term "three-dimensional memory" refers to a semiconductor device formed by a memory cell transistor string (referred to herein as a "memory cell string", such as a NAND memory cell string) arranged in an array on a main surface of a substrate or source layer and extending in a direction perpendicular to the substrate or source layer. As used herein, the term "vertical / vertically" means nominally perpendicular to the main surface (i.e., lateral surface) of the substrate or source layer.

[0054] In the development of NAND memory, the storage cells of early NAND memory particles are mostly single-level cells (SLC), that is, one storage cell stores 1 bit of data. At this time, each storage cell has two states, specifically 0 and 1.

[0055] With the development of NAND memory, the storage unit of NAND memory particles has gradually evolved from a single-level cell to a multi-level cell (MLC), that is, one storage unit stores 2 bits of data. Then the triple level cell (TLC) was introduced, that is, one storage unit stores 3 bits of data. Even the quad level cell (QLC) was introduced, that is, one storage unit stores 4 bits of data. Correspondingly, the state of the storage unit of the NAND memory particle has also changed from 2 to 4, 8 or even 16.

[0056] NAND memory cells can have 2 n states, n is the number of bits that a memory cell can store. For example, an SLC memory cell can have 2 states, an MLC memory cell can have 4 states, a TLC memory cell can have 8 states, and a QLC memory cell can have 16 states. n The states can include an erase state and 2 n -1 programming state. NAND memory can program and / or read data page by page. During the programming operation, the NAND memory cell is programmed to have 2 n The programming operation of NAND memory is divided into three steps: pressure programming (i.e., applying programming pulses), program verification (PV), and scanning verification results.

[0057] For NAND memory, the programming time (t PROG ) is an important indicator to measure the performance of NAND memory. Therefore, how to improve the programming speed and shorten the programming time while ensuring the programming quality (for example, ensuring the read budget window) is an urgent problem to be solved. Among them, since the duration of the applied programming pulse cannot be changed, the number of applied programming pulses, the number of programming verifications, the time for each programming verification, and the time for scanning the verification results are all important factors that determine the programming time. Taking the QLC storage cell as an example, the time for programming verification of 15 states accounts for more than half of the programming time. Therefore, reducing the time for programming verification of each state is crucial to improving the programming time.

[0058] Therefore, a programming verification method is proposed, and each programming verification state includes a corresponding starting time. Taking a TLC memory cell as an example, the TLC memory cell has 1 erase state and 7 programming states, and its programming states are sequentially recorded as L1, L2, L3, L4, L5, L6 and L7 from the 1st state to the 7th state. As shown in Table 1, Table 1 is a table of programming verification operations and starting times for different programming states. Among them, PV1 represents a programming verification operation for the 1st state (L1), PV2 represents a programming verification operation for the 2nd state (L2), and so on.

[0059] Table 1

[0060] Program Verification (PV) Start time (start loop) PV1 1 PV2 3 PV3 4 PV4 5 PV5 7 PV6 9 PV7 11

[0061] The start time of the program verification operation can be defined by the number of programming pulses after which the program verification operation is started. For example, the start time of the program verification operation of the first state is 1, which means that the program verification of the first state starts after the first programming pulse is applied and before the second programming pulse is applied.

[0062] Compared with performing programming verification on each state after each application of a programming pulse, the above-mentioned programming verification method reduces the number of programming verifications to a certain extent, but there will be differences in programming characteristics when different units are programmed at the same time. For each state, setting the same starting time for all dies, blocks or word lines (WL) will still result in errors. In addition, this method of determining the time for starting verification of each state by the number of program pulse loop counts cannot adapt to the programming speed of storage cells in different program / erase cycles. Among them, (end of life, EOL) is faster than (begin of life, BOL). Therefore, in order to avoid over-programming, the time of programming verification will be set earlier to ensure normal programming of EOL.

[0063] In order to reduce programming time, a dynamic program verify start (DPVS) algorithm is proposed, in which the number of successful memory cells (pass cells) in the current state determines whether to start verification in the next programming state. By adaptively adjusting the programming speed of memory cells, the verification time overhead can be reduced.

[0064] Taking QLC NAND flash memory as an example, a 16-16 two-pass programming scheme is often used. The two-pass programming scheme can reduce the coupling effect of adjacent word lines (WL). Among them, the two-pass programming scheme includes coarse programming and fine programming. In addition, coarse programming is performed first in the programming operation, and then fine programming is performed. The DPVS algorithm is applied in both coarse programming and fine programming. Among them, the verification times of coarse programming are shown in Table 2, and the verification times of fine programming are shown in Table 3.

[0065] Table 2

[0066] frequency 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 p1 √ √ √ √ √ √ √ p2 √ √ √ √ √ √ √ √ p3 √ √ √ √ √ p4 √ √ √ √ √ p5 √ √ √ √ p6 √ √ √ √ p7 √ √ √ √ p8 √ √ √ √ p9 √ √ √ √ p10 √ √ √ √ p11 √ √ √ √ p12 √ √ √ √ √ p13 √ √ √ √ √ p14 √ √ √ √ √ p15 √ √ √ √ √

[0067] Table 3

[0068] frequency 1 2 3 4 5 6 7 8 9 9 10 12 13 14 15 16 17 18 19 20 21 22 23 24 25 p1 √ √ √ √ √ √ √ √ p2 √ √ √ √ √ √ √ √ √ √ √ p3 √ √ √ √ √ √ √ √ √ √ √ p4 √ √ √ √ √ √ √ √ √ p5 √ √ √ √ √ √ √ √ √ √ p6 √ √ √ √ √ √ √ √ √ √ √ p7 √ √ √ √ √ √ √ √ √ √ p8 √ √ √ √ √ √ √ √ √ √ √ p9 √ √ √ √ √ √ √ √ √ √ p10 √ √ √ √ √ √ √ √ √ p11 √ √ √ √ √ √ √ √ p12 √ √ √ p13 √ p14 p15

[0069] Table 3 (continued)

[0070]

[0071]

[0072] It can be seen from Table 2 and Table 3 that, when the DPVS algorithm is applied, the verification times of fine programming are greater than those of coarse programming. Moreover, after the coarse programming is completed and before the fine programming begins, the memory cells are roughly distributed in their respective threshold voltage ranges. If the number of successful memory cells in the current state is continued to be used to determine whether to start the verification of the next programming state, the fine programming will be affected by the coarse programming, increasing the verification times of the fine programming.

[0073] like Figure 1 As shown, Figure 1 A threshold voltage distribution diagram of a current programming state provided in an embodiment of the present application. Figure 1 , and the threshold voltage distribution diagram of the final coarse programming of the current state, and the threshold voltage distribution diagram of the final fine programming of the current state are shown. Figure 1 It can be seen that after the coarse programming of the current state is completed and before the fine programming of the current state is started, the number of memory cells obtained based on the verification voltage of the fine programming includes the number of memory cells that have reached the current state in the coarse programming. If it is determined whether to perform the verification operation of the next programming state in the fine programming based on the number of memory cells, the number of verifications in the fine programming will increase.

[0074] Therefore, an embodiment of the present application provides a method for operating a memory, in which a two-step programming method is adopted, including coarse programming and fine programming. In the coarse programming, a first preset value is used to determine whether to perform a first programming verification operation for the next programming state, and a second preset value is used to determine whether to perform a second programming verification operation for the next programming state. Compared with the use of the same preset value for coarse programming and fine programming, the method for operating a memory provided by the embodiment of the present application adopts different preset values ​​for coarse programming and fine programming, which can reduce the impact of coarse programming on fine programming, thereby reducing the number of verifications for fine programming and reducing programming time.

[0075] To facilitate understanding, the storage system to which the storage operation method provided in the embodiment of the present application is applied is first introduced below.

[0076] like Figure 2 As shown, Figure 2 A schematic diagram of the structure of an exemplary system S1 having a storage system 10 provided in an embodiment of the present disclosure. The system S1 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device therein. The storage system 10 (also referred to as a NAND memory system) includes a memory 101 and a controller 102. The storage system 10 may communicate with a host computer 20 through the controller 102, wherein the controller 102 may be coupled to the memory 101 via a memory channel 30. In some embodiments, the memory 101 in the present disclosure may be a three-dimensional non-volatile memory, such as a NAND flash memory, which may also be referred to as a flash memory or a NAND memory. Of course, the memory 101 in the present disclosure may also be other memories. The storage system 10 may have more than one memory 101, and each memory 101 may be managed by a controller 102.

[0077] In some embodiments, the host computer 20 may be a processor of an electronic device, such as a central processing unit (CPU), a system-on-chip (SoC), or an application processor (AP). The host computer 20 may send data to be stored in the storage system 10 or read data stored in the storage system 10.

[0078] Controller 102 may process input / output (I / O) requests received from host computer 20, ensure data integrity and efficient storage, and may also manage memory 101. Memory channel 30 may provide data and control communications between controller 102 and memory 101 via a data bus.

[0079] Continue to refer Figure 2 , the memory 101 may be a memory chip (package), a memory die, or any portion of a memory die, and may include one or more storage planes 1011, each of which may include multiple storage blocks 10111. The same and concurrent operations may occur at each storage plane 1011. The size of the storage block 10111 may be megabytes (MB), and the storage block 10111 is the smallest unit for performing an erase operation. Figure 1 The memory 101 illustrated in the example includes four storage planes 1011, and each storage plane 1011 includes six storage blocks 10111. Each storage block 10111 may include a plurality of storage cells, wherein each storage cell may be addressed by, for example, a bit line (BL) and a word line (WL). The bit lines and word lines may be arranged vertically (e.g., in rows and columns, respectively) to form an array of metal lines. The directions of the bit lines and word lines are Figure 1 In the present disclosure, one or more storage blocks 10111 may also be referred to as a "storage array" or "array". The storage array is a core area in a memory device that performs storage functions.

[0080] The memory 101 also includes a peripheral circuit area 1012, which is a peripheral area of ​​the storage plane 1011. The peripheral circuit area 1012 (also referred to as a peripheral circuit) contains many digital, analog and / or mixed signal circuits (e.g., page buffer / sense amplifier 10121, row decoder / word line driver 10122, column decoder / bit line driver 10123 and peripheral control circuit 10124) to support the functions of the memory 101. Among them, the peripheral control circuit 10124 may include registers, active and / or passive semiconductor devices, such as transistors, diodes, capacitors or resistors, etc. The peripheral control circuit 10124 of the peripheral circuit area 1012 can be configured to initiate a programming operation on a selected memory cell of a NAND memory string in the memory block 10111. In some embodiments, the peripheral control circuit 10124 receives a programming command from the controller 102 through an interface, and in response, sends control signals to the row decoder / word line driver 10122, column decoder / bit line driver 10123, and voltage generator ( Figure 2), to initiate a programming operation on the selected memory cell.

[0081] Notice, Figure 2 The layout of the electronic devices in the storage system 10 and the memory 101 in FIG. 1 is shown as an example. The storage system 10 and the memory 101 may have other layouts and may include additional devices. For example, the memory 101 may also include a high voltage charge pump, input-output circuits, etc. The storage system 10 may also include firmware and a data scrambler, etc. In some embodiments, the peripheral circuit area 1012 and the storage array may be independently formed on separate wafers and connected to each other by wafer bonding.

[0082] The controller 102 and one or more memories 101 may be integrated into various types of storage devices, for example, in the same package, such as a universal flash storage (UFS) package or an embedded multi-media card (eMMC) package. That is, the storage system 10 may be implemented and packaged into different types of terminal electronic products. Figure 3 In one example shown in FIG. 1 , the controller 102 and the single memory 101 may be integrated into a memory card 40. The memory card 40 may include a personal computer memory card international association (PCMCIA), a compact flash (CF) card, a smart media (SM) card, a memory stick, a multimedia card (MMC), a secure digital memory card (SD card), or a UFS, etc. The memory card 40 may also include a memory card connector 41 that couples the memory card 40 to the host computer 20. In the example shown in FIG. 1 , the memory card 40 may include a memory card connector 41 that couples the memory card 40 to the host computer 20. Figure 4 In another example shown in FIG. 1 , the controller 102 and the plurality of memories 101 may be integrated into a solid state drive (SSD) 50 . The SSD 50 may further include an SSD connector 51 that couples the SSD 50 with the host computer 20 .

[0083] like Figure 5 As shown, Figure 5A schematic diagram of the structure of a memory 101 provided in an embodiment of the present disclosure. The memory 101 includes one or more memory blocks 10111. Each memory block 10111 includes a memory string 60. Each memory string 60 includes a memory cell 601. The memory cells 601 sharing the same bit line form the memory string 60. The memory string 60 may also include at least one field effect transistor (e.g., a metal-oxide-semiconductor field-effect transistor (MOSFET)) at each end, which is controlled by a top select gate (TSG) 71 and a bottom select gate (BSG) 72, respectively. The drain terminal of the top select gate 71 may be connected to a bit line 80, and the source terminal of the bottom select gate 72 may be connected to an array common source (ACS) 82. The ACS 82 may be shared by the memory strings 60 in the entire memory block 10111, and is also referred to as a common source line (SL).

[0084] In some embodiments, the peripheral circuit area 1012 of the memory 101 may support the erase operation of the GIDL assisted technology. The memory block 10111 may be coupled to the row decoder / word line driver 10122 via the word line 81, the bottom select gate 72, and the top select gate 71. The memory block 10111 may be coupled to the page buffer / sense amplifier 10121 via the bit line 80. The row decoder / word line driver 10122 may select one of the memory blocks 10111 on the memory 101 in response to the X path control signal provided by the peripheral control circuit 10124. The row decoder / word line driver 10122 may pass the voltage provided from the voltage generator 90 to the word line 81 according to the X path control signal. During the read and program operations, the row decoder / word line driver 10122 may pass the read voltage Vread and the program voltage Vpgm to the selected word line 81 according to the X path control signal received from the peripheral control circuit 10124, and pass the pass voltage Vpass to the non-selected word line 81.

[0085] The column decoder / bit line driver 10123 can pass the inhibit voltage Vinhibit to the non-selected bit line according to the Y path control signal received from the peripheral control circuit 10124, and connect the selected bit line 80 to the ground. That is, the column decoder / bit line driver 10123 can be configured to select or deselect one or more storage strings 60 according to the Y path control signal from the peripheral control circuit 10124. The page buffer / sense amplifier 10121 can be configured to read data from the storage block 10111 and program (write) data to the storage block 10111 according to the Y path control signal from the peripheral control circuit 10124. For example, the page buffer / sense amplifier 10121 can store a page of data to be programmed into a memory page. In another example, the page buffer / sense amplifier 10121 can perform a verification operation to ensure that the data has been correctly programmed into each memory cell 601. In yet another example, during a read operation, the page buffer / sense amplifier 10121 can sense the current flowing through the bit line 80 reflecting the logic state (ie, data) of the memory cell 601 , as well as the amplification rate of amplifying a small signal to a measurable signal.

[0086] The input / output buffer 91 may transfer I / O data from / to the page buffer / sense amplifier 10121, and transfer an address ADDR signal or a command CMD signal to the peripheral control circuit 10124. In some embodiments, the input / output buffer 91 may be used as an interface between the controller 102 and the memory 101.

[0087] The peripheral control circuit 10124 may control the page buffer / sense amplifier 10121 and the row decoder / word line driver 10122 in response to the command CMD delivered by the input / output buffer 91. During a programming operation, the peripheral control circuit 10124 may control the row decoder / word line driver 10122 and the page buffer / sense amplifier 10121 to program the selected memory cell 601. During a read operation, the peripheral control circuit 10124 may control the row decoder / word line driver 10122 and the page buffer / sense amplifier 10121 to read the selected memory cell 601. The X-path control signal includes a row address X-ADDR, and the Y-path control signal includes a column address Y-ADDR, which may be used to locate the selected memory cell 601 in the memory block 10111. The row address X-ADDR may include a page index, a block index, and a plane index to identify a memory page, a memory block 10111, and a memory plane 1011, respectively. The column address Y-ADDR may identify a byte or word in the data of the memory page.

[0088] In some embodiments, the peripheral control circuit 10124 may include one or more control logic units. Each control logic unit described herein may include a software module and / or a firmware module running on a processor, such as a microcontroller unit (MCU) as part of the peripheral control circuit 10124, or a hardware module of a finite-state machine (FSM), such as an integrated circuit (IC), such as an application-specific IC (ASIC), a field-programmable gate array (FPGA), etc., or a combination of software modules, firmware modules, and hardware modules.

[0089] The voltage generator 90 may generate voltages provided to the word lines 81 and the bit lines 80 under the control of the peripheral control circuit 10124. The voltages generated by the voltage generator 90 include a read voltage Vread, a program voltage Vpgm, a pass voltage Vpass, an inhibit voltage Vinhibit, and the like.

[0090] In some embodiments, the memory 101 may be formed based on floating gate technology. In some embodiments, the memory 101 may be formed based on charge trapping technology. The memory 101 based on charge trapping may provide high storage density and high intrinsic reliability. The stored data or logic state (e.g., the threshold voltage Vth of the memory cell 601) depends on the amount of charge trapped in the storage layer. In some embodiments, the memory 101 may be a three-dimensional (3D) memory device in which the memory cells 601 may be stacked vertically on top of each other.

[0091] In some embodiments, when performing an erase operation, by implementing a negative voltage difference between the gate and source terminals (e.g., ACS82) of 601, all trapped electron charges in the storage layer of the memory cell 601 can be removed, and all memory cells 601 in the same memory block 10111 can be reset to the erase state ER as logic "1". For example, the voltage difference can be induced by setting the control gate in the memory cell 601 to ground and applying a positive voltage to the source line 82. In this example, a voltage pulse can be applied to the memory cell 601 in the erase operation.

[0092] Applied to the memory described above, the present application embodiment provides a memory operation method, such as Figure 6 As shown, Figure 6 A flowchart of a memory operation method provided in an embodiment of the present application. The memory operation method includes the following steps.

[0093] S601. The memory performs multiple first programming verification operations on multiple storage cells of the memory to obtain multiple storage cells in the 1st programming state to the i-th programming state, where i is a positive integer. In the first programming verification operation, based on whether the first verification result reaches a first preset value, it is determined whether to perform the first programming verification operation for the next programming state, and the first verification result includes the number of storage cells in the current programming state.

[0094] Exemplarily, the memory may include a memory array composed of a plurality of memory cells, and the memory cells may include single-level cells, multi-level cells, three-level cells, four-level cells, or cells with a higher number of levels.

[0095] The storage operation method provided in the embodiment of the present application adopts a two-step programming method. Taking QLC NAND as an example, the number of programming states of the memory can be 15, that is, i=15. That is, in the rough programming, multiple first programming verification operations are performed on multiple storage cells of the memory to obtain multiple storage cells in the first programming state to the fifteenth programming state. Among them, the storage cells in the first programming state to the fifteenth programming state are storage cells with a wider distribution.

[0096] Among them, the first verification result includes the number of storage cells in the current programming state. In addition, the first verification result can also include first type indication information indicating whether each verified storage cell has passed programming, and second type indication information indicating whether each verified storage cell has failed programming.

[0097] The step length of the multiple programming pulses of the first programming verification operation is greater than the step length of the multiple programming pulses of the second programming verification operation. Therefore, the first programming verification operation can be understood as rough programming, and the second programming verification operation can be understood as fine programming. Both rough programming and fine programming can adopt incremental step pulse programming (ISPP), and the step length of rough programming is greater than the step length of fine programming. The memory is first rough programmed to quickly reach different programming states and improve the programming speed, and then fine programming is performed to obtain better programming quality and shorten the programming time.

[0098] The first programming verification operation may include a first programming operation and a first verification operation. The first programming operation may be understood as applying a first programming pulse to the memory cell. The first verification operation may be understood as applying a first verification voltage to the memory cell. The number of memory cells reaching the current programming state may be obtained based on the first verification voltage of the current programming state.

[0099] S602: The memory performs a second program verification operation on the memory cell in the nth programming state to obtain a second verification result of the memory cell in the nth programming state, where n is a positive integer. Specifically, n should be a positive integer less than i.

[0100] Exemplarily, the second programming verification operation may include a second programming operation and a second verification operation. The second programming operation may be understood as applying a second programming pulse to the memory cell. The second verification operation may be understood as applying a second verification voltage to the memory cell. The number of memory cells reaching the current programming state may be obtained based on the second verification voltage of the current programming state.

[0101] Specifically, the memory applies a second programming pulse to the memory cell in the nth programming state, and obtains a second verification result of the memory cell that reaches the nth programming state based on the second verification voltage of the nth programming state. The second verification result is the number of successful bits programmed to the nth programming state. In addition, the second verification result may also include first-type indication information indicating whether each memory cell being verified has passed programming, and second-type indication information indicating whether each memory cell being verified has failed programming.

[0102] S603: If the second verification result of the memory cell in the nth programming state is greater than or equal to the second preset value, the memory performs a second program verification operation on the memory cell in the (n+1)th programming state, and the second preset value is different from the first preset value.

[0103] Exemplarily, when the second verification result is greater than or equal to the second preset value, it indicates that more memory cells have reached the nth programming state, and it can be predicted that after applying the next programming pulse, there will be memory cells whose target programming state is the n+1th programming state that can reach the n+1th programming state. Therefore, after applying the next programming pulse, it is necessary to start the second programming verification operation for the n+1th programming state. In this way, the occurrence of over-programming can be reduced and the programming quality can be improved.

[0104] For example, compared with using the same preset value for coarse programming and fine programming, the first preset value and the second preset value in the memory operation method provided in the embodiment of the present application are different. Therefore, in fine programming, the influence of the number of successful storage cells that already exist after the coarse programming is completed can be eliminated, thereby reducing the number of verification times for fine programming.

[0105] Optionally, the memory operation method further includes: if a second verification result of the memory cell in the nth programming state is less than a second preset value, the memory performs a second program verification operation on the memory cell in the nth programming state.

[0106] Exemplarily, when the second verification result is less than the second preset value, it indicates that no memory cell or only a small number of memory cells have reached the nth programming state. Then, it can be predicted that after applying the next programming pulse, almost no memory cell whose target programming state is the n+1th programming state can reach the n+1th programming state, that is, the n+1th programming state will not be programmed successfully. Therefore, after applying the next encoding pulse, there is no need to perform the second programming verification operation on the n+1th programming state. In this way, the number of programming states that need to be verified in the next second programming verification operation can be reduced, which is conducive to shortening the programming verification time, reducing the number of verification results to be processed, and improving programming efficiency.

[0107] In another implementation, the second verification result may also be the number of failed bits for programming the nth programming state. If the second verification result is less than the third preset value, it is determined to perform the second programming verification operation on the storage cell in the n+1th programming state. If the second verification result is greater than or equal to the third preset value, it is determined to perform the second programming verification operation on the storage cell in the nth programming state.

[0108] Exemplarily, binary coding may be used to indicate whether a memory cell has been programmed. For example, 0 may be used to indicate whether programming has been passed, and 1 may be used to indicate whether programming has not been passed. 0 may also be used to indicate whether programming has not been passed, and 1 may be used to indicate whether programming has been passed. During implementation, those skilled in the art may select an appropriate method to indicate whether a memory cell has been programmed according to actual conditions, and the embodiments of the present disclosure are not limited thereto.

[0109] It can be understood that when the number of failed bits for programming the nth programming state is less than the third preset value, it can be considered that the programming of the nth programming state is successfully completed. Therefore, in the next second programming verification operation, it is not necessary to perform programming verification on the nth programming state. In this way, compared with verifying the nth programming state every time, the programming verification time can be shortened. When the number of failed bits for programming the nth programming state is greater than or equal to the third preset value, it can be considered that the programming of the nth programming state has not been successful. Therefore, in the next second programming verification operation, it is necessary to continue to perform programming verification on the nth programming state.

[0110] Optionally, before step S602, the memory operation method may further include: the memory obtains a pre-verification result of a memory cell in an nth programming state based on a verification voltage of a second program verification operation.

[0111] Exemplarily, after the coarse programming is completed and before the fine programming is started, the pre-verification result is obtained. The pre-verification result is the number of storage cells that have reached the nth programming state after the coarse programming is completed. The pre-verification result can be understood as the influence of the coarse programming on the fine programming. In order to improve the accuracy of the fine programming, the influence of the pre-verification result should be eliminated in the fine programming.

[0112] Specifically, after the first fine programming is performed, a second verification result can be obtained based on the verification voltage of the fine programming. At this time, if the second verification result includes the number of memory cells in the nth programming state, the second preset value is greater than the first preset value. Figure 7 As shown, Figure 7 A threshold voltage distribution diagram of an n-th programming state provided in an embodiment of the present application. Figure 7 , the threshold voltage distribution diagram of the final rough programming of the nth programming state, the threshold voltage distribution diagram of the final fine programming of the nth programming state, and the threshold voltage distribution diagram of the first fine programming are shown. A pre-verification result can be obtained based on the verification voltage of the fine programming. At this time, the second verification result includes the pre-verification result, that is, the second verification result includes the number of storage cells that have been programmed in the rough programming. In order to reduce the risk of over-programming, the second preset value should be set to be greater than the first preset value, that is, the preset value of the fine programming is greater than the preset value of the rough programming.

[0113] In addition, if the second verification result includes the number of memory cells in the nth programming state other than the number of memory cells corresponding to the pre-verification result, the second preset value is less than the first preset value. Figure 8 As shown, Figure 8 Another threshold voltage distribution diagram of the nth programming state provided in the embodiment of the present application. Figure 8 The threshold voltage distribution diagram of the final rough programming of the nth programming state, the threshold voltage distribution diagram of the final fine programming of the nth programming state, and the threshold voltage distribution diagram of the first fine programming are shown in FIG. A pre-verification result can be obtained based on the verification voltage of the fine programming. At this time, the second verification result includes the number of storage cells in the nth programming state other than the number of storage cells corresponding to the pre-verification result, that is, the second verification result does not include the pre-verification result. In order to reduce the risk of over-programming, the second preset value should be set to be smaller than the first preset value, that is, the preset value of the fine programming is smaller than the preset value of the rough programming.

[0114] Optionally, S601 may include S6011 to S6014, such as Fig. 9 As shown, Fig. 9 A flowchart for roughly programming a memory provided in an embodiment of the present application.

[0115] S6011. The memory performs a first program verification operation on the memory cell in the mth programming state to obtain a first verification result of the memory cell in the mth programming state, where m is a positive integer.

[0116] Exemplarily, the first programming verification operation may include a first programming operation and a first verification operation, wherein the first programming operation is to apply a programming pulse to the memory cell in the mth programming state, and a first verification result may be obtained based on a first verification voltage of the first verification operation, wherein the first verification result is the number of successful bits programmed in the mth programming state.

[0117] S6012: If the first verification result of the memory cell in the mth programming state is greater than or equal to the first preset value, the memory performs a first program verification operation on the memory cell in the (m+1)th programming state.

[0118] Exemplarily, when the first verification result is greater than or equal to the first preset value, it indicates that more memory cells have reached the mth programming state, and it can be predicted that after applying the next programming pulse, the memory cell storing the target programming state as the m+1th programming state can reach the m+1th programming state. Therefore, after applying the next programming pulse, it is necessary to start the first programming verification operation for the m+1th programming state. In this way, the occurrence of over-programming can be reduced and the programming quality can be improved.

[0119] S6013: If the first verification result of the memory cell in the mth programming state is less than the first preset value, the memory performs a first program verification operation on the memory cell in the mth programming state.

[0120] Exemplarily, when the first verification result is less than the second preset value, it indicates that no memory cell or only a small number of memory cells have reached the mth programming state. Then, it can be predicted that after applying the next programming pulse, almost no memory cell whose target programming state is the m+1th programming state can reach the m+1th programming state, that is, the m+1th programming state will not be programmed successfully. Therefore, after applying the next encoding pulse, there is no need to perform the first programming verification operation on the m+1th programming state. In this way, the number of programming states that need to be verified in the next first programming verification operation can be reduced, which is conducive to shortening the programming verification time, reducing the number of verification results to be processed, and improving programming efficiency.

[0121] In another implementation, the first verification result may also be the number of failed bits for programming the mth programming state. If the first verification result is less than a fourth preset value, it is determined that the first programming verification operation is performed on the storage cell in the m+1th programming state. If the first verification result is greater than or equal to the fourth preset value, it is determined that the first programming verification operation is performed on the storage cell in the mth programming state.

[0122] It can be understood that when the number of failed bits for programming the mth programming state is less than the fourth preset value, it can be considered that the programming of the mth programming state is successfully completed. Therefore, in the next first programming verification operation, it is not necessary to perform programming verification on the mth programming state. In this way, compared with verifying the mth programming state every time, the programming verification time can be shortened and the programming speed can be increased. When the number of failed bits for programming the mth programming state is greater than or equal to the fourth preset value, it can be considered that the programming of the mth programming state has not been successful. Therefore, in the next first programming verification operation, it is necessary to continue to perform programming verification on the mth programming state.

[0123] S6014: If a first verification result obtained by performing a first program verification operation on the memory cell in the highest programming state is greater than or equal to a first preset value, a plurality of memory cells in the first programming state to the i-th programming state are obtained.

[0124] Exemplarily, if the first verification result includes the number of memory cells reaching the highest programming state, when the first verification result is greater than or equal to the first preset value, it indicates that a relatively large number of memory cells reach the highest programming state, that is, the rough programming process is completed.

[0125] Optionally, the memory operation method further includes: the memory obtains a first number of first program verification operations, and determines a first preset value according to the first number. The memory obtains a second number of second program verification operations, and determines a second preset value according to the second number.

[0126] Exemplarily, the first number and the second number can be understood as the number of cycles, wherein an erase operation and a write operation are performed on the memory, which is called a cycle. As the number of cycles increases, the programming performance of the memory may change, resulting in a change in programming speed. It is understandable that the cycle is defined by the smallest unit of programming. For example, when encoding is performed with a block as the smallest unit, the number of cycles of each storage unit in the block is substantially the same. In addition, when the memory is programmed with different smallest units, the number of cycles obtained is the number of cycles of the smallest unit performed by the programming.

[0127] Compared with the fixed first preset value and second preset value, in the embodiment of the present application, the number of programming verification operations is obtained and the preset value is determined according to the number. Therefore, in the programming verification operation, the programming characteristics that change with the number of cycles can be tracked, and the range of the preset value can be flexibly adjusted to reduce the slow programming speed caused by improper determination of the preset value, which is conducive to improving the programming speed and ensuring the programming quality.

[0128] Some embodiments of the present disclosure also provide an electronic device. The electronic device may be any one of a mobile phone, a desktop computer, a tablet computer, a laptop computer, a server, a vehicle-mounted device, a wearable device (such as a smart watch, a smart bracelet, smart glasses, etc.), a mobile power supply, a game console, a digital multimedia player, etc.

[0129] The electronic device may include the memory system described above, and may also include at least one of a central processing unit (CPU) and a cache.

[0130] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A method for operating a memory, characterized in that: The method comprises: Performing a plurality of first programming verification operations on a plurality of storage cells of the memory to obtain a plurality of storage cells in a first programming state to an i-th programming state, where i is a positive integer, determining whether to perform the first programming verification operation of a next programming state based on whether a first verification result reaches a first preset value in the first programming verification operation, and the first verification result includes the number of storage cells in a current programming state; Performing a second program verification operation on a memory cell in an n-th programming state to obtain a second verification result of the memory cell in the n-th programming state, where n is a positive integer; If the second verification result of the memory cell in the nth programming state is greater than or equal to a second preset value, the second programming verification operation is performed on the memory cell in the (n+1)th programming state, and the second preset value is different from the first preset value.

2. The method according to claim 1, characterized in that Before performing a second program verification operation on the memory cell in the nth programming state to obtain a second verification result of the memory cell in the nth programming state, the method further includes: A pre-verification result of the memory cell in the nth program state is acquired based on the verification voltage of the second program verification operation.

3. The method according to claim 2, characterized in that The second verification result includes the number of memory cells in an nth programming state, and the second preset value is greater than the first preset value.

4. The method according to claim 2, characterized in that: The second verification result includes the number of memory cells in the nth programming state except the number of memory cells corresponding to the pre-verification result, and the second preset value is smaller than the first preset value.

5. The operating method according to claim 1, characterized in that: The method of performing a plurality of first program verification operations on a plurality of storage cells of the memory to obtain a plurality of storage cells in a first programming state to an i-th programming state comprises: Performing the first program verification operation on the memory cell in the mth programming state to obtain a first verification result of the memory cell in the mth programming state, where m is a positive integer; If the first verification result of the memory cell in the mth programming state is greater than or equal to the first preset value, performing the first program verification operation on the memory cell in the (m+1)th programming state; If the first verification result of the memory cell in the mth programming state is less than the first preset value, performing the first program verification operation on the memory cell in the mth programming state; If the first verification result obtained by performing the first program verification operation on the memory cell in the highest programming state is greater than or equal to the first preset value, a plurality of memory cells in the 1st programming state to the i-th programming state are obtained.

6. The operating method according to claim 1, characterized in that: A step size of a plurality of program pulses of the first program verification operation is greater than a step size of a plurality of program pulses of the second program verification operation.

7. The operating method according to claim 1, characterized in that: The method further comprises: If the second verification result of the memory cell in the nth programming state is less than the second preset value, the second program verification operation is performed on the memory cell in the nth programming state.

8. The operating method according to claim 1, characterized in that: The method further comprises: Obtaining a first number of the first programming verification operation, and determining the first preset value according to the first number; A second number of the second program verification operation is obtained, and the second preset value is determined according to the second number.

9. A memory, characterized in that: The memory comprises: A memory cell array, the memory cell array comprising a plurality of memory cells; A peripheral circuit is coupled to the memory cell array, and the peripheral circuit is configured to: Performing a plurality of first programming verification operations on a plurality of storage cells of the memory to obtain a plurality of storage cells in a first programming state to an i-th programming state, where i is a positive integer, determining whether to perform the first programming verification operation of a next programming state based on whether a first verification result reaches a first preset value in the first programming verification operation, and the first verification result includes the number of storage cells in a current programming state; Performing a second program verification operation on a memory cell in an n-th programming state to obtain a second verification result of the memory cell in the n-th programming state, where n is a positive integer; If the second verification result of the memory cell in the nth programming state is greater than or equal to a second preset value, the second programming verification operation is performed on the memory cell in the (n+1)th programming state, and the second preset value is different from the first preset value.

10. The memory according to claim 9, characterized in that: The peripheral circuit is further configured as: A pre-verification result of the memory cell in the nth program state is acquired based on the verification voltage of the second program verification operation.

11. The memory according to claim 10, characterized in that: The second verification result includes the number of memory cells in an nth programming state, and the second preset value is greater than the first preset value.

12. The memory according to claim 10, characterized in that: The second verification result includes the number of memory cells in the nth programming state except the number of memory cells corresponding to the pre-verification result, and the second preset value is smaller than the first preset value.

13. The memory according to claim 10, characterized in that: The peripheral circuit is further configured as: Performing the first program verification operation on the memory cell in the mth programming state to obtain a first verification result of the memory cell in the mth programming state, where m is a positive integer; If the first verification result of the memory cell in the mth programming state is greater than or equal to the first preset value, performing the first program verification operation on the memory cell in the (m+1)th programming state; If the first verification result of the memory cell in the mth programming state is less than the first preset value, performing the first program verification operation on the memory cell in the mth programming state; If the first verification result obtained by performing the first program verification operation on the memory cell in the highest programming state is greater than or equal to the first preset value, a plurality of memory cells in the 1st programming state to the i-th programming state are obtained.

14. The memory according to claim 10, characterized in that: A step size of a plurality of program pulses of the first program verification operation is greater than a step size of a plurality of program pulses of the second program verification operation.

15. The memory according to claim 10, characterized in that: The peripheral circuit is further configured as: If the second verification result of the memory cell in the nth programming state is less than the second preset value, the second program verification operation is performed on the memory cell in the nth programming state.

16. The memory according to claim 10, characterized in that: The peripheral circuit is further configured as: Obtaining a first number of the first programming verification operation, and determining the first preset value according to the first number; A second number of the second program verification operation is obtained, and the second preset value is determined according to the second number.

17. A memory system, characterized in that: The memory system comprises: One or more memories as claimed in any one of claims 10 to 16; A memory controller is coupled to the memory and configured to control the memory.

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