Wafer level proximity sensor and manufacturing method thereof

Abstract

The invention relates to a wafer level proximity sensor and a method of manufacturing the same. The wafer level proximity sensor is formed by processing a silicon substrate wafer and a silicon cap wafer, respectively, bonding the cap wafer to the substrate wafer to form a bonded wafer interlayer, and then selectively thinning the silicon substrate wafer and the silicon cap wafer. The method comprises the following steps: firstly, thinning a silicon substrate wafer, and forming an interconnection structure of a silicon through hole in the thinned silicon substrate wafer; the silicon cap wafer is then thinned to expose an opening facing an area of the thinned silicon substrate wafer where the photosensitive region is located and an opening facing an area of the thinned silicon substrate wafer where the emitter die is to be mounted. After mounting the emitter die, the opening in the thinned silicon cap wafer is filled with a transparent material. The thinned silicon cap wafer also includes an opaque light barrier to block light transmission between the openings.

Description

Technical Field

[0001] The present disclosure relates generally to sensor technology, and in particular to wafer-level proximity (such as, for example, time-of-flight (ToF)) sensors. Background Art

[0002] Electronic sensor technology is now being incorporated into many consumer products, including automobiles, appliances, and mobile devices such as smartphones. Electronic microsensors can be used to detect environmental conditions such as temperature, humidity, rainfall, sound, etc. Such devices can also be used to detect the operating mode of the consumer appliance in which they are installed, such as the orientation of the smartphone, the use of voice commands, ambient light, etc. Microsensors have many advantages due to their size, reliability, and low cost. As electronic microsensors become smaller and cheaper, the demand for them is also higher.

[0003] An example of an electronic microsensor is a proximity sensor, which detects the presence of a nearby object without physical contact. Some proximity sensors emit a light beam that is reflected from the target object. The reflected light beam is then captured by the proximity sensor and compared to the emitted light beam or to the ambient light level to detect changes that can yield information about the target object. One specific embodiment of such a sensor known to those skilled in the art is a time-of-flight (ToF) sensor, which measures the time difference between the emission of a light beam and the return of the light beam reflected by a target to calculate the distance to the target.

[0004] Reference now Figure 1, which shows a cross-sectional view of a conventional ToF proximity microsensor module 100. The module 100 is housed in a chip package 102 mounted on a substrate 104. The substrate 104 may, for example, include a printed circuit board including a front connection pad 106, a rear connection pad 108, and an electrical connection network 110 (with lines and through holes) for electrically connecting the front connection pad and the rear connection pad. A sensor integrated circuit die 112 is mounted to the front surface of the substrate 104 and is electrically connected to the front connection pad 106 by a bonding wire. An emitter integrated circuit die 114 is mounted to the front surface of the substrate 104 and is electrically connected to the front connection pad 106 by a bonding wire. The sensor integrated circuit die 112 includes a first photosensitive region 116 and a second photosensitive region 118. The emitter integrated circuit die 114 includes a photoelectric emission region 120. A cap 124 is mounted to the substrate 104. The cap 124 is made of an opaque material and includes a peripheral side wall and a front wall. The distal ends of the peripheral side walls are mounted to the substrate 104 using a suitable adhesive. An opening is provided in the front wall that is generally vertically aligned with the location of the first photosensitive region 116 of the sensor integrated circuit die 112 and the photo-emissive region 120 of the emitter integrated circuit die 114. The inner wall of the cap is located between the first photosensitive region 116 and the second photosensitive region 118. Each opening in the front wall of the cap 124 is filled with a transparent optical element 128 (such as, for example, including a lens and possibly an optical filter).

[0005] In operation, light is emitted from the photo-emissive region 120 of the transmitter integrated circuit die 114. The light is internally reflected within the cap 124 while being blocked by the inner wall from reaching the first photosensitive region 116, and is detected by the second photosensitive region 118. The light also propagates to the outside of the microsensor module 100 through the transparent optical element 128a to illuminate the target object. The light reflected by the target object returns to the microsensor module 100, passes through the transparent optical element 128b, and is detected by the first photosensitive region 116. The sensor integrated circuit die 112 measures the time difference between the internally reflected light being sensed by the second photosensitive region 118 and the return light reflected by the target object being sensed by the first photosensitive region 116, and then calculates the distance from the microsensor module 100 to the target object based on the measured time difference.

[0006] Reference now Figure 2, which shows a cross-sectional view of a conventional wafer-level ToF proximity microsensor module 200 (e.g., see U.S. Patent Publication No. 2017 / 0287886, which is incorporated herein by reference). The wafer-level proximity microsensor module 200 is manufactured as an integrated sensor package. First, the silicon integrated circuit substrate wafer 202 and the silicon cap wafer 204 are processed separately. The separate wafers 202, 204 are then bonded to form a bonded wafer sandwich. The upper and lower surfaces of the bonded wafer sandwich are then further processed, and finally, the bonded wafer sandwich is singulated (or sliced) into separate proximity microsensor modules 200 by a cutting operation.

[0007] The module 200 includes a sensor integrated circuit die 212 formed from a silicon integrated circuit substrate wafer 202. The sensor integrated circuit die 212 includes a first photosensitive region 216 and a second photosensitive region 218. Through silicon vias 213 form an electrical connection network 210 for electrically connecting the front connection pads 206 of the sensor integrated circuit die 212 to a redistribution layer on the back side of the sensor integrated circuit die 212, the redistribution layer including the back connection pads 208. The emitter integrated circuit die 214 is mounted to the front surface of the sensor integrated circuit die 212 and electrically connected to the front connection pads 206. The module 200 also includes a silicon cap 224 mounted to the sensor integrated circuit die 212. The silicon cap 224 has openings disposed therein that are generally vertically aligned with the locations of the first photosensitive region 216 of the sensor integrated circuit die 212 and the photo-emissive region 220 of the emitter integrated circuit die 214. Each opening is filled with a transparent material (such as, for example, a transparent epoxy) that forms a transparent optical element 228.

[0008] In operation, light is emitted from the photo-emissive region 220 of the transmitter integrated circuit die 214. A portion of the light is internally reflected within the transparent optical element 228a and detected by the second photosensitive region 218. Another portion of the light propagates through the transparent optical element 228a to the outside of the microsensor module 200 to illuminate the target object. The light reflected by the target object returns to the microsensor module 200, passes through the transparent optical element 228b, and is detected by the first photosensitive region 216. The sensor integrated circuit die 212 measures the time difference between the internal refracted light sensed by the second photosensitive region 218 and the return light reflected by the target object sensed by the first photosensitive region 216, and then calculates the distance from the microsensor module 200 to the target object based on the measured time difference.

[0009] The wafer-level proximity microsensor module 200 has many advantages over the conventional proximity microsensor module 100. For example, the wafer-level proximity microsensor module 200 is smaller and cheaper to manufacture than the conventional proximity microsensor module 100. However, there is concern about addressing light propagation, providing improved light isolation with respect to crosstalk between photosensitive regions, and improving methods of manufacturing wafer-level proximity microsensor modules. Summary of the invention

[0010] In an embodiment, a method includes: forming at least one photosensitive region and at least one front connection pad at each of a plurality of integrated circuit regions of a silicon integrated circuit substrate wafer; forming a plurality of first grooves and a plurality of second grooves in a silicon cap wafer; providing an opaque light barrier at the silicon cap wafer to block light from being transmitted through the silicon cap wafer between the first grooves and the second grooves; wafer-to-wafer bonding the silicon cap wafer to a silicon integrated circuit substrate wafer to form a bonded wafer sandwich, wherein an opening of each first groove in the silicon cap wafer faces a corresponding photosensitive region of the silicon integrated circuit substrate wafer, and wherein an opening of each second groove in the silicon cap wafer faces a corresponding front connection pad of the silicon integrated circuit substrate wafer; and then, performing back grinding to thin the bonded wafer. a silicon integrated circuit substrate wafer having a sandwich; forming through silicon vias in the thinned silicon integrated circuit substrate wafer, wherein at least some of the through silicon vias are electrically connected to the at least one photosensitive region in each of the plurality of integrated circuit regions; then, performing back grinding to thin the silicon cap wafer and expose the openings of the first groove and the second groove; installing a light emitter integrated circuit die in the opening of each second groove, the light emitter integrated circuit die being mounted to the thinned silicon integrated circuit substrate wafer and electrically connected to the at least one front connection pad; filling the openings of the first groove and the second groove with a transparent material; and in a singulation operation, cutting through the bonded wafer sandwich between adjacent integrated circuit regions to produce a plurality of individual wafer-level microsensor modules.

[0011] In an embodiment, a device includes: an integrated circuit substrate including at least one photosensitive area and at least one front connection pad; a silicon cap, a silicon cap chip bonded to the integrated circuit substrate, the silicon cap including a first opening extending through the thickness of the silicon cap at the at least one photosensitive area, and also including a second opening extending through the thickness of the silicon cap at the area where the at least one front connection pad is located; wherein the silicon cap also includes an opaque light barrier to block light from being transmitted through the silicon cap wafer between the first opening and the second opening; a light emitter integrated circuit die mounted to the integrated circuit substrate at the area in the second opening and electrically connected to the at least one front connection pad; and a transparent material filling each of the first opening and the second opening. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] For a better understanding of the embodiments, reference will now be made, by way of example only, to the accompanying drawings, in which:

[0013] Figure 1 is a cross-sectional view of a conventional time-of-flight (ToF) proximity microsensor module;

[0014] Figure 2 is a cross-sectional view of a conventional wafer-level ToF proximity microsensor module;

[0015] Figure 3A-3C is a cross-sectional view of a wafer-level ToF proximity microsensor module;

[0016] Figure 4A-Figure 4K Shown for manufacturing Figure 3A The steps of the method for wafer-level ToF proximity microsensor module; and

[0017] Figure 5 and Figure 6 Each shows the Figure 3B and Figure 3C The micro sensor module 300 shown in FIG. Figure 4C The processing steps of the processing steps. DETAILED DESCRIPTION

[0018] In the following description, certain specific details are set forth in order to provide a comprehensive understanding of various aspects of the disclosed subject matter. However, the disclosed subject matter can be practiced without these specific details. In some cases, well-known structures and semiconductor processing methods that include embodiments of the subject matter disclosed herein are not described in detail to avoid obscuring the description of other aspects of the disclosure.

[0019] References to forming layers throughout the specification may require the use of conventional thin film deposition techniques to deposit insulating and / or conductive and / or semiconductor materials, including processes such as chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), metal organic chemical vapor deposition (MOCVD), plasma enhanced chemical vapor deposition (PECVD), plasma vapor deposition (PVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), electroplating, electro-less plating, etc. Examples of these processes are cited herein to describe specific embodiments. However, the present disclosure and references to certain deposition techniques should not be limited to those described. For example, in some cases, a description that references CVD can be completed using PVD instead, or a description that specifies electroplating can be completed using electroless plating instead.

[0020] References throughout the specification to conventional photolithography techniques known in the semiconductor fabrication art for patterning various thin films may include a spin-on exposure-development process sequence, typically followed by an etching process. Alternatively or additionally, photoresists may also be used to pattern a hard mask, such as a silicon nitride hard mask, which in turn may be used to pattern an underlying film.

[0021] References to conventional etching techniques known in the semiconductor manufacturing field for selective removal of polysilicon, silicon nitride, silicon dioxide, metal, photoresist, polyimide or similar materials throughout the specification include processes such as wet chemical etching, reactive ion (plasma) etching (RIE), cleaning, wet cleaning, pre-cleaning, spray cleaning, chemical mechanical planarization (CMP), etc. Specific embodiments are described herein by citing examples of these processes. However, the disclosure and references to certain deposition techniques should not be limited to those described. In some cases, two such techniques can be interchangeable. For example, stripping a photoresist may require immersing the sample in a wet chemical bath, alternatively, spraying the wet chemicals directly onto the sample.

[0022] Reference now Figure 3A , which shows a cross-sectional view of a wafer-level ToF proximity microsensor module 300. The wafer-level proximity microsensor module 300 is manufactured as an integrated sensor package. Details of the wafer-level manufacturing process are provided below and in Figure 4A-Figure 4K . In short, the silicon integrated circuit substrate wafer 302 and the silicon cap wafer 304 are processed separately. Then, the separate wafers 302, 304 are bonded to form a bonded wafer sandwich. Then, the upper and lower surfaces of the bonded wafer sandwich are further processed, and finally, the bonded wafer sandwich is singulated into individual proximity micro sensor modules 300.

[0023] Module 300 includes a sensor integrated circuit die 312 formed from a silicon integrated circuit substrate wafer 302. Sensor integrated circuit die 312 includes a first photosensitive region 316 and a second photosensitive region 318. Through silicon vias 313 form an electrical connection network 310 for electrically connecting front connection pads 306 of sensor integrated circuit die 312 to a redistribution layer on the back side of sensor integrated circuit die 312, the redistribution layer including back connection pads 308. Transmitter integrated circuit die 314 is mounted to the front surface of sensor integrated circuit die 312 and electrically connected to the front connection pads 306. Module 300 also includes a silicon cap 324 mounted to sensor integrated circuit die 312. Silicon cap 324 has openings disposed therein that are generally vertically aligned with the locations of first photosensitive region 316 of sensor integrated circuit die 312 and photoemissive region 320 of transmitter integrated circuit die 314. The sidewalls of the openings are lined with a layer 350 of an opaque material (e.g., black oxide, metal, or other suitable material for blocking infrared light) to address optical crosstalk issues between photosensitive regions. Layer 350 can be molded within the openings or deposited using a conformal deposition or plating process. Each opening is filled with a transparent material (such as, for example, a clear epoxy) that forms a transparent optical element 328.

[0024] The module 300 may also include a patterned opaque material (e.g., black oxide, metal, or other suitable material for blocking infrared light) layer 352 on the top surface of the silicon cap 324 to block light from entering the silicon cap 324. The layer 352 may be molded onto the top surface or deposited using a conformal deposition or plating process. The patterning of the opaque material layer 352 (performed using a molding operation or a photolithography operation) defines an optical aperture 354 that is vertically aligned with the location of the first photosensitive region 316 of the sensor integrated circuit die 312 and the photoelectric emission region 320 of the emitter integrated circuit die 314.

[0025] Reference now Figure 3B , which shows a cross-sectional view of another embodiment of a wafer-level ToF proximity microsensor module 300 . Figure 3A and Figure 3B Like reference numerals in the drawings refer to like parts. Figure 3B The examples in Figure 3A The difference of the embodiment in FIG. 1 is that the optical crosstalk blocking function in the silicon cap 324 is Figure 3B The transparent optical elements 328a, 328b are provided by a block 354 of opaque material (e.g., black oxide, metal, or other suitable material for blocking infrared light) located between the openings filled with the transparent optical elements 328a, 328b. The block 354 can be formed by filling the channel or opening in the silicon cap 324 with the opaque material. Again, this can be achieved by molding within the opening or depositing using a conformal deposition or electroplating process.

[0026] Reference now Figure 3C , which shows a cross-sectional view of another embodiment of a wafer-level ToF proximity microsensor module 300 . Figure 3A , Figure 3B and Figure 3C Like reference numerals in the drawings refer to like parts. Figure 3C The examples in Figure 3A and Figure 3B The difference of the embodiment in FIG. 1 is that the optical crosstalk blocking function in the silicon cap 324 is Figure 3C The transparent optical element 328a, 328b is provided by a ring 356 of opaque material (e.g., black oxide, metal, or other suitable material for blocking infrared light) surrounding each opening filled with the transparent optical element 328a, 328b. The ring 356 can be formed by filling the annular channel or opening in the silicon cap 324 with the opaque material. Again, this can be achieved by molding within the opening or depositing using a conformal deposition or electroplating process.

[0027] In operation, light is emitted from the photo-emissive region 320 of the transmitter integrated circuit die 314. A portion of this light is internally reflected within the transparent optical element 328a and detected by the second photosensitive region 318. It will be noted that the light barrier formed by the opaque material layer 350, the opaque material block 354, or the opaque material ring 356 blocks the emitted light from propagating through the silicon cap 324 toward the first photosensitive region 316. Another portion of the light propagates through the transparent optical element 328a to the exterior of the microsensor module 300 to illuminate a target object. Light reflected by the target object returns to the microsensor module 300, passes through the transparent optical element 328b, and is detected by the first photosensitive region 316. It will be noted that the light barrier formed by the opaque material layer 350, the opaque material block 354, or the opaque material ring 356 blocks the returning reflected emitted light from propagating through the silicon cap 324 toward the second photosensitive region 318. The sensor integrated circuit die 312 measures the time difference between the internal refracted light sensed by the second photosensitive region 318 and the return light reflected by the target object sensed by the first photosensitive region 316 and then calculates the distance from the micro sensor module 300 to the target object based on the measured time difference.

[0028] Reference now Figure 4A-Figure 4K , which shows the manufacturing Figure 3A These processing steps can also be used to utilize the microsensor module 300 as described herein and Figure 5 and Figure 6 The modifications shown in the Figure 3B and Figure 3C A micro sensor module 300 is provided.

[0029] Figure 4A- A silicon integrated circuit substrate wafer 302 is manufactured using conventional techniques well known to those skilled in the art. The thickness of the wafer 302 may be, for example, in the range of 50-100 μm. The wafer includes a plurality of integrated circuit regions 402, each of which is manufactured to include a front connection pad 306, a first photosensitive region 316, and a second photosensitive region 318. Sufficient vacant space is provided between adjacent integrated circuit regions 402 to allow singulation. Although the photosensitive regions 316, 318 and the front connection pad 306 are illustrated as being located on the upper surface of the silicon integrated circuit substrate wafer 302, it should be understood that this is only a simplified illustration, and those skilled in the art should understand that the photosensors of the photosensitive regions 316, 318 are typically located at or within the semiconductor material of the wafer 302, and the front connection pad 306 is typically located in a metallization interconnect layer of the wafer 302 extending above the semiconductor material. The photosensitive regions 316 , 318 may, for example, be formed by an array of photosensors such as photodiodes or single photon avalanche diodes (SPADs).

[0030] Figure 4B - Using conventional photolithography processing techniques, an array of grooves 404a, 404b is etched in the silicon cap wafer 304. The thickness of the wafer 304 can be, for example, in the range of 200-300 μm. The grooves 404 can be opened to a suitable depth using a chemical etching process. In the embodiment mentioned, the grooves 404 have a rectangular or square profile of suitable size. The profile can include, for example, rounded corners. The depth of the etched openings of the grooves 404a, 404b is controlled to be less than the thickness of the wafer 304. The size of the etched opening of the groove 404a is controlled to exceed the area occupied by the second photosensitive area 318, certain front connection pads 306, and the space occupied by the transmitter integrated circuit die 314 mounted to these specific front connection pads. The size of the etched opening of the groove 404b is controlled to exceed the area occupied by the first photosensitive area 316. Sufficient space is provided between certain adjacent grooves 404 to allow singulation.

[0031] Figure 4C - A layer of opaque material 406 is deposited on the sidewalls and bottom of the trenches 404a, 404b. The material may include, for example, black oxide, metal, or other suitable material for blocking infrared light. For example, layer 406 may be formed using a molding process or a conformal deposition or plating process. A planarization process may be used to remove the portion of layer 406 that is above the top surface of wafer 304. As discussed below, at this point in the manufacturing method, an alternative Figure 5 or Figure 6 The processing steps shown in .

[0032] Figure 4D-The silicon cap wafer 304 is then flipped over and mounted to the upper surface of the silicon integrated circuit substrate wafer 302. This mounting can be achieved using wafer-to-wafer bonding to form a bonded wafer sandwich. The bonding can, for example, utilize an adhesive (e.g., epoxy) material. Alternatively, a molecular bonding process can be used. When mounting the silicon cap wafer 304 to the silicon integrated circuit substrate wafer 302, care is taken to align the opening of each groove 404a with the area of ​​the silicon integrated circuit substrate wafer 302 where the second photosensitive area 318, certain front connection pads 306, and the space to be occupied by the transmitter integrated circuit die 314 mounted to these specific front connection pads are located. In addition, when mounting the silicon cap wafer 304 to the silicon integrated circuit substrate wafer 302, care is taken to align the opening of each groove 404b with the area of ​​the silicon integrated circuit substrate wafer 302 where the first photosensitive area 316 is located.

[0033] Figure 4E - A back grinding process is then applied to thin the silicon integrated circuit substrate wafer 302 of the bonded wafer sandwich to define the thickness of the sensor integrated circuit die 312. The thinned thickness of the wafer 302 is selected to be suitable for subsequent processing operations (e.g., see Figure 4F 304) and is less than the original wafer thickness. Note that at this point in the manufacturing process, the entire thickness of the silicon cap wafer 304 is present to provide rigidity to the bonded wafer sandwich during back grinding of the silicon integrated circuit substrate wafer 302.

[0034] Figure 4F -Through silicon vias 313 and rear connection pads 308 of the electrical connection network 310 are then formed in the thinned silicon integrated circuit substrate wafer 302 of the bonded wafer sandwich. The electrical connection network 310 may also include a redistribution layer on the back surface of the thinned silicon integrated circuit substrate wafer 302. The through silicon vias 313 extend completely through the thinned thickness of the silicon integrated circuit substrate wafer 302 from the rear connection pads 308 to the front connection pads 306. The through silicon vias 313 may be formed using any suitable through silicon via fabrication process known to those skilled in the art. Note that at this point in the fabrication process, the entire thickness of the silicon cap wafer 304 is still present to provide rigidity to the bonded wafer sandwich during the through silicon via fabrication process.

[0035] exist Figure 4E and Figure 4F The presence of the full thickness of the silicon cap wafer 304 is important during the fabrication steps because it minimizes the risk of damaging the silicon integrated circuit substrate wafer 302 that is bonded to the wafer sandwich.

[0036] Figure 4G- A back grinding process is then applied to thin the silicon cap wafer 304 of the bonded wafer sandwich to define the thickness of the silicon cap 324 and expose the openings of the trenches 404a, 404b. The thinned thickness of the wafer 304 is selected to be suitable for subsequent processing operations and is less than the original wafer thickness. Figure 5 and Figure 6 In the case of the embodiment shown in , such back grinding of the silicon cap wafer 304 of the bonded wafer sandwich will further reach the opaque material filled trenches 430, 432, thereby providing a block 354 and a ring 356, respectively.

[0037] Note that in Figure 4A In the manufacturing step shown in FIG. 3 , a protective material layer (schematically shown in dot-dash lines) may be deposited to cover and protect each photosensitive region 316, 318 when manufacturing the substrate wafer 302. The protective material layer is used to protect the region 316, 318 from being damaged by the execution of Figure 4G Damage or contamination caused by back grinding during the manufacturing steps shown in Figure 4G At any suitable point after back grinding and subsequently below Fig. 4I Before filling the openings of the trenches 430, 432 in the manufacturing step, the protective material layer can be removed by selective etching or cleaning. The protective material layer can include, for example, an easily removable water-soluble layer. Alternatively, an organic material layer can be used.

[0038] Figure 4H -The transmitter integrated circuit die 314 is then mounted to the upper surface of the silicon integrated circuit substrate wafer 302 in the exposed opening of the groove 404a and electrically connected to the front connection pads 306. The transmitter integrated circuit die 314 may, for example, include a semiconductor-based vertical cavity surface emitting laser (VCSEL) diode. Although not specifically illustrated, soldering and / or wire bonding may be used to electrically connect to the front connection pads 306.

[0039] Fig. 4I The exposed openings of the trenches 404a and 404b are then filled with a transparent material, such as a transparent epoxy, to form the transparent optical element 328. After filling, a planarization process may be performed to remove excess transparent material on the top surface of the thinned silicon cap wafer 304.

[0040] Figure 4J- A patterned layer of opaque material 352 is then deposited on the top surface of the silicon cap 324 and partially covers the transparent optical element 328. The layer 352 may, for example, include black oxide, metal, or other suitable material for blocking infrared light. The layer 352 may be formed by molding or deposition. The patterning of the layer of opaque material 352 (by a molding process or a photolithography process) defines an optical aperture 354 that is vertically aligned with the location of the first photosensitive region 316 of the sensor integrated circuit die 312 and the photoelectric emissive region 320 of the emitter integrated circuit die 314. In addition, solder balls are attached to the rear connection pads 308. The solder balls may, for example, be arranged in a ball grid array pattern.

[0041] Figure 4K The thinned bonded wafer sandwich is then subjected to a singulation or dicing process 460 to cut through the stacked and thinned wafers between the integrated circuit regions 402 and produce individual wafer-level proximity microsensor modules 300. Note that the attachment of solder balls may alternatively be performed after singulation.

[0042] Additionally, an optical filter layer and / or an optical lens may be mounted to extend over each optical aperture 354 .

[0043] Reference now Figure 5 , which shows the manufacturing Figure 3B The micro sensor module 300 shown in FIG. Figure 4C Here, instead of using an opaque layer 406 lining the openings of the trenches 404a and 404b, a trench 430 is formed in the upper surface of the silicon cap wafer 304 between the openings of the trenches 404a and 404b, and the trench 430 is filled with an opaque material to form a block 354. The opaque material may include, for example, black oxide, metal, or other suitable material for blocking infrared light. Preferably, the opaque material is provided using a molding process. A trench etch and fill process may alternatively be used.

[0044] Reference now Figure 6 , which shows the manufacturing Figure 3C The micro sensor module 300 shown in FIG. Figure 4C Here, instead of using an opaque layer 406 lining the openings of the grooves 404a and 404b, grooves 432a, 432b are formed in the upper surface of the silicon cap wafer 304, annularly surrounding the openings of the grooves 404a and 404b, respectively. These grooves 432a, 432b are filled with an opaque material to form a ring 356. The opaque material may include, for example, black oxide, metal, or other suitable material for blocking infrared light. Preferably, the opaque material is provided using a molding process. A trench etching and filling process may alternatively be used.

[0045] In a preferred embodiment, the micro sensor module 300 is a component of an electronic device such as a smart phone. More specifically, the micro sensor module 300 can be integrated into or integrated with a touch screen of the electronic device, for example.

[0046] Although the present invention has been described and illustrated in detail in the drawings and the foregoing description, these descriptions and illustrations should be considered illustrative or exemplary rather than restrictive; the present invention is not limited to the disclosed embodiments. Other variations of the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention by studying the drawings, the disclosure, and the appended claims.

Claims

1. A method comprising: forming at least one photosensitive region and at least one front connection pad at each of a plurality of integrated circuit regions of a silicon integrated circuit substrate wafer; forming a plurality of first trenches and a plurality of second trenches in a silicon cap wafer; providing an opaque light barrier at the silicon cap wafer to block light from being transmitted through the silicon cap wafer between the first trench and the second trench; Wafer-to-wafer bonding the silicon cap wafer to the silicon integrated circuit substrate wafer to form a bonded wafer sandwich, wherein an opening of each first trench in the silicon cap wafer faces a corresponding photosensitive region of the silicon integrated circuit substrate wafer, and wherein an opening of each second trench in the silicon cap wafer faces a corresponding front connection pad of the silicon integrated circuit substrate wafer; Then, back grinding is performed to thin the silicon integrated circuit substrate wafer bonded to the wafer sandwich; forming through silicon vias in the thinned silicon integrated circuit substrate wafer, wherein at least some of the through silicon vias are electrically connected to the at least one photosensitive region in each of the plurality of integrated circuit regions; Then, performing back grinding to thin the silicon cap wafer and expose openings of the first trench and the second trench; mounting a light emitter integrated circuit die in the opening of each second trench, the light emitter integrated circuit die being mounted to the thinned silicon integrated circuit substrate wafer and electrically connected to the at least one front connection pad; filling the openings of the first trench and the second trench with a transparent material; as well as In a singulation operation, the bonded wafer sandwich is cut through between adjacent integrated circuit regions to produce a plurality of individual wafer-level microsensor modules.

2. The method of claim 1, wherein providing an opaque light barrier comprises lining the sidewalls and the bottom of each first trench and each second trench with a layer of opaque material.

3. The method of claim 1 , wherein providing the opaque light barrier comprises forming a trench in the upper surface of the silicon cap wafer between the first trench and the second trench, and filling the trench with an opaque material to form a block of opaque material between the first trench and the second trench.

4. The method of claim 1 , wherein providing the opaque light barrier comprises forming an annular groove in the upper surface of the silicon cap wafer around each of the first groove and the second groove, and filling the annular groove with an opaque material to form an opaque material ring around each of the first groove and the second groove.

5. The method according to claim 1, further comprising: Before wafer-to-wafer bonding, each photosensitive area is covered with a protective layer; as well as After back grinding is performed to thin the silicon cap wafer, the protective layer is removed.

6. The method of claim 1, further comprising: After filling the openings of the first and second trenches with the transparent material, covering the upper surface of the thinned silicon cap wafer with a patterned opaque material layer including a hole over each of the transparent material-filled openings of the first and second trenches.

7. A device comprising: An integrated circuit substrate including at least one photosensitive region and at least one front connection pad; a silicon cap wafer bonded to the integrated circuit substrate, the silicon cap including a first opening extending through the thickness of the silicon cap at the at least one photosensitive region, and further including a second opening extending through the thickness of the silicon cap at the region where the at least one front connection pad is located; wherein the silicon cap further comprises an opaque light barrier to block light from being transmitted through the silicon cap wafer between the first opening and the second opening; a light emitter integrated circuit die mounted to the integrated circuit substrate at the region in the second opening and electrically connected to the at least one front connection pad; as well as A transparent material is filled in each of the first opening and the second opening.

8. The apparatus of claim 7, wherein the opaque light barrier comprises a layer of opaque material lining sidewalls of each first opening and each second opening.

9. The device of claim 7, wherein the opaque light barrier comprises a groove in the upper surface of the silicon cap between the first opening and the second opening, and an opaque material filled in the groove to form an opaque material block between the first opening and the second opening.

10. The device of claim 7, wherein the opaque light barrier comprises an annular groove in the upper surface of the silicon cap surrounding each of the first opening and the second opening, and an opaque material filled in each annular groove to form a ring of opaque material surrounding each of the first opening and the second opening.

11. The apparatus of claim 7, further comprising a patterned opaque material layer covering an upper surface of the silicon cap, the patterned opaque material layer comprising a hole over each of the first opening and the second opening filled with a transparent material.

12. A smart phone comprising the device as claimed in claim 7.

13. A touch screen for an electronic device, wherein the touch screen integrates the device as claimed in claim 7.

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