Semiconductor structure and forming method thereof
By designing semiconductor structures with specific light transmittance relationships in semiconductor integrated circuit manufacturing, including substrate, alignment mark layer and cover layer, the problem of difficulty in improving alignment mark accuracy is solved, and higher optical alignment accuracy is achieved and Semiconductor structural performance.
Patent Information
- Application Number
- CN202310786935.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-06-29
- Publication Date
- 2024-12-31
AI Technical Summary
In the manufacturing process of semiconductor integrated circuits, how to improve the dimensional accuracy, morphological accuracy and position accuracy of alignment marks to cope with the manufacturing difficulty and complexity challenges brought about by the reduction of technical nodes.
Design a semiconductor structure, including a substrate, an alignment mark layer and a cover layer, ensure that the light transmittance of the alignment mark layer is less than that of The light transmittance of the substrate and the cover layer is greater than that of the alignment mark layer, thereby identifying the alignment mark layer through the cover layer and improving the optical alignment accuracy.
This method improves the optical alignment accuracy in subsequent patterning processes, avoids the influence of the thickness of the cover layer on the accuracy of the alignment mark layer, and thus improves the performance of the semiconductor structure.
Smart Images
Figure CN119230526A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art
[0002] With the rapid growth of the semiconductor integrated circuit (IC) industry, semiconductor technology continues to move towards smaller process nodes driven by Moore's Law, making integrated circuits develop in the direction of smaller size, higher circuit precision and higher circuit complexity.
[0003] In the development of integrated circuits, the functional density (i.e. the number of internal connection structures of each chip) is gradually increasing, while the geometric size (i.e. the minimum component size that can be produced using process steps) is gradually decreasing, which correspondingly increases the difficulty and complexity of integrated circuit manufacturing.
[0004] At present, as technology nodes continue to shrink, how to improve the size accuracy, shape accuracy and position accuracy of alignment marks has become a challenge. Summary of the invention
[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the size accuracy, shape accuracy and position accuracy of an alignment mark, so as to improve the performance of the semiconductor structure.
[0006] To solve the above problems, an embodiment of the present invention provides a semiconductor structure, comprising: a substrate, the substrate comprising an alignment area, an initial alignment mark formed in the substrate of the alignment area; an alignment mark layer, located on the substrate of the alignment area and covering the initial alignment mark, the transmittance of the alignment mark layer is less than the transmittance of the substrate; a covering layer, located on the substrate and the alignment mark layer, the transmittance of the covering layer is greater than the transmittance of the alignment mark layer.
[0007] Optionally, a groove is formed in the substrate of the alignment area to provide the uneven initial alignment mark.
[0008] Optionally, along the normal direction of the top surface of the substrate, the depth of the groove is less than or equal to 770 microns.
[0009] Optionally, the opening size of the groove is less than or equal to 300 mm.
[0010] Optionally, the alignment mark layer conformally covers the initial alignment mark.
[0011] Optionally, along a normal direction of the top surface of the substrate, a thickness of the alignment mark layer is less than or equal to 770 micrometers.
[0012] Optionally, the material of the alignment mark layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride and silicon carbide.
[0013] Optionally, the substrate includes a plurality of discretely arranged alignment areas; the number of the alignment mark layers is multiple, and each alignment mark layer is discrete from each other.
[0014] Optionally, the material of the substrate includes one or more of silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, indium gallium, silicon on insulator and germanium on insulator.
[0015] Optionally, the material of the cover layer includes one or more of silicon, germanium, silicon germanium, silicon carbide and gallium arsenide.
[0016] Optionally, the material of the covering layer is the same as that of the substrate.
[0017] Correspondingly, an embodiment of the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising an alignment area, an initial alignment mark formed in the substrate of the alignment area; forming an alignment mark layer covering the initial alignment mark on the substrate of the alignment area, the transmittance of the alignment mark layer being less than the transmittance of the substrate; and forming a covering layer on the substrate and the alignment mark layer, the transmittance of the covering layer being greater than the transmittance of the alignment mark layer.
[0018] Optionally, the step of forming the alignment mark layer includes: forming an alignment mark material layer on the substrate; removing the alignment mark material layer located at other positions outside the alignment area, and using the remaining alignment mark material layer located in the alignment area as the alignment mark layer.
[0019] Optionally, the step of removing the alignment mark material layer at remaining locations outside the alignment area includes: forming a patterned mask layer on the substrate, the mask layer covering the alignment mark material layer in the alignment area and exposing the alignment mark material layer at remaining locations outside the alignment area; and removing the alignment mark material layer exposed by the mask layer.
[0020] Optionally, the process of forming the alignment mark material layer includes one or more of a chemical vapor deposition process, an atomic layer deposition process and a physical vapor deposition process.
[0021] Optionally, the process of removing the alignment mark material layer at the remaining positions outside the alignment area includes one or both of a dry etching process and a wet etching process.
[0022] Optionally, in the step of providing a substrate, a groove is formed in the substrate of the alignment area to provide the uneven initial alignment mark.
[0023] Optionally, in the step of forming the alignment mark layer, the alignment mark layer conformally covers the initial alignment mark.
[0024] Optionally, in the step of providing a substrate, the substrate includes a plurality of discretely arranged alignment areas; and in the step of forming the alignment mark layer, a plurality of mutually discrete alignment mark layers are formed.
[0025] Optionally, in the step of forming the covering layer, the material of the covering layer is the same as the material of the substrate.
[0026] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:
[0027] The semiconductor structure provided by the embodiment of the present invention includes an alignment mark layer located on the substrate of the alignment area and covering the initial alignment mark, wherein the transmittance of the alignment mark layer is less than the transmittance of the substrate, and a covering layer located on the substrate and the alignment mark layer, wherein the transmittance of the covering layer is greater than the transmittance of the alignment mark layer. Since the transmittance of the alignment mark layer is less than the transmittance of the substrate and the covering layer, the alignment mark layer located between the covering layer and the substrate can be identified through the covering layer, and the dimensional accuracy, morphological accuracy and positional accuracy of the alignment mark layer are not affected by the thickness of the covering layer, thereby improving the optical alignment accuracy in the subsequent graphic process, and correspondingly also facilitating that the thickness of the covering layer is not limited, thereby improving the performance of the semiconductor structure.
[0028] In the method for forming a semiconductor structure provided by an embodiment of the present invention, an alignment mark layer covering the initial alignment mark is formed on the substrate of the alignment area, the transmittance of the alignment mark layer is less than the transmittance of the substrate, and a covering layer is formed on the substrate and the alignment mark layer, the transmittance of the covering layer is greater than the transmittance of the alignment mark layer. Since the transmittance of the alignment mark layer is less than the transmittance of the substrate and the covering layer, the alignment mark layer located between the covering layer and the substrate can be identified through the covering layer, and the dimensional accuracy, morphological accuracy and position accuracy of the alignment mark layer are not affected by the thickness of the covering layer, thereby improving the optical alignment accuracy in the subsequent graphic process, and correspondingly, it is also beneficial to make the thickness of the covering layer unrestricted, thereby improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0029] Figure 1 is a schematic structural diagram of a first embodiment of a semiconductor structure;
[0030] Figure 2 is a schematic structural diagram of a second embodiment of a semiconductor structure;
[0031] Figure 3 is a schematic structural diagram of a third embodiment of a semiconductor structure;
[0032] Figure 4 is a schematic structural diagram of an embodiment of a semiconductor structure of the present invention;
[0033] Figure 5 is a schematic diagram of a partial structure of a substrate in an embodiment of a semiconductor structure of the present invention;
[0034] Figures 6 to 11 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION
[0035] At present, the performance of semiconductor structures still needs to be improved. Now, combining a semiconductor structure, we analyze the reasons why the performance of semiconductor structures needs to be improved. Figure 1 is a schematic structural diagram of a first embodiment of a semiconductor structure; Figure 2 is a schematic structural diagram of a second embodiment of a semiconductor structure; Figure 3 It is a schematic structural diagram of a third embodiment of a semiconductor structure.
[0036] refer to Figure 1 The semiconductor structure includes: a substrate 10, the substrate 10 includes an alignment area i', and an initial alignment mark 11 with an uneven surface is formed in the substrate 10 of the alignment area i'; a covering layer 12, located on the substrate 10 and the initial alignment mark 11, and an alignment mark 13 corresponding to the morphology of the initial alignment mark 11 is formed in the covering layer 12.
[0037] The research found that Figure 2 As shown in FIG. 1 , when the thickness of the cover layer 12′ is large, the morphology of the initial alignment mark 11′ is easily deformed when being transmitted to the cover layer 12′, that is, the morphology of the alignment mark 13′ is relatively smooth compared with the morphology of the initial alignment mark 11′, resulting in poor dimensional accuracy and morphological accuracy of the alignment mark 13′, thereby making the optical alignment accuracy in the subsequent patterning process poor; moreover, as shown in FIG. Figure 3 As shown, when the thickness of the cover layer 12 ″ is further increased, it is difficult to form an alignment mark corresponding to the initial alignment mark 11 ″ in the cover layer 12 ″.
[0038] In order to solve the above technical problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate, the substrate including an alignment area, an initial alignment mark formed in the substrate of the alignment area; an alignment mark layer, located on the substrate of the alignment area and covering the initial alignment mark, the transmittance of the alignment mark layer is less than the transmittance of the substrate; a covering layer, located on the substrate and the alignment mark layer, the transmittance of the covering layer is greater than the transmittance of the alignment mark layer.
[0039] The semiconductor structure provided by the embodiment of the present invention includes an alignment mark layer located on the substrate in the alignment area and covering the initial alignment mark, the light transmittance of the alignment mark layer is less than the light transmittance of the substrate, and a covering layer located on the substrate and the alignment mark layer, the light transmittance of the covering layer is greater than the light transmittance of the alignment mark layer. Since the light transmittance of the alignment mark layer is less than the light transmittance of the substrate and the covering layer, the alignment mark layer located between the covering layer and the substrate can be identified through the covering layer, and the dimensional accuracy, morphological accuracy and position accuracy of the alignment mark layer are not affected by the thickness of the covering layer, thereby improving the optical alignment accuracy in the subsequent graphic process, and correspondingly, it is also beneficial to make the thickness of the covering layer unrestricted, thereby improving the performance of the semiconductor structure.
[0040] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and understandable, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0041] Figure 4 is a schematic structural diagram of an embodiment of a semiconductor structure of the present invention; Figure 5 It is a schematic diagram of a local structure of a substrate in an embodiment of a semiconductor structure of the present invention.
[0042] In this embodiment, the semiconductor structure includes: a substrate 100, the substrate 100 includes an alignment area i, and an initial alignment mark 101 is formed in the substrate 100 in the alignment area i; an alignment mark layer 120, which is located on the substrate 100 in the alignment area i and covers the initial alignment mark 101, and the transmittance of the alignment mark layer 120 is less than the transmittance of the substrate 100; and a covering layer 140, which is located on the substrate 100 and the alignment mark layer 120, and the transmittance of the covering layer 140 is greater than the transmittance of the alignment mark layer 120.
[0043] The substrate 100 is used to provide a process platform for forming a semiconductor structure.
[0044] In this embodiment, the material of the substrate 100 includes one or more of silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, indium gallium, silicon on insulator, and germanium on insulator.
[0045] Silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, indium gallium, silicon on insulator and germanium on insulator have good light transmittance, which can easily make the transmittance of the alignment mark layer 120 lower than the transmittance of the substrate 100, so that in the subsequent patterning process, the relevant patterning equipment can recognize the alignment mark layer 120.
[0046] As an example, the material of the substrate 100 is silicon. Silicon substrate is a commonly used material in semiconductor processes, and has a low cost, which is conducive to reducing process costs and process difficulty.
[0047] The alignment region i is used to provide a process platform for forming the alignment mark layer 120 .
[0048] In this embodiment, the substrate 100 includes a plurality of discretely arranged alignment regions i.
[0049] The substrate 100 includes a plurality of discretely disposed alignment regions i, so as to form a plurality of mutually discrete alignment mark layers 120 .
[0050] As an example, only one alignment area i is shown here.
[0051] In this embodiment, the substrate 100 further includes a device region (not labeled).
[0052] The device region is used to form various semiconductor devices (eg, source, drain, gate, etc.).
[0053] In other embodiments, the substrate may further include other regions.
[0054] The initial alignment mark 101 is used to provide a process basis for forming the alignment mark layer 120 .
[0055] In this embodiment, a groove 102 (such as Figure 5 ), for providing an uneven initial alignment mark 101.
[0056] The groove 102 and the substrate 100 outside the groove 102 together form an uneven initial alignment mark 101 .
[0057] It should be noted that the depth h of the groove 102 along the normal direction of the top surface of the substrate 100 should not be too large. If the depth h of the groove 102 is too large, it is easy to make the process of forming the groove 102 more difficult, and it is also easy to increase the difficulty of forming the alignment mark layer 120 in the groove 102; therefore, in this embodiment, along the normal direction of the top surface of the substrate 100, the depth h of the groove 102 is less than or equal to 770 microns.
[0058] It should also be noted that the opening size w of the groove 102 should not be too large. If the opening size w of the groove 102 is too large, the lateral size of the initial alignment mark 101 is likely to be too large, and the area of the alignment region i is likely to be too large, thereby making the area of the semiconductor structure too large. Therefore, in this embodiment, the opening size w of the groove 102 is less than or equal to 300 mm.
[0059] The lateral direction refers to a direction perpendicular to the sidewall of the groove 102 .
[0060] In this embodiment, the substrate 100 has doping ions therein, and the doping ions are used to change the resistance value of the substrate 100 .
[0061] The doping ions in the substrate 100 are used to change the resistance of the substrate 100 so that the resistance of the substrate 100 meets the process requirements.
[0062] Specifically, the doping ions include nitrogen ions, phosphorus ions, fluorine ions, boron ions, boron fluoride ions, arsenic ions, antimony ions, indium ions, carbon ions, germanium ions, and the like.
[0063] The alignment mark layer 120 is used for optical alignment in a subsequent patterning process.
[0064] The light transmittance of the alignment mark layer 120 is lower than that of the substrate 100 , so that the alignment mark layer 120 can be identified by relevant equipment for optical alignment, and thus used for optical alignment in subsequent patterning processes.
[0065] It should be noted that, compared with the solution of using a cover layer to provide the alignment mark, by additionally providing the alignment mark layer 120 , the thickness or material of the alignment mark layer 120 can be adjusted separately to meet the requirements of optical alignment.
[0066] It should also be noted that the thickness of the alignment mark layer 120 should not be too large along the normal direction of the top surface of the substrate 100. If the thickness of the alignment mark layer 120 is too large, it is easy to increase the difficulty of forming the alignment mark layer 120, which will lead to poor morphological accuracy and dimensional accuracy of the alignment mark layer 120, and also to poor effect of the alignment mark layer 120 as an alignment mark in the subsequent patterning process, thereby making the effect of improving the optical alignment accuracy in the subsequent patterning process unsatisfactory. Therefore, in this embodiment, along the normal direction of the top surface of the substrate 100, the thickness of the alignment mark layer 120 is less than or equal to 770 microns.
[0067] It should also be noted that the material of the alignment mark layer 120 includes one or more of silicon oxide, silicon nitride, silicon oxynitride and silicon carbide.
[0068] Silicon oxide, silicon nitride, silicon oxynitride and silicon carbide are commonly used materials in semiconductor processes, which are easy to obtain and have low process costs. In addition, silicon oxide, silicon nitride, silicon oxynitride and silicon carbide have low light transmittance, which can easily make the transmittance of the alignment mark layer 120 lower than the transmittance of the substrate 100, and also easily make the transmittance of the alignment mark layer 120 lower than the transmittance of the covering layer 140. Correspondingly, it is also easy to make the reflectivity of the alignment mark layer 120 better, thereby making it easier for related equipment to identify the alignment mark layer.
[0069] In this embodiment, there are a plurality of alignment mark layers 120 , and each alignment mark layer 120 is separate from each other.
[0070] There are a plurality of alignment mark layers 120 , and each alignment mark layer 120 is separated from each other, which is beneficial to improving the reliability of the alignment mark layer 120 .
[0071] In this embodiment, the alignment mark layer 120 conformally covers the initial alignment mark 101 .
[0072] The alignment mark layer 120 conformally covers the initial alignment mark 101, that is, the morphology, size and position of the alignment mark layer 120 are associated with the morphology, size and position of the initial alignment mark 101. In other words, by making the alignment mark layer 120 conformally cover the initial alignment mark 101, it is easy to transfer the morphology of the initial alignment mark 101 to the alignment mark layer 120, so that the alignment mark layer 120 is easy to be recognized by related equipment, and the morphology, size and position of the alignment mark layer 120 are easy to control, which is beneficial to improve the optical alignment accuracy in the subsequent graphic process.
[0073] Combined with reference Figure 4 and Figure 5 Specifically, a groove 102 is formed in the substrate 100 of the alignment area i to provide an uneven initial alignment mark 101. Accordingly, the alignment mark layer 120 conformally covers the groove 102 of the initial alignment mark 101 and the substrate 100 of the alignment area i outside the groove 102.
[0074] The alignment mark layer 120 conformally covers the groove 102 of the initial alignment mark 101 and the substrate 100 outside the groove 102, which makes it easy for the alignment mark layer 120 to have concave and convex portions corresponding to the initial alignment mark 101, and makes it easy for the alignment mark layer 120 to have better morphological accuracy, dimensional accuracy and positional accuracy, thereby making it easy to achieve a more ideal effect of improving the optical alignment accuracy in the subsequent graphic process.
[0075] The cover layer 140 covers the substrate 100 and the alignment mark layer 120 to provide a process basis for subsequent processes, thereby forming a semiconductor device.
[0076] The alignment mark layer 120 is located on the substrate 100 in the alignment area i and covers the initial alignment mark 101. The light transmittance of the alignment mark layer 120 is less than the light transmittance of the substrate 100. The cover layer 140 is located on the substrate 100 and the alignment mark layer 120. The light transmittance of the cover layer 140 is greater than the light transmittance of the alignment mark layer 120. Since the light transmittance of the alignment mark layer 120 is less than the light transmittance of the substrate 100 and the cover layer 140, the alignment mark layer 120 located between the cover layer 140 and the substrate 100 can be identified through the cover layer 140, and the size accuracy, shape accuracy and position accuracy of the alignment mark layer 120 are not affected by the thickness of the cover layer 140, thereby improving the optical alignment accuracy in the subsequent patterning process, and correspondingly, it is also beneficial to make the thickness of the cover layer 140 unrestricted, thereby improving the performance of the semiconductor structure.
[0077] In this embodiment, the material of the cover layer 140 includes one or more of silicon, germanium, silicon germanium, silicon carbide and gallium arsenide.
[0078] Silicon, germanium, silicon germanium, silicon carbide or gallium arsenide has good light transmittance, which can easily make the light transmittance of the cover layer 140 greater than the light transmittance of the alignment mark layer 120, so that in the subsequent graphic process, it is easy for light to pass through the cover layer 140 to identify the alignment mark layer 120 located between the cover layer 140 and the substrate 100.
[0079] In this embodiment, the material of the covering layer 140 is the same as that of the substrate 100 .
[0080] The material of the cover layer 140 is the same as that of the substrate 100 , which is beneficial to improving process compatibility.
[0081] It should be noted that the cover layer 140 can be formed by an epitaxial growth process, which is conducive to improving the formation quality of the cover layer 140 and reducing defects in the cover layer 140, thereby improving the performance of the semiconductor structure. Accordingly, the material of the cover layer 140 is the same as that of the substrate 100.
[0082] As an example, the material of the substrate 100 is silicon. Accordingly, the material of the cover layer 140 is also silicon.
[0083] As an example, the substrate 100 is used as the bottom substrate, and the cover layer 140 is used as the top substrate to form a semiconductor device. In other embodiments, the cover layer can also be other film layers required for preparing semiconductor devices (such as other semiconductor layers or dielectric layers, etc.).
[0084] Correspondingly, the present invention also provides a method for forming a semiconductor structure. Figures 6 to 11 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.
[0085] refer to Figure 6 to Figure 7 , a substrate 500 is provided, the substrate 500 includes an alignment area I, and an initial alignment mark 501 is formed in the substrate 500 in the alignment area I.
[0086] The substrate 500 is used to provide a process platform for subsequent process steps.
[0087] In this embodiment, the material of the substrate 500 includes one or more of silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, indium gallium, silicon on insulator, and germanium on insulator.
[0088] Silicon, silicon germanium, silicon carbide, gallium arsenide, indium gallium, silicon on insulator and germanium on insulator have good transmittance, which can easily make the transmittance of the subsequently formed alignment mark layer lower than the transmittance of the substrate 500, so that in the subsequent patterning process, the relevant patterning equipment can recognize the alignment mark layer.
[0089] As an example, the material of the substrate 500 is silicon. Silicon substrate is a commonly used material in semiconductor processes, has a low cost, and is conducive to reducing process costs and process difficulty.
[0090] The alignment area I is used to provide a process platform for subsequently forming an alignment mark layer.
[0091] In this embodiment, in the step of providing the substrate 500 , the substrate 500 includes a plurality of alignment areas I that are separately arranged.
[0092] The substrate 500 includes a plurality of discretely arranged alignment areas I, so as to facilitate the subsequent formation of a plurality of mutually discrete alignment mark layers.
[0093] As an example, only one alignment area I is shown here.
[0094] In this embodiment, the substrate 500 further includes a device region (not labeled).
[0095] The device region is used to form various semiconductor devices (eg, source, drain, gate, etc.).
[0096] In other embodiments, the substrate 500 may further include other regions.
[0097] The initial alignment mark 501 is used to provide a process basis for subsequently forming an alignment mark layer.
[0098] In this embodiment, in the step of providing the substrate 500 , a groove 502 is formed in the substrate 500 in the alignment area I, for providing an uneven initial alignment mark 501 .
[0099] The groove 502 and the substrate 500 outside the groove 502 are used together to form an uneven initial alignment mark 501 .
[0100] Specifically, in the step of providing the substrate 500 , an etching stop layer 510 is formed on the top of the substrate 500 outside the groove 502 .
[0101] In this embodiment, the step of forming the groove 502 in the substrate 500 in the alignment area I includes: forming an etch stop layer 510 and a first photolithography mask layer (not shown) covering the etch stop layer 510 on the substrate 500; taking the etch stop layer 510 as a stop position, patterning the first photolithography mask layer, and forming a mask opening (not shown) in the first photolithography mask layer, wherein the mask opening is located above the substrate 500 in the alignment area I and exposes the top of the etch stop layer 510; taking the first photolithography mask layer as a mask, removing the etch stop layer 510 at the bottom of the mask opening and a portion of the thickness of the substrate 500 along the mask opening to form the groove 502 (as shown in FIG. 1 ). Figure 6 After forming the groove 502, the etching stop layer 510 is removed (as shown in Figure 7The process of removing the etch stop layer 510 includes a wet etching process, a dry etching process, a chemical mechanical polishing process, etc. The etch stop layer 510 can improve the size accuracy, shape accuracy and position accuracy of the groove 502 during the formation of the groove 502.
[0102] Moreover, the material of the first photolithography mask layer is generally an organic material, and the first photolithography mask layer is formed on the etch stop layer 510, which is beneficial to reduce the probability of the substrate 500 being damaged during the formation of the first photolithography mask layer.
[0103] More specifically, the material of the etch stop layer 510 includes silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, fluorine-doped silicon glass (FSG), titanium dioxide, etc. As an example, the material of the etch stop layer 510 includes silicon oxide.
[0104] It should be noted that the depth of the groove 502 should not be too large along the normal direction of the top surface of the substrate 500. If the depth H of the groove 502 is too large, it is easy to make the process of forming the groove 502 more difficult, and it is also easy to increase the difficulty of subsequently forming an alignment mark layer in the groove 502. Therefore, in this embodiment, along the normal direction of the top surface of the substrate 500, the depth H of the groove 502 is less than or equal to 770 microns.
[0105] It should also be noted that the opening size W of the groove 502 should not be too large. If the opening size W of the groove 502 is too large, the lateral size of the initial alignment mark 501 is likely to be too large, and the area of the alignment region I is likely to be too large, thereby making the area of the semiconductor structure too large. Therefore, in this embodiment, the opening size W of the groove 502 is less than or equal to 300 mm.
[0106] The lateral direction refers to a direction perpendicular to the side wall of the groove 502 .
[0107] In this embodiment, after the step of providing the substrate 500 and before forming the alignment mark layer, the forming method further includes: performing ion doping on the substrate 500 to change the resistance value of the substrate 500 .
[0108] The substrate 500 is subjected to an ion doping process to change the resistance value of the substrate 500 so that the resistance value of the substrate 500 meets the process requirements.
[0109] Specifically, the doping ions of the ion doping process include nitrogen ions, phosphorus ions, fluorine ions, boron ions, boron fluoride ions, arsenic ions, antimony ions, indium ions, carbon ions, germanium ions, and the like.
[0110] refer to Figures 8 to 10 , an alignment mark layer 520 covering the initial alignment mark 501 is formed on the substrate 500 in the alignment area I, and the light transmittance of the alignment mark layer 520 is lower than the light transmittance of the substrate 500.
[0111] The alignment mark layer 520 is used for optical alignment in a subsequent patterning process.
[0112] The light transmittance of the alignment mark layer 520 is lower than the light transmittance of the substrate 500 , so that the alignment mark layer 520 can be identified by the relevant equipment of optical alignment, and thus used for optical alignment in the subsequent patterning process.
[0113] It should be noted that, compared with the solution of using a cover layer to provide the alignment mark, by additionally providing the alignment mark layer 520 , the thickness or material of the alignment mark layer 520 can be adjusted separately to meet the requirements of optical alignment.
[0114] It should also be noted that the thickness of the alignment mark layer 520 should not be too large along the normal direction of the top surface of the substrate 500. If the thickness of the alignment mark layer 520 is too large, it is easy to increase the difficulty of the process of forming the alignment mark layer 520, which is easy to make the alignment mark layer 520 have poor morphological accuracy and dimensional accuracy, and it is also easy to make the alignment mark layer 520 not work well as an alignment mark in the subsequent patterning process, so that the effect of improving the optical alignment accuracy in the subsequent patterning process is not ideal. Therefore, in this embodiment, along the normal direction of the top surface of the substrate 500, the thickness of the alignment mark layer 520 ranges from less than or equal to 770 microns.
[0115] It should also be noted that the material of the alignment mark layer 520 includes one or more of silicon oxide, silicon nitride, silicon oxynitride and silicon carbide.
[0116] Silicon oxide, silicon nitride, silicon oxynitride and silicon carbide are commonly used materials in semiconductor processes, which are easy to obtain and have low process costs. In addition, silicon oxide, silicon nitride, silicon oxynitride and silicon carbide have low light transmittance, which can easily make the transmittance of the alignment mark layer 520 lower than the transmittance of the substrate 500, and also easily make the transmittance of the alignment mark layer 520 lower than the transmittance of the subsequently formed covering layer. Correspondingly, it is also easy to make the reflectivity of the alignment mark layer 520 better, thereby making it easier for related equipment to identify the alignment mark layer.
[0117] In this embodiment, the step of forming the alignment mark layer 520 includes: forming an alignment mark material layer 521 (eg, Figure 8 Remove the alignment mark material layer 521 located outside the alignment area I, and the remaining alignment mark material layer 521 located in the alignment area I is used as the alignment mark layer 520 (as shown); Figures 9 and 10 shown).
[0118] An alignment mark material layer 521 is first formed on the substrate 500, and then the alignment mark material layer 521 located in the remaining positions outside the alignment area I is removed. The remaining alignment mark material layer 521 located in the alignment area I is used as the alignment mark layer 520, which is beneficial to reducing the process difficulty of forming the alignment mark layer 520 and improving the formation quality of the alignment mark layer 520.
[0119] Specifically in this embodiment, the alignment mark material layer 521 conformally covers the bottom and sidewalls of the groove 502 and the top of the substrate 500 outside the groove.
[0120] It should be noted that the process of forming the alignment mark material layer 521 includes one or more of a chemical vapor deposition process, an atomic layer deposition process and a physical vapor deposition process.
[0121] The chemical vapor deposition process has high process compatibility and low process cost. The atomic layer deposition process includes multiple atomic layer deposition cycles, so the step coverage of the atomic layer deposition process is good. The physical vapor deposition process has a simple process, low pollution, and dense film formation. The process of forming the alignment mark material layer 521 includes one or more of the chemical vapor deposition process, the atomic layer deposition process, and the physical vapor deposition process, which is conducive to improving the compatibility with the existing process.
[0122] Specifically, the step of removing the alignment mark material layer 521 at the remaining positions outside the alignment area I includes: forming a patterned mask layer 530 on the substrate 500, the mask layer 530 covering the alignment mark material layer 521 at the alignment area I and exposing the alignment mark material layer 521 at the remaining positions outside the alignment area I (such as Fig. 9 ); removing the alignment mark material layer 521 exposed by the mask layer 530 (as shown); Fig.10 shown).
[0123] In the process of removing the alignment mark material layer 521 in the remaining positions outside the alignment area I, the mask layer 530 serves as an etching mask, which is beneficial to reduce the probability of damage to the alignment mark material layer 521 in the alignment area I, thereby helping to improve the morphological accuracy, dimensional accuracy and positional accuracy of the alignment mark layer 520, and further helping to improve the optical alignment accuracy in the subsequent graphic process.
[0124] More specifically, the process of removing the alignment mark material layer 521 at the remaining positions outside the alignment region I includes one or both of a dry etching process and a wet etching process.
[0125] The dry etching process has the advantages of high etching rate, good etching directionality, strong process controllability, etc. The cost of the wet etching process is relatively low, the operation steps are simple, and a large etching selectivity ratio can be achieved. The process of removing the alignment mark material layer 521 located at the remaining positions outside the alignment area I includes one or both of the dry etching process and the wet etching process, which is conducive to improving the compatibility with the existing process.
[0126] In this embodiment, after removing the alignment mark material layer 521 exposed by the mask layer 530 , the method further includes: removing the mask layer 530 .
[0127] In this embodiment, in the step of forming the alignment mark layer 520 , a plurality of mutually separate alignment mark layers 520 are formed.
[0128] Forming a plurality of mutually separate alignment mark layers 520 is beneficial to improving the reliability of the alignment mark layer 520 .
[0129] In this embodiment, in the step of forming the alignment mark layer 520 , the alignment mark layer 520 conformally covers the initial alignment mark 501 .
[0130] The alignment mark layer 520 conformally covers the initial alignment mark 501, that is, the morphology, size and position of the alignment mark layer 520 are associated with the morphology, size and position of the initial alignment mark 501. In other words, by making the alignment mark layer 520 conformally cover the initial alignment mark 501, it is easy to transfer the morphology of the initial alignment mark 501 to the alignment mark layer 520, so that the alignment mark layer 520 is easy to be recognized by related equipment, and the morphology, size and position of the alignment mark layer 520 are easy to control, which is beneficial to improve the optical alignment accuracy in the subsequent graphic process.
[0131] Specifically, in the step of providing the substrate 500, a groove 502 is formed in the substrate 500 of the alignment area I, for providing an uneven initial alignment mark 501. Accordingly, in the step of forming the alignment mark layer 520, the alignment mark layer 520 conformally covers the groove 502 of the initial alignment mark 501 and the substrate 500 of the alignment area I outside the groove 502.
[0132] The alignment mark layer 520 conformally covers the groove 502 of the initial alignment mark 501 and the substrate 500 of the alignment area I outside the groove 502, which makes it easy for the alignment mark layer 520 to have concave and convex portions corresponding to the initial alignment mark 501, and makes it easy for the alignment mark layer 520 to have better morphological accuracy, dimensional accuracy and positional accuracy, thereby making it easy to achieve a more ideal effect of improving the optical alignment accuracy in the subsequent graphic process.
[0133] refer to Fig.11, a cover layer 540 is formed on the substrate 500 and the alignment mark layer 520 , and the light transmittance of the cover layer 540 is greater than the light transmittance of the alignment mark layer 520 .
[0134] The cover layer 540 covers the substrate 500 and the alignment mark layer 520 to provide a process basis for subsequent processes, thereby forming a semiconductor device.
[0135] First, an alignment mark layer 520 covering the initial alignment mark 501 is formed on the substrate 500 in the alignment area, and the light transmittance of the alignment mark layer 520 is less than the light transmittance of the substrate 500. Then, a cover layer 540 is formed on the substrate 500 and the alignment mark layer 520, and the light transmittance of the cover layer 540 is greater than the light transmittance of the alignment mark layer 520. Since the light transmittance of the alignment mark layer 520 is less than the light transmittance of the substrate 500 and the cover layer 540, the alignment mark layer 520 located between the cover layer 540 and the substrate 500 can be identified through the cover layer 540, and the size accuracy, shape accuracy and position accuracy of the alignment mark layer 520 are not affected by the thickness of the cover layer 540, thereby improving the optical alignment accuracy in the subsequent patterning process, and correspondingly, it is also beneficial to make the thickness of the cover layer 540 unrestricted, thereby improving the performance of the semiconductor structure.
[0136] In this embodiment, the process of forming the cover layer 540 includes an epitaxial growth process. In other implementations, the process of forming the cover layer 540 may also include a deposition process, a bonding process, or a mixed crystal orientation process.
[0137] The epitaxial growth process has the advantages of simple process, fast growth, low cost, easy process control and industrial mass production, which is beneficial to improving the formation quality of the cover layer 540, thereby improving the performance of semiconductor devices subsequently formed on the cover layer 540.
[0138] In this embodiment, the material of the cover layer 540 includes one or more of silicon, germanium, silicon germanium, silicon carbide and gallium arsenide.
[0139] Silicon, germanium, silicon germanium, silicon carbide and gallium arsenide have good light transmittance, which can easily make the transmittance of the covering layer 540 greater than the transmittance of the alignment mark layer 520, so that in the subsequent graphic process, it is easy for light to pass through the covering layer 540 to identify the alignment mark layer 520 located between the covering layer 540 and the substrate 500.
[0140] In this embodiment, in the step of forming the covering layer 540 , the material of the covering layer 540 is the same as that of the substrate 500 .
[0141] The material of the cover layer 540 is the same as that of the substrate 500 , which is beneficial to improving process compatibility.
[0142] Specifically, the process of forming the cover layer 540 includes an epitaxial growth process. Accordingly, in the step of forming the cover layer 540 , the material of the cover layer 540 is the same as that of the substrate 500 .
[0143] The cover layer 540 is formed by an epitaxial growth process, and the material of the cover layer 540 is the same as that of the substrate 500, which is beneficial to improving the formation quality of the cover layer 540 and reducing defects in the cover layer 540, thereby improving the performance of the semiconductor structure.
[0144] As an example, the material of the substrate 500 is silicon. Accordingly, the material of the cover layer 540 is also silicon.
[0145] As an example, the substrate 500 is used as the bottom substrate, and the cover layer 540 is used as the top substrate to form a semiconductor device. In other embodiments, the cover layer can also be other film layers required for preparing semiconductor devices (such as other semiconductor layers or dielectric layers, etc.).
[0146] Continue to refer Fig.11 After forming the cover layer 540 , the forming method further includes: forming a second photolithography mask layer 550 on the cover layer 540 .
[0147] The second photolithography mask layer 550 is used as an etching mask in the subsequent patterning process. As an example, the material of the second photolithography mask layer 550 is photoresist.
[0148] It should be noted that the semiconductor structure of the above embodiment can be formed by the formation method described in the above embodiment, or by other formation methods. For the specific description of the semiconductor structure of this embodiment, reference can be made to the relevant description of the formation method.
[0149] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.
Claims
1. A semiconductor structure, characterized in that: include: a substrate, the substrate comprising an alignment region, an initial alignment mark being formed in the substrate of the alignment region; an alignment mark layer, located on the substrate in the alignment area and covering the initial alignment mark, wherein the light transmittance of the alignment mark layer is less than the light transmittance of the substrate; The covering layer is located on the substrate and the alignment mark layer, and the light transmittance of the covering layer is greater than the light transmittance of the alignment mark layer.
2. The semiconductor structure according to claim 1, wherein: A groove is formed in the base of the alignment area to provide the uneven initial alignment mark.
3. The semiconductor structure according to claim 2, wherein: Along the normal direction of the top surface of the substrate, the depth of the groove is less than or equal to 770 micrometers.
4. The semiconductor structure according to claim 2, wherein: The opening size of the groove is less than or equal to 300 mm.
5. The semiconductor structure according to claim 1 or 2, characterized in that: The alignment mark layer conformally covers the initial alignment mark.
6. The semiconductor structure according to claim 1, wherein: Along the normal direction of the top surface of the substrate, the thickness of the alignment mark layer is less than or equal to 770 micrometers.
7. The semiconductor structure according to claim 1, wherein: The material of the alignment mark layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride and silicon carbide.
8. The semiconductor structure according to claim 1, wherein: The substrate comprises a plurality of discretely arranged alignment areas; the number of the alignment mark layers is multiple, and each alignment mark layer is discrete from each other.
9. The semiconductor structure according to claim 1, wherein: The material of the substrate includes one or more of silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, indium gallium, silicon on insulator and germanium on insulator.
10. The semiconductor structure according to claim 1, wherein: The material of the cover layer includes one or more of silicon, germanium, silicon germanium, silicon carbide and gallium arsenide.
11. The semiconductor structure according to claim 1, wherein: The material of the cover layer is the same as that of the substrate.
12. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising an alignment area, an initial alignment mark formed in the substrate of the alignment area; forming an alignment mark layer covering the initial alignment mark on the substrate in the alignment area, wherein the light transmittance of the alignment mark layer is less than the light transmittance of the substrate; A cover layer is formed on the substrate and the alignment mark layer, wherein the light transmittance of the cover layer is greater than the light transmittance of the alignment mark layer.
13. The method for forming a semiconductor structure according to claim 12, wherein: The step of forming the alignment mark layer comprises: forming an alignment mark material layer on the substrate; The alignment mark material layer at the remaining positions outside the alignment area is removed, and the remaining alignment mark material layer at the alignment area is used as the alignment mark layer.
14. The method for forming a semiconductor structure according to claim 13, wherein: The step of removing the alignment mark material layer at the remaining positions outside the alignment area comprises: Forming a patterned mask layer on the substrate, wherein the mask layer covers the alignment mark material layer in the alignment area and exposes the alignment mark material layer in other locations outside the alignment area; The alignment mark material layer exposed by the mask layer is removed.
15. The method for forming a semiconductor structure according to claim 13, wherein: The process of forming the alignment mark material layer includes one or more of a chemical vapor deposition process, an atomic layer deposition process and a physical vapor deposition process.
16. The method for forming a semiconductor structure according to claim 13, wherein: The process of removing the alignment mark material layer at the remaining positions outside the alignment area includes one or both of a dry etching process and a wet etching process.
17. The method for forming a semiconductor structure according to claim 12, wherein: In the step of providing a substrate, a groove is formed in the substrate of the alignment area to provide the uneven initial alignment mark.
18. The method for forming a semiconductor structure according to claim 12 or 17, wherein: In the step of forming the alignment mark layer, the alignment mark layer conformally covers the initial alignment mark.
19. The method for forming a semiconductor structure according to claim 12, wherein: In the step of providing a substrate, the substrate includes a plurality of discretely disposed alignment regions; In the step of forming the alignment mark layer, a plurality of mutually separate alignment mark layers are formed.
20. The method for forming a semiconductor structure according to claim 12, wherein: In the step of forming the cover layer, a material of the cover layer is the same as a material of the substrate.