A packaged chip and a signal testing method and system based on the packaged chip

Abstract

A packaged chip and a signal testing method and system based on the packaged chip, involving a packaged chip, including: a first packaging structure and a radio frequency packaging structure arranged above the first packaging structure; the first packaging structure includes a first chip arranged on a bottom substrate, and an operational amplifier chipset, a communication interface chip and a data storage chip are arranged around the first chip; a second chip and a third chip stacked in sequence are arranged on the upper layer of the first chip; the operational amplifier chipset includes an operational amplifier chip, an analog switch and a resistor and capacitor device, and is arranged adjacent to the communication interface chip and the data storage chip. The present application integrates an operational amplifier circuit for signal processing on the bottom substrate, and only needs to provide a power supply and a test interface to realize signal testing and signal conversion output; the stacked structure design has a higher degree of integration and a smaller packaging volume; it can match radio frequency chips of different specifications, and the radio frequency circuit is isolated from other circuits, which can avoid interference from radio frequency signals and reduce system noise.

Description

Technical Field

[0001] The present invention belongs to the technical field of chip packaging, and in particular relates to a packaged chip and a signal testing method and system based on the packaged chip. Background Art

[0002] With the development of electronic technology, electronic products are becoming more and more miniaturized and integrated, while the board-level signal processing system can no longer meet the needs of electronic products towards miniaturization. System-in-package technology (SIP) is to encapsulate bare cores and passive devices with multiple functions in a single package to form an independent packaged chip with specific functions, which is the miniaturization of board-level systems. SIP technology can help products reduce size and power consumption, while traditional signal acquisition and processing devices are costly and bulky, and the complex system design of multiple chips makes it difficult to achieve the goal of small-volume product design.

[0003] Most of the existing packaged chips only integrate ADC chips, DAC chips, storage chips and core processing chips for signal conversion, and also require additional peripheral signal processing circuits to process the signals, making it difficult to achieve true integration. Summary of the invention

[0004] The present application integrates an operational amplifier circuit for signal processing on the bottom substrate, and only needs to provide power supply and test interface to realize signal testing and signal conversion output; the stacked structure design has higher integration and smaller packaging volume; it can match RF chips of different specifications, and the RF circuit is electrically isolated from other circuits, which can avoid interference from RF signals and reduce noise in the test system.

[0005] Other purposes and advantages of the present invention can be further understood from the technical features disclosed in the present invention.

[0006] In order to achieve one, part or all of the above purposes or other purposes, the present invention provides a packaged chip and a signal testing method and system based on the packaged chip.

[0007] A packaged chip, comprising:

[0008] A first packaging structure and a radio frequency packaging structure disposed thereon, wherein the first packaging structure and the radio frequency packaging structure are welded by solder balls;

[0009] The first packaging structure includes a first chip disposed on a bottom substrate, an operational amplifier chipset disposed around the first chip, and a communication interface chip and a data storage chip disposed adjacent to the operational amplifier chipset;

[0010] A second chip and a third chip stacked in sequence are arranged on the upper layer of the first chip;

[0011] The operational amplifier chipset comprises a first operational amplifier chip, a second operational amplifier chip, an analog switch and a resistor and capacitor device.

[0012] The first operational amplifier chip and the second operational amplifier chip are operational amplifiers of different types;

[0013] The first operational amplifier chip is laid flat on the bottom substrate through a wire bonding process;

[0014] The resistor and capacitor components are welded on the bottom substrate by surface mounting technology;

[0015] The second operational amplifier chip and the analog switch are reversely soldered on the bottom substrate through a rewiring process.

[0016] The resistor and capacitor components are arranged around the operational amplifier chip and the analog switch.

[0017] The second chip is disposed above the first chip through a supporting assembly and connected to the bottom substrate through a wire bonding process;

[0018] A transfer layer is provided between the second chip and the third chip, the third chip is wire-bonded to the transfer layer, and the transfer layer is wire-bonded to the bottom substrate.

[0019] The transfer layer includes a transfer substrate, and a plurality of pads are arranged on the periphery of the transfer substrate;

[0020] The third chip is wire-bonded to the transfer substrate, and the transfer substrate is wire-bonded to the base substrate via the pads.

[0021] The third chip does not completely cover the transfer substrate, and there is a gap between the third chip and the pads on the periphery of the transfer substrate.

[0022] The supporting component is a gasket, the first chip is 1 / 2 to 2 / 3 of the height of the gasket, and there is a distance between the gasket and the first chip.

[0023] The first packaging structure further includes a first plastic packaging layer, which is located on the upper side of the bottom substrate and plasticizes the chip on the upper side of the bottom substrate and the space not occupied by the chip, and there is a distance between the first plastic packaging layer and the RF packaging structure;

[0024] A plurality of solder balls are evenly arranged on the periphery of the upper surface of the bottom substrate, and through holes are formed in the first plastic sealing layer corresponding to the positions of the solder balls on the upper surface of the bottom substrate by a laser perforation process, and the through holes expose the solder balls on the upper surface of the bottom substrate;

[0025] The height of the solder ball is lower than the height of the first plastic packaging layer.

[0026] The RF packaging structure includes a RF substrate and a RF chip located on the RF substrate;

[0027] The RF chip is arranged in the middle of the upper surface of the RF substrate, and a plurality of solder balls are evenly arranged on the periphery of the lower surface of the RF substrate;

[0028] The solder balls on the lower surface of the RF substrate are soldered to the solder balls on the upper surface of the bottom substrate exposed by the first packaging structure through an SMT soldering process;

[0029] The solder balls on the lower surface of the RF substrate and the solder balls on the upper surface of the bottom substrate exposed by the first packaging structure are soldered by a reflow soldering process.

[0030] The radio frequency packaging structure includes a radio frequency chip;

[0031] The radio frequency chip is soldered to the solder balls on the upper surface of the bottom substrate exposed by the first packaging structure through a plurality of solder balls of the same size.

[0032] A plurality of solder balls are evenly distributed on the lower surface of the bottom substrate for connecting an external power supply interface and an IO signal interface.

[0033] A signal testing method based on a packaged chip, comprising:

[0034] The radio frequency chip inputs a first analog signal to an input signal processing circuit;

[0035] The input signal processing circuit collects the first analog signal, performs filtering, shaping and amplification processing on the first analog signal to generate a first single-ended signal; the first operational amplifier chip converts the first single-ended signal into a first differential signal;

[0036] The analog-to-digital / digital-to-analog conversion module processes the first differential signal to generate a second differential signal, and transmits the second differential signal to the output signal processing circuit;

[0037] The output signal processing circuit processes the second differential signal to generate a second single-ended signal and transmits the second single-ended signal to the radio frequency chip.

[0038] The input signal processing circuit comprises:

[0039] A high-pass filter, wherein the high-pass filter is formed by connecting a second operational amplifier chip, an analog switch, and a plurality of resistor and capacitor components;

[0040] A low-pass filter, wherein the low-pass filter is formed by connecting a second operational amplifier chip, an analog switch, and a plurality of resistor and capacitor components;

[0041] The high-pass filter and the low-pass filter are used to filter out signals with different bandwidths;

[0042] And, a three-stage operational amplifier circuit, which is composed of three second operational amplifier chips, analog switches and a plurality of resistor and capacitor devices connected in sequence, and amplifies the signal.

[0043] The analog-to-digital / digital-to-analog conversion module comprises:

[0044] a first chip, wherein the first chip converts the first differential signal into a digital signal;

[0045] a second chip, wherein the second chip processes the converted digital signal through an algorithm;

[0046] A third chip converts the processed digital signal into the second differential signal and outputs the second differential signal to the output signal processing circuit.

[0047] The output signal processing circuit comprises:

[0048] A differential input amplifier circuit composed of the second operational amplifier chip and a plurality of resistor and capacitor components;

[0049] The differential input amplifier circuit converts the received second differential signal into a second single-ended signal, transmits the second single-ended signal to the emitter follower circuit, and outputs the second single-ended signal to the radio frequency circuit of the radio frequency chip.

[0050] A signal testing system based on a packaged chip, comprising:

[0051] Package chips and test boards;

[0052] The test board includes a packaged chip test base, an IO connector, a USB connector, a power supply circuit and a decoupling capacitor;

[0053] The packaged chip test base is used to carry the packaged chip and perform signal testing on the packaged chip;

[0054] The IO connector is electrically connected to the solder balls on the lower surface of the bottom substrate of the packaged chip, and the IO test signal of the packaged chip is transmitted to the logic analyzer, and the signal is analyzed by the logic analyzer;

[0055] The USB connector is connected to the host computer and the communication interface chip, transmits the commands of the host computer and monitors the signal acquisition of the packaged chip in real time;

[0056] The power supply circuit supplies power to the packaged chip through a power supply interface.

[0057] Compared with the prior art, the beneficial effects of the present invention mainly include:

[0058] 1. The present application integrates an operational amplifier circuit for processing signals on the bottom substrate, and only needs to provide power supply and test interface to realize signal testing and signal conversion output;

[0059] 2. This application adopts a stacked structure design with higher integration and smaller packaging volume;

[0060] 3. The radio frequency circuit of the present application is electrically isolated from other circuits, which can avoid interference from radio frequency signals and reduce noise in the test system.

[0061] In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] In order to more clearly illustrate the technical solutions in the specific embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0063] Figure 1 This is a side view of the packaged chip provided in Example 1 of the present application.

[0064] Figure 2 This is a top view of the packaged chip provided in Example 1 of the present application.

[0065] Figure 3 A side view of the packaged chip provided in Example 2 of the present application.

[0066] Figure 4 This is a schematic diagram of the input signal processing circuit provided in Example 3 of the present application.

[0067] Figure 5 This is a schematic diagram of the output signal processing circuit provided in Example 3 of the present application.

[0068] Figure 6 Schematic diagram of the test system provided in Example 4 of the present application. DETAILED DESCRIPTION

[0069] The above and other technical contents, features and effects of the present invention will be clearly presented in the following detailed description of a preferred embodiment with reference to the drawings. The directional terms mentioned in the following embodiments, such as up, down, left, right, front or back, etc., are only referenced to the directions of the attached drawings. Therefore, the directional terms used are used to illustrate and not to limit the present invention.

[0070] The present application integrates an operational amplifier circuit for signal processing on the bottom substrate, and only needs to provide power supply and test interface to realize signal testing and signal conversion output; the stacked structure design has higher integration and smaller packaging volume; it can match RF chips of different specifications, and the RF circuit is electrically isolated from other circuits, which can avoid interference from RF signals and reduce noise in the test system.

[0071] The following will describe the various embodiments of the present application in detail with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the various embodiments of the present application, many technical details are provided in order to enable the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solution claimed in the present application can be implemented.

[0072] Figure 1 Shown is a side view of the packaged chip provided in Example 1 of the present application.

[0073] like Figure 1 As shown, a packaged chip includes:

[0074] A first packaging structure 1 and a radio frequency packaging structure 2 arranged thereon, wherein the first packaging structure 1 and the radio frequency packaging structure 2 are welded by solder balls;

[0075] The first packaging structure 1 includes a first chip 11 disposed on a bottom substrate, an operational amplifier chipset 12 disposed around the first chip 11, and a communication interface chip 13 and a data storage chip 14 disposed adjacent to the operational amplifier chipset 12;

[0076] The first chip 11 is provided with a second chip 111 and a third chip 112 stacked in sequence on the upper layer;

[0077] The operational amplifier chipset 12 includes a first operational amplifier chip 121 , a second operational amplifier chip 122 , an analog switch 123 , and a resistor and capacitor device 124 .

[0078] Figure 2 Shown is a top view of the packaged chip provided in Example 1 of the present application.

[0079] like Figure 2 As shown, the first operational amplifier chip 121 and the second operational amplifier chip 122 are operational amplifiers of different types; wherein the first operational amplifier chip 121 is laid flat on the bottom substrate 3 by a wire bonding process; the resistor and capacitor device 124 is welded on the bottom substrate by an SMT process; the second operational amplifier chip 122 and the analog switch 123 are reversely welded on the bottom substrate 3 by a rewiring process; the resistor and capacitor device 124 is arranged around the first operational amplifier chip 121, the second operational amplifier chip 122 and the analog switch 123.

[0080] like Figure 1As shown, the second chip 111 is arranged above the first chip 11 through the supporting component 4, and is connected to the bottom substrate 3 through the wire bonding process; since the third chip 112 is smaller than the second chip 111 and the size difference is large, it cannot be directly wire bonded to the bottom substrate 3 (the bonding wire is too long and will collapse), and a transfer layer needs to be arranged between the second chip 111 and the third chip 112, the third chip 112 is wire bonded to the transfer layer, and the transfer layer is wire bonded to the bottom substrate 3.

[0081] Specifically, the transfer layer includes a transfer substrate 5, and a plurality of pads 51 are arranged on the periphery of the transfer substrate 5; the third chip 112 is wire-bonded to the transfer substrate 5, and the transfer substrate 5 is wire-bonded to the bottom substrate 3 through the pads 51; the transfer substrate 5 provides physical support for the upper chip, thereby reducing the design size of the chip.

[0082] Among them, the third chip 112 does not completely cover the adapter substrate 5, and there is a distance between it and the pad 51 on the periphery of the adapter substrate 5; the supporting component 4 is a gasket, the first chip 11 is 1 / 2 to 2 / 3 of the height of the gasket, and there is a distance between the gasket and the first chip 11.

[0083] As a preferred embodiment of the present invention, the first chip 11 of this embodiment is an ADC chip, the second chip 111 is a 9mm*9mm FPGA chip, the communication interface chip 13 is an RS422 chip, the data storage chip 14 is a FLASH chip, the bottom substrate 3 has a size of 17mm*17mm, the adapter substrate 5 has a size of 8mm*8mm, and the third chip 112 is a 4.29*3.08 DAC chip.

[0084] The first packaging structure further includes a first plastic packaging layer, which is located on the upper side of the bottom substrate 3 and plasticizes the chip on the upper side of the bottom substrate 3 and the space not occupied by the chip, and there is a distance between the first plastic packaging layer and the RF packaging structure 2;

[0085] A plurality of solder balls are evenly distributed around the upper surface of the bottom substrate 3 , and through holes are formed in the first plastic packaging layer corresponding to the positions of the solder balls on the upper surface of the bottom substrate 3 by a laser perforation process, and the through holes expose the solder balls on the upper surface of the bottom substrate 3 .

[0086] Specifically, Figure 1 As shown, the RF packaging structure includes an RF substrate 21, and an RF chip 22 located on the RF substrate 21; the RF chip 22 is arranged in the middle of the upper surface of the RF substrate 21, and a plurality of solder balls are evenly distributed on the periphery of the lower surface of the RF substrate 21; the solder balls on the lower surface of the RF substrate 21 and the solder balls on the upper surface of the bottom substrate 3 exposed by the first packaging structure 1 are welded through a reflow soldering process.

[0087] In addition, a plurality of solder balls are evenly distributed on the lower surface of the bottom substrate 3 for connecting an external power supply interface and an IO signal interface.

[0088] As a preferred embodiment of the present invention, this embodiment exposes the external signal in the upper part of the first packaging structure 1 through the molding laser packaging technology, which can match the RF chips 22 of different specifications, thereby increasing the packaging flexibility of the first packaging structure 1. In addition, the stacking scheme of the first packaging structure 1 allows the circuit of the RF chip 22 to be electrically isolated from other circuits, thereby avoiding the interference of RF signals on other electrical signals and reducing the noise of the test system.

[0089] As a preferred embodiment of the present invention, the second chip 111 of this embodiment is an FPGA chip, which adopts the cost-effective EQ6HL45 chip based on the 40nm CMOS process of Zhongke Yihaiwei, with an effective gate capacity of 4.25 million gates, supporting multiple configuration modes such as active serial / parallel, passive serial / parallel, JTAG, SPI, etc.; the first chip 11 is an ADC chip, and the high-speed 14-bit ADC adopts MT4449 that maintains excellent AC performance at high-frequency input, with a sampling rate of 250MHz and parallel LVDS data output; the third chip 112 is a DAC chip, and the high-speed DAC chip adopts a 16Bit 250MSPS dual-channel DACAS9747 that can synthesize high-quality bandwidth signals; the operational amplifier chips 121 and 122 adopt high-performance, low-cost voltage feedback operational amplifier MS8052; the analog switch 123 adopts a multiplexed analog switch MS713; the data storage chip 14 is a FLASH chip, which adopts the 64M capacity E25Q64; the communication interface chip 13 adopts the RS422 chip of MS2583.

[0090] As a preferred embodiment of the present invention, a BGA256 package with a pitch of 1.0 mm is used in this embodiment, and the final package size of the finished product is 17 mm*17 mm, and the package thickness is 2.0 mm, which greatly improves the miniaturization and integration of the packaged product.

[0091] Figure 3 A side view of the packaged chip provided in Example 2 of the present application.

[0092] like Figure 3 As shown, the RF packaging structure 2 includes a RF chip 22; the RF chip 22 is soldered to the solder balls on the upper surface of the bottom substrate 3 exposed by the first packaging structure 1 through a plurality of solder balls of the same size.

[0093] A signal testing method based on a packaged chip, comprising:

[0094] The RF chip 22 inputs the first analog signal to the input signal processing circuit;

[0095] The input signal processing circuit collects the first analog signal, performs filtering, shaping and amplification processing on the first analog signal to generate a first single-ended signal; the first operational amplifier chip converts the first single-ended signal into a first differential signal;

[0096] The analog-to-digital conversion module processes the first differential signal to generate a second differential signal, and transmits the second differential signal to the output signal processing circuit;

[0097] The output signal processing circuit processes the second differential signal to generate a second single-ended signal and transmits the second single-ended signal to the radio frequency chip.

[0098] Figure 4 This is a schematic diagram of the input signal processing circuit provided in Example 3 of the present application.

[0099] The input signal processing circuit includes:

[0100] A high-pass filter, wherein the high-pass filter is formed by connecting a second operational amplifier chip, an analog switch, and a plurality of resistor and capacitor components;

[0101] A low-pass filter, wherein the low-pass filter is formed by connecting a second operational amplifier chip, an analog switch, and a plurality of resistor and capacitor components;

[0102] High-pass filters and low-pass filters are used to filter out signals with different bandwidths;

[0103] And, a three-stage operational amplifier circuit, which is composed of three second operational amplifier chips, analog switches and a number of resistor and capacitor devices connected in sequence, amplifies the signal.

[0104] Specifically, Figure 4 As shown, the multi-way analog switch 1, the multi-way analog switch 2, the operational amplifier 2-1 and the peripheral resistor and capacitor components constitute a high-pass filter. By switching the analog switch, resistors with different resistance values ​​are matched, and then the cut-off frequency of the high-pass filter is adjusted. The cut-off frequency can be 500KHz, 200KHz, and 100KHz;

[0105] Multi-channel analog switch 3, multi-channel analog switch 4, op amp 2-2 and peripheral resistors and capacitors form a low-pass filter. By switching the analog switch, resistors with different resistance values ​​are matched to adjust the cutoff frequency of the low-pass filter; the cutoff frequency can be 1MHz, 5MHz, and 20MHz. The first two filters form a bandpass filter. By switching the analog switch, a total of eight filters with different bandwidths, such as 500KHz-1MHz, 500KHz-5MHz, and 500KHz-20MHz, can be formed.

[0106] The signal output by the bandpass filter is amplified by a three-stage operational amplifier circuit constructed by operational amplifiers 2-3, 2-4, 2-5 and resistors and capacitors. After being processed by the three-stage operational amplifier circuit, the signal can be amplified by up to 1000 times. The amplified signal is sent to operational amplifier 1 for single-ended to differential conversion processing.

[0107] The analog-to-digital / digital-to-analog conversion module includes:

[0108] A first chip, wherein the first chip ADC converts the first differential analog signal into an LVDS digital signal;

[0109] A second chip, the second chip processes the converted digital signal through an algorithm;

[0110] The third chip, the third chip DAC converts the processed digital signal into a second differential analog signal and outputs it to the output signal processing circuit.

[0111] Figure 5 This is a schematic diagram of the output signal processing circuit provided in Example 3 of the present application.

[0112] like Figure 5 As shown, the output signal processing circuit includes:

[0113] A differential input amplifier circuit composed of a second operational amplifier chip and a plurality of resistor and capacitor components;

[0114] The differential input amplifier circuit converts the received second differential analog signal into a second single-ended signal, which is transmitted to the emitter follower circuit to reduce the influence between the previous and next stage signals, and provides a low-impedance signal to maintain voltage stability, and then output to the RF circuit in the RF chip.

[0115] Figure 5 VREF in the figure is a fixed amplitude signal output by another DAC, that is, the other circuit is Figure 5 The reference voltage provided by the circuit is used here to mix the original signal with this fixed amplitude signal using an adding circuit to provide a DC bias for the original signal.

[0116] Figure 6 Shown is a schematic diagram of the test system provided in Example 4 of the present application.

[0117] like Figure 6 As shown, a signal testing system based on a packaged chip comprises:

[0118] Package chips and test boards;

[0119] The test board includes a packaged chip test base, an IO connector, a USB connector, a power circuit, and a decoupling capacitor;

[0120] The packaged chip test base is used to carry the packaged chip and perform signal testing on the packaged chip;

[0121] The IO connector is electrically connected to the solder ball on the lower surface of the bottom substrate of the packaged chip, and the IO test signal of the packaged chip is transmitted to the logic analyzer, and the signal is analyzed by the logic analyzer;

[0122] The USB connector connects the host computer and the communication interface chip, transmits the host computer's commands and monitors the signal acquisition of the packaged chip in real time;

[0123] The power circuit supplies power to the packaged chip through the power supply interface.

[0124] The test system of this application no longer requires peripheral configuration circuits. It only needs to power the system to complete the signal acquisition and conversion output. It has high accuracy, fast response, wide dynamic measurement range, high stability and anti-interference.

[0125] The present application integrates an operational amplifier circuit for signal processing on the bottom substrate, and only needs to provide power supply and test interface to realize signal testing and signal conversion output; the stacked structure design has higher integration and smaller packaging volume; it can match RF chips of different specifications, and the RF circuit is electrically isolated from other circuits, which can avoid interference from RF signals and reduce noise in the test system.

[0126] In order to facilitate the description, some common English nouns or letters used in the present invention are only used for exemplary reference rather than restrictive interpretation or specific usage, and the protection scope of the present invention should not be limited by their possible Chinese translations or specific letters.

[0127] It should also be noted that, in this document, relational terms such as "first" and "second" are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

Claims

1. A packaged chip, characterized in that: include: A first packaging structure and a radio frequency packaging structure disposed thereon, wherein the first packaging structure and the radio frequency packaging structure are welded by solder balls; The first packaging structure includes a first chip disposed on a bottom substrate, an operational amplifier chipset disposed around the first chip, and a communication interface chip and a data storage chip disposed adjacent to the operational amplifier chipset; A second chip and a third chip stacked in sequence are arranged on the upper layer of the first chip; The operational amplifier chipset includes a first operational amplifier chip, a second operational amplifier chip, an analog switch, and a resistor and capacitor device; The first operational amplifier chip and the second operational amplifier chip are operational amplifiers of different types; The first operational amplifier chip is laid flat on the bottom substrate through a wire bonding process; The resistor and capacitor components are welded on the bottom substrate by surface mounting technology; The second operational amplifier chip and the analog switch are reversely soldered on the bottom substrate through a rewiring process; The resistor and capacitor components are arranged around the operational amplifier chip and the analog switch.

2. A packaged chip according to claim 1, characterized in that: The second chip is disposed above the first chip through a supporting assembly and connected to the bottom substrate through a wire bonding process; A transfer layer is provided between the second chip and the third chip, the third chip is wire-bonded to the transfer layer, and the transfer layer is wire-bonded to the bottom substrate.

3. A packaged chip according to claim 2, characterized in that: The transfer layer includes a transfer substrate, and a plurality of pads are arranged on the periphery of the transfer substrate; The third chip is wire-bonded to the transfer substrate, and the transfer substrate is wire-bonded to the base substrate via the pads.

4. The packaged chip according to claim 3, characterized in that: The third chip does not completely cover the transfer substrate, and there is a distance between the third chip and the peripheral pads of the transfer substrate.

5. The packaged chip according to claim 2, characterized in that: The supporting component is a gasket, the first chip is 1 / 2 to 2 / 3 of the height of the gasket, and there is a distance between the gasket and the first chip.

6. The packaged chip according to claim 1, characterized in that: The first packaging structure further includes a first plastic packaging layer, which is located on the upper side of the bottom substrate and plasticizes the chip on the upper side of the bottom substrate and the space not occupied by the chip, and there is a distance between the first plastic packaging layer and the RF packaging structure; A plurality of solder balls are evenly arranged on the periphery of the upper surface of the bottom substrate, and through holes are formed in the first plastic sealing layer corresponding to the positions of the solder balls on the upper surface of the bottom substrate by a laser perforation process, and the through holes expose the solder balls on the upper surface of the bottom substrate; The height of the solder ball is lower than the height of the first plastic packaging layer.

7. The packaged chip according to claim 6, characterized in that: The RF packaging structure includes a RF substrate and a RF chip located on the RF substrate; The RF chip is arranged in the middle of the upper surface of the RF substrate, and a plurality of solder balls are evenly arranged on the periphery of the lower surface of the RF substrate; The solder balls on the lower surface of the RF substrate and the solder balls on the upper surface of the bottom substrate exposed by the first packaging structure are soldered by a reflow soldering process.

8. The packaged chip according to claim 6, characterized in that: The radio frequency packaging structure includes a radio frequency chip; The radio frequency chip is soldered to the solder balls on the upper surface of the bottom substrate exposed by the first packaging structure through a plurality of solder balls of the same size.

9. The packaged chip according to claim 6, characterized in that: A plurality of solder balls are evenly distributed on the lower surface of the bottom substrate for connecting an external power supply interface and an IO signal interface.

10. A signal testing method based on packaged chips, characterized in that: include: The packaged chip comprises: A first packaging structure and a radio frequency packaging structure disposed thereon, wherein the first packaging structure and the radio frequency packaging structure are welded by solder balls; The first packaging structure includes a first chip disposed on a bottom substrate, an operational amplifier chipset disposed around the first chip, and a communication interface chip and a data storage chip disposed adjacent to the operational amplifier chipset; A second chip and a third chip stacked in sequence are arranged on the upper layer of the first chip; The operational amplifier chipset includes a first operational amplifier chip, a second operational amplifier chip, an analog switch, and a resistor and capacitor device; The radio frequency packaging structure includes a radio frequency chip; The radio frequency chip inputs a first analog signal to an input signal processing circuit; The input signal processing circuit collects the first analog signal, performs filtering, shaping and amplification processing on the first analog signal to generate a first single-ended signal; the first operational amplifier chip converts the first single-ended signal into a first differential signal; The analog-to-digital / digital-to-analog conversion module processes the first differential signal to generate a second differential signal, and transmits the second differential signal to the output signal processing circuit; The output signal processing circuit processes the second differential signal to generate a second single-ended signal and transmits the second single-ended signal to the radio frequency chip.

11. The signal testing method based on packaged chip according to claim 10, characterized in that: The input signal processing circuit comprises: A high-pass filter, wherein the high-pass filter is formed by connecting a second operational amplifier chip, an analog switch, and a plurality of resistor and capacitor components; A low-pass filter, wherein the low-pass filter is formed by connecting a second operational amplifier chip, an analog switch, and a plurality of resistor and capacitor components; The high-pass filter and the low-pass filter are used to filter out signals with different bandwidths; And, a three-stage operational amplifier circuit, which is composed of three second operational amplifier chips, analog switches and a plurality of resistor and capacitor devices connected in sequence, and amplifies the signal.

12. The signal testing method based on packaged chip according to claim 10, characterized in that: The analog-to-digital / digital-to-analog conversion module comprises: a first chip, wherein the first chip converts the first differential signal into a digital signal; A second chip, the second chip processes the converted digital signal through an algorithm; a third chip, the third chip converts the processed digital signal into the second differential signal and outputs it to the output signal processing circuit.

13. The signal testing method based on packaged chip according to claim 10, characterized in that: The output signal processing circuit comprises: A differential input amplifier circuit composed of a second operational amplifier chip and a plurality of resistor and capacitor components; The differential input amplifier circuit converts the received second differential signal into a second single-ended signal, transmits the second single-ended signal to the emitter follower circuit, and outputs the second single-ended signal to the radio frequency circuit of the radio frequency chip.

14. A signal testing system based on packaged chips, characterized in that: include: Package chips and test boards; The packaged chip comprises: A first packaging structure and a radio frequency packaging structure disposed thereon, wherein the first packaging structure and the radio frequency packaging structure are welded by solder balls; The first packaging structure includes a first chip disposed on a bottom substrate, an operational amplifier chipset disposed around the first chip, and a communication interface chip and a data storage chip disposed adjacent to the operational amplifier chipset; A second chip and a third chip stacked in sequence are arranged on the upper layer of the first chip; The operational amplifier chipset includes a first operational amplifier chip, a second operational amplifier chip, an analog switch, and a resistor and capacitor device; The radio frequency packaging structure includes a radio frequency chip; The test board includes a packaged chip test base, an IO connector, a USB connector, a power supply circuit and a decoupling capacitor; The packaged chip test base is used to carry the packaged chip and perform signal testing on the packaged chip; The IO connector is electrically connected to the solder balls on the lower surface of the bottom substrate of the packaged chip, and the IO test signal of the packaged chip is transmitted to the logic analyzer, and the signal is analyzed by the logic analyzer; The USB connector is connected to a host computer and a communication interface chip, transmits commands from the host computer and monitors signal acquisition of the packaged chip in real time; The power supply circuit supplies power to the packaged chip through a power supply interface.

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