A dummy filling method for high-speed analog chips

Abstract

The present invention provides a dummy filling method for high-speed analog chips, the method comprising: testing the limit size and limit spacing of the process layer used to block the dummy filling of each metal layer; using the blocking process layer of the limit size at equal spacing of the metal layer where the dummy needs to be filled; making each blocking process layer into a blocking unit; and filling the dummy according to the limit spacing and the blocking unit. The present invention controls the filling dummy density according to each chip type, which not only meets the DRC requirements, but also reduces the additional parasitic capacitance generated by filling the dummy, which causes a significant decrease in chip performance.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a dummy filling method for a high-speed analog chip. Background Art

[0002] ‌Dummy filling‌ is a technique used in circuit design or chip manufacturing to improve the manufacturability of the design and ensure the consistency and reliability of the circuit. Specifically, dummy filling involves adding some elements that do not carry valid data to the design. These elements are usually called dummy elements or dummy structures. These elements can be metal, polysilicon, diffusion layers, etc., depending on the design requirements and manufacturing process.

[0003] In the chip manufacturing process, if the metal density in certain areas is uneven, after CMP (chemical mechanical polishing), it is very likely to cause the chip surface to dent, resulting in tape-out failure. In order to avoid this risk point, it is necessary to fill the dummy in the low-density area of ​​the layout to improve the overall flatness, thereby achieving the effect of improving the yield. There will also be checks on density in DRCrule. Density that is too low or too high is not allowed. Especially at advanced process nodes, the density requirements have become extremely stringent. At present, the existing technology uses the filler rule provided by the foundary to fill the dummy. However, this rule does not have an option for the density of filling the dummy, and it is almost filled to the maximum. After filling, the density is occasionally too high and does not meet the DRC density requirements. The existing technology has developed scripts for automatic filling of dummy through python, skill, etc., and uses scripts to fill in certain key module areas.

[0004] However, using the foundary filler rule to fill the dummy will inevitably increase a large amount of dense metal, which will produce additional parasitic capacitance. In the process before 28nm, the impact of these parasitic capacitances on high-speed sensitive circuits and high-speed signal routing is almost negligible, but as the process size becomes smaller, the impact will become larger and larger. In the 7nm process, the impact is even more than 5%. The script developed by me cannot support large-scale use on chips. If it is only used in some important sensitive areas, and other areas are still filled with the foundary dummy filler rule, although the DRC requirements can be met in the end, the overall density of the chip is still uneven, and there is still a certain risk. Secondly, in advanced processes, there are certain requirements for the density of metal holes and other layers, which will increase the difficulty of the script a lot. Summary of the invention

[0005] The purpose of the present invention is to provide a dummy filling method for high-speed analog chips. The method can control the density of filling dummy according to the type of each chip, so as to meet the DRC requirements and reduce the additional parasitic capacitance generated by filling dummy, which causes a significant decrease in chip performance. The method can also be used on a large scale without causing the phenomenon of uneven density.

[0006] A dummy filling method for a high-speed analog chip, comprising:

[0007] Test the limit size and spacing of each metal layer to block dummy filling.

[0008] Using the barrier process layer of the limit size at equal intervals in the metal layer required to fill the dummy;

[0009] Each barrier process layer is made into a barrier unit;

[0010] The dummy is filled according to the limit spacing and the blocking unit.

[0011] Preferably, before testing the limit size and limit spacing of the process level for blocking dummy filling of each metal layer, the method further comprises:

[0012] Get the minimum and maximum density requirements for the metal layers of the chip to be populated.

[0013] Preferably, the testing of the limit size and limit spacing of the process level for blocking dummy filling of each metal layer includes:

[0014] Process hierarchy rules designed to block dummy fill;

[0015] Design test circuits;

[0016] Applying a process layer for blocking dummy filling in the test circuit;

[0017] Verify whether the test circuit can work normally;

[0018] The size and spacing of the process layers used to block the dummy filling are changed multiple times to test the limit size and limit spacing of the process layers used to block the dummy filling of each metal layer.

[0019] Preferably, the process hierarchy rules designed to block dummy filling include:

[0020] Add Dummy structures according to the shape, size and position of the board;

[0021] The Dummy structure is optimized according to the parameters of the metal layer.

[0022] Preferably, the design test circuit comprises:

[0023] Construct basic circuits based on the shape, size, and location of the layout;

[0024] Adjust the parameters of the basic circuit according to the functional requirements;

[0025] Test the test circuit for integrity, stability and compatibility.

[0026] Preferably, the use of the barrier process layers of the limit size at equal intervals in the metal layer to be filled with the dummy includes:

[0027] Use the calibreDRC tool to fill dummy, and the filled dummy is equal to the minimum density requirement of DRC.

[0028] Preferably, the step of making each barrier process layer into a barrier unit comprises:

[0029] Constructing a blocking unit template;

[0030] Fill in the parameters in the blocking unit template;

[0031] Generates blocking cells.

[0032] A dummy filling system for high-speed analog chips, comprising:

[0033] A test module is used to test the limit size and limit spacing of each metal layer's process layer used to block dummy filling;

[0034] A first filling module is used to use a barrier process layer of the limit size at equal intervals in the metal layer to be filled with the dummy;

[0035] A processing module, used for making each barrier process layer into a barrier unit;

[0036] The second filling module is used to fill the dummy according to the limit spacing and the blocking unit.

[0037] An electronic device comprises: a chip, a processor and a memory, wherein the memory is used to store computer program codes, the computer program codes include computer instructions, and when the chip executes the computer instructions, the electronic device executes a dummy filling method for high-speed analog chips.

[0038] A computer-readable storage medium stores a computer program, wherein the computer program includes program instructions. When the program instructions are executed by a processor of an electronic device, the processor is caused to execute a dummy filling method for a high-speed analog chip.

[0039] The beneficial effects of the present invention are: 1. The present invention can control the density of filling dummy according to the type of each chip, so as to meet the DRC requirements and reduce the additional parasitic capacitance generated by filling dummy, which causes a significant decrease in chip performance; 2. The present invention can be used on a large scale without causing the phenomenon of uneven density. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0041] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0042] Figure 1 This is a flow chart of a dummy filling method for a high-speed analog chip according to the present invention;

[0043] Figure 2 It is a schematic diagram of the structure of the blocking unit of the present invention;

[0044] Figure 3 A schematic diagram for comparing the magnitude of parasitic capacitance of the present invention;

[0045] Figure 4 The figure is a schematic diagram of the hardware structure of an electronic device of the present invention. DETAILED DESCRIPTION

[0046] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0047] In addition, the descriptions of "first", "second", etc. in the present invention are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0048] The dummies filled with foundary filler rules will inevitably add a large amount of dense metal, which will produce additional parasitic capacitance. In the process before 28nm, the impact of these parasitic capacitances on high-speed sensitive circuits and high-speed signal routing is almost negligible. However, as the process size becomes smaller, the impact will become greater and greater. In the 7nm process, the impact even exceeds 5%. The script developed by individuals cannot support large-scale use on chips. If it is only used in some important sensitive areas, and other areas are still filled with foundary dummy filler rules, although the DRC requirements can be met in the end, the overall density of the chip is still uneven, and there is still a certain risk. Secondly, in advanced processes, there are certain requirements for the density of metal holes and other layers, which will increase the difficulty of the script a lot.

[0049] The present invention can control the density of filling dummies according to the type of each chip, so as to meet the DRC requirements and reduce the significant decline in chip performance caused by the additional parasitic capacitance generated by filling dummies; the present invention can be used on a large scale without causing the phenomenon of uneven density.

[0050] Example 1

[0051] A dummy filling method for high-speed analog chips, refer to Figure 1 ,include:

[0052] S100, testing the limit size and spacing of each metal layer used to block dummy filling.

[0053] The process layer used to block dummy filling is the process layer used to block dummy filling. Each layer of metal has its corresponding blocking process layer. The main function of the process layer used to block dummy filling is to ensure the consistency of diffusion. In analog layout design, the addition of dummy (pseudo) structures, such as the Dummy Poly Gate of MOS tubes, is to solve the problem of diffusion inconsistency. Diffusion is a key step in the semiconductor manufacturing process, involving the introduction of dopants into semiconductor materials to change their electrical properties. Due to the different shapes, sizes and positions of the layout, the diffusion process may have different effects in different areas of the layout, resulting in uneven device performance, which affects the function of the entire chip. To solve this problem, engineers add dummy structures to the layout. Although these structures do not participate in the actual operation of the device, their presence can change the shape and density of the layout, thereby affecting the diffusion process. By properly designing and placing dummy structures, the diffusion process can be made more uniform throughout the layout, thereby improving the performance of the device. The application of process layers used to block dummy filling also involves optimizing the design of dummy structures, which may include changing the size, shape, position of the dummy structure and its relative position to other mechanisms to achieve the best diffusion consistency. This optimization usually needs to be carried out through simulation and experimentation to ensure the performance and reliability of the chip.

[0054] The maximum size and maximum spacing of each process layer used to block dummy filling are tested in turn. This means that a blocking process layer of this size is used with equal spacing on the top layer of the module or chip where dummy needs to be filled, and then the calibreDRC tool is used to fill the dummy, and the filled dummy can just pass the minimum density requirement of DRC.

[0055] S200, using a barrier process layer of a maximum size at equal intervals in the metal layer to be filled with the dummy;

[0056] The barrier process hierarchy is used to define the boundary conditions of the physical design and ensure that the layout of the design meets specific physical constraints, such as preventing the layout from being too close to a specific area or avoiding certain undesirable layout situations. By setting blockage in key areas, other design elements can be prevented from intruding into these areas, thereby ensuring the stability and reliability of the design. For example, setting blockage near the power and ground lines can prevent signal interference. With the barrier process hierarchy, designers can more finely control the layout and routing of the design, optimize the design rules, and ensure that the design meets specific performance and reliability requirements. In the back-end design, the use of the barrier process hierarchy helps to improve production efficiency because the pre-defined physical boundaries and rules can reduce the problems found in the design stage, thereby reducing the cost of later modifications and iterations. It is crucial to maintain the consistency of the barrier process hierarchy throughout the design process because it directly affects the final layout and performance of the design. The barrier process hierarchy ensures the stability and reliability of the design by defining physical boundaries, preventing layout interference, optimizing design rules, etc., while improving production efficiency and ensuring design consistency.

[0057] S300, making each barrier process layer into a barrier unit;

[0058] ‌The main purpose of blocking cells is to increase the density of the layout and solve specific problems in the layout. ‌In integrated circuit design, the density of the layout is an important consideration because it directly affects the performance and reliability of the chip. To increase the density of the layout, designers may use blocking cells (DBUCs), which are special layout cells used to increase the density of the layout. DBUCs are often used to fill gaps in the layout to reduce or eliminate potential latch-up risks. These DBUCs can be placed in sensitive areas of the layout, such as the active area, to provide additional protection and stability. DBUCs can also be used to solve specific problems in the layout, such as when solving DRC (design rule check) and LVS (layout and schematic comparison check) problems. By adding DBUCs, designers can adjust the density of the layout to meet specific design rule requirements while ensuring the consistency of the layout with the schematic. This approach is particularly effective in solving problems in sensitive areas in the layout, such as when the Substrate ports of two devices need to be connected. A special Layer can be used to box the two devices together and connect them by adding DBUCs. DBUC not only helps to improve the density of the layout and solve density-related problems, but also enhances the stability and reliability of the layout, ensuring the performance and security of the chip.

[0059] S400, fill dummy cells according to the limit spacing and blocking cells.

[0060] This technology is mainly aimed at designing the process level used to block dummy filling, so as to obtain a set of blocking units suitable for this process. Finally, the calibreDRC tool is used for filling.

[0061] Preferably, S100, before testing the limit size and limit spacing of the process layer for blocking dummy filling of each metal layer, further includes:

[0062] Get the minimum and maximum density requirements for the metal layers of the chip to be populated.

[0063] Check the process design manual for the description of the density of the metal layer of the chip to be filled, confirm the maximum and minimum density requirements of the metal layer, and facilitate the compression of the test interval in the subsequent steps. It can be easier to find the maximum size and maximum spacing of each metal layer to block the dummy filling process layer, which can save a lot of time.

[0064] Preferably, S100, testing the limit size and limit spacing of the process layer for blocking dummy filling of each metal layer includes:

[0065] S110, a process hierarchy rule designed to block dummy filling;

[0066] The process hierarchy rules designed to block dummy filling are mainly to ensure the operation of the chip by adding dummy metal to fill the upper metal layer to ensure the connectivity of the power supply and well area. The main purpose of this rule is to improve the uniformity and consistency of the layout by adding dummy structures, especially in analog layout design. By adding dummy structures that do not participate in the actual operation of the device, the shape and density of the layout can be changed, which in turn affects the diffusion process, making the diffusion process more uniform throughout the layout, thereby improving the performance of the device. This method of adding dummy structures is an optimization method. By properly designing and placing dummy structures, the problem of diffusion inconsistency caused by differences in layout shape, size, and position can be solved to ensure the normal functioning of the chip.

[0067] S120, design test circuit;

[0068] S130, applying a process layer for blocking dummy filling in the test circuit;

[0069] S140, verifying whether the test circuit can work normally;

[0070] S150, changing the size and spacing of the process layers used to block the dummy filling multiple times to test the limit size and limit spacing of the process layers used to block the dummy filling of each metal layer.

[0071] In chip design, the process layer of the metal layer used to block dummy filling is used to solve some problems in the process, such as inconsistent density and preventing chip damage during mechanical grinding or chemical etching. In order to test the limit size and limit spacing of the process layer used to block dummy filling in each metal layer, a series of experiments and simulations are required. In the semiconductor manufacturing rules, there is a layer specifically used to define the process layer used to block dummy filling. The position corresponding to this layer of graphics will not be automatically added with dummy. Through DRC testing, it is possible to check whether the design of dummy blockage complies with the process rules, including whether its size and spacing are within the allowed range. By adjusting the size and spacing of dummy blockage, the best protection effect can be found while ensuring that the design meets the process requirements. Adding dummy structures to the layout design, such as the Dummy Poly Gate of MOS tubes, can ensure the consistency of diffusion. Through simulation and experiments, the design of the dummy structure can be optimized to achieve the best diffusion consistency. This involves changing the size, shape, position of the dummy structure, and its relative position to other mechanisms. By adjusting these parameters, the limit size and spacing of the process layer used to block dummy filling can be tested to ensure the performance and reliability of the chip. Testing the limit size and spacing of each metal layer used to block dummy filling requires experiments and simulations, taking into account multiple aspects such as inconsistent metal density, prevention of chip damage, DRC inspection, and dummy structure optimization in layout design.

[0072] Preferably, S110, the process hierarchy rules designed to prevent dummy filling include:

[0073] S111, add Dummy structures according to the shape, size and position of the layout;

[0074] Layout is an important part of integrated circuit design. It involves converting the designed and simulated optimized circuit into a series of geometric figures. These figures contain all physical information about the device, such as the size of the integrated circuit, the topological definition of each layer, etc. There are specific rules for the design of the layout, which are formulated according to the process characteristics of the integrated circuit manufacturer. Different processes have different design rules. Designers can only start designing after obtaining the rules provided by the manufacturer. The layout should be checked regularly during the design process to avoid the accumulation of errors that make it difficult to modify. The shape, size and position of the layout are mainly determined by the designer according to the requirements of the circuit and certain process parameters. Layout design is the basic condition for manufacturing integrated circuits, and its rationality has a great influence on the yield, circuit performance and reliability. Layout design must be compatible with circuit design, process design and process level. At the same time, the designer must be familiar with process conditions, device physics, circuit principles and other contents. The layout design process includes steps such as design rule checking (DRC), electrical rule checking (ERC), and layout and circuit diagram comparison (LVS) to ensure the correctness and effectiveness of the layout.

[0075] S112, optimizing the Dummy structure according to the parameters of the metal layer.

[0076] Optimizing the dummy structure mainly involves adjusting the size, shape, position and relative position of the dummy with other structures through simulation and experiment to achieve the best diffusion consistency. Careful adjustments are made to multiple aspects of the dummy structure to ensure that its performance in a specific application is optimal. For example, in layout design, the use of dummy is intended to optimize circuit performance. By adding dummy structures to actual designs, engineers are able to simulate and experiment to achieve design goals by changing the design parameters of the dummy structure, such as size, shape and position. This optimization process involves not only technical adjustments, but also the prediction and resolution of problems that may be encountered in actual applications of the dummy structure to ensure that it can effectively improve the performance and reliability of the circuit.

[0077] Preferably, S120, designing a test circuit includes:

[0078] S121, construct basic circuits according to the shape, size and position of the layout;

[0079] Before designing a test circuit, you need to understand the design of the circuit board in detail, including its function, schematic diagram, PCB layout, etc., and then build the basic circuit according to the shape, size and position of the layout.

[0080] S122, adjusting parameters of the basic circuit according to functional requirements;

[0081] S123, perform integrity, stability and compatibility tests on the test circuit.

[0082] ‌Circuit integrity, stability and compatibility testing‌ is an important part of ensuring the performance and reliability of circuit systems. These tests cover different aspects of the circuit system to ensure that the circuit can operate normally and stably under different conditions and is compatible with other systems or devices. Circuit integrity testing‌ focuses on the integrity and stability of the power system to ensure that the power supply can provide stable and reliable power to electronic devices. This includes voltage stability testing, current capacity testing, resistance and inductance testing, ripple and noise testing, power path analysis, thermal management testing, and electromagnetic compatibility (EMC) testing. Through these tests, the performance indicators of the power system, such as response time, transmission rate, efficiency, etc., can be evaluated to ensure that the power system can maintain a stable output voltage when the load changes, provide sufficient current to meet the maximum load requirements, and will not interfere with other electronic devices. ‌Circuit stability testing‌ focuses on verifying the circuit system's ability to operate stably under various load conditions. This includes performance testing to verify the system's operation under high load, low load, and sudden load conditions. Through these tests, the system's performance indicators, such as response time, transmission rate, efficiency, etc., can be evaluated to ensure that the power system remains stable during long-term operation. ‌ Compatibility testing focuses on verifying the compatibility of the circuit system with other systems or devices. This includes simulating the communication and linkage operation of the system with other devices to verify their compatibility. Compatibility testing focuses on the analysis of the compatible environment, which is usually performed after determining the environment in which the software is running. Through these tests, it can be ensured that the power system can work properly when it needs to be linked with other systems and equipment.

[0083] Circuit integrity, stability and compatibility testing are key steps to ensure safe, stable and reliable operation of circuit systems. These tests can evaluate the performance indicators of circuit systems and ensure that the power supply system can provide stable and reliable power while maintaining stable operation under various conditions and being compatible with other systems or equipment.

[0084] Preferably, in S200, the use of a barrier process layer with a limit size at equal spacing in the metal layer to be filled with the dummy includes:

[0085] Use the calibreDRC tool to fill dummy, and the filled dummy is equal to the minimum density requirement of DRC.

[0086] Take Samsung 4nm as an example, Figure 2 It is a blocking unit made and arranged in proportion to the maximum spacing.

[0087] Figure 3After extracting the parasitic capacitance of a high-speed module in three cases, the parasitic capacitance on a key node N0 is selected. The first 53.4f is the parasitic capacitance value extracted after filling the dummy with the foundary filler rule. The second 50f is the parasitic capacitance value extracted after filling the dummy with this technology. The third 48.9f is the parasitic capacitance value directly extracted without filling any dummy. It can be seen that when directly filled with the foundary filler rule, the parasitic capacitance of the N0 node increases by about 9% compared to the parasitic capacitance when no dummy is filled, while using this technology to fill, it only increases by about 2%, and the impact is significantly reduced.

[0088] Preferably, S300, forming each barrier process layer into a barrier unit includes:

[0089] S310, constructing a blocking unit template;

[0090] ‌Blocking cell templates are virtual cells used in chip design to increase the density of the layout and meet the design rule check (DRC) requirements. ‌In chip design, in order to meet specific design rules and process requirements, it is often necessary to add dummy structures to ensure that the density of the layout meets the requirements, while also ensuring that the layout complies with the design rules. Blocking cell templates are templates used to generate these dummy structures. These templates are usually provided by design tools or created by yourself according to the requirements of a specific process design kit (PDK). They can be used to add dummy metal layers, dummy vias, etc. in the layout to fill space or meet specific density requirements.

[0091] The use of blocking cell templates may include the following steps: Define dummy structures: Define the shape and size of the dummy structures to be added according to the design rules and PDK requirements. Create templates: Use design tools or manually create templates for these dummy structures to ensure that they meet the design rules and process requirements. Apply templates: Select the areas in the layout where dummy structures need to be added, apply these templates, and generate dummy structures. Perform DRC check: After adding the dummy structures, perform a design rule check (DRC) to ensure that all added dummy structures meet the design rule requirements. By using blocking cell templates, the present invention can effectively improve the density of the layout while ensuring that the layout meets all design rules and process requirements, thereby improving the reliability and performance of the chip design.

[0092] S320, filling in the parameters in the blocking unit template;

[0093] When creating a pcell (Parameterized Cell) of the UDD (use define devices) function, you need to define CDF parameters, which include data types, variable information, etc. Specific to the blocking cell template, these parameters are used to describe and define specific properties of the cell, such as size, position, connection method, etc. By defining them in the Parameters section in the UDD Assistant toolbar, you can ensure the flexibility and reusability of the pcell. The setting of these parameters directly affects the function and performance of the blocking cell, so its definition process needs to be carefully considered and tested to ensure that the final generated cell meets the design requirements.

[0094] S330, generating a blocking unit.

[0095] In the embodiment of the present invention, the entire process of generating a blocking cell involves multiple steps, including creating a UDD cell in a custom compiler, defining parameters, adding a Dummy structure, and optimizing the design of the Dummy structure. Creating a UDD cell in a custom compiler includes creating a viewType type starting with udd, and the UDD Assistant toolbar appears on the left side of the layout window. In this toolbar, you can operate on basic layers, such as performing Align Size Boolean operations, and define information such as the data type of the CDF parameter of the pcell. Define parameters, open the Parameter Definition Editor interface from the udd assistant to add corresponding parameters and default values, and these parameters will define the behavior and properties of the pcell. Adding Dummy structures to the layout design includes understanding the diffusion process and recognizing that the diffusion process may have different effects in different areas of the layout due to different shapes, sizes, and positions of the layout. To solve this problem, engineers added Dummy structures to the layout. These structures do not participate in the actual operation of the device, but their presence can change the shape and density of the layout, thereby affecting the diffusion process. By properly designing and placing Dummy structures, the diffusion process can be made more uniform throughout the layout, thereby improving the performance of the device. Optimize the design of the Dummy structure. In actual design, engineers need to optimize the design of the Dummy structure through simulation and experimentation to achieve the best diffusion consistency. This may involve changing the size, shape, position of the Dummy structure, and its relative position to other structures. Generate and optimize the blocking unit to ensure the uniformity and consistency of the layout design, thereby improving the performance and reliability of the chip.

[0096] Example 2

[0097] A dummy filling system for high-speed analog chips, comprising:

[0098] A test module is used to test the limit size and limit spacing of each metal layer's process layer used to block dummy filling;

[0099] The first filling module is used to use a barrier process layer of a limit size at equal intervals in the metal layer to be filled with the dummy;

[0100] A processing module, used for making each barrier process layer into a barrier unit;

[0101] The second filling module is used to fill the dummy according to the limit spacing and the blocking unit.

[0102] Example 3

[0103] An electronic device includes: a chip, a processor and a memory, the memory is used to store computer program codes, the computer program codes include computer instructions, and when the chip executes the computer instructions, the electronic device executes a dummy filling method for high-speed analog chips.

[0104] refer to Figure 4 , the electronic device 2 includes a processor 21, a memory 22, an input device 23, and an output device 24. The processor 21, the memory 22, the input device 23, and the output device 24 are coupled via a connector, and the connector includes various interfaces, transmission lines, or buses, etc., which are not limited in the embodiments of the present invention. It should be understood that in various embodiments of the present invention, coupling refers to mutual connection in a specific manner, including direct connection or indirect connection through other devices, for example, through various interfaces, transmission lines, buses, etc.

[0105] The processor 21 may be one or more graphics processing units (GPUs). When the processor 21 is a GPU, the GPU may be a single-core GPU or a multi-core GPU. Optionally, the processor 21 may be a processor group consisting of multiple GPUs, and the multiple processors are coupled to each other via one or more buses. Optionally, the processor may also be other types of processors, etc., which are not limited in the embodiments of the present invention.

[0106] The memory 22 can be used to store computer program instructions and various computer program codes including program codes for executing the scheme of the present invention. Optionally, the memory includes but is not limited to random access memory (RAM), read-only memory (ROM), erasable programmable read only memory (EPROM), or portable read only memory (CD-ROM), which is used for related instructions and data.

[0107] The input device 23 is used to input data and / or signals, and the output device 24 is used to output data and / or signals. The output device 24 and the input device 23 may be independent devices or an integrated device.

[0108] Example 4

[0109] A computer-readable storage medium stores a computer program, wherein the computer program includes program instructions. When the program instructions are executed by a processor of an electronic device, the processor is caused to execute a dummy filling method for a high-speed analog chip.

[0110] The present invention can control the density of filling dummies according to the type of each chip, so as to meet the DRC requirements and reduce the significant decline in chip performance caused by the additional parasitic capacitance generated by filling dummies; the present invention can be used on a large scale without causing the phenomenon of uneven density.

[0111] The foregoing is merely a specific embodiment of the present invention, which enables those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A dummy filling method for high-speed analog chips, characterized in that: include: Test the limit size and spacing of each metal layer to block dummy filling. The limit size and limit spacing of the process layer for blocking dummy filling of each metal layer in the test include: Process hierarchy rules designed to block dummy fill; Design test circuits; Applying a process layer for blocking dummy filling in the test circuit; Verify whether the test circuit can work normally; The size and spacing of the process layers used to block the dummy filling are changed many times to test the limit size and limit spacing of the process layers used to block the dummy filling of each metal layer; Using the barrier process layer of the limit size at equal intervals in the metal layer required to fill the dummy; Each barrier process layer is made into a barrier unit; The step of making each barrier process layer into a barrier unit comprises: Constructing a blocking unit template; Fill in the parameters in the blocking unit template; Generate blocking units; The dummy is filled according to the limit spacing and the blocking unit.

2. A dummy filling method for a high-speed analog chip according to claim 1, characterized in that: Before testing the limit size and limit spacing of the process layer for blocking dummy filling of each metal layer, the method further includes: Get the minimum and maximum density requirements for the metal layers of the chip to be populated.

3. A dummy filling method for a high-speed analog chip according to claim 1, characterized in that: The process hierarchy rules designed to block dummy filling include: Add Dummy structures according to the shape, size and position of the board; The Dummy structure is optimized according to the parameters of the metal layer.

4. A dummy filling method for a high-speed analog chip according to claim 1, characterized in that: The design test circuit comprises: Construct basic circuits based on the shape, size, and location of the layout; Adjust the parameters of the basic circuit according to the functional requirements; Test the test circuit for integrity, stability and compatibility.

5. A dummy filling method for high-speed analog chip according to claim 1, characterized in that: The barrier process layer of the limit size is used at equal intervals in the metal layer to be filled with the dummy, including: Use the calibreDRC tool to fill dummy, and the filled dummy is equal to the minimum density requirement of DRC.

6. A dummy filling system for high-speed analog chips, applied to a dummy filling method for high-speed analog chips as claimed in any one of claims 1 to 5, characterized in that: include: A test module is used to test the limit size and limit spacing of each metal layer's process layer used to block dummy filling; A first filling module is used to use a barrier process layer of the limit size at equal intervals in the metal layer to be filled with the dummy; A processing module, used for making each barrier process layer into a barrier unit; The second filling module is used to fill the dummy according to the limit spacing and the blocking unit.

7. An electronic device, characterized in that: include: A chip, a processor and a memory, wherein the memory is used to store computer program code, wherein the computer program code includes computer instructions. When the chip executes the computer instructions, the electronic device executes a dummy filling method for a high-speed analog chip as described in any one of claims 1 to 5.

8. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, which includes program instructions. When the program instructions are executed by a processor of an electronic device, the processor executes a dummy filling method for a high-speed analog chip as described in any one of claims 1 to 5.

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