Image sensor

Abstract

An image sensor is provided. The image sensor includes: a substrate including a first surface and a second surface facing away from each other, where the substrate includes a plurality of pixel regions; an isolation pattern extending from the first surface and into the substrate, where the isolation pattern is between the plurality of pixel regions; and an anti-reflection layer on the isolation pattern, where the isolation pattern includes a first device isolation pattern and a second device isolation pattern, the first device isolation pattern contacts the anti-reflection layer, the second device isolation pattern is spaced apart from the anti-reflection layer, where the first device isolation pattern includes a first dielectric layer and a conductive reflective layer, and the second device isolation pattern includes a second dielectric layer and a conductive reflective layer. The conductive reflective layer is on the first dielectric layer, where a top surface of the conductive reflective layer and a top surface of the first dielectric layer are the same distance from the second surface of the substrate.

Description

[0001] This application claims the priority of Korean Patent Application No. 10-2023-0083441 filed in the Korean Intellectual Property Office on June 28, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates to image sensors and methods of manufacturing image sensors, and more particularly, to complementary metal oxide semiconductor (CMOS) image sensors and methods of manufacturing the same. Background Art

[0003] Image sensor is a semiconductor device that converts optical images into electrical signals. Recent advances in the computer industry and the communications industry have led to a strong demand for high-performance image sensors in various consumer electronic devices (such as digital cameras, camcorders, PCS (personal communication systems), gaming devices, security cameras, medical miniature cameras, etc.). Image sensors can be classified as charge coupled devices (CCD) type or complementary metal oxide semiconductor (CMOS) type. CMOS type image sensors can be abbreviated as CIS (CMOS image sensor). CIS has a plurality of pixels arranged in two dimensions. Each of the pixels includes a photodiode. The photodiode converts incident light into an electrical signal. Multiple pixels are defined by a deep isolation pattern disposed therebetween. Summary of the invention

[0004] Some embodiments of the present disclosure provide an image sensor configured to minimize or suppress the occurrence of dark current and a method of manufacturing the image sensor.

[0005] Some embodiments of the present disclosure provide an image sensor configured to increase light reflection efficiency and configured to improve sensitivity, and a method of manufacturing the image sensor.

[0006] Some embodiments of the present disclosure provide a highly integrated image sensor and a method of manufacturing the image sensor.

[0007] According to some embodiments of the present disclosure, an image sensor may include: a substrate including a first surface and a second surface facing back to each other, wherein the substrate includes a plurality of pixel regions; an isolation pattern extending from the first surface and into the substrate, wherein the isolation pattern is located between the plurality of pixel regions; and an anti-reflection layer located on the isolation pattern, wherein the isolation pattern includes a first device isolation pattern and a second device isolation pattern, the first device isolation pattern contacts the anti-reflection layer, and the second device isolation pattern is spaced apart from the anti-reflection layer, wherein the first device isolation pattern includes a first dielectric layer and a conductive reflective layer, the conductive reflective layer is located on the first dielectric layer, wherein a top surface of the conductive reflective layer and a top surface of the first dielectric layer are at the same distance from the second surface of the substrate.

[0008] According to some embodiments of the present disclosure, an image sensor may include: a substrate including a first surface and a second surface facing back to each other, wherein the substrate includes a plurality of pixel regions; an isolation pattern extending from the first surface and into the substrate, wherein the isolation pattern is located between the plurality of pixel regions; and an anti-reflection layer located on the isolation pattern, wherein the isolation pattern includes a first device isolation pattern and a second device isolation pattern, the first device isolation pattern contacts the anti-reflection layer, and the second device isolation pattern is spaced apart from the anti-reflection layer, wherein the first device isolation pattern includes a first dielectric layer and a conductive reflective layer, the conductive reflective layer is located on the first dielectric layer, wherein the anti-reflection layer includes a parallel layer portion and a vertical layer portion, the parallel layer portion extends in a direction parallel to the first surface of the substrate, and the vertical layer portion extends from the parallel layer portion toward the second surface of the substrate and contacts the conductive reflective layer.

[0009] According to some embodiments of the present disclosure, an image sensor may include: a substrate including a first surface and a second surface facing back to each other, wherein the substrate includes a plurality of pixel regions; a plurality of microlenses located on the first surface of the substrate; a transfer gate located on the second surface of the substrate; an isolation pattern extending from the first surface and extending into the substrate, wherein the isolation pattern is located between the plurality of pixel regions; and an anti-reflection layer located on the isolation pattern, wherein the isolation pattern includes a first device isolation pattern and a second device isolation pattern, the first device isolation pattern contacts the anti-reflection layer, and the second device isolation pattern is spaced apart from the anti-reflection layer, wherein the first device isolation pattern includes a first dielectric layer and a conductive reflective layer, the conductive reflective layer is located on the first dielectric layer, wherein the second device isolation pattern includes a buried layer, a conductive pad and a dielectric pad, the conductive pad is located on the buried layer, and the dielectric pad is located on the conductive pad, wherein the anti-reflection layer includes a parallel layer portion and a vertical layer portion, the parallel layer portion is parallel to the first surface of the substrate, the vertical layer portion extends from the parallel layer portion and extends toward the second surface of the substrate, wherein the vertical layer portion contacts the conductive reflective layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 A simplified block diagram of an image sensor according to some embodiments of the present disclosure is shown.

[0011] Figure 2 A circuit diagram of an active pixel sensor array of an image sensor according to some embodiments of the present disclosure is shown.

[0012] Figure 3 A plan view of an image sensor according to some embodiments of the present disclosure is shown.

[0013] Figure 4A Shown along Figure 3 A cross-sectional view taken along line AA'.

[0014] Figure 4B Shows Figure 4A An enlarged view of part M1.

[0015] Figure 4C Shown along Figure 3 A cross-sectional view taken along line BB'.

[0016] Figure 4D Shows Figure 4C An enlarged view of part M2.

[0017] Figure 5A The image sensor according to some embodiments of the present disclosure is shown along Figure 3 A cross-sectional view taken along line AA'.

[0018] Figure 5B Shows Figure 5A An enlarged view of part M1.

[0019] Figure 5C The image sensor according to some embodiments of the present disclosure is shown along Figure 3 A cross-sectional view taken along line BB'.

[0020] Figure 5D Shows Figure 5C An enlarged view of part M2.

[0021] Fig. 6A , Figure 6B , Fig. 7A , Figure 7B , Fig. 8A , Figure 8B , Fig.9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig.11A and Fig. 11B According to some embodiments of the present disclosure, Figure 3 A cross-sectional view of a method of manufacturing an image sensor taken along line AA′ and line BB′. DETAILED DESCRIPTION

[0022] In order to clarify the present disclosure, parts not related to the description will be omitted, and the same elements or equivalents are represented by the same reference numerals throughout the specification. In addition, since the sizes and thicknesses of the constituent members shown in the drawings are arbitrarily given for better understanding and ease of description, the present disclosure is not limited to the sizes and thicknesses shown. In the drawings, the thicknesses of layers, films, plates, regions, etc. are exaggerated for clarity. In the drawings, the thicknesses of some layers and regions are excessively presented for better understanding and ease of description.

[0023] It will be understood that when an element such as a layer, film, region or substrate is referred to as "on" another element, the element may be directly on the other element, or there may be an intermediate element. On the contrary, when an element is referred to as "directly on" another element, there is no intermediate element. In addition, for ease of description, spatial relative terms such as "under...", "under...", "under (lower part)", "over...", "upper (upper part)", etc. may be used here to describe the relationship between an element or feature and another (other) element or feature as shown in the accompanying drawings. It will be understood that, in addition to the orientations depicted in the accompanying drawings, spatial relative terms are intended to cover different orientations of the device in use or operation. For example, if the device in the accompanying drawings is turned over, the element described as "under" or "under" other elements or features will then be oriented to "above" the other elements or features. Therefore, the term "under..." can cover both upper and lower orientations. The device can be oriented in addition (rotated 90 degrees or in other orientations), and the spatial relative descriptors used here can be interpreted accordingly.

[0024] In addition, unless explicitly described to the contrary, the word "include" and its variations will be understood to imply the inclusion of the stated elements but not to exclude any other elements. As used herein, the phrase "at least one of A, B and C" refers to the logic (A "or" B "or" C) using the non-exclusive logic "or", and should not be interpreted as indicating "at least one of A, at least one of B and at least one of C". As used herein, unless the context clearly states otherwise, the singular forms "one", "one (kind / person)" and "the (the)" are also intended to include plural forms. It will also be understood that when the terms "include", "comprising" and / or their variations are used here, the stated features, steps, operations, elements and / or components are explained, but the presence or addition of one or more other features, steps, operations, elements, components and / or their groups are not excluded. The term "and / or" includes any combination and all combinations of one or more of the relevant listed items. The term "connected" may be used herein to refer to a physical connection and / or an electrical connection, and may refer to a direct or indirect physical connection and / or electrical connection. The phrase "element A surrounds element B" may refer to element A at least partially surrounding element B. The phrase "element A is filled with element B" or "element B fills element A" refers to element B being at least partially in the space defined by element A. As used herein, "element A is at the same level as element B" refers to at least one surface of element A being coplanar with at least one surface of element B.

[0025] Some embodiments of the present disclosure will now be described in detail below with reference to the accompanying drawings.

[0026] Figure 1 A simplified block diagram illustrating an image sensor according to some embodiments of the present disclosure is shown.

[0027] Reference Figure 1 , the image sensor may include an active pixel sensor array 1001, a row decoder 1002, a row driver 1003, a column decoder 1004, a timing generator 1005, a correlated double sampler (CDS) 1006, an analog-to-digital converter (ADC) 1007 and an input / output (I / O) buffer 1008.

[0028] The active pixel sensor array 1001 may include a plurality of two-dimensionally arranged unit pixels, each of which is configured to convert an optical signal into an electrical signal. The active pixel sensor array 1001 may be driven by a plurality of driving signals such as a pixel selection signal, a reset signal, and a charge transfer signal from a row driver 1003. The correlated double sampler 1006 may receive the converted electrical signal.

[0029] The row driver 1003 may provide a number of driving signals for driving a number of unit pixels to the active pixel sensor array 1001 according to the decoding result obtained from the row decoder 1002. When the unit pixels are arranged in a matrix shape, driving signals may be provided for each row.

[0030] The timing generator 1005 may provide timing signals and control signals to the row decoder 1002 and the column decoder 1004 .

[0031] The correlated double sampler 1006 may receive the electrical signal generated by the active pixel sensor array 1001, and may hold and sample the received electrical signal. The correlated double sampler 1006 may perform a double sampling operation to sample a specific noise level and a signal level of the electrical signal, and may then output a difference level corresponding to the difference between the noise level and the signal level.

[0032] The analog-to-digital converter 1007 may convert an analog signal corresponding to the difference level received from the correlated double sampler 1006 into a digital signal and then output the converted digital signal.

[0033] The input / output buffer 1008 may latch the digital signal and then sequentially output the latched digital signal to an image signal processing unit (not shown) in response to a decoding result obtained from the column decoder 1004 .

[0034] Figure 2 A circuit diagram illustrating an active pixel sensor array of an image sensor according to some embodiments of the present disclosure is shown.

[0035] Reference Figure 1 and Figure 2, the active pixel sensor array 1001 may include a plurality of pixel regions PX, and the pixel regions PX may be arranged in a matrix shape. Each pixel region PX may include a transfer transistor TX. Each pixel region PX may also include logic transistors RX, SX, and DX. The logic transistors RX, SX, and DX may include a reset transistor RX, a selection transistor SX, and a source follower transistor DX. The transfer transistor TX may include a transfer gate TG. Each of the pixel regions PX may also include a photoelectric conversion element PD and a floating diffusion region FD. The logic transistors RX, SX, and DX may be shared by a plurality of pixel regions PX.

[0036] The photoelectric conversion element PD can generate and accumulate photocharges in proportion to the amount of external incident light. The photoelectric conversion element PD may include a photodiode, a phototransistor, a photogate, a pinned photodiode, or a combination thereof. The transfer transistor TX may transfer the charge generated in the photoelectric conversion element PD to the floating diffusion area FD. The floating diffusion area FD may accumulate and store the charge generated and transferred from the photoelectric conversion element PD. The source follower transistor DX may be controlled by the amount of photocharge accumulated in the floating diffusion area FD.

[0037] The reset transistor RX including the reset gate RG may periodically reset the charges accumulated in the floating diffusion area FD. The reset transistor RX may have a drain electrode connected to the floating diffusion area FD and a power supply voltage V DD When the reset transistor RX is turned on, the floating diffusion area FD may be supplied with a power supply voltage V supplied from the source electrode of the reset transistor RX. DD Therefore, when the reset transistor RX is turned on, the charges accumulated in the floating diffusion area FD may be exhausted (discharged), and thus the floating diffusion area FD may be reset.

[0038] The source follower transistor DX including the source follower gate SF may be used as a source follower buffer amplifier. The source follower transistor DX may amplify the change in the potential of the floating diffusion area FD and may output the amplified potential to the output line V OUT .

[0039] The selection transistor SX including the selection gate SEL can select each row of pixel regions PX to be read out. When the selection transistor SX is turned on, the power supply voltage V DD Applied to the drain electrode of the source follower transistor DX.

[0040] Figure 3 A plan view showing an image sensor according to some embodiments of the present disclosure is shown. Figure 4A Shown along Figure 3 A cross-sectional view taken along line AA'. Figure 4BShows Shows Figure 4A An enlarged view of part M1. Figure 4C Shown along Figure 3 A cross-sectional view taken along line BB'. Figure 4D Shows Shows Figure 4C An enlarged view of part M2.

[0041] Reference Figure 3 and FIG. 4A to FIG. 4D , a substrate 100 may be provided. For example, the substrate 100 may be a single crystal silicon wafer, a silicon epitaxial layer, or a silicon on insulator (SOI) substrate. The substrate 100 may be doped with impurities to have a first conductivity type (e.g., p-type). The substrate 100 may have a first surface 100A and a second surface 100B facing away from each other. The first surface 100A may be spaced apart from the second surface 100B in a first direction D1, and the second surface 100B may be spaced apart from the first surface 100A in a second direction D2. The first direction D1 and the second direction D2 may be opposite to each other.

[0042] The substrate 100 may include a plurality of pixel regions PX. For example, when viewed in a plane, the substrate 100 may include a first pixel region PX1, a second pixel region PX2, a third pixel region PX3, and a fourth pixel region PX4 sequentially arranged in a clockwise direction. The first pixel region PX1 and the second pixel region PX2 may be adjacent to each other in a third direction D3, and the third pixel region PX3 and the fourth pixel region PX4 may be adjacent to each other in the third direction D3. The third direction D3 may be parallel to the second surface 100B of the substrate 100. The second pixel region PX2 and the third pixel region PX3 may be adjacent to each other in a fourth direction D4, and the first pixel region PX1 and the fourth pixel region PX4 may be adjacent to each other in the fourth direction D4. The fourth direction D4 may be parallel to the second surface 100B of the substrate 100 and may intersect with the third direction D3.

[0043] The isolation pattern DTI may be in the substrate 100. The isolation pattern DTI may separate the pixel regions PX from each other. The isolation pattern DTI may penetrate the substrate 100 along the second direction D2 between the pixel regions PX or extend through the substrate 100 along the second direction D2.

[0044] The isolation pattern DTI may be disposed in an isolation trench ITR extending from the first surface 100A toward the second surface 100B. The isolation trench ITR may include a deep trench DTR and an extension trench ETR. When viewed in a plane, the isolation pattern DTI may have a mesh shape in which lines extending in the third direction D3 and lines extending in the fourth direction D4 intersect each other.

[0045] The isolation pattern DTI may extend from the second surface 100B into the substrate 100 and may be disposed between a plurality of pixel regions PX. The isolation pattern DTI may include a first device isolation pattern BDTI and a second device isolation pattern FDTI. The first device isolation pattern BDTI may be adjacent to the first surface 100A of the substrate 100, and the second device isolation pattern FDTI may be adjacent to the second surface 100B of the substrate 100. The first device isolation pattern BDTI may be disposed in the extension trench ETR. The second device isolation pattern FDTI may be disposed in the deep trench DTR.

[0046] In an embodiment, a distance (eg, length or height) of the first device isolation pattern BDTI in the second direction D2 may be smaller than a distance (eg, length or height) of the second device isolation pattern FDTI in the second direction D2. The first device isolation pattern BDTI may be disposed on the second device isolation pattern FDTI.

[0047] The first device isolation pattern BDTI may include a first dielectric layer 36 and a conductive reflective layer 35 on the first dielectric layer 36 .

[0048] The extension trench ETR may have a bent portion ETR_C. The bent portion ETR_C may be formed at a position where the first device isolation pattern BDTI and the second device isolation pattern FDTI contact each other. The bent portion ETR_C may be disposed between the first device isolation pattern BDTI and the second device isolation pattern FDTI.

[0049] The first dielectric layer 36 may be formed to conformally cover or overlap the extension trench ETR. The first dielectric layer 36 may form a first additional trench ATR1.

[0050] The first dielectric layer 36 may include a dielectric material. The first dielectric layer 36 may include an oxide. The first dielectric layer 36 may include, for example, Al 2 O 3 、HfO、SiO 2 and / or plasma enhanced oxides (PEOX, SiO 2 ). The conductive reflective layer 35 may include a conductive material. The conductive reflective layer 35 may include, for example, Cu, Al, W, Ti, and / or Ag.

[0051] The conductive reflective layer 35 may be buried in the first dielectric layer 36. The conductive reflective layer 35 may be in the first additional trench ATR1. The conductive reflective layer 35 may have a top surface 35T located at the same level as the top surface 36T of the first dielectric layer 36 (e.g., the top surface 35T of the conductive reflective layer 35 and the top surface 36T of the first dielectric layer 36 are at the same distance from the second surface 100B of the substrate 100 in the first direction D1). The first dielectric layer 36 may have a width 36W greater than the width 35W of the conductive reflective layer 35.

[0052] The anti-reflection layer 42 may be disposed on the first device isolation pattern BDTI. The anti-reflection layer 42 may be disposed on the first surface 100A of the substrate 100 and cover / overlap the first surface 100A of the substrate 100. The anti-reflection layer 42 may have a bottom surface 42B in contact with the first surface 100A of the substrate 100, the top surface 36T of the first dielectric layer 36, and the top surface 35T of the conductive reflective layer 35. The top surface 35T of the conductive reflective layer 35 may be coplanar with the top surface 36T of the first dielectric layer 36 and the bottom surface 42B of the anti-reflection layer 42.

[0053] The anti-reflection layer 42 may include an oxide. The anti-reflection layer 42 may include, for example, Al 2 O 3 、HfO、SiO 2 and / or plasma enhanced oxides (PEOX, SiO 2 The anti-reflection layer 42 may include the same material as that of the first dielectric layer 36 .

[0054] The second device isolation pattern FDTI may be disposed under the first device isolation pattern BDTI The second device isolation pattern FDTI may include a buried layer 22 , a conductive pad 14 on the buried layer 22 , a dielectric pad 12 on the conductive pad 14 , and a buried dielectric pattern 16 .

[0055] The buried layer 22 may have a side surface and a top surface at least partially surrounded by the conductive liner 14. The conductive liner 14 may have an inner sidewall 14IS in contact with the buried layer 22. The conductive liner 14 may have an outer sidewall 14OS in contact with the dielectric liner 12.

[0056] The conductive liner 14 may have a width 14W greater than a width 22W of the buried layer 22. The width 14W of the conductive liner 14 may be less than a width 36W of the first dielectric layer 36.

[0057] The dielectric liner 12 may at least partially surround a top surface of the conductive liner 14 and an outer sidewall 14OS of the conductive liner 14 .

[0058] The buried layer 22 may include polysilicon or oxide. The buried layer 22 may include, for example, boron-doped silicon or undoped silicon. For example, the buried layer 22 may include SiO 2 .

[0059] The conductive pad 14 may include silicon. For example, the conductive pad 14 may include boron-doped silicon.

[0060] The dielectric liner 12 may include an oxide or a nitride. For example, the dielectric liner 12 may include SiO 2 or Si 3 N 4 The dielectric liner 12 and the first dielectric layer 36 may include different materials. The dielectric liner 12 and the first dielectric layer 36 may have different lattice constants. An interface may exist between the dielectric liner 12 and the first dielectric layer 36.

[0061] The dielectric liner 12 may have a top surface 12T including a curved surface 12C and a flat surface 12F parallel to the first surface 100A of the substrate 100. The curved surface 12C may be disposed between the flat surface 12F and the side surface of the dielectric liner 12.

[0062] The buried dielectric pattern 16 may penetrate or extend through the shallow device isolation portion STI. The dielectric liner 12 may be interposed between the buried dielectric pattern 16 and the shallow device isolation portion STI.

[0063] The photoelectric conversion element PD may be disposed in each of the pixel regions PX. The photoelectric conversion element PD may also be doped with impurities having a second conductivity type (e.g., n-type) opposite to the first conductivity type. The impurities doped into the photoelectric conversion element PD and the impurities having the first conductivity type in the substrate 100 may constitute a PN junction, thereby providing a photodiode.

[0064] The shallow device isolation trench STR may be recessed from the second surface 100B of the substrate 100 into the substrate 100 , and the shallow device isolation portion STI may be in the shallow device isolation trench STR. The shallow device isolation portion STI may be disposed adjacent to the second surface 100B of the substrate 100 .

[0065] The shallow device isolation portion STI may include a first isolation portion 32 and a second isolation portion 34. The first isolation portion 32 may conformally cover the inner wall of the shallow device isolation trench STR or overlap with the inner wall of the shallow device isolation trench STR. The second isolation portion 34 may be in the shallow device isolation trench STR. The first isolation portion 32 and the second isolation portion 34 may independently include at least one selected from silicon oxide (SiO), silicon nitride (SiN), silicon carbon nitride (SiCN), silicon carbon nitride (SiOCN) and combinations thereof. The isolation pattern DTI may extend in the second direction D2 and extend through the shallow device isolation portion STI. On the pixel area PX, the shallow device isolation portion STI may define an active area adjacent to the second surface 100B of the substrate 100. It may be directed to Figure 2 The transistors TX, RX, DX and SX are provided with active regions.

[0066] In each pixel region PX, the transmission gate TG may be disposed on the second surface 100B of the substrate 100. For example, a portion of the transmission gate TG may be buried in the substrate 100. The transmission gate TG may be a vertical type. Alternatively, the transmission gate TG may be a planar type flat on the second surface 100B of the substrate 100.

[0067] The gate dielectric pattern GI may be interposed between the transmission gate TG and the substrate 100. A floating diffusion region (not shown) may be disposed in the substrate 100 while being adjacent to one side of the transmission gate TG. For example, the floating diffusion region (not shown) may be implanted with impurities having a second conductivity type.

[0068] According to some embodiments of the present disclosure, light may enter the substrate 100 through the first surface 100A of the substrate 100. Electron-hole pairs may be generated from the incident light at the PN junction. These generated electrons may move toward the photoelectric conversion element PD. When a voltage is applied to the transmission gate TG, the electrons may move to the floating diffusion region (not shown).

[0069] The interlayer dielectric layer ILD may be disposed on the second surface 100B of the substrate 100 and cover / overlap the second surface 100B of the substrate 100. The interlayer dielectric layer ILD may be a multilayer structure including at least one selected from a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a porous low-k dielectric layer, and a combination thereof. The interlayer dielectric layer ILD may have a wiring 60 disposed therein. A floating diffusion region (not shown) may be connected to the wiring 60.

[0070] The light shielding pattern 48 may be disposed on the anti-reflection layer 42. The low refraction pattern 50 may be correspondingly disposed on the light shielding pattern 48. When viewed in a plane, the light shielding pattern 48 and the low refraction pattern 50 may overlap with the isolation pattern DTI and may have a grid shape. The light shielding pattern 48 may include, for example, titanium. The low refraction pattern 50 may have the same thickness as that of the light shielding pattern 48 in the third direction D3 and include an organic material. The low refraction pattern 50 may have a refractive index smaller than that of the color filters CF1 and CF2 to be discussed below. The light shielding pattern 48 and the low refraction pattern 50 may prevent crosstalk between adjacent pixel regions PX.

[0071] Color filters CF1 and CF2 may be disposed between the low refraction patterns 50. Color filters CF1 and CF2 may each have one of blue, green, and red. Alternatively, color filters CF1 and CF2 may have different colors such as cyan, magenta, or yellow. In the image sensor according to the present embodiment, color filters CF1 and CF2 may be arranged in a Bayer pattern. Alternatively, color filters CF1 and CF2 may be arranged in a 2×2 Tetra pattern, a 3×3 Nona pattern, and a 4×4 Hexadeca pattern.

[0072] The micro lenses ML may be disposed on the color filters CF1 and CF2. The micro lenses ML may have edges that are in contact and connected to each other.

[0073] Figure 5A FIG. 1 shows an image sensor according to some embodiments of the present disclosure. Figure 3 A cross-sectional view taken along line AA'. Figure 5B Shows Shows Figure 5A An enlarged view of part M1. Figure 5C FIG. 1 shows an image sensor according to some embodiments of the present disclosure. Figure 3 A cross-sectional view taken along line BB'. Figure 5D Shows Shows Figure 5C For the sake of brevity, repeated description will be omitted.

[0074] Reference Figure 3 and FIG. 5A to FIG. 5D , the isolation pattern DTI may be located in the substrate 100. The isolation pattern DTI may include a first device isolation pattern BDTI and a second device isolation pattern FDTI. The first device isolation pattern BDTI may be adjacent to the first surface 100A of the substrate 100, and the second device isolation pattern FDTI may be adjacent to the second surface 100B of the substrate 100. The first device isolation pattern BDTI may be disposed in the extension trench ETR. The second device isolation pattern FDTI may be disposed in the deep trench DTR.

[0075] The first device isolation pattern BDTI may include a first dielectric layer 36 and a conductive reflective layer 35 a on the first dielectric layer 36 .

[0076] The extension trench ETR may have a bent portion ETR_C. The bent portion ETR_C may be formed at a position where the first device isolation pattern BDTI and the second device isolation pattern FDTI contact each other. The bent portion ETR_C may be disposed between the first device isolation pattern BDTI and the second device isolation pattern FDTI.

[0077] The first dielectric layer 36 may be formed to conformally cover or overlap the extension trench ETR. The first dielectric layer 36 may form a first additional trench ATR1.

[0078] The conductive reflective layer 35a may be formed to conformally cover or overlap the first additional trench ATR1. The conductive reflective layer 35a may form a second additional trench ATR2. The second additional trench ATR2 may be filled therein with a vertical layer portion 42aV of an anti-reflective layer 42a to be discussed below.

[0079] The anti-reflection layer 42a may be disposed on the first device isolation pattern BDTI. The anti-reflection layer 42a may include a parallel layer portion 42aH and a vertical layer portion 42aV. The parallel layer portion 42aH may extend in a direction parallel to the first surface 100A of the substrate 100. The vertical layer portion 42aV may contact the conductive reflective layer 35a while extending from the first surface 100A of the substrate 100 toward the second surface 100B. The vertical layer portion 42aV may be in the second additional trench ATR2. The vertical layer portion 42aV may have a side surface and a bottom surface 42aVB in contact with the conductive reflective layer 35a. The side surface and the bottom surface 42aVB of the vertical layer portion 42aV may be at least partially surrounded by the conductive reflective layer 35a.

[0080] The conductive reflective layer 35a may have a top surface 35aT located at the same level as the bottom surface 42aHB of the parallel layer portion 42aH (e.g., the top surface 35aT and the bottom surface 42aHB are at the same distance from the second surface 100B of the substrate 100 in the first direction D1). The first dielectric layer 36 may have a top surface 36T located at the same level as the bottom surface 42aHB of the parallel layer portion 42aH (e.g., the top surface 36T and the bottom surface 42aHB are at the same distance from the second surface 100B of the substrate 100 in the first direction D1). The bottom surface 42aHB of the parallel layer portion 42aH may be in contact with the top surface 36T of the first dielectric layer 36. The bottom surface 42aHB of the parallel layer portion 42aH may be in contact with the top surface 35aT of the conductive reflective layer 35a.

[0081] The vertical layer portion 42aV may have a bottom surface 42aVB located at a level higher than that of the bottom surface 35aB of the conductive reflective layer 35a (e.g., the distance of the bottom surface 42aVB from the second surface 100B of the substrate 100 in the first direction D1 is greater than the distance of the bottom surface 35aB from the second surface 100B of the substrate 100 in the first direction D1). The level of the bottom surface 42aVB of the vertical layer portion 42aV may be higher than that of the bottom surface 36B of the first dielectric layer 36 (e.g., the distance of the bottom surface 42aVB from the second surface 100B of the substrate 100 in the first direction D1 is greater than the distance of the bottom surface 36B from the second surface 100B of the substrate 100 in the first direction D1). The level of the bottom surface 35aB of the conductive reflective layer 35a may be higher than the level of the bottom surface 36B of the first dielectric layer 36 (for example, the distance between the bottom surface 35aB and the second surface 100B of the substrate 100 in the first direction D1 is greater than the distance between the bottom surface 36B and the second surface 100B of the substrate 100 in the first direction D1).

[0082] The second device isolation pattern FDTI may be disposed under the first device isolation pattern BDTI The second device isolation pattern FDTI may include a buried layer 22 , a conductive pad 14 on the buried layer 22 , and a dielectric liner 12 on the conductive pad 14 .

[0083] The vertical layer portion 42aV may have a width 42aVW, which may be smaller than the width 14W of the conductive pad 14. The width 42aVW of the vertical layer portion 42aV may be smaller than the width 35aW of the conductive reflective layer 35a.

[0084] FIG. 6A to FIG. 11B A method of manufacturing an image sensor according to some embodiments of the present disclosure is shown. Figure 3 A cross-sectional view taken along line AA' and line BB'.

[0085] Reference Fig. 6A and Figure 6B , the substrate 100 may be prepared. The interlayer dielectric layer ILD, the wiring 60 in the interlayer dielectric layer ILD, the gate dielectric pattern GI, the transfer gate TG, and the substrate 100 on the interlayer dielectric layer ILD may be provided using a wiring process, a trimming process, and a bonding process.

[0086] The substrate 100 may be provided therein with and include a shallow device isolation portion STI and a preliminary second device isolation pattern pFDTI. The preliminary second device isolation pattern pFDTI may be provided in the deep trench DTR and may include a buried dielectric pattern 16, a buried layer 22 on the buried dielectric pattern 16, a conductive pad 14 on the buried layer 22, and a dielectric pad 12 on the conductive pad 14. The top surface of the dielectric liner 12 may be flat.

[0087] Reference Fig. 7A and Figure 7B , a first upper trench UTR1 may be formed. The formation of the first upper trench UTR1 may include forming a mask pattern on the first surface 100A of the substrate 100 and etching the substrate 100 using the mask pattern as an etching mask. After the etching process, a portion of the mask pattern may remain (or may not remain). The bottom surface of the first upper trench UTR1 may include a curved surface.

[0088] During the formation of the first upper trench UTR1, the top surface of the dielectric liner 12 may be partially etched. The top surface of the dielectric liner 12 may be exposed. The exposed top surface of the dielectric liner 12 may include a curved surface. The second device isolation pattern FDTI may be defined as referring to a preliminary second device isolation pattern pFDTI whose dielectric liner 12 is etched.

[0089] Reference Fig. 8A and Figure 8B , a preliminary first dielectric layer p36 may be formed to cover the inner wall of the first upper trench UTR1 and the first surface 100A of the substrate 100 or overlap the inner wall of the first upper trench UTR1 and the first surface 100A of the substrate 100. The preliminary first dielectric layer p36 may conformally cover the inner wall of the first upper trench UTR1 and the first surface 100A of the substrate 100 or conformally overlap the inner wall of the first upper trench UTR1 and the first surface 100A of the substrate 100. Therefore, the preliminary first dielectric layer p36 may form a second upper trench UTR2.

[0090] Reference Fig.9A and Fig. 9B A preliminary conductive reflective layer p35 may be formed on the preliminary first dielectric layer p36. The preliminary conductive reflective layer p35 may be formed to be located in the second upper trench UTR2 and to cover or overlap a top surface of the preliminary first dielectric layer p36.

[0091] Reference Fig. 10A and Fig. 10B, an upper portion of the preliminary conductive reflective layer p35 may be removed, and an upper portion of the preliminary first dielectric layer p36 may also be removed. The preliminary conductive reflective layer p35 and the preliminary first dielectric layer p36 may be removed to expose the first surface 100A of the substrate 100. Removing the upper portion of the preliminary conductive reflective layer p35 and the upper portion of the preliminary first dielectric layer p36 may include, for example, removing the preliminary first dielectric layer p36 and the preliminary conductive reflective layer p35 to allow the preliminary first dielectric layer p36 to remain in the first upper trench UTR1 and to allow the preliminary conductive reflective layer p35 to remain in the second upper trench UTR2. Removing the upper portion of the preliminary conductive reflective layer p35 and the upper portion of the preliminary first dielectric layer p36 may include performing an etch-back process on the preliminary conductive reflective layer p35 and the preliminary first dielectric layer p36.

[0092] An upper portion of the preliminary first dielectric layer p36 may be removed to form a first dielectric layer 36. The preliminary first dielectric layer p36 may be separated into the first dielectric layer 36. An upper portion of the preliminary conductive reflective layer p35 may be removed to form a conductive reflective layer 35. The preliminary conductive reflective layer p35 may be separated into the conductive reflective layer 35. Thus, a first device isolation pattern BDTI including the conductive reflective layer 35 and the first dielectric layer 36 may be formed.

[0093] Reference Fig.11A and Fig. 11B , an anti-reflection layer 42 may be formed on the first surface 100A of the substrate 100 , the conductive reflective layer 35 , and the first dielectric layer 36 .

[0094] Thereafter, a light shielding pattern 48 may be formed on the anti-reflection layer 42, and a low-refractive pattern 50 may be formed on the light shielding pattern 48 (see, for example, Figure 4A and Figure 4C ). Color filters CF1 and CF2 may be formed between the low refraction patterns 50. Micro lenses ML may be formed on the color filters CF1 and CF2, so that a Figures 3 to 4D The image sensor shown in .

[0095] According to the present disclosure, an image sensor may be configured such that a conductive reflective layer may be included on a dielectric layer of a first device isolation pattern, and thus the conductive reflective layer may increase light reflection efficiency and improve sensitivity of the image sensor.

[0096] According to the present disclosure, a conductive reflective layer may be included on a dielectric layer of a first device isolation pattern, a second device isolation pattern may include a buried layer and a conductive pad, a contact for a negative bias (negative bias) may be connected to the conductive reflective layer of the first device isolation pattern and the buried layer and the conductive pad of the second device isolation pattern, and a negative bias may be applied.

[0097] The foregoing description provides some embodiments for explaining the present disclosure. Therefore, the present disclosure is not limited to the above embodiments, and it will be understood by those skilled in the art that changes in form and detail may be made therein without departing from the spirit and essential features of the present disclosure.

Claims

1. An image sensor, comprising: A substrate, comprising a first surface and a second surface facing away from each other, wherein the substrate comprises a plurality of pixel regions; an isolation pattern extending from the first surface and into the substrate, wherein the isolation pattern is located between the plurality of pixel regions; and an anti-reflection layer, located on the isolation pattern, The isolation pattern includes: a first device isolation pattern contacting the anti-reflection layer; and a second device isolation pattern spaced apart from the anti-reflection layer. The first device isolation pattern includes: a first dielectric layer; and a conductive reflective layer, which is located on the first dielectric layer, and The top surface of the conductive reflective layer and the top surface of the first dielectric layer are at the same distance from the second surface of the substrate.

2. The image sensor according to claim 1, wherein: The first device isolation pattern is located in the extension trench, The extended groove includes a curved portion, and The bent portion is located between the first device isolation pattern and the second device isolation pattern.

3. The image sensor according to claim 1, wherein: The second device isolation pattern includes: buried layer; a conductive pad disposed on the buried layer; and A dielectric pad is located on the conductive pad.

4. The image sensor according to claim 3, wherein: The lattice constant of the first dielectric layer is different from the lattice constant of the dielectric liner.

5. The image sensor according to claim 3, wherein: The top surface of the dielectric liner includes a curved surface.

6. The image sensor according to claim 3, wherein: The dielectric liner and the first dielectric layer include different materials.

7. The image sensor according to claim 1, wherein: The conductive reflective layer includes at least one of Cu, Al, W, Ti, and Ag.

8. The image sensor according to claim 1, wherein: The anti-reflection layer includes a parallel layer portion and a vertical layer portion. The top surface of the conductive reflective layer contacts the bottom surface of the parallel layer portion, and The vertical layer portion is at least partially surrounded by the conductive reflective layer.

9. The image sensor according to claim 8, wherein: A bottom surface of the vertical layer portion is a first distance from the second surface of the substrate, a bottom surface of the conductive reflective layer is a second distance from the second surface of the substrate, and the first distance is greater than the second distance.

10. An image sensor, comprising: A substrate, comprising a first surface and a second surface facing away from each other, wherein the substrate comprises a plurality of pixel regions; an isolation pattern extending from the first surface and into the substrate, wherein the isolation pattern is located between the plurality of pixel regions; and an anti-reflection layer, located on the isolation pattern, The isolation pattern includes: a first device isolation pattern contacting the anti-reflection layer; and a second device isolation pattern spaced apart from the anti-reflection layer. The first device isolation pattern includes: a first dielectric layer; and a conductive reflective layer, which is located on the first dielectric layer, and The anti-reflection layer includes: a parallel layer portion extending in a direction parallel to the first surface of the substrate; and a vertical layer portion extending from the parallel layer portion toward the second surface of the substrate and contacting the conductive reflective layer.

11. The image sensor according to claim 10, wherein: The bottom surface of the vertical layer portion is a first distance from the second surface of the substrate, the bottom surface of the first dielectric layer is a second distance from the second surface of the substrate, and the first distance is greater than the second distance.

12. The image sensor according to claim 10, wherein: A bottom surface of the parallel layer portion contacts a top surface of the first dielectric layer and a top surface of the conductive reflective layer.

13. The image sensor according to claim 10, wherein: The second device isolation pattern includes: buried layer; a conductive pad disposed on the buried layer; and A dielectric pad is located on the conductive pad.

14. The image sensor according to claim 13, wherein: The width of the conductive pad is greater than the width of the vertical layer portion.

15. The image sensor according to claim 13, wherein: The buried layer includes polysilicon or SiO2, and The conductive liner includes boron-doped silicon.

16. The image sensor according to claim 13, wherein: The conductive reflective layer includes at least one of Cu, Al, W, Ti, and Ag.

17. The image sensor according to claim 13, wherein: The top surface of the dielectric liner includes a curved surface and a flat surface parallel to the first surface of the substrate.

18. The image sensor according to claim 10, wherein: The side surfaces and the bottom surface of the vertical layer portion are at least partially surrounded by the conductive reflective layer.

19. An image sensor, comprising: A substrate, comprising a first surface and a second surface facing away from each other, wherein the substrate comprises a plurality of pixel regions; A plurality of micro lenses are disposed on the first surface of the substrate; a transmission gate disposed on the second surface of the substrate; an isolation pattern extending from the first surface and into the substrate, wherein the isolation pattern is located between the plurality of pixel regions; and an anti-reflection layer, located on the isolation pattern, The isolation pattern includes: a first device isolation pattern contacting the anti-reflection layer; and a second device isolation pattern spaced apart from the anti-reflection layer. The first device isolation pattern includes: a first dielectric layer; and a conductive reflective layer located on the first dielectric layer. The second device isolation pattern includes: a buried layer; a conductive pad located on the buried layer; and a dielectric pad located on the conductive pad, and The anti-reflection layer includes: a parallel layer portion parallel to the first surface of the substrate; and a vertical layer portion extending from the parallel layer portion and toward the second surface of the substrate, wherein the vertical layer portion contacts the conductive reflective layer.

20. The image sensor according to claim 19, wherein: A bottom surface of the first dielectric layer contacts a top surface of the dielectric liner, and The first dielectric layer and the dielectric liner include different materials.

Images