Semiconductor structure and forming method thereof

Abstract

Semiconductor structures and methods of forming the same are provided. The semiconductor structure includes: a semiconductor substrate; a plurality of transistors disposed on the semiconductor substrate and including a plurality of gate structures extending longitudinally along a first direction; a metallization layer disposed over the plurality of transistors, the metallization layer including a plurality of metal layers and a plurality of contact vias; a dielectric layer over the metallization layer; a plurality of dielectric fins extending in parallel along the first direction and disposed over the dielectric layer; a semiconductor layer conformally disposed over the plurality of dielectric fins; a source contact and a drain contact disposed directly over the semiconductor layer; and a gate structure disposed over the semiconductor layer and between the source contact and the drain contact.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor structures and methods of forming the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs, each with smaller and more complex circuits than the previous one. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or wire) that can be produced using a manufacturing process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs. This scaling down also increases the complexity of handling and manufacturing ICs.

[0003] The IC manufacturing process flow can generally be divided into front-end of line (FEOL) processes and back-end of line (BEOL) processes. FEOL processes include those processes associated with manufacturing active IC devices such as transistors. BEOL processes refer to those processes associated with manufacturing interconnect structures that interconnect IC components manufactured at the FEOL level. Larger active devices can be manufactured at the BEOL level. The industry is actively seeking improvements to these BEOL active devices for various purposes. Summary of the invention

[0004] According to one aspect of an embodiment of the present application, a semiconductor structure is provided, comprising: a semiconductor substrate; a plurality of transistors arranged on the semiconductor substrate and comprising a plurality of gate structures extending longitudinally along a first direction; a metallization layer arranged above the plurality of transistors, the metallization layer comprising a plurality of metal layers and a plurality of contact vias; a dielectric layer located above the metallization layer; a plurality of dielectric fins extending in parallel along a first direction and arranged above the dielectric layer; a semiconductor layer conformally arranged above the plurality of dielectric fins; a source contact and a drain contact directly arranged above the semiconductor layer; and a gate structure arranged above the semiconductor layer and located between the source contact and the drain contact.

[0005] According to another aspect of an embodiment of the present application, a semiconductor structure is provided, comprising: a first dielectric layer; a plurality of metal lines partially disposed in the first dielectric layer and extending longitudinally along a first direction; a gate dielectric layer conformally disposed above a top surface of the first dielectric layer and the plurality of metal lines, and in direct contact with the top surfaces of the first dielectric layer and the plurality of metal lines; an interface layer conformally disposed above the gate dielectric layer; a semiconductor layer disposed above the interface layer; a second dielectric layer disposed above the semiconductor layer; and a source contact and a drain contact extending through the second dielectric layer to contact the semiconductor layer.

[0006] According to another aspect of an embodiment of the present application, a method for forming a semiconductor structure is provided, comprising: forming a transistor on a substrate; forming a metallization layer above the transistor, the metallization layer comprising: a first dielectric layer, and a plurality of metal lines, arranged in the first dielectric layer and extending longitudinally along a first direction; etching the first dielectric layer and the plurality of metal lines to form a recess; depositing a gate dielectric layer above the recess; depositing an interface layer above the gate dielectric layer; depositing a semiconductor layer above the interface layer; depositing a second dielectric layer above the semiconductor layer; after depositing the second dielectric layer, planarizing the first dielectric layer and the second dielectric layer; and forming a source contact and a drain contact through the second dielectric layer to contact the semiconductor layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read in conjunction with the accompanying drawings, various aspects of the present invention can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0008] Figure 1 A flowchart showing a method for forming a back-end semiconductor device according to one or more aspects of the present invention;

[0009] Figure 2-Figure 12 According to one or more aspects of the present invention, Figure 1 A partial cross-sectional view of a workpiece at various manufacturing stages of the method;

[0010] Figure 13-Figure 16 Shows that you can use Figure 1 A partial cross-sectional view of an alternative back-end semiconductor device formed by the method;

[0011] Fig.17 A flow chart showing another method for forming a back-end semiconductor device according to one or more aspects of the present invention;

[0012] Figure 18-Figure 29 Shows that you can use Fig.17 A partial cross-sectional view of an alternative back-end semiconductor device formed by the method;

[0013] Figure 30-Figure 35 Shows that you can use Fig.17 A partial cross-sectional view of an alternative back-end semiconductor device formed by the method;

[0014] Figure 36-Figure 43 A partial cross-sectional view of a semiconductor structure in which a back-end semiconductor device of the present invention is used to access a memory device is shown. DETAILED DESCRIPTION

[0015] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact with each other, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0016] For ease of description, spatially relative terms such as "under," "beneath," "lower," "over," "upper," etc. may be used herein to easily describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0017] In addition, when "about," "approximately," etc. are used to describe a number or a range of numbers, the term is intended to encompass numbers within a reasonable range that take into account variations inherently caused during manufacturing as understood by a person of ordinary skill in the art. For example, based on known manufacturing tolerances associated with manufacturing a component having features associated with the number, the number or range of numbers encompasses a reasonable range that includes the described number, for example, within + / - 10% of the described number. For example, a material layer having a thickness of "about 5 nm" may encompass a range of sizes from 4.25 nm to 5.75 nm, where a person of ordinary skill in the art knows that the manufacturing tolerance associated with depositing material layers is + / - 15%. When describing various aspects of a transistor, the source / drain regions may refer to the source or drain, either individually or collectively, depending on the context.

[0018] IC manufacturing process flows can generally be divided into front-end-of-line (FEOL) processes and back-end-of-line (BEOL) processes. FEOL processes include processes associated with manufacturing active IC devices such as transistors. For example, FEOL processes may include forming isolation components, gate structures, and source / drain components. BEOL processes refer to processes associated with manufacturing interconnect structures that interconnect IC components manufactured at the FEOL level. Due to the special properties of contact with components of IC devices (e.g., contact with gate structures and / or source / drain components), the manufacturing processes used for them can sometimes be called mid-end-of-line (MEOL) processes. In order to reduce wiring or to reduce the number of transistors at the FEOL level, active devices are sometimes also manufactured at the BEOL level. However, in order to avoid thermal damage to the FEOL structure, the manufacture of back-end active devices is limited by surface process temperatures. These process temperature limitations may result in insufficient drive current. Improvements need to be made on back-end active devices.

[0019] The present invention provides a back-end active device and a method for forming the same. The back-end active device of the present invention includes a channel region that tracks a three-dimensional (3D) topography to provide a greater drive current. Based on the 3D topography, the back-end active device of the present invention has two configurations - a high drive current configuration and a low leakage configuration. The back-end active device of the present invention can be used as a header / foot device for power gating or access devices for various BEOL memory devices. Power gating is a technique for reducing the power consumption of an integrated circuit (IC) device by shutting down a portion of the IC device when the IC device is not in use or in a power saving mode. A header device or a foot device can be used to activate power gating. The header device gates the power supply (VDD) rail, and the foot device gates the ground (VSS) rail. It is desirable to manufacture a header / foot device that can provide sufficient drive current without taking up too much space in the FEOL layer.

[0020] Various aspects of the invention will now be described in more detail with reference to the accompanying drawings. Figure 1 and Fig.17 The present invention includes flowcharts of methods 100 and 300 for forming a semiconductor device according to an embodiment of the present invention. Methods 100 and 300 are merely examples and are not intended to limit the present invention to what is explicitly shown in method 100 and method 300. Additional steps may be provided before, during, and after method 100 or method 300, and some of the steps described may be replaced, removed, or reordered for additional embodiments of the method. For the sake of simplicity, not all steps are described in detail. Figure 2-Figure 12 Describing method 100, Figure 2-Figure 12 The invention includes partial cross-sectional views of a workpiece 200 at different stages of manufacture according to an embodiment of the method 100. Figure 18-Figure 29 Describing method 300, Figure 18-Figure 29300. For the avoidance of doubt, in all Figure 1-Figure 29 , the X direction is perpendicular to the Y direction, and the Z direction is perpendicular to the X direction and the Y direction. Since the workpiece 200 will be formed into a semiconductor device at the end of its manufacturing process, the workpiece 200 may be referred to as a semiconductor device 200 or a semiconductor structure 200 according to context requirements.

[0021] refer to Figure 1 and Figure 2 The method 100 includes a block 102 in which a workpiece 200 is received. Figure 2 As shown, the workpiece 200 may include a device substrate 10 and a first interconnect structure 20 disposed above the device substrate 10. The device substrate 10 may include a semiconductor substrate 202 and a transistor 203 on the semiconductor substrate 202. The semiconductor substrate 202 may be a silicon (Si) substrate. In some other embodiments, the semiconductor substrate 202 may include other semiconductors, such as germanium (Ge), silicon germanium (SiGe), or III-V semiconductor materials. Exemplary III-V semiconductor materials may include gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), gallium nitride (GaN), gallium arsenic phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium phosphide (GaInP), and indium gallium arsenide (InGaAs). The semiconductor substrate 202 may also include an insulating layer, such as a silicon oxide layer, to have a silicon on insulator (SOI) structure.

[0022] Each transistor 203 can be a multi-gate device. Here, a multi-gate device generally refers to a device having a gate structure, or a portion thereof, that is disposed above more than one side of a channel region. Fin field effect transistors (FinFETs) and gate-all-around (GAA) transistors are examples of multi-gate devices that have become popular and promising candidates for high-performance and low-leakage applications. FinFETs have a high-side channel surrounded by a gate on more than one side (e.g., the gate surrounds the top and sidewalls of a "fin" of semiconductor material extending from a substrate). The gate structure of a GAA transistor can extend partially or completely around the channel region to provide access to the channel region on two or more sides. Because its gate structure surrounds the channel region, a GAA transistor may also be referred to as a wrap-around gate transistor (SGT) or a multi-bridge channel (MBC) transistor. The channel region of a GAA transistor may be in the form of a nanowire, a nanosheet, or other nanostructure, and therefore, a GAA transistor may also be referred to as a nanowire transistor or a nanosheet transistor. As Figure 2As shown in FIG. 1 , each transistor 203 includes a channel region 204 extending between two source / drain features 206 along the X direction. A gate structure 210 is disposed above the channel region 204. The transistors 203 may be spaced apart from each other by isolation features 208. Figure 2 It is not explicitly shown, but when the transistor 203 is a GAA transistor, the channel region 204 includes a plurality of channel components extending between two source / drain features 206 along the X direction, and the gate structure 210 surrounds each of the plurality of channel components in the channel region 204 .

[0023] Figure 2 The first interconnect structure 20 shown in the figure can be part of an interconnect structure, which can also include a second interconnect structure 30 (described below). In this regard, the first interconnect structure 20 is disposed below the back-end active device, and the second interconnect structure 30 is disposed above the back-end active device. The first interconnect structure 20 and the second interconnect structure 30 as a whole can include between about 8 and about 15 metallization layers, each metallization layer including contact vias and wires embedded in an inter-metal dielectric (IMD) layer. The contact vias and wires can include copper, titanium nitride, or a combination thereof. Since the lower metallization layers closer to the device substrate 10 are generally too crowded to accommodate the back-end devices, the first interconnect structure 20 may include 4 to 12 metallization layers. In the depicted example, the first interconnect structure 20 includes 4 metallization layers—M1, M2, M3, and M4.

[0024] refer to Figure 1 and Figure 3 , the method 100 includes a block 104, in which a dielectric spacer layer 211 is deposited over the workpiece 200. In some embodiments, the dielectric spacer layer 211 may include silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbonitride. In some embodiments, the dielectric spacer layer 211 may be deposited using chemical vapor deposition (CVD) or a suitable deposition method. In some examples, the dielectric spacer layer 211 may have a thickness between about 30 nm and about 200 nm, which may occupy about half of the IMD layer of the topmost metallization layer of the first interconnect structure 20.

[0025] refer to Figure 1 and Figure 4 The method 100 includes block 106, where the dielectric spacer layer 211 is patterned to form a fin structure 212. At block 106, the dielectric spacer layer 211 is patterned using a photolithography process and an etching process. Figure 4As shown in , the dielectric spacer layer 211 can be divided into a plurality of portions, and each portion is patterned to have a wavy structure to increase the surface area. In the depicted embodiment, the dielectric spacer layer 211 is patterned to form a groove 213 that defines the fin structure 212. In some examples, the groove 213 does not extend through the dielectric spacer layer 211, so that the fin structure 212 is elevated from the base dielectric spacer layer 211. Figure 4 As shown, the trenches 213 and the fin structures 212 form a wavy dielectric spacer structure that provides a three-dimensional (3D) topography to increase the channel area.

[0026] refer to Figure 1 , Figure 5 ,and Figure 6 , the method 100 includes a block 108, in which a semiconductor layer 214 is deposited over the fin structure 212. In some embodiments, the semiconductor layer 214 may be a two-dimensional (2D) or low-dimensional semiconductor layer that may be formed or transferred over the fin structure 212 at a temperature that does not cause substantial damage to the front-end structure. Example semiconductor materials for the semiconductor layer 214 may include molybdenum sulfide (MoS2), tungsten selenide (WSe2), cuprous oxide (Cu2O), carbon nanotubes (CNTs), indium oxide (InO), or indium gallium zinc oxide (IGZO). In some embodiments, the semiconductor layer 214 may be synthesized or grown on a growth substrate such as a sapphire substrate, a crystalline copper substrate, a diamond substrate, a silicon substrate, or a silicon oxide substrate, and then transferred to the fin structure 212. In some alternative embodiments, the semiconductor layer 214 may be deposited on the fin structure 212 using atomic layer deposition (ALD). The semiconductor layer 214 may be transferred or deposited on the fin structure 212 at a process temperature between about 150° C. and about 400° C. To show the semiconductor layer 214 and the layers deposited thereon in more detail, a portion of the fin structure 212 is magnified and shown in FIG. Figure 6 In some embodiments, semiconductor layer 214 can be conformally deposited over the surface of fin structure 212, including over the surface exposed in trench 213. In some examples, semiconductor layer 214 can have a thickness between about 0.5 nm and about 10 nm. Figure 6 In some embodiments not explicitly shown in the figure, a photoresist feature or a bottom anti-reflective coating (BARC) feature may be formed over the semiconductor layer 214 to define a gate opening over the channel region C while covering a designated source / drain region (S / D) of the semiconductor layer 214. As will be further described below, when the source / drain region (S / D) is formed along the spreading direction ( Figure 5When the source / drain regions (S / D) sandwich the channel region C along the longitudinal direction ( Figure 5 When the channel region C is clamped in the Y direction in the figure, the resulting back-end device has a large channel width and can be called a high drive current configuration.

[0027] refer to Figure 1 , Figure 5 ,and Figure 6 , the method 100 includes a block 110, wherein a gate structure 220 is formed over the semiconductor layer 214. To better illustrate the layers in the gate structure 220, Figure 5 A portion of the gate structure 220 in FIG. Figure 6 In Figure 6 In some embodiments shown in , the gate structure 220 includes an interface layer 216 on the semiconductor layer 214, a gate dielectric layer 218 above the interface layer 216, and a gate electrode layer 219 above the gate dielectric layer 218. In embodiments where the gate opening is defined by a photoresist feature or a BARC feature in the channel region C, the interface layer 216, the gate dielectric layer 218, and the gate electrode layer 219 are deposited above the gate opening. The interface layer 216 may include silicon oxide, a van der Waals (VDW) air gap, aluminum oxide, or titanium oxide, and may be deposited using ALD, CVD, or a suitable method. The VDW air gap refers to an air gap formed when the semiconductor layer 214 is transferred to the fin structure 212. In some examples, the interface layer 216 may have a thickness between about 0.5 nm and about 1 nm. In some embodiments, the gate dielectric layer 218 may include hafnium oxide, zirconium oxide, hafnium zirconium oxide, or a sandwich structure including hafnium oxide and zirconium oxide, and may be deposited using CVD or a suitable method. The material used for the gate dielectric layer 218 may be referred to as a high-k dielectric material because its dielectric constant is greater than the dielectric constant of silicon oxide, which is approximately 3.9. In some instances, the gate dielectric layer 218 may be between approximately 1.5 nm and approximately 3.5 nm. The gate electrode layer 219 may include titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), ruthenium (Ru), or copper (Cu), and may be deposited using physical vapor deposition (PVD), CVD, or a suitable method. After depositing the interface layer 216, the gate dielectric layer 218, and the gate electrode layer 219, a planarization process, such as a chemical mechanical polishing (CMP) process, is then performed to remove excess material above the photoresist features or BARC features. After planarization, the photoresist features or BARC features are selectively removed by ashing or selective etching to form Figure 5After forming the gate structure 220, the first back-end transistor 400 is formed.

[0028] It should be noted that the thickness ranges of the semiconductor layer 214, the interface layer 216, and the gate dielectric layer 218 in the first back-end transistor 400 (and other back-end transistors described in the present invention) are not trivial and are selected to be similar to their counterparts in transistor 203. The first back-end transistor 400 (and other back-end transistors described in the present invention) has an effective gate dielectric layer thickness substantially the same as that of transistor 203. In other words, the first back-end transistor 400 (and other back-end transistors described in the present invention) has the same threshold voltage as transistor 203. The difference between the first back-end transistor 400 and transistor 203 lies in their location and effective channel width. The first back-end transistor 400 (and other back-end transistors described in the present invention) is located in a BEOL level such as an interconnect structure. Due to the enlarged device area or footprint and the wavy structure, the first back-end transistor 400 has a much larger channel width than transistor 203. As a result, the first back-end transistor 400 (and other back-end transistors described in the present invention) has a much larger drive current than transistor 203.

[0029] refer to Figure 1 and Figure 7 , the method 100 includes block 112, in which a dielectric layer 230 is deposited over the gate structure 220. After forming the gate structure 220, the dielectric layer is deposited over the workpiece 200 using spin coating or flowable CVD (FCVD). The dielectric layer 230 may include tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silica glass (BSG), undoped silica glass (USG), and / or other suitable dielectric materials. The material used for the dielectric layer 230 may be referred to as a low-k dielectric material because its dielectric constant is less than the dielectric constant of silicon oxide, which is approximately 3.9.

[0030] refer to Figure 1 and Figure 8-Figure 11 , the method 100 includes a block 114, in which a source / drain contact 232 connected to the semiconductor layer 214 is formed. As briefly described above, the back-end device of the present invention can be in a low leakage configuration or a high drive current configuration. When low leakage is desired, the length of the channel region C is parallel to the propagation direction of the fin structure 212. When a high drive current is desired, the length of the channel region C is parallel to the longitudinal direction of the fin structure 212. Figure 8 shows a low leakage configuration, Fig.10 A high drive current configuration is shown. Figure 8 The channel region C in the fin structure 212 is sandwiched between the source / drain regions (S / D) along the X direction. Along the X direction, the channel length tracks the topography of the fin structure 212 in the channel region C and is thus maximized. Figure 8 This extended channel length shown in helps reduce leakage. Fig.10 The channel region C in the channel region C is sandwiched between the source / drain regions (S / D) along the Y direction. Along the X direction, the channel width tracks the topography of the fin structure 212 in the channel region C and is therefore maximized. Fig.10 This increased channel width shown in helps to increase the drive current.

[0031] In an exemplary process for forming the source / drain contacts 232, source / drain contact openings are formed through the dielectric layer 230 to expose the semiconductor layer 214 in the source / drain regions (S / D). A metal fill layer is then deposited in the source / drain contact openings to form the source / drain contacts 232. In some embodiments, the metal fill layer may include beryllium (Be), nickel (Ni), platinum (Pt), gold (Au), yttrium (Y), ytterbium (Yb), titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), or a combination thereof, and may be deposited using PVD or CVD. Reference Fig. 9 In an embodiment where a low leakage configuration is desired, each source / drain contact 232 is elongated along the Y direction, parallel to the fin structure 212. Fig.11 In embodiments where a high drive current configuration is desired, each source / drain contact 232 is elongated along the X direction, perpendicular to the longitudinal direction of the fin structure 212 .

[0032] refer to Figure 1 and Fig.12 , the method 100 includes a block 116, in which a second interconnect structure 30 is formed above the dielectric layer 230. In some embodiments, the first interconnect structure 20 below the first back-end transistor 400 and the second interconnect structure 30 above the first back-end transistor 400 are both part of the interconnect structure. The second interconnect structure 30 may include between 4 and 10 metallization layers, each metallization layer including contact vias and wires embedded in an inter-metal dielectric (IMD) layer. In some embodiments where the first back-end transistor 400 is formed on the topmost metallization layer, the operation at block 116 may be omitted, and the workpiece 200 does not include the second interconnect structure 30. In those embodiments, the first interconnect structure 20 is the only front-side interconnect structure.

[0033] As described above, when the operation of block 108 of method 100 is performed before the operation of block 110, the first back-end transistor 400 may be formed. As a result, the gate structure 220 is disposed above the semiconductor layer 214. Since the gate structure 220 is disposed above the semiconductor layer 214, the first back-end transistor 400 may be referred to as a top gate structure 220. Fig.13 and Fig.14 In some alternative embodiments shown in , the operation at block 110 may be performed before the operation at block 108 . Fig.13 2 shows a semiconductor structure 200, wherein a first back gate structure 2200 is formed above the fin structure 212 before forming the semiconductor layer 214. In order to better illustrate the various layers in the first back gate structure 2200, Fig.13 a part of the Fig.14 As shown in Fig.14 As shown in , a first back gate structure 2200 is formed above the fin structure 212, and a semiconductor layer 214 is disposed on the first back gate structure 2200. The first back gate structure 2200 includes a gate electrode layer 219 disposed directly on the fin structure 212, a gate dielectric layer 218 disposed directly on the gate electrode layer 219, and an interface layer 216 disposed directly on the gate dielectric layer 218. Then the semiconductor layer 214 is deposited on the interface layer 216. The materials and deposition methods of the gate electrode layer 219, the gate dielectric layer 218, the interface layer 216, and the semiconductor layer 214 have been described above and will not be repeated here. Fig.13 As shown in , since the semiconductor layer 214 is now located above the first back gate structure 2200, the source / drain contact 233 can land directly on the semiconductor layer 214. For ease of reference, Fig.13 and Fig.14 The back-end transistor shown in can be referred to as the second back-end transistor 402.

[0034] exist Fig.15 and Fig.16 In some embodiments shown in FIG. 1 , a gate electrode layer 219 is deposited and patterned to form a wavy gate electrode 2192, which includes Figure 4 In order to better illustrate the details, Fig.15 a part of the Fig.16. After forming the wavy gate electrode 2192, a gate dielectric layer 218 is deposited over the wavy gate electrode 2192. Then an interface layer 216 is deposited over the gate dielectric layer 218. A semiconductor layer 214 is deposited over the interface layer. The materials and deposition methods of the gate dielectric layer 218, the interface layer 216, and the semiconductor layer 214 have been described above and will not be repeated here. The wavy gate electrode 2192 has the same composition as the gate electrode layer 219. For ease of reference, the wavy gate electrode 2192, the gate dielectric layer 218, and the interface layer 216 may be collectively referred to as a second back gate structure 2202.

[0035] The patterning of the dielectric spacer layer at block 106 of method 100 includes using a photolithography process to form the fin structure 212. In some alternative embodiments, for example Fig.17 The method 300 may introduce a self-aligned etching process to reduce the complexity of the photolithography process and the photomask used in the photolithography process.

[0036] refer to Fig.17 and Fig.18 The method 300 includes a block 302, wherein a workpiece 200 is received. Figure 2 As shown in , the workpiece 200 may include a device substrate 10 and a first interconnect structure 20 disposed above the device substrate 10. The device substrate 10 may include a semiconductor substrate 202 and a transistor 203 on the semiconductor substrate 202. The semiconductor substrate 202 may be a silicon (Si) substrate. In some other embodiments, the semiconductor substrate 202 may include other semiconductors, such as germanium (Ge), silicon germanium (SiGe), or III-V semiconductor materials. Exemplary III-V semiconductor materials may include gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), gallium nitride (GaN), gallium arsenic phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium phosphide (GaInP), and indium gallium arsenide (InGaAs). The semiconductor substrate 202 may also include an insulating layer, such as a silicon oxide layer, to have a silicon on insulator (SOI) structure.

[0037] Each transistor 203 can be a multi-gate device. Here, a multi-gate device generally refers to a device having a gate structure, or a portion thereof, that is disposed above more than one side of a channel region. Fin field effect transistors (FinFETs) and gate-all-around (GAA) transistors are examples of multi-gate devices that have become popular and promising candidates for high-performance and low-leakage applications. FinFETs have a high-side channel surrounded by a gate on more than one side (e.g., the gate surrounds the top and sidewalls of a "fin" of semiconductor material extending from a substrate). The gate structure of a GAA transistor can extend partially or completely around the channel region to provide access to the channel region on two or more sides. Because its gate structure surrounds the channel region, a GAA transistor may also be referred to as a wrap-around gate transistor (SGT) or a multi-bridge channel (MBC) transistor. The channel region of a GAA transistor may be in the form of a nanowire, a nanosheet, or other nanostructure, and therefore, a GAA transistor may also be referred to as a nanowire transistor or a nanosheet transistor. As Figure 2 As shown in FIG. 1 , each transistor 203 includes a channel region 204 extending between two source / drain features 206 along the X direction. A gate structure 210 is disposed above the channel region 204. The transistors 203 may be spaced apart from each other by isolation features 208. Figure 2 It is not explicitly shown, but when the transistor 203 is a GAA transistor, the channel region 204 includes a plurality of channel components extending between two source / drain features 206 along the X direction, and the gate structure 210 surrounds each of the plurality of channel components in the channel region 204 .

[0038] Figure 2 The first interconnect structure 20 shown in the figure can be part of an interconnect structure, which can also include a second interconnect structure 30 (described below). In this regard, the first interconnect structure 20 is disposed below the back-end active device, while the second interconnect structure 30 is disposed above the back-end active device. The first interconnect structure 20 and the second interconnect structure 30 as a whole can include between about 8 and about 15 metallization layers, each metallization layer including contact vias and wires embedded in an inter-metal dielectric (IMD) layer. Since the lower metallization layers closer to the device substrate 10 are generally too crowded to accommodate the back-end devices, the first interconnect structure 20 may include 4 to 5 metallization layers. In the depicted example, the first interconnect structure 20 includes 4 metallization layers—M1, M2, M3, and M4.

[0039] refer to Fig.17 and Fig.19 The method 300 includes block 304, in which a metallization layer is formed over the first interconnect structure 20. Fig.19As shown in , the metallization layer formed at block 304 may be part of an M4 metallization layer M4. Fig.19 The metallization layer in includes an IMD layer 241 and a power pad 240, an analog power pad 242, and a plurality of fin gate electrodes 244 embedded in the IMD layer 241. In some embodiments, the power pad 240, the analog power pad 242, and the plurality of fin gate electrodes 244 include titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), ruthenium (Ru), or copper (Cu). In some embodiments, the power pad 240 is electrically connected to a positive power supply voltage (Vdd), and the analog power pad 242 is electrically connected to a logic circuit implemented using transistor 203. Each of the plurality of fin gate electrodes 244 extends longitudinally along the Y direction.

[0040] refer to Fig.17 and Fig. 20 , the method 300 includes a block 306, wherein the IMD layer 241 in the metallization layer is selectively etched back to expose the fin structure gate electrode 244. The operation at block 306 forms a gate trench 246. To form the gate trench 246, a patterned mask 243 is formed over the metallization layer formed at block 304. The patterned mask 243 may include a patterned photoresist layer or a patterned BARC layer. Fig. 20 In some embodiments not explicitly shown in FIG. 2 , one or more hard mask layers may be deposited over the workpiece 200 prior to depositing the patterned mask 243 . Fig. 20 In some embodiments represented in , the patterned mask 243 completely covers the power pad 240 and the analog power pad 242. Although the etching process at box 306 is selective to the IMD layer 241, it also recesses the multiple fin gate electrodes 244 to reduce their height. In some embodiments, the etching process at box 306 may include a dry etching process, and the dry etching process includes using oxygen-containing gas, hydrogen, nitrogen, fluorine-containing gas (e.g., NF3, CF4, SF6, CH2F2, CHF3, and / or C2F6), chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and / or BCl3), bromine-containing gas (e.g., HBr and / or CHBr3), iodine-containing gas (e.g., CF3I). Fig. 20 As shown in FIG. 2 , after etching back, the recessed fin gate electrode 244 is exposed and raised above the IMD layer 241 .

[0041] refer to Fig.17 , Fig.21 ,and Fig. 22The method 300 includes block 308, where a gate dielectric layer 250 is deposited over the fin gate electrode 244 in the gate trench 246. In some embodiments, the gate dielectric layer 250 may include hafnium oxide, zirconium oxide, hafnium zirconium oxide, or a sandwich structure including hafnium oxide and zirconium oxide, and may be deposited using CVD or a suitable method. Fig.21 As shown in FIG. 2 , the gate dielectric layer 250 is conformally deposited in the gate trench 246, directly contacting the top surface of the fin gate electrode 244 and the exposed surface of the IMD layer 241. In order to show the fin gate electrode 244 and the layers deposited thereon in more detail, Fig.21 a part of the Fig. 22 As shown in Fig. 22 As shown in FIG. 8 , the gate dielectric layer 250 is deposited directly on the fin gate electrode 244 .

[0042] refer to Fig.17 , Fig.21 ,and Fig. 22 , the method 300 includes a block 310, wherein an interfacial layer 252 is deposited over the gate dielectric layer 250. The interfacial layer 252 may include silicon oxide, VDW air gap, aluminum oxide, or titanium oxide, and may be deposited using CVD or a suitable method. In some examples, the interfacial layer 252 may have a thickness between about 1.5 nm and about 3.5 nm. To illustrate the fin gate electrode 244 and the layers deposited thereon in more detail, Fig.21 a part of the Fig. 22 As shown in Fig. 22 As shown in , the fin gate electrode 244 , the gate dielectric layer 250 , and the interface layer 252 may be referred to as a third back gate structure 2204 .

[0043] refer to Fig.17 , Fig.21 ,and Fig. 22 , method 300 includes block 312, where a semiconductor layer 254 is deposited over the interface layer 252. In some embodiments, the semiconductor layer 254 may be a two-dimensional (2D) or low-dimensional semiconductor layer that can be satisfactorily deposited at a temperature that does not cause substantial damage to the front-end structure. Exemplary semiconductor materials for the semiconductor layer 254 may include molybdenum sulfide (MoS2), tungsten selenide (WSe2), cuprous oxide (Cu2O), carbon nanotubes (CNTs), indium oxide (InO), or indium gallium zinc oxide (IGZO). To illustrate the semiconductor layer 254 and the layers deposited thereon in more detail, Fig.21 a part of the Fig. 22In some embodiments, the semiconductor layer 254 can be conformally deposited over the surface of the interfacial layer 252 exposed in the gate trench 246. In some examples, the semiconductor layer 254 can have a thickness between about 0.5 nm and about 10 nm.

[0044] refer to Fig.17 and Fig.23 , method 300 includes box 314, in which a dielectric layer 256 is deposited over the semiconductor layer 254. After depositing the semiconductor layer 254, the dielectric layer 256 is deposited over the workpiece 200 using spin coating or flowable CVD (FCVD). The dielectric layer 256 may include tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped quartz glass (BSG), undoped quartz glass (USG), and / or other suitable dielectric materials. The material used for the dielectric layer 256 may be referred to as a low-k dielectric material because its dielectric constant is less than the dielectric constant of silicon oxide, which is approximately 3.9. After depositing the dielectric layer 256, a planarization process, such as a chemical mechanical polishing (CMP) process, is performed to remove excess material and provide a flat top surface. As Fig.23 As shown in FIG. 1 , after the planarization process, the top surfaces of the power pad 240 , the gate dielectric layer 250 , the interface layer 252 , the semiconductor layer 254 , the dielectric layer 256 , the analog power pad 242 , and the IMD layer 241 are coplanar.

[0045] refer to Fig.17 and Fig.24 , method 300 includes box 316, in which a source / drain contact 260 connected to the semiconductor layer 254 is formed. In an exemplary process for forming the source / drain contact 260, a source / drain contact opening is formed through the dielectric layer 256 to expose the semiconductor layer 254 in the source / drain region. A metal fill layer is then deposited in the source / drain contact opening to form the source / drain contact 260. In some embodiments, the metal fill layer may include beryllium (Be), nickel (Ni), platinum (Pt), gold (Au), yttrium (Y), ytterbium (Yb), titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), or a combination thereof, and may be deposited using PVD or CVD. Reference Fig.24 In embodiments where a low leakage configuration is desired, each source / drain contact 260 is elongated along the Y direction, parallel to the fin gate electrode 244 . Fig.24 The back-end transistor shown in FIG. 404 may be referred to as a third back-end transistor 404. Figure 25-28In embodiments requiring a high drive current configuration, each source / drain contact 260 is elongated along the X direction, perpendicular to the longitudinal direction of the fin-shaped gate electrode 244 . Figure 25-28 The back-end transistor shown in can be referred to as a fourth back-end transistor 406. Fig.25 is a partial top view of the fourth back-end transistor 406. Fig.26 , Fig. 27 ,and Fig.28 Partial cross-sectional views along lines A-A', B-B', and CC' are shown. Fig.25 and Fig. 27 As shown in FIG. 1 , metal line 270 and contact vias connected thereto electrically connect one of source / drain contacts 260 to power supply pad 240. Fig.25 and Fig.28 As shown in , another metal line 272 and a contact via connected thereto electrically connect another one of the source / drain contacts 260 to the analog power pad 242 .

[0046] refer to Fig.17 and Fig.29 , the method 300 includes a block 318, in which a second interconnect structure 30 is formed over the dielectric layer 230. In some embodiments, the first interconnect structure 20 under the third back-end device 404 and the second interconnect structure 30 over the third back-end transistor 404 are both part of the interconnect structure. The second interconnect structure 30 may include between 4 and 10 metallization layers, each metallization layer including contact vias and wires embedded in an inter-metal dielectric (IMD) layer. In some embodiments in which the third back-end transistor 404 is formed on the topmost metallization layer, the operation at block 318 may be omitted, and the workpiece 200 does not include the second interconnect structure 30. In those embodiments, the first interconnect structure 20 is the only front-side interconnect structure.

[0047] The method 300 may also be used to form a dual-gate back-end device, which has not only a back-gate structure but also a top-gate structure. Fig.30 and Fig.31A fifth back-end transistor 408 is shown, which includes a third back-gate structure 2204 below the semiconductor layer 254 and also includes a top gate structure 2206. The formation of the third back-gate structure 2204 and the semiconductor layer 254 has been described above, and the relevant content will be omitted for the sake of brevity. As an alternative to depositing the dielectric layer 256 above the semiconductor layer 254, a top interface layer 2520 is deposited above the semiconductor layer 254, a top gate dielectric layer 2500 is deposited above the top interface layer 2520, and a top gate electrode layer 258 is deposited above the top gate dielectric layer 2500 to form a top gate structure 2206. The composition and formation process for the top interface layer 2520, the top gate dielectric layer 2500, and the top gate electrode layer 258 can be similar to the composition and formation process of the interface layer 252, the gate dielectric layer 250, and the bottom gate electrode layer 244, respectively. Therefore, detailed descriptions of the top interface layer 2520, the top gate dielectric layer 2500, and the top gate electrode layer 258 are omitted. Fig.30 and Fig.31 It is not explicitly shown in FIG. 4 , but the source / drain contacts for the fifth back-end transistor 408 may be elongated along the X direction to have a high drive current configuration.

[0048] The low leakage configuration of the fifth back-end transistor 408 is Fig.32 and Fig.33 As shown in Fig.32 and Fig.33 As shown in FIG. 2 , the source / drain contacts 262 are connected to the source / drain regions not covered by the top gate structure 2206. The source / drain contacts 262 land directly on the semiconductor layer 254 rather than extending through the top gate structure 2206. Since the channel length between the two source / drain contacts 262 tracks above and below the fin gate structure 244, the channel length is increased to reduce leakage.

[0049] exist Fig.34 and Fig.35 In some embodiments shown in , the method 300 can also be applied to the backside interconnect structure 10B to form the sixth back-end transistor 410. Fig.34 In the embodiment, the workpiece 200 includes not only the front interconnect structures 20 and 30, but also the back interconnect structure 10B. By following similar operations in the method 300 to form the back fin gate structure 244B and other layers in the back gate structure 2208, a sixth back-end transistor 410 can be formed in the back interconnect structure 10B. For better illustration, a portion of the sixth back-end transistor 410 is enlarged and shown in FIG. Fig.35 As shown in Fig.35As shown in FIG. 2 , the back gate structure 2208 includes a back fin gate structure 244B, a gate dielectric layer 250, and an interface layer 252. The interface layer 252 is bonded to the top surface of the semiconductor layer 254 (at Fig.35 A back dielectric layer 274 may be deposited over the semiconductor layer 254 for insulation.

[0050] The back-end transistor of the present invention, whether in a low leakage configuration or a high drive current configuration, can be implemented in combination with different memory devices. Fig.36 A low leakage first back end transistor 400 connected to an embedded dynamic random access memory (eDRAM) device 500 is shown. Fig.37 , Fig.38 ,and Fig.39 A high drive current first back-end transistor 400 integrated into a ferroelectric field effect transistor (FeFET) 440 is shown. Fig.40 and Fig.41 A low leakage first back end transistor 400 used as an access device for a magnetoresistive random access memory (MRAM) device 600 is shown. Fig.42 and Fig.43 A low leakage first back end transistor 400 used as an access device for a resistive random access memory (ReRAM) device 700 is shown.

[0051] refer to Fig.36 , the eDRAM device 500 can be disposed on the source / drain contact 232 of the first back-end transistor 400 and connected thereto. The eDRAM device 500 can have a metal-insulator-metal (MIM) structure. In the depicted embodiment, a trench is formed above the source / drain contact 232, and a high-k dielectric layer 510 is deposited above the trench. In some embodiments, the high-k dielectric layer 510 includes a zirconium oxide layer. The eDRAM device 500 also includes a top electrode 520 above the high-k dielectric layer 510. In some examples, the top electrode 520 can include titanium nitride (TiN), tungsten (W), or copper (Cu).

[0052] Fig.37 The FeFET 440 and the first back-end transistor 400 formed in the fifth metallization layer M5 above the M4 metallization layer are shown. Fig.38 As shown in , each FeFET 440 is built on the first back-end transistor 400 described above. Fig.38In some embodiments shown in , the FeFET 440 includes a semiconductor layer 214 formed over a fin structure 212 formed of a dielectric spacer material. An interface layer 216 is disposed on and in contact with the semiconductor layer 214. A gate dielectric layer 218 is disposed on and in contact with the interface layer 216, and a gate electrode layer 219 is disposed on and in contact with the gate dielectric layer 218. The thickness, formation process, and composition of the semiconductor layer 214, the interface layer 216, the gate dielectric layer 218, and the gate electrode layer 219 have been described in detail above and will not be repeated here for the sake of brevity. In the depicted embodiment, although the bottom surface of the gate electrode layer 219 tracks the shape of the fin structure 212 and has a wavy profile, the top surface of the gate electrode layer 219 is flat or planar. The ferroelectric layer 430 is deposited on and in contact with the flat top surface of the gate electrode layer 219. As a result, the effective width of the interface layer 216 is greater than the effective width of the ferroelectric layer 430. The ferroelectric layer 430 may include hafnium zirconium oxide (HZO) and have a crystal structure exhibiting ferroelectricity. Fig.38 In some embodiments not explicitly described herein, the gate dielectric layer 218 may be formed from Fig.38 It is completely omitted in the structure shown in .

[0053] because Fig.38 The FeFET in the Fig.38 The source / drain regions and source / drain contacts of the FeFET 440 are not shown. Fig.39 As shown in FIG. 4 , in the top view, the Y direction is upward on the paper rather than into the paper, and the channel width of the FeFET 440 extends along the X direction, perpendicular to the Y direction, and the fin structure 212 extends longitudinally along the width and remains parallel. Fig.39 As shown in FIG, source / drain contacts 450 of FeFET 440 are spaced apart on both sides of ferroelectric layer 430 or gate structure 220. The gate voltage applied to FeFET 440 can change the dipole moment in ferroelectric layer 430. The dipole moment can be used as a bias to change the threshold voltage of FeFET 440. In this sense, FeFET 440 can be used as a memory device.

[0054] refer to Fig.40 , the MRAM device 600 may be disposed on the source / drain contact 232 of the first back-end transistor 400 and connected thereto. The MRAM device 600 may have a magnetic tunnel junction (MTJ) structure. Fig.41In the embodiment depicted in , the MRAM device 600 includes a bottom electrode 610, a synthetic antiferromagnetic (SAF) layer 612 above the bottom electrode 610, a spacer layer 614 above the SAF layer 612, a reference layer 616 above the spacer layer 614, an oxide barrier layer 618 above the reference layer 616, a free layer 620 above the oxide barrier layer 618, a capping layer 622 above the free layer 620, and a top electrode 624 above the capping layer 622. In some embodiments, the bottom electrode 610 and the top electrode 624 may include titanium nitride (TiN), copper (Cu), tungsten (W), or nickel (Ni). The SAF layer 612 may include cobalt (Co), platinum (Pt), or a combination thereof. The spacer layer 614 and the capping layer 622 may include titanium (Ti) or tantalum (Ta). The free layer 620 and the reference layer 616 may include cobalt (Co), iron (Fe), boron (B), ruthenium (Ru), etc. The oxide barrier layer 618 may include magnesium oxide (MgO), aluminum oxide (Al 2 O 3 ), or the like.

[0055] refer to Fig.42 , the ReRAM device 700 may be disposed on the source / drain contact 232 of the first back-end transistor 400 and connected thereto. Fig.43 As shown, the ReRAM device 700 may include a bottom electrode 710, a switching medium (SM) layer 720 above the bottom electrode 710, and a top electrode 730 above the SM layer 720. In some embodiments, the bottom electrode 710 and the top electrode 730 may include titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), or ruthenium (Ru). The SM layer 720 may include hafnium oxide.

[0056] In one exemplary aspect, the present invention relates to a semiconductor structure. The semiconductor structure includes: a semiconductor substrate; a plurality of transistors disposed on the semiconductor substrate and including a plurality of gate structures extending longitudinally along a first direction; a metallization layer disposed above the plurality of transistors, the metallization layer including a plurality of metal layers and a plurality of contact vias; a dielectric layer located above the metallization layer; a plurality of dielectric fins extending in parallel along a first direction and disposed above the dielectric layer; a semiconductor layer conformally disposed above the plurality of dielectric fins; a source contact and a drain contact disposed directly above the semiconductor layer; and a gate structure disposed above the semiconductor layer and between the source contact and the drain contact.

[0057] In some embodiments, the semiconductor layer includes a low-dimensional semiconductor material. In some embodiments, the low-dimensional semiconductor material includes molybdenum sulfide (MoS2), tungsten selenide (WSe2), carbon nanotubes, indium oxide, or indium gallium zinc oxide (IGZO). In some embodiments, the gate structure is disposed between the source contact and the drain contact along a first direction. In some instances, the gate structure is disposed between the source contact and the drain contact along a second direction perpendicular to the first direction. In some embodiments, the gate structure includes: an interface layer disposed on the semiconductor layer; a gate dielectric layer disposed above the interface layer; and a gate electrode disposed above the gate dielectric layer. In some embodiments, the interface layer includes silicon oxide, a van der Waals air gap, aluminum oxide, or titanium oxide. In some instances, the gate dielectric layer includes hafnium oxide, zirconium oxide, hafnium zirconium oxide, or a combination thereof. In some embodiments, the gate electrode includes titanium nitride, tantalum nitride, tungsten, ruthenium, or copper.

[0058] In another exemplary aspect, the present invention relates to a semiconductor structure. The semiconductor structure includes: a first dielectric layer; a plurality of metal lines partially disposed in the first dielectric layer and extending longitudinally along a first direction; a gate dielectric layer conformally disposed above and in direct contact with the top surfaces of the first dielectric layer and the plurality of metal lines; an interface layer conformally disposed above the gate dielectric layer; a semiconductor layer disposed above the interface layer; a second dielectric layer disposed above the semiconductor layer; and a source contact and a drain contact extending through the second dielectric layer to contact the semiconductor layer.

[0059] In some embodiments, the topmost surface of the first dielectric layer is higher than the top surfaces of the plurality of metal lines. In some embodiments, the topmost surface of the first dielectric layer is coplanar with the top surface of the second dielectric layer. In some embodiments, a portion of the gate dielectric layer, a portion of the interface layer, and a portion of the semiconductor layer extend below the top surfaces of the plurality of metal lines. In some embodiments, the gate dielectric layer comprises hafnium oxide, zirconium oxide, hafnium zirconium oxide, or a combination thereof. In some embodiments, the semiconductor layer comprises molybdenum sulfide (MoS2), tungsten selenide (WSe2), cuprous oxide (Cu2O), carbon nanotubes, indium oxide, or indium gallium zinc oxide (IGZO).

[0060] In another exemplary aspect, the present invention relates to a method for forming a semiconductor structure. The method includes: forming a transistor on a substrate; forming a metallization layer above the transistor, so that the metallization layer includes a first dielectric layer and a plurality of metal lines disposed in the first dielectric layer and extending longitudinally along a first direction; etching the first dielectric layer and the plurality of metal lines to form a recess; depositing a gate dielectric layer above the recess; depositing an interface layer above the gate dielectric layer; depositing a semiconductor layer above the interface layer; depositing a second dielectric layer above the semiconductor layer; after depositing the second dielectric layer, planarizing the first dielectric layer and the second dielectric layer; and forming a source contact and a drain contact through the second dielectric layer to contact the semiconductor layer.

[0061] In some embodiments, after etching, the top surface of the plurality of metal lines in the recess rises above the top surface of the first dielectric layer in the recess. In some embodiments, the gate dielectric layer is in direct contact with the top surface of the plurality of metal lines. In some examples, the semiconductor layer includes molybdenum sulfide (MoS2), tungsten selenide (WSe2), cuprous oxide (Cu2O), carbon nanotubes, indium oxide, or indium gallium zinc oxide (IGZO). In some embodiments, the gate dielectric layer includes hafnium oxide, zirconium oxide, hafnium zirconium oxide, or a combination thereof.

[0062] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for performing the same or similar purposes and / or achieving the same or similar advantages as the present disclosure. Those skilled in the art should also be aware that such equivalent structures do not depart from the spirit and scope of the present disclosure, and various changes, substitutions and modifications can be made without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor structure comprising: Semiconductor substrate; A plurality of transistors are disposed on the semiconductor substrate and include a plurality of gate structures extending longitudinally along a first direction; A metallization layer is disposed above the plurality of transistors, the metallization layer comprising a plurality of metal layers and a plurality of contact vias; a dielectric layer located above the metallization layer; a plurality of dielectric fins extending in parallel along the first direction and disposed above the dielectric layer; a semiconductor layer conformally disposed over the plurality of dielectric fins; a source contact and a drain contact disposed directly above the semiconductor layer; as well as The gate structure is disposed above the semiconductor layer and between the source contact and the drain contact.

2. The semiconductor structure according to claim 1, wherein: The semiconductor layer includes a low-dimensional semiconductor material.

3. The semiconductor structure according to claim 2, wherein: The low-dimensional semiconductor material includes molybdenum sulfide (MoS2), tungsten selenide (WSe2), carbon nanotubes, indium oxide, or indium gallium zinc oxide (IGZO).

4. The semiconductor structure according to claim 1, wherein: The gate structure is disposed between the source contact and the drain contact along the first direction.

5. The semiconductor structure according to claim 1, wherein: The gate structure is disposed between the source contact and the drain contact along a second direction perpendicular to the first direction.

6. The semiconductor structure according to claim 1, wherein: The gate structure comprises: An interface layer, disposed on the semiconductor layer; a gate dielectric layer located above the interface layer; and The gate electrode is located above the gate dielectric layer.

7. A semiconductor structure comprising: a first dielectric layer; a plurality of metal lines partially disposed in the first dielectric layer and extending longitudinally along a first direction; a gate dielectric layer conformally disposed above and in direct contact with top surfaces of the first dielectric layer and the plurality of metal lines; an interface layer conformally disposed above the gate dielectric layer; A semiconductor layer, disposed above the interface layer; A second dielectric layer disposed above the semiconductor layer; as well as A source contact and a drain contact extend through the second dielectric layer to contact the semiconductor layer.

8. A method of forming a semiconductor structure, comprising: forming a transistor on a substrate; A metallization layer is formed above the transistor, the metallization layer comprising: a first dielectric layer, and a plurality of metal lines disposed in the first dielectric layer and extending longitudinally along a first direction; etching the first dielectric layer and the plurality of metal lines to form recesses; depositing a gate dielectric layer over the recess; depositing an interfacial layer over the gate dielectric layer; depositing a semiconductor layer over the interface layer; depositing a second dielectric layer over the semiconductor layer; After said depositing said second dielectric layer, planarizing said first dielectric layer and said second dielectric layer; and A source contact and a drain contact are formed through the second dielectric layer to contact the semiconductor layer.

9. The method according to claim 8, wherein: After the etching, top surfaces of the plurality of metal lines in the recess rise above a top surface of the first dielectric layer in the recess.

10. The method according to claim 9, wherein: The gate dielectric layer is in direct contact with the top surfaces of the plurality of metal lines.

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