Transistors with dielectric spacing and methods of making same

Abstract

A transistor device and a method of manufacture are provided in which the transistor device may include a semiconductor substrate, a first dielectric layer disposed on a surface of the semiconductor substrate, a second dielectric layer disposed directly on the first dielectric layer, a gate structure disposed directly on the surface of the semiconductor substrate, and a gate electrode disposed directly on the gate structure. And a spacer structure. A first opening through the first dielectric layer and the second dielectric layer may correspond to a gate channel. Portions of the first dielectric layer and the second dielectric layer may be directly between a portion of the gate structure and the surface of the semiconductor substrate. The spacer structure may be disposed in the gate channel and between the gate structure and the semiconductor substrate. The spacer structure may be in contact with respective side surfaces of the first dielectric layer and the second dielectric layer that at least partially define the gate channel.

Description

Technical Field

[0001] Embodiments of the subject matter described herein relate generally to transistor devices, and more particularly, to semiconductor power transistor dielectric spacing. Background Art

[0002] High power field effect transistor (FET) devices are widely used in a variety of electronic components and systems. Although various advances have been made in improving the gain, efficiency and other characteristics of power FETs used to provide amplification in radio frequency (RF) communication systems, challenges remain in manufacturing such devices. For example, due in part to the transparency of silicon carbide (SiC) substrates and in part due to side effects such as heteroepitaxial growth (used to grow gallium nitride (GaN) on SiC) resulting in a lack of sufficiently uniform flatness of GaN substrates on SiC, manufacturing FETs with short gate lengths using only photolithography is more challenging for GaN-based FETs on SiC than for silicon (Si)-based FETs. As another example, dielectric layers exposed to multiple dry etching processes during device fabrication may experience plasma damage and etching-induced thickness variations, thereby unduly affecting performance and reliability. Summary of the invention

[0003] A brief overview of various exemplary embodiments is presented below. Some simplifications and omissions may be made in the following overview, which is intended to highlight and introduce some aspects of the various exemplary embodiments, but not to limit the scope. A detailed description of the exemplary embodiments sufficient to allow a person of ordinary skill in the art to obtain and use these concepts will be presented in subsequent sections.

[0004] In an example embodiment, a transistor device includes a semiconductor substrate; a first dielectric layer, the first dielectric layer being disposed on a surface of the semiconductor substrate; a second dielectric layer, the second dielectric layer being disposed directly on the first dielectric layer; a gate structure, the gate structure being disposed directly on the surface of the semiconductor substrate in the gate channel; and at least one dielectric spacer structure, the at least one dielectric spacer structure being disposed in the gate channel and between the gate structure and the semiconductor substrate. The gate channel is at least partially defined by a first opening extending through the first dielectric layer and the second dielectric layer. Portions of the first dielectric layer and the second dielectric layer are directly between portions of the gate structure and the surface of the semiconductor substrate. The at least one dielectric spacer structure is in direct contact with respective side surfaces of the first dielectric layer and the second dielectric layer that at least partially define the gate channel.

[0005] In one or more embodiments, the at least one dielectric spacer structure comprises a first layer and a second layer. The first layer is arranged to be in direct contact with the respective side surfaces of the first dielectric layer and the second dielectric layer and with the surface of the semiconductor substrate. The second layer is arranged to be in direct contact with each of the first layer and the gate structure.

[0006] In one or more embodiments, a portion of the first layer is disposed directly between the second dielectric layer and the surface of the semiconductor substrate.

[0007] In one or more embodiments, the transistor device further includes an interlayer dielectric layer disposed over the first dielectric layer, the second dielectric layer, and the gate structure.

[0008] In one or more embodiments, the transistor device further includes a field plate, which is arranged to at least partially overlap the interlayer dielectric layer and the gate structure, such that the interlayer dielectric layer is interposed between the gate structure and the field plate.

[0009] In one or more embodiments, the field plate extends through the first dielectric layer, the second dielectric layer, and a second opening in the interlayer dielectric layer. The second opening at least partially defines a field plate trench.

[0010] In one or more embodiments, the transistor device further includes a third dielectric layer, which is directly disposed on the surfaces of the interlayer dielectric layer, the first dielectric layer and the second dielectric layer, and on the surface of the semiconductor substrate, wherein the field plate is directly disposed on the third dielectric layer.

[0011] In one or more embodiments, the third dielectric layer is disposed in the field plate trench and separates the field plate from the surface of the semiconductor substrate.

[0012] In an example embodiment, a method for manufacturing a transistor device includes the following steps: providing a semiconductor substrate; forming a first dielectric layer on the semiconductor substrate; forming a second dielectric layer on the first dielectric layer; forming a gate trench by performing a patterned dry etch to form a first opening in the second dielectric layer and performing a first wet etch to form a second opening in the first dielectric layer; forming a dielectric spacer structure in the gate trench; and forming a gate structure, the gate structure being at least partially disposed in the gate trench and contacting surfaces of the semiconductor substrate, the second dielectric layer, and the dielectric spacer structure.

[0013] In one or more embodiments, forming the dielectric spacer structure includes: forming a first layer over the semiconductor substrate and in the gate trench; forming a second layer on the first layer; and etching to remove a portion of the first layer and a portion of the second layer.

[0014] In one or more embodiments, the first layer includes an oxide material and the second layer includes a nitride material.

[0015] In one or more embodiments, etching to remove a portion of the first layer and a portion of the second layer includes: performing a dry etch to remove the portion of the second layer; and performing a second wet etch to remove the portion of the first layer.

[0016] In one or more embodiments, performing the patterned etching to remove a portion of the first layer and a portion of the second layer includes: performing dry etching to remove the portion of the second layer; forming a first patterned photoresist layer having a third opening overlapping the gate channel above the semiconductor substrate; forming a second patterned photoresist layer having a fourth opening overlapping the gate channel above the semiconductor substrate; and after forming the first patterned photoresist layer and the second patterned photoresist layer, performing a second wet etching to remove the portion of the first layer.

[0017] In one or more embodiments, the method further includes: forming an interlayer dielectric layer on the gate structure and the second dielectric layer; and forming a field plate over the interlayer dielectric layer, wherein at least a portion of the field plate overlaps the gate structure.

[0018] In one or more embodiments, a first patterned dry etch is performed to further form a fifth opening in the second dielectric layer, and the first wet etch is performed to further form a sixth opening in the first dielectric layer overlapping with the fifth opening to expose the surface of the semiconductor substrate, the fifth opening and the sixth opening correspond to a field plate channel, and the field plate is at least partially disposed in the field plate channel.

[0019] In one or more embodiments, forming the first layer further includes forming the first layer in the field plate trench.

[0020] In one or more embodiments, the method further includes performing a second patterned dry etch to form a seventh opening in the interlayer dielectric layer, exposing a portion of the first layer through the seventh opening.

[0021] In one or more embodiments, the method further includes: before forming the field plate, performing a third wet etch to remove the portion of the first layer exposed through the seventh opening; and before forming the field plate, forming a third dielectric layer disposed on the surface of the interlayer dielectric layer and on the surface of the semiconductor substrate in the field plate channel.

[0022] In one or more embodiments, forming the gate structure includes: forming a first patterned photoresist layer having a third opening overlapping the gate channel above the semiconductor substrate; forming a second patterned photoresist layer having a fourth opening overlapping the gate channel above the semiconductor substrate; and depositing metal above the semiconductor substrate, a first portion of the metal being deposited through the third opening and the fourth opening to form the gate structure, and a second portion of the metal being deposited on a surface of the first patterned photoresist layer.

[0023] In one or more embodiments, the method further includes removing the second portion of the metal by simultaneously removing the first patterned photoresist layer and the second patterned photoresist layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] A more complete understanding of the subject matter may be obtained by referring to the detailed description and claims when considered in conjunction with the following drawings, in which like reference numerals refer to like elements throughout the drawings.

[0025] Figure 1 is a cross-sectional side view of a transistor device according to various embodiments.

[0026] Figure 2 is a method for manufacturing a Figure 1 A process flow chart of a method for a transistor device.

[0027] Figure 3-16 is a diagram depicting a schematic diagram of a semiconductor device in various stages of manufacture according to various embodiments. Figure 1 Cross-sectional view of a transistor device.

[0028] Fig.17 is a cross-sectional side view of a transistor device according to various embodiments.

[0029] Fig.18 is a method for manufacturing a Fig.17 A process flow chart of a method for a transistor device.

[0030] Figure 19-35 is a diagram depicting a schematic diagram of a semiconductor device in various stages of manufacture according to various embodiments. Fig.17 Cross-sectional view of a transistor device. DETAILED DESCRIPTION

[0031] The following detailed description is merely illustrative in nature and is not intended to limit the subject matter or the embodiments of the present application and the use of these embodiments. In addition, there is no intention to be bound by any explicit or implicit theory presented in the foregoing technical field, background technology or the following detailed description.

[0032] For simplicity and clarity of illustration, the drawings illustrate general constructions, and descriptions and details of well-known features and techniques may be omitted to avoid unnecessary confusion of the embodiments described herein. In addition, the elements in the drawings may not be drawn to scale. For example, the dimensions of certain elements or regions in the drawings may be enlarged relative to other elements or regions to help improve understanding of the embodiments described herein.

[0033] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims can be used to distinguish similar elements, and are not necessarily used to describe a specific sequence or time order. It should be understood that the terms used in this way are interchangeable where appropriate, so that the embodiments described herein can, for example, operate in a sequence different from the sequence shown or described herein. In addition, the terms "including", "having" and any variations thereof are intended to cover non-exclusive inclusions, so that the process, method, object or device including a series of elements is not necessarily limited to those elements, but may include other elements that are not explicitly listed or inherent to such a process, method, object or device. As used herein, the term "coupled" is defined as being connected directly or indirectly in an electrical or non-electrical manner. As used herein, the terms "substantially" and "substantially" mean that it is sufficient to achieve the purpose of the statement in a practical manner, and slight defects (if any) are not important for the purpose of the statement. As used herein, the words "exemplary" and "example" mean "serving as an example, instance or illustration". Any embodiment described as exemplary or example herein should not necessarily be interpreted as being preferred or advantageous over other embodiments.

[0034] Unless otherwise stated, directional references such as "top", "bottom", "left", "right", "above", "below", etc. are not intended to require any preferred orientation, but are made for illustration purposes with reference to the orientation of the corresponding figure or figures.

[0035] For the sake of brevity, conventional semiconductor manufacturing techniques may not be described in detail herein. In addition, certain terms may also be used herein for reference only and are therefore not intended to be limiting. For example, unless the context clearly indicates, the terms "first", "second", and other such numerical terms referring to structures do not imply a sequence or order.

[0036] Various embodiments described herein relate to transistor devices and associated fabrication methods in which one or more dielectric layers damaged by exposure to dry etching (e.g., due to plasma damage) are removed and replaced (at least partially) during a fabrication process. As will be described, removal and replacement of dry-etch damaged dielectric layers can advantageously reduce performance variations in such dielectric layers, can advantageously improve thickness uniformity of dielectric layers in transistor devices, and can advantageously reduce the incidence of charge carrier trapping at or near the surface of a semiconductor substrate.

[0037] In one or more embodiments, when manufacturing a transistor device, a first dielectric layer is formed on the surface of a semiconductor substrate, and a second dielectric layer is formed on the first dielectric layer. A gate trench is formed at least in part by first performing a patterned dry etch on the second dielectric layer, during which the first dielectric layer acts as an etch stop layer to avoid damage to the surface of the semiconductor substrate. The portion of the first dielectric layer exposed (and possibly damaged) during the dry etch is subsequently removed via patterned or unpatterned wet etching. Then, a spacing structure in the gate trench is formed on the surface of the semiconductor substrate by forming a first spacer layer above the semiconductor substrate, forming a second spacer layer above the semiconductor substrate, performing an isotropic dry etching process to remove a portion of the second spacer layer (using the first spacer layer as an etch stop layer), and performing wet etching to remove a portion of the first spacer layer. The first spacer layer and the second spacer layer may include dielectric materials having different etching rates with respect to one or more etching processes, for example, oxide materials and nitride materials as non-limiting examples. In this way, the remaining portion of the first spacer layer disposed below the remaining portion of the second spacer layer is not exposed to dry etching damage.

[0038] By using the first spacer layer as an etch stop layer instead of previously etched (and possibly damaged) portions of the first dielectric layer as an etch stop layer, better thickness uniformity of the dielectric material (between the second spacer layer and the semiconductor surface (in this case, the first spacer layer)) can be achieved, and the thickness can be more accurately controlled. By using the first spacer layer as an etch stop layer instead of previously etched (and possibly damaged) portions of the first dielectric layer as an etch stop layer when performing a dry etch of the second spacer layer, charge carrier trapping between the dielectric material of the second spacer layer and the surface of the semiconductor substrate can be advantageously reduced.

[0039] In one or more embodiments, a field plate trench and a gate trench are formed simultaneously via dry etching and wet etching for removing portions of the second dielectric layer and portions of the first dielectric layer, respectively. The surface of the semiconductor substrate is initially exposed through the field plate trench. Then, a portion of the first spacer layer is directly formed on the surface of the semiconductor substrate in the field plate trench, thereby protecting the surface of the semiconductor substrate during the subsequent dry etching of the second spacer layer. After forming the spacer structure in the gate trench, a conductive gate structure is formed by depositing a gate metal in and around the gate trench. After forming the gate structure, an interlayer dielectric (ILD) layer is formed over the gate structure, the second dielectric layer, and on a portion of the first spacer layer disposed in the field plate trench. A patterned dry etch is performed to form an opening in the ILD layer that overlaps the field plate trench, wherein the portion of the first spacer layer disposed in the field plate trench acts as an etch stop layer for the patterned dry etching of the ILD layer.

[0040] In one or more embodiments, a wet etch is then performed to remove portions of the first spacer layer disposed in the field plate trenches and exposed through the openings in the ILD layer (these portions have been damaged during the patterned dry etching of the ILD layer), thereby exposing the surface of the semiconductor substrate. A third dielectric layer is then formed over the ILD layer and on the surface of the semiconductor substrate exposed in the field plate trenches. A conductive field plate is then formed on the third dielectric layer, wherein at least a portion of the field plate is disposed in the field plate trenches. When performing a dry etch of the second spacer layer, better thickness uniformity of the dielectric material (in this case, the third dielectric layer) between the field plate metal and the semiconductor surface can be achieved, and the thickness can be more accurately controlled.

[0041] In one or more other embodiments, the portion of the first spacer layer in the field plate trench is not removed, but the field plate is formed directly on the portion of the ILD layer and the portion of the first spacer layer disposed in the field plate trench.

[0042] Figure 1 1 is a cross-sectional side view of a transistor device 100 according to one or more embodiments. The transistor device 100 may be formed on a semiconductor die having a base semiconductor substrate 110 (sometimes referred to herein as "substrate 110") and an overlying buildup structure 120. The substrate 110 is defined by an upper surface 113 and a lower surface 111 and a sidewall extending between the substrate lower surface 111 and the substrate upper surface 113. The buildup structure 120 includes a plurality of additional electrical structures, patterned conductive layers, and dielectric layers therein, and the buildup structure 120 is disposed in direct contact with and overlying the upper surface 113 of the substrate 110.

[0043] In one or more embodiments, an active region 150 is defined corresponding to a portion of the substrate 110 and an overlying portion of the buildup structure 120. One or more isolation regions 114 located at the upper surface 113 may be included within the substrate 110. The active region 150 may include a portion of the substrate 110 extending between at least two isolation regions 114.

[0044] In one or more embodiments, the semiconductor substrate 110 may include a main semiconductor substrate 102 (sometimes referred to herein as "main substrate 102") and a plurality of layers overlying the main substrate 102. In one or more embodiments, the layers overlying the main substrate 102 may include a buffer layer 104, a channel layer 106, and a barrier layer 112, all of which will be described in more detail below.

[0045] In one or more embodiments, the stacked structure 120 is formed on and above the upper surface 113 of the substrate 110 and includes various electrical structures (e.g., gate electrode 128, ohmic contact structures 134, 136), dielectric layers (e.g., dielectric layers 116, 118, 130, 138) and dielectric structures (e.g., spacer structure 125), and patterned conductive layers (e.g., field plate 135, interconnect layers 140, 141).

[0046] In one or more embodiments, a backside metal layer 142 is formed on the lower surface 111 of the substrate 110. The backside metal layer 142 may be electrically connected to a conductive material 146 (i.e., an electrically conductive material) formed in a through substrate via (TSV) 144, which electrically connects the backside metal layer 142 to the interconnect layer 140 at the upper surface 113 of the substrate 110.

[0047] A transistor 101 is formed in an active region 150 of the transistor device 100. In one or more embodiments, the transistor 101 is a field effect transistor (FET) including a gate electrode 128 (sometimes referred to herein as a "control electrode 128" or "gate structure 128"), a first ohmic contact structure 134 (sometimes referred to herein as a "source electrode 134" or "current carrying electrode" 134) proximate to but spaced apart from a first sidewall of the gate electrode 128, and a second ohmic contact structure 136 (sometimes referred to as a "drain electrode 136" or "current carrying electrode 136") proximate to but spaced apart from a second sidewall of the gate electrode 128, each of which is disposed at an upper surface 113 of a substrate 110 and formed in a buildup structure 120 overlying the substrate 110. In one or more embodiments, the transistor 101 is a high electron mobility transistor (HEMT). In one or more embodiments, the transistor 101 is a gallium nitride (GaN) HEMT. It should be understood that these are non-limiting examples and that transistor 101 may be another suitable type of transistor according to one or more other embodiments.

[0048] The ohmic contact structures 134, 136 are formed at and above the upper surface 113 of the substrate 110. In one or more embodiments, the respective interfaces between the ohmic contact structures 134, 136 and the respective portions of the substrate 110 correspond to non-rectifying low-resistance junctions (i.e., “ohmic contacts”) through which current can be easily conducted between the semiconductor material of the substrate 110 and the conductive material of the ohmic contact structures 134, 136. For example, the ohmic contact structures 134, 136 can be formed substantially in a plane relative to each other, and the source electrode 134 and the drain electrode 136 can both extend through at least the dielectric layers 116, 118 (sometimes referred to herein as “first dielectric layer 116” and “second dielectric layer 118”, respectively) to directly contact the upper surface 113 of the substrate 110. In addition, the ohmic contact structures 134, 136 can be electrically coupled to opposite ends of the channel 108 disposed in the channel layer 106 of the substrate 110, respectively. The first ohmic contact structure 134 can be electrically coupled to the TSV 144 and the backside metal layer 142 through patterned portions of one or more interconnect metal layers (e.g., interconnect layer 140) of the buildup structure 120. For example, the second ohmic contact structure 136 can be electrically coupled to an output (not shown) of the transistor device 100 via the interconnect layer 141.

[0049] In one or more embodiments, the gate electrode 128 may be a metal structure electromagnetically coupled to the channel 108. In one or more embodiments, the gate electrode 128 includes a metal material, such as, as a non-limiting example, gold, nickel, copper, tungsten, or any suitable combination of these metal materials. In one or more other embodiments, the gate electrode 128 includes a non-metal material, such as, as a non-limiting example, appropriately doped polysilicon. According to an embodiment, the gate electrode 128 extends through at least the first dielectric layer 116 and the second dielectric layer 118 and between the spacing structures 125 to contact the upper surface 113 of the substrate 110 between the ohmic contact structures 134, 136. The openings in the first dielectric layer 116 and the second dielectric layer 118, which are at least partially defined by the spacing structures 125, are sometimes referred to herein as "gate channels" through which portions of the gate electrode 128 are formed. The region of the buildup structure 120 where the gate electrode 128 is formed is sometimes referred to herein as a "gate channel region". In one or more embodiments, the interface at which the gate electrode 128 contacts the substrate 110 is a Schottky contact.

[0050] In one or more embodiments, the buildup structure 120 includes dielectric layers 116, 118 disposed over the upper surface 113 of the substrate 110, a pair of dielectric structures 125 disposed in the gate trench and in direct contact with the sidewalls of the dielectric layers 116 and 118, an interlayer dielectric (ILD) layer 130 formed on the gate electrode 128 and a portion of the dielectric layer 118, a field plate 135 formed on a portion of the ILD layer 130 (an overlapping portion of the gate electrode 128), and a dielectric layer 138 formed over the field plate 135 and a portion of the ILD layer 130. The dielectric spacer structures 125 may each be formed of a first spacer layer and a second spacer layer, respectively, wherein the first spacer layer is disposed in direct contact with the surface 113 of the substrate 110 and the sidewalls of the dielectric layers 116, 118, and the second spacer layer is disposed on a surface of the first spacer layer and in direct contact with the gate electrode 128. As used herein, a "sidewall" or "side surface" of a given layer or structure refers to a surface that is not substantially parallel (e.g., within about 45 degrees of being normal to or perpendicular to) a plane of the surface 113 of the substrate 110. As described above, the gate electrode 128 may extend through the openings in the dielectric layers 116, 118 and between the spacing structures 125. Each of the gate electrode 128 and the ohmic contact structures 134, 136 contacts the upper surface 113 of the substrate 110 at various points directly above the channel 108. In one or more embodiments, the first dielectric layer 116 may have a thickness in a range of about 30 angstroms to about 1,500 angstroms, and the second dielectric layer 118 may have a thickness in a range of about 100 angstroms to about 4,000 angstroms, although other suitable thickness values ​​may also be used. As used herein, unless otherwise stated, a value is considered to be "about" or "approximately" equal to a stated number if the value is within + / -10% of the stated number.

[0051] In one or more embodiments, the dielectric layers 116, 118 and the first and second spacer layers of the dielectric spacer structure 125 are formed of respective dielectric materials, such as aluminum oxide (Al2O3), silicon nitride (SiN; sometimes Si3N4), silicon oxide (SiO2), silicon oxynitride (SiON), aluminum nitride (AlN), silicon aluminum nitride (SiAlN), hafnium oxide (HfO2), zirconium oxide (ZrO2), titanium oxide (TiO2), or other suitable dielectric materials. In one or more embodiments, the first dielectric layer 116 can be etched separately from the second dielectric layer 118 with respect to one or more etching processes (e.g., as non-limiting examples, a wet chemical etching process, such as buffered oxide etching (BOE) or phosphoric acid etching; or a dry etching process, such as reactive ion etching (RIE) or other suitable plasma etching processes). For example, the first dielectric layer 116 and the first spacer layer of the spacer structure 125 may each be formed of the same first dielectric material (e.g., an oxide material, such as aluminum oxide (AlOx)), and the second dielectric layer 118 and the second spacer layer of the spacer structure 125 may each be formed of the same second dielectric material (e.g., a nitride material, such as silicon nitride (SiNx)) that is separately etchable relative to the first dielectric material. In one or more other embodiments, the first dielectric layer 116 and the first spacer layer of the spacer structure 125 may be formed of different dielectric materials (e.g., different oxide materials), respectively. In one or more other embodiments, the second dielectric layer 118 and the second spacer layer of the spacer structure 125 may be formed of different dielectric materials (e.g., different nitride materials), respectively. For example, the first dielectric layer 116 may be formed of an oxide (e.g., as a non-limiting example, SiO2, ZrO2, HfO2, Al2O3, or TiO2), the second dielectric layer 118 may be formed of a nitride (e.g., as a non-limiting example, SiN, AlN, SiAlN), the first spacer layer of the spacer structure 125 may be formed of an oxide material (e.g., as a non-limiting example, SiO2, ZrO2, HfO2, Al2O3, or TiO2), and the second spacer layer of the spacer structure 125 may be formed of a nitride material (e.g., as a non-limiting example, SiN, AlN, SiAlN). Herein, with respect to a given etching process, two given materials are considered to be "individually etchable" with respect to a given etching process if the etching rate of the first of the two materials is significantly greater (e.g., approximately 1.5 times greater or greater) than the etching rate of the second of the two materials.

[0052] In one or more embodiments, dielectric layers 116, 118 and first and second spacer layers of dielectric spacer structure 125 are formed over substrate 110 using a corresponding chemical vapor deposition process such as low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), or atomic layer deposition (ALD). For example, in one or more embodiments, first dielectric layer 116 may be AlO formed using an ALD process. x In one or more embodiments, the second dielectric layer 118 may be SiNx formed using a PECVD process.

[0053] The spacer structure 125 may be disposed in a gate channel in which a portion of the gate electrode 128 is formed. For example, the spacer structure 125 may be disposed on the surface 113 of the substrate 110 in the gate channel. The sidewalls of the first dielectric layer 116 and the second dielectric layer 118 may define the sidewalls of the gate channel. As will be described, the spacer structure 125 may reduce the gate length of the gate electrode 128 (e.g., to a gate length that is smaller than the gate length that can be achieved with conventional lithographic equipment and techniques). In addition, by controlling the size of the spacer structure 125, the gate length of the gate electrode 128 may be selectively adjusted.

[0054] The field plate 135 may be formed by a portion of the first conductive layer that overlaps the gate electrode 128, portions of the dielectric layers 116, 118, and portions of the ILD layer 130. Figure 1 108), a conductive material strip (not shown in the cross section currently shown) is formed in region 132 to electrically connect field plate 135 to interconnect layer 140. At other points above trench 108, dielectric material from dielectric layer 138 may alternatively be formed in region 132, such as Figure 1 The conductive material strip formed in region 132 (in conjunction with interconnect layer 140) electrically couples field plate 135 to source electrode 134 and conductive material 146 of TSV 144 (e.g., to a ground or reference potential for situations where back metal 142 is coupled to or otherwise configured to provide an electrical ground or reference potential).

[0055] The field plate 135 may be formed of one or more conductive materials, such as, by way of non-limiting example, titanium tungsten (TiW), titanium tungsten nitride (TiWN), tungsten silicide (WSi). In one or more embodiments, at least some portions of the field plate 135 overlie the gate electrode 128 and are thus proximate to one or more sidewalls and an upper surface of the gate electrode 128, wherein a portion of the ILD layer 130 is disposed directly between the field plate 135 and the gate electrode 128.

[0056] Figure 2 is a diagram illustrating a method for manufacturing a transistor device (eg, Figure 1 For enhanced understanding, Figure 2 Can be used with Figure 3-16 Also check out, Figure 3-16 is a diagram depicting a schematic diagram of a semiconductor device in various stages of manufacture according to various embodiments. Figure 1 1 is a cross-sectional view of a transistor device 100 .

[0057] First reference Figure 2 Step 202 and Figure 3 , in a first manufacturing stage 300, a semiconductor substrate 110 is provided, and an active region 150 is defined in the semiconductor substrate 110. As previously mentioned, the semiconductor substrate 110 may include a main semiconductor substrate 102 (sometimes referred to as "main substrate 102") and a plurality of layers overlying the main substrate 102. In one or more embodiments, the layers overlying the main substrate 102 include a buffer layer 104, a channel layer 106, and a barrier layer 112.

[0058] In one or more embodiments, the main substrate 102 includes an upper surface 302 and can be formed of silicon carbide (SiC). In one or more other embodiments, the main substrate 102 can include other materials, such as sapphire, silicon (Si), gallium nitride (GaN), aluminum nitride (AlN), diamond, boron nitride (BN), polycrystalline SiC, silicon on insulator, gallium arsenide (GaAs), indium phosphide (InP) and other substantially insulating or highly resistive materials.

[0059] The buffer layer 104 may be formed on the upper surface 302 of the main substrate 102. The buffer layer 104 may include one or more Group III nitride semiconductor layers. In one or more embodiments, the buffer layer 104 includes multiple layers of semiconductor material, wherein each layer of the buffer layer 104 may include, for example, an epitaxially grown Group III nitride layer. In such an embodiment, the epitaxially grown Group III nitride layer of the buffer layer 104 may include, for example, a nitrogen (N) polarity (i.e., N-face) or gallium (Ga) polarity (i.e., Ga-face) material. In one or more other embodiments, the semiconductor layer of the buffer layer 104 may not be epitaxially grown. In yet other embodiments, the semiconductor layer of the buffer layer 104 may include Si, GaAs, InP or other suitable materials.

[0060] In one or more embodiments, the buffer layer 104 may include an Al2O3 layer having a molar fraction of aluminum of X. X Ga 1-XN represents at least one AlGaN mixed crystal layer of a composition of , and X can take a value between 0 and 1. The total thickness of the buffer layer 104 including all of its constituent layers can be between about 100 angstroms and about 100,000 angstroms, but other thicknesses can also be used. An extreme X value of 0 produces pure GaN, while a value of 1 produces pure aluminum nitride (AlN). In one or more embodiments, the buffer layer 104 can include a nucleation zone composed of AlN. The nucleation zone begins at the interface between the host substrate 102 and the buffer layer 104 and can extend from about 100 angstroms to about 1,000 angstroms into the buffer layer 104. The buffer layer 104 can include additional Al formed above the nucleation zone. X Ga 1-X N layer. Additional Al X Ga 1-X The thickness of the N layer may be between about 100 angstroms and about 50,000 angstroms, although other thicknesses may be used. X Ga 1-X The N layer can be configured as a GaN layer (X=0), where Al X Ga 1-X The N layer is not intentionally doped (NID). Alternatively, additional Al X Ga 1-X The N layer may be configured as one or more GaN layers, wherein the one or more GaN layers are intentionally doped with a dopant, which may include iron (Fe), chromium (Cr), carbon (C), or other suitable dopants that render the buffer layer 104 substantially insulating or highly resistive. The dopant concentration may be about 10 17 cm -3 With about 10 19 cm -3 However, other higher or lower concentrations may be used. X Ga 1-X The N layer can be configured to have X = 0.01 to 0.10, where Al X Ga 1X N is NID, or alternatively, where Al X Ga 1-X N is intentionally doped with Fe, Cr, C, combinations of these components, or other suitable dopant species. In one or more other embodiments, additional Al X Ga 1-X The N layer can be configured as a superlattice, where additional Al X Ga 1-X The N layer consists of a series of alternating NID layers or doped Al X Ga 1-X N layers, where the value of X takes a value between 0 and 1. In yet other embodiments, the buffer layer 104 may include aY Ga 1-Y N, where the indium mole fraction Y can take a value between 0 and 1. The thickness of the InGaN layer can be between about 10 angstroms and about 1,000 angstroms, although other thicknesses can also be used.

[0061] In one or more embodiments, the channel layer 106 may be formed on the buffer layer 104. The channel layer 106 may include one or more III-nitride semiconductor layers. The channel layer 106 may include Al X Ga 1-X N layers, where X takes a value between 0 and 1. In one or more embodiments, the channel layer 106 is configured as GaN (X=0), although other X values ​​may also be used. The thickness of the channel layer 106 may be between about 50 angstroms and about 10,000 angstroms, although other thicknesses may also be used. The channel layer 106 may be NID, or alternatively, may include Si, Ge, C, Fe, Cr, or other suitable dopants. The dopant concentration may be about 10 16 cm -3 With about 10 19 cm -3 In other embodiments, the channel layer 106 may include NID or doped In Y Ga 1-Y N, where the indium mole fraction Y can take a value between 0 and 1.

[0062] According to one or more embodiments, the barrier layer 112 may be formed over the channel layer 106. The barrier layer 112 may include one or more III-N semiconductor layers. The barrier layer 112 may have a larger band gap and / or a larger spontaneous polarization than the channel layer 106, and when the barrier layer 112 is over the channel layer 106, the channel 108 may be formed in the form of a two-dimensional electron gas (2-DEG) within the channel layer 106 adjacent to the interface between the channel layer 106 and the barrier layer 112. In addition, the tensile strain between the barrier layer 112 and the channel layer 106 may cause additional piezoelectric charges to be introduced into the 2-DEG and the channel 108. The barrier layer 112 may include a multi-layer structure, wherein the first layer of the barrier layer 112 may include at least one NID Al X Ga 1-XN layers, where X takes a value between 0 and 1. In one or more embodiments, X may take a value between 0.1 and 0.35, although other X values ​​may also be used. The first layer of barrier layer 112 may have a thickness between about 50 angstroms and about 1,000 angstroms, although other thicknesses may also be used. Barrier layer 112 may be NID, or alternatively, may include Si, Ge, C, Fe, Cr, or other suitable dopants. The dopant concentration may be about 10 16 cm -3 with 10 19 cm -3 However, other higher or lower concentrations may also be used.

[0063] In one or more embodiments, an additional AlN interlayer barrier (not shown) may be formed between the channel layer 106 and the barrier layer 112. The AlN interlayer barrier may introduce additional spontaneous and piezoelectric polarization, thereby increasing the channel charge and improving electron confinement of the resulting 2-DEG forming the channel 108.

[0064] In other embodiments, the barrier layer 112 may include a Y Al 1-Y N, wherein the indium mole fraction Y can take a value between about 0.1 and about 0.2, although other values ​​of Y can also be used. In the case of using InAlN to form the barrier layer 112, the thickness of the barrier layer 112 can be between about 50 angstroms and about 1,000 angstroms, although other thicknesses can also be used. In the case of using InAlN to form the barrier layer 112, the InAlN can be NID, or alternatively, can include Si, Ge, C, Fe, Cr or other suitable dopants. The dopant concentration can be between about 10 16 cm -3 With about 10 19 cm -3 However, other higher or lower concentrations may also be used.

[0065] In one or more embodiments, a capping layer (not shown) may be formed over the barrier layer 112. When included, the capping layer provides a stable surface for the substrate 110 and serves to protect the upper surface 113 of the substrate 110 from chemical and environmental exposure incidental to wafer processing. The capping layer may include one or more III-N semiconductor layers and is supported by the barrier layer 112. In one or more embodiments, the capping layer includes GaN. The thickness of the capping layer may be between about 5 angstroms and about 100 angstroms, although other thicknesses may also be used. The capping layer may be NID, or alternatively, may include Si, Ge, C, Fe, Cr, or other suitable dopants. The dopant concentration may be about 10 16 cm-3 with 10 19 cm -3 However, other higher or lower concentrations may also be used.

[0066] The isolation regions 114 may be formed via an implantation process configured to damage the epitaxial layer and / or other semiconductor layers to produce a high resistive region of the substrate 110, thereby rendering the substrate 110 highly resistive or semi-insulating in the high resistive region while leaving the crystal structure intact in the active region 150. In other embodiments (not shown), one or more of the isolation regions 114 may be formed by removing a portion of one or more of the epitaxial layer and / or other semiconductor layers of the substrate 110 and leaving an active region "table" (e.g., active region 150) surrounded by the isolation regions 114 (i.e., surrounded by a region of highly resistive or semi-insulating material). Subsequently, a high resistive or semi-insulating material may be formed within the active region 150. Figure 1 transistor 101.

[0067] Next reference Figure 2 Step 204 and Figure 4 During the manufacturing stage 400, a first dielectric layer 116 is formed on (e.g., directly on and in contact with) the upper surface 113 of the semiconductor substrate 110. As described above, in one or more embodiments, the first dielectric layer 116 may have a thickness in a range of about 30 angstroms to about 1,500 angstroms. The first dielectric layer 116 may be formed of a dielectric material, such as, as non-limiting examples, Al2O3, SiN, Si3N4, SiO2, SiON, AlN, SiAlN, HfO2, ZrO2, TiO2, or another suitable material that may be deposited via chemical vapor deposition (e.g., LPCVD). In one or more embodiments, the first dielectric layer 116 may include an oxide (e.g., as non-limiting examples, SiO2, ZrO2, HfO2, Al2O3, or TiO2).

[0068] Next reference Figure 2 Step 206 and Figure 5During the manufacturing stage 500, a second dielectric layer 118 is formed on the first dielectric layer 116 (e.g., directly on and in contact with the first dielectric layer 116). As described above, in one or more embodiments, the second dielectric layer 118 can have a thickness in a range of about 100 angstroms to about 4,000 angstroms. The second dielectric layer 118 can be formed of a dielectric material, such as, as non-limiting examples, Al2O3, SiN, Si3N4, SiO2, SiON, AlN, SiAlN, HfO2, ZrO2, TiO2, or another suitable material that can be deposited via plasma enhanced chemical vapor deposition (e.g., PECVD). In one or more embodiments, the second dielectric layer 118 can include a nitride (e.g., as non-limiting examples, SiN, AlN, SiAlN).

[0069] Next reference Figure 2 Step 208 and Figure 6 During fabrication stage 600, a patterned dry etch is performed to form openings 602 in second dielectric layer 118. Herein, a "patterned etch process" refers to a process that performs material etching in conjunction with a photolithography process such that material is etched through openings in a patterned photoresist layer.

[0070] For example, during the manufacturing stage 600, an anisotropic dry etching process (e.g., as a non-limiting example, an RIE process or other plasma etching process) is performed in conjunction with a photolithography process to remove portions of the second dielectric layer 118, thereby forming an opening 602 in the second dielectric layer 118, through which the surface of the first dielectric layer 116 is exposed. The first dielectric layer 116 can act as an etch stop layer for this dry etching process, thereby mitigating or preventing damage to the surface 113 of the substrate 110. This causes the exposed portion 604 of the first dielectric layer 116 to be damaged by the dry etching process (e.g., due to plasma damage).

[0071] In addition, some of the exposed portion 604 of the first dielectric layer 116 is removed during the dry etching process, and the amount of material removed in this manner may be process dependent and may not be uniform across transistor devices fabricated simultaneously (e.g., when processing a wafer including multiple transistor devices). This may result in uncertainty in the thickness of the exposed portion 604 and undesirable non-uniformity of the exposed portion 604.

[0072] Next reference Figure 2 Step 210 and Figure 7During manufacturing stage 700, a wet etch is performed to remove the portion 604 of the first dielectric layer 116 that was damaged by exposure to the etching process at step 208, thereby forming an opening 702 extending through the first dielectric layer 116 and the second dielectric layer 118. In one or more embodiments, the wet etch is a patterned wet etch. In one or more other embodiments, the wet etch is performed without using a photolithography process, and instead the opening 702 is formed by utilizing an existing pattern generated by the dry etching process used at step 208.

[0073] In one or more embodiments, portion 604 of first dielectric layer 116 is removed via an anisotropic wet etching process that selectively etches the dielectric substance (e.g., oxide material) of first dielectric layer 116 at a higher etching rate than the dielectric material (e.g., nitride material) of second dielectric layer 118. As shown, the wet etching may partially undercut second dielectric layer 118 in the region of opening 702. Opening 702 may correspond to a portion of the second dielectric layer 118 that is formed in a subsequent manufacturing stage (e.g., Fig.13 The manufacturing stage 1300 of the gate structure at least partially forms a gate channel. In this document, unless otherwise specified, "wet etching" generally refers to wet chemical etching.

[0074] Removing portion 604 of first dielectric layer 116 in this manner avoids portion 604 from acting as a charge carrier trapping center in transistor 101 due to damage to portion 604 caused by dry etching in step 208. Removing portion 604 of first dielectric layer 116 also avoids or reduces thickness non-uniformities in first dielectric layer 116 due to partial etching of portion 604 during dry etching in step 208.

[0075] Next reference Figure 2 Step 212 and Figure 8 During the manufacturing stage 800, a first spacer layer 148 is formed over the substrate 110. The first spacer layer 148 may be formed directly on the top and side surfaces of the second dielectric layer 118, the side surfaces of the first dielectric layer 116, and the surface 113 of the substrate 110 exposed by the opening 702. In one or more embodiments, the first spacer layer 148 may be formed of a dielectric material, such as, as non-limiting examples, Al2O3, SiN, Si3N4, SiO2, SiON, AlN, SiAlN, HfO2, ZrO2, TiO2, or another suitable material that may be deposited via chemical vapor deposition (e.g., LPCVD). In one or more embodiments, the first spacer layer 148 may include an oxide (e.g., as non-limiting examples, SiO2, ZrO2, HfO2, Al2O3, or TiO2).

[0076] Next reference Figure 2 Step 214 and Fig. 9 During the manufacturing stage 900, a second spacer layer 902 is formed over the substrate 110. The second spacer layer 902 can be formed directly on the surface of the first spacer layer 148. In one or more embodiments, the second spacer layer 902 can be formed of a dielectric material, such as, as non-limiting examples, Al2O3, SiN, Si3N4, SiO2, SiON, AlN, SiAlN, HfO2, ZrO2, TiO2, or another suitable material that can be deposited via plasma enhanced chemical vapor deposition (e.g., PECVD). In one or more embodiments, the second spacer layer 902 can include a nitride (e.g., as non-limiting examples, SiN, AlN, SiAlN).

[0077] Next reference Figure 2 Step 216 and Fig.10 During the manufacturing stage 1000, a dry etch is performed to remove portions of the second spacer layer 902. According to various embodiments, the dry etch may be patterned or non-patterned (e.g., a blanket dry etch). For example, during the manufacturing stage 1000, an anisotropic dry etch process (e.g., as a non-limiting example, an RIE process or other plasma etching process) may be performed to remove portions of the second spacer layer 902. Since the second spacer layer 902 has a greater thickness at the edge of the gate channel, portions 1002 of the second spacer layer 902 remain in the gate channel when this dry etching process is completed. The first spacer layer 148 may act as an etch stop layer for this dry etching process, thereby mitigating or preventing damage to the surface 113 of the substrate 110. This causes the exposed portions of the first spacer layer 148 to be damaged by the dry etching process (e.g., due to plasma damage).

[0078] Next reference Figure 2 Step 218 and Fig.11, at manufacturing stage 1100, a first patterned photoresist layer 1102 and a second patterned photoresist layer 1104 are formed over a substrate 110. For example, the first patterned photoresist layer 1102 and the second patterned photoresist layer 1104 may be formed via respective photolithography processes, each of which includes spin coating a photoresist material (e.g., a resin) over the substrate 110, exposing the photoresist material to ultraviolet (UV) light through a patterned mask and baking at a predetermined temperature, and removing portions of the photoresist material using a developer (e.g., removing those portions exposed to UV light when a positive photoresist material is used, or removing those portions not exposed to UV when a negative photoresist material is used). An opening 1106 is formed through the first photoresist layer 1102 and the second photoresist layer 1104, exposing a region including a gate channel 1108 (i.e., a "gate channel region") through the opening 1106.

[0079] In one or more embodiments, the first photoresist layer 1102 can be developed simultaneously with the second photoresist layer 1104. As shown, the opening in the first photoresist layer 1102 can be wider than the opening in the second photoresist layer 1104, such that the second photoresist layer 1104 overhangs the first photoresist layer 1102 in the region of the opening 1106.

[0080] In an exemplary embodiment, the first photoresist layer 1102 has a thickness of about 0.5 μm to about 2 μm, but it is understood that other suitable thicknesses may be used. In an exemplary embodiment, the second photoresist layer 1104 has a thickness of between about 0.25 μm and about 1.5 μm, but other suitable thicknesses may also be used.

[0081] Next reference Figure 2 Step 220 and Fig.12During the manufacturing stage 1200, a wet etch is performed to remove the exposed portions of the first spacer layer 148 (i.e., the portions exposed by the opening 1106). For example, the exposed portions of the first spacer layer 148 damaged by the dry etching process in step 216 are removed via this wet etching process. Some portions of the first spacer layer 148 remain upon completion of this wet etching process, and these portions are disposed on the top surface of the second dielectric layer 118 and are in direct contact with the sidewalls of the first dielectric layer 116 in the gate trench 1108, the sidewalls of the second dielectric layer 118, and the surface 113 of the substrate 110. Due to the undercut portion of the first dielectric layer 116 being filled at or near the gate trench 1108, at least some of these remaining portions of the first spacer layer 148 are directly disposed between the second dielectric layer 118 and the surface 113 of the substrate 110. The remaining portions of the first spacer layer 148 in the gate trench 1108 together with the portion 1002 form the spacer structure 125 in the gate trench 1108.

[0082] The width of each spacer structure 125 corresponds to the respective thickness of the first spacer layer 148 and the second spacer layer 902 (e.g., a greater initial thickness of the layers 148 and 902 when deposited corresponds to a wider spacer structure 125). Thus, the width of the spacer structure 125 can be set based on the amount of dielectric material deposited when forming each of the first spacer layer 148 and the second spacer layer 902.

[0083] In this manner, the gate length of the transistor device 100 may be adjusted by adjusting the thickness of the dielectric material deposited when forming the first spacer layer 148 and the second spacer layer 902. For example, forming thicker spacers 148, 902 results in wider spacers 125, which reduces the gate length of the subsequently formed gate structure 128. In some cases, by forming sufficiently wide spacers 125, a gate length at the bottom of the gate electrode 128 may be achieved that would otherwise not be achievable using only conventional photolithography techniques.

[0084] Next reference Figure 2 Step 222 and Fig.13 , at manufacturing stage 1300, a gate structure 128 is formed through an opening 1106 in the first photoresist layer 1102 and the second photoresist layer 1104. The gate structure 128 can be electromagnetically coupled to the channel 108 through the upper surface 113 of the substrate 110 and the barrier layer 112. During operation of the transistor device 100, a potential change on the gate structure 128 can shift the quasi-Fermi level of the barrier layer 112 compared to the quasi-Fermi level of the channel layer 106, thereby modulating the electron concentration in the channel 108 within the portion of the substrate 110 below the gate structure 128.

[0085] In one or more embodiments, the gate structure 128 may be configured as a Schottky gate and may be formed over and in direct contact with the substrate upper surface 113 using a Schottky material layer and a conductive metal layer. In one or more embodiments, a Schottky or other suitable material may be combined with a highly conductive material in a metal stack to form the gate structure 128. For example, a Schottky material layer may first be formed in contact with the substrate 110, and a conductive low stress metal may be deposited over the Schottky material to form the gate structure 128. In one or more other embodiments, the gate structure 128 may be formed on a gate dielectric or gate oxide (not shown) on the upper surface 113 of the substrate 110, thereby forming a metal insulator semiconductor (MIS) junction or a metal oxide semiconductor (MOS) junction that may be electrically coupled to the channel 108 through the gate dielectric or gate oxide layer.

[0086] According to one or more embodiments, the gate structure 128 may have a T-shaped cross-section, as shown in the current example, with a vertical stem through at least the first dielectric layer 116 and the second dielectric layer 118 in the gate channel 1108 on the substrate 110, and a wider portion above the vertical stem having a horizontal portion overlying and contacting the upper surface of the second dielectric layer 118 and a portion of the spacer structure 125. In one or more other embodiments (not shown), the gate structure 128 may have a square or circular cross-sectional shape. In one or more other embodiments, the vertical stem or lower portion of the gate structure 128 may be recessed through the upper surface 113 of the semiconductor substrate 110 and may partially extend into the barrier layer 112, thereby increasing the electrical coupling of the gate structure 128 to the channel 108 through the barrier layer 112.

[0087] The gate metal of the gate structure 128 may be deposited by evaporation, sputtering, chemical vapor deposition or other suitable processes. For example, a first portion of the deposited gate metal may be disposed in the opening 1106 to form at least a portion of the gate structure 128, and a second portion of the deposited gate metal may be disposed on the upper surface of the second photoresist layer 1104.

[0088] Next reference Figure 2 Step 224 and Fig.14, at manufacturing stage 1400, the first photoresist layer 1102, the second photoresist layer 1104, and the second portion of the gate metal deposited on the surface of the second photoresist layer 1104 are simultaneously removed via a stripping process. For example, in the stripping process, a photoresist stripper (e.g., a solvent such as acetone, 1-methyl-2-pyrrolidone, or dimethyl sulfoxide) can be applied to remove the first photoresist layer 1102 and the second photoresist layer 1104, which separates (i.e., "strips") the excess gate metal on the surface of the second photoresist layer 1104.

[0089] Although combined Figure 2 Steps 220, 222, 224 and Figure 11-14 The manufacturing stages 1100, 1200, 1300, 1400 of the present invention describe a double-layer lift-off process, but it should be understood that this is for illustration and not limitation. For example, in one or more other embodiments, when forming the gate structure 128, other photolithography processes (e.g., using a single photoresist layer developed with an undercut profile) may be used instead.

[0090] Next reference Figure 2 Step 226 and Fig.15 At manufacturing stage 1500, an ILD layer 130 is formed over the substrate 110 (e.g., in contact with a surface of each of the second dielectric layer 118, the first spacer layer 148, and the gate structure 128). In one or more embodiments, the ILD layer 130 has a thickness in a range of about 500 angstroms to about 10,000 angstroms, although other suitable thicknesses may also be used. As non-limiting examples, the ILD layer 130 may be formed of silicon nitride, silicon oxide, silicon oxynitride, or other suitable dielectric materials.

[0091] Next reference Figure 2 Step 228 and Fig.16 , at manufacturing stage 1600, a field plate 135 is formed on the ILD layer 130. For example, a patterned conductive layer (e.g., deposited via sputtering, evaporation, or chemical vapor deposition, and then patterned using a suitable photolithography process, as non-limiting examples) can be formed over the substrate 110 to form the field plate 135. For example, the conductive layer can include a conductive material such as TiW, TiWN, WSi, or other suitable materials. The conductive layer can have a thickness in a range of about 100 angstroms to about 5,000 angstroms, although other suitable thicknesses can also be used.

[0092] It should be understood that additional processing steps may be performed to fabricate the transistor device 100, and these additional processing steps may be performed during the Figure 2As non-limiting examples, such processing steps may include depositing and patterning additional dielectric layers (e.g., dielectric layer 138 or other applicable dielectric layers) and metal layers (e.g., interconnect layers 140, 141 or other applicable metal layers).

[0093] In one or more embodiments, it may be desirable to position a portion of a field plate of a transistor device closer to the surface of a substrate (e.g., compared to a situation where the field plate only directly overlaps a gate structure), which may be accomplished by forming a field plate channel that extends through a dielectric layer above the substrate offset from the gate channel. Fig.17 1 shows a cross-sectional side view of a transistor device 1700 including a transistor 1701. The transistor 1701 includes a field plate trench 1708 and a third dielectric layer 1702. The third dielectric layer 1702 is disposed on the surface of the ILD layer 130 and is disposed in the field plate trench 1708, on the sidewalls of the first dielectric layer 116 and the second dielectric layer 118, and on the surface 113 of the substrate 110. It should be noted that various features of the transistor device 1700 correspond to the above-mentioned features in conjunction with Figure 1 Like reference numerals are used herein to denote like elements with respect to the features described for the transistor device 100 , wherein the description of these elements is not necessarily repeated herein for the sake of brevity.

[0094] The third dielectric layer 1702 may be formed of a dielectric material, such as, by way of non-limiting example, Al2O3, SiN, Si3N4, SiO2, SiON, AlN, SiAlN, HfO2, ZrO2, TiO2, or another suitable material that may be deposited via chemical vapor deposition (e.g., LPCVD). The field plate 1704 is disposed directly on the third dielectric layer 1702. The field plate 1704 may be similar to the dielectric material of the present invention in terms of at least material and thickness. Figure 1 The field plate 1704 may at least partially overlap the gate structure 128 and the gate channel and may be at least partially disposed in the field plate channel 1708 such that a portion of the third dielectric layer 1702 in the field plate channel 1708 is directly between the surface 113 of the substrate 110 and the field plate 1704.

[0095] A portion of the first spacer layer 148 may be disposed on the upper surface of the second dielectric layer 118 as part of the spacer structure 125. The first spacer layer 148 may be similar to the dielectric layer 118 in terms of at least material and thickness. Figure 8-10 The first spacer layer 148 is formed by a plurality of layers of the semiconductor device.

[0096] The dielectric layer 1706 may be disposed directly on the field plate 1704 and a portion of the third dielectric layer 1702. The dielectric layer 1706 may be similar to the dielectric layer 1704 in terms of at least material and thickness. Figure 1 of dielectric layer 138.

[0097] The third dielectric layer 1702 may be formed after forming the field plate trench 1708 and before forming the field plate 1704. Using a dielectric layer (i.e., the third dielectric layer 1702) formed after forming the field plate trench 1708 to separate the field plate 1704 from the surface 113 of the substrate 110 ensures that this dielectric material has not been damaged by an etch (e.g., dry etch) used to form an opening in the ILD layer 130 that overlaps the field plate trench 1708. Removing and replacing damaged dielectric material in the field plate trench 1708 reduces the likelihood of charge carrier traps existing in the field plate trench 1708, which advantageously improves the performance of the transistor device 1700. This approach also provides better thickness uniformity of the dielectric material separating the field plate 1704 from the surface 113 in the field plate trench 1708, which advantageously reduces process variations regarding the amount of separation between the field plate 1704 and the surface 113 in the field plate trench 1708.

[0098] The arrangement shown in the current example is for illustration and not limitation.For example, in one or more other embodiments, the third dielectric layer 1702 may be omitted, and the first spacer layer 148 may instead cover the surface 113 of the substrate 110 in the field plate trench 1708 .

[0099] Fig.18 is a diagram illustrating a method for manufacturing a transistor device (eg, Fig.17 For enhanced understanding, Fig.18 Can be used with Figure 19-35 Also check out, Figure 19-35 is a diagram depicting a schematic diagram of a semiconductor device in various stages of manufacture according to various embodiments. Fig.17 1700 is a cross-sectional view of a transistor device.

[0100] First reference Fig.18 Step 1802 and Fig.19 In a first manufacturing stage 1900, a semiconductor substrate 110 is provided and an active region 150 is defined in the semiconductor substrate 110. It should be noted that various features of step 1802 and the first manufacturing stage 1900 correspond to the above-mentioned steps in conjunction with Figure 2 Step 202 and Figure 3 For the features described in the manufacturing stage 300 of the present invention, similar reference numerals are used to represent similar elements. For the sake of brevity, the description of these elements will not be repeated here.

[0101] Next reference Fig.18 Step 1804 and Fig. 20During the manufacturing stage 2000, a first dielectric layer 116 is formed on (e.g., directly on and in contact with) the upper surface 113 of the semiconductor substrate 110. As described above, in one or more embodiments, the first dielectric layer 116 may have a thickness in a range of about 30 angstroms to about 1,500 angstroms. The first dielectric layer 116 may be formed of a dielectric material, such as, as non-limiting examples, Al2O3, SiN, Si3N4, SiO2, SiON, AlN, SiAlN, HfO2, ZrO2, TiO2, or another suitable material that may be deposited via chemical vapor deposition (e.g., LPCVD). In one or more embodiments, the first dielectric layer 116 may include an oxide (e.g., as non-limiting examples, SiO2, ZrO2, HfO2, Al2O3, or TiO2).

[0102] Next reference Fig.18 Step 1806 and Fig.21 During the manufacturing stage 2100, a second dielectric layer 118 is formed on the first dielectric layer 116 (e.g., directly on and in contact with the first dielectric layer 116). As described above, in one or more embodiments, the second dielectric layer 118 can have a thickness in a range of about 100 angstroms to about 4,000 angstroms. The second dielectric layer 118 can be formed of a dielectric material, such as, as non-limiting examples, Al2O3, SiN, Si3N4, SiO2, SiON, AlN, SiAlN, HfO2, ZrO2, TiO2, or another suitable material that can be deposited via plasma enhanced chemical vapor deposition (e.g., PECVD). In one or more embodiments, the second dielectric layer 118 can include a nitride (e.g., as non-limiting examples, SiN, AlN, SiAlN).

[0103] Next reference Fig.18 Step 1808 and Fig. 22During the manufacturing stage 2200, a patterned dry etch is performed to form an opening 2202 and an opening 2204 in the second dielectric layer 118. For example, during the manufacturing stage 2200, an anisotropic dry etch process (e.g., as a non-limiting example, an RIE process or other plasma etch process) is performed in combination with a photolithography process to remove portions of the second dielectric layer 118, thereby forming openings 2202, 2204 in the second dielectric layer 118, through which the surface of the first dielectric layer 116 is exposed. The first dielectric layer 116 can act as an etch stop layer for this dry etch process, thereby mitigating or preventing damage to the surface 113 of the substrate 110. This causes the exposed portions 2206, 2208 of the first dielectric layer 116 to be damaged by the dry etch process (e.g., due to plasma damage).

[0104] In addition, some of the exposed portions 2206, 2208 of the first dielectric layer 116 are removed during the dry etching process, and the amount of material removed in this manner depends on the process and may not be uniform across transistor devices fabricated simultaneously (e.g., when processing a wafer including multiple transistor devices). This results in uncertainty in the thickness of the exposed portions 2206, 2208 and reduces the thickness uniformity of the exposed portions 2206, 2208.

[0105] Next reference Fig.18 Step 1810 and Fig.23 During the manufacturing stage 2300, a wet etch is performed to remove portions 2206, 2208 of the first dielectric layer 116 damaged by exposure to the etching process at step 1808, thereby forming an opening 2302 and an opening 2304 extending through the first dielectric layer 116 and the second dielectric layer 118. In one or more embodiments, the wet etch is a patterned wet etch. In one or more other embodiments, the wet etch is performed without using a photolithography process, and instead the openings 2302, 2304 are formed by utilizing an existing pattern generated by a dry etching process used at step 1808.

[0106] In one or more embodiments, portions 2206, 2208 of the first dielectric layer 116 are removed via an anisotropic wet etching process that selectively etches the dielectric substance (e.g., oxide material) of the first dielectric layer 116 at a higher etching rate than the dielectric material (e.g., nitride material) of the second dielectric layer 118. As shown, the wet etching may partially undercut the second dielectric layer 118 in the region of the openings 2302, 2304. The opening 2302 may correspond to a portion of the second dielectric layer 118 that is formed in a subsequent manufacturing stage (e.g., Fig.29The gate channel of the gate structure is at least partially formed at the manufacturing stage 2900 of the present invention. The opening 2304 may correspond to the gate channel of the gate structure at a subsequent manufacturing stage (e.g., Fig.35 In manufacturing stage 3500 ), a field plate trench 1708 of the field plate 1704 is formed.

[0107] Removing portions 2206, 2208 of the first dielectric layer 116 in this manner avoids portions 2206, 2208 from acting as charge carrier trapping centers in the transistor 1701 due to damage to portions 2206, 2208 resulting from the dry etching in step 1808. Removing portions 2206, 2208 of the first dielectric layer 116 also avoids or reduces thickness non-uniformities in the first dielectric layer 116 due to partial etching of portions 2206, 2208 during the dry etching in step 1808.

[0108] Next reference Fig.18 Step 1812 and Fig.24 During the manufacturing stage 2400, a first spacer layer 148 is formed over the substrate 110. The first spacer layer 148 may be formed directly on the top and side surfaces of the second dielectric layer 118, the side surfaces of the first dielectric layer 116, and the surface 113 of the substrate 110 exposed by the openings 2302, 2304. In one or more embodiments, the first spacer layer 148 may be formed of a dielectric material, such as, as non-limiting examples, Al2O3, SiN, Si3N4, SiO2, SiON, AlN, SiAlN, HfO2, ZrO2, TiO2, or another suitable material that may be deposited via chemical vapor deposition (e.g., LPCVD). In one or more embodiments, the first spacer layer 148 may include an oxide (e.g., as non-limiting examples, SiO2, ZrO2, HfO2, Al2O3, or TiO2).

[0109] Next reference Fig.18 Step 1814 and Fig.25 During the manufacturing stage 2500, a second spacer layer 2502 is formed over the substrate 110. The second spacer layer 2502 can be formed directly on the surface of the first spacer layer 148. In one or more embodiments, the second spacer layer 2502 can be formed of a dielectric material, such as, as non-limiting examples, Al2O3, SiN, Si3N4, SiO2, SiON, AlN, SiAlN, HfO2, ZrO2, TiO2, or another suitable material that can be deposited via plasma enhanced chemical vapor deposition (e.g., PECVD). In one or more embodiments, the second spacer layer 2502 can include a nitride (e.g., as non-limiting examples, SiN, AlN, SiAlN).

[0110] Next reference Fig.18 Step 1816 and Fig.26 During the manufacturing stage 2600, a dry etch is performed to remove portions of the second spacer layer 2502. According to various embodiments, the dry etch may be patterned or non-patterned (e.g., blanket dry etch). For example, during the manufacturing stage 2600, an anisotropic dry etch process (e.g., as a non-limiting example, an RIE process or other plasma etch process) is performed to remove portions of the second spacer layer 2502. Since the second spacer layer 2502 has a greater thickness at the edges of the gate trench 2606 and the field plate trench 1708, portions 2602 of the second spacer layer 2502 remain in the gate trench 2606 when this dry etch process is completed, and portions 2604 of the second spacer layer 2502 remain in the field plate trench 1708. The first spacer layer 148 may act as an etch stop layer for this dry etch process, thereby mitigating or preventing damage to the surface 113 of the substrate 110. This causes the exposed portions of the first spacer layer 148 to be damaged by the dry etch process (e.g., due to plasma damage).

[0111] Next reference Fig.18 Step 1818 and Fig. 27 , at manufacturing stage 2700, a first patterned photoresist layer 2702 and a second patterned photoresist layer 2704 are formed over substrate 110. For example, first patterned photoresist layer 2702 and second patterned photoresist layer 2704 may be formed via respective photolithography processes, each of which includes spin coating a photoresist material (e.g., resin) over substrate 110, exposing the photoresist material to ultraviolet (UV) light through a patterned mask and baking at a predetermined temperature, and removing portions of the photoresist material using a developer (e.g., removing those portions exposed to UV light when a positive photoresist material is used, or removing those portions not exposed to UV when a negative photoresist material is used). An opening 2706 is formed through first photoresist layer 2702 and second photoresist layer 2704, exposing a region including gate channel 2606 (i.e., a "gate channel region") through the opening 2706.

[0112] In one or more embodiments, the first photoresist layer 2702 can be developed simultaneously with the second photoresist layer 2704. As shown, the opening in the first photoresist layer 2702 can be wider than the opening in the second photoresist layer 2704, such that the second photoresist layer 2704 overhangs the first photoresist layer 2702 in the area of ​​the opening 2706.

[0113] In an exemplary embodiment, the first photoresist layer 2702 has a thickness of about 0.5 μm to about 2 μm, but it is understood that other suitable thicknesses may be used. In an exemplary embodiment, the second photoresist layer 2704 has a thickness of between about 0.25 μm and about 1.5 μm, but other suitable thicknesses may also be used.

[0114] Next reference Fig.18 Step 1820 and Fig.28 During the manufacturing stage 2800, a wet etch is performed to remove the exposed portions of the first spacer layer 148, thereby exposing the surface 113 of the substrate 110 in the gate trench 2606. For example, portions of the first spacer layer 148 exposed through the opening 2706 and damaged by the dry etching process in step 1816 are removed via this wet etching process. Some portions of the first spacer layer 148 remain after this wet etching process is completed. For example, the remaining portions of the first spacer layer 148 are included in the spacer structure 125 and are disposed in direct contact with the sidewalls of the first dielectric layer 116, the sidewalls of the second dielectric layer 118, and the surface 113 of the substrate 110 in the gate trench 2606. For example, other remaining portions of the first spacer layer 148 are disposed on the upper surface of the second dielectric layer 118 and on the sidewalls of the first dielectric layer 116 and the second dielectric layer 118 and the surface 113 of the substrate 110 in the field plate trench 1708. Due to the undercut portion of the first dielectric layer 116 being filled at or near the gate trench 2606, at least some of these remaining portions of the first spacer layer 148 are disposed directly between the second dielectric layer 118 and the surface 113 of the substrate 110. These remaining portions of the first spacer layer 148 together with the portion 2602 of the second spacer layer 2502 form a spacer structure 125 in the gate trench 2606.

[0115] The width of each spacer structure 125 corresponds to the respective thickness of the first spacer layer 148 and the second spacer layer 2502 (e.g., a greater initial thickness of the layers 148 and 2502 when deposited corresponds to a wider spacer structure 125). Thus, the width of the spacer structure 125 can be set based on the amount of dielectric material deposited when forming each of the first spacer layer 148 and the second spacer layer 2502.

[0116] In this manner, the gate length of the transistor device 1700 may be adjusted by adjusting the thickness of the dielectric material deposited when forming the first spacer layer 148 and the second spacer layer 2502. For example, forming thicker spacers 148, 2502 may result in wider spacers 125, which reduces the gate length of the subsequently formed gate structure 128. In one or more embodiments, by forming sufficiently wide spacers 125, a gate length at the bottom of the gate electrode 128 may be achieved that would otherwise be unattainable using only conventional photolithography techniques.

[0117] Next reference Fig.18 Step 1822 and Fig.29 , at manufacturing stage 2900, a gate structure 128 is formed through an opening 2706 that extends through the first photoresist layer 2702 and the second photoresist layer 2704. The gate structure 128 may be electromagnetically coupled to the channel 108 through the upper surface 113 of the substrate 110 and the barrier layer 112. During operation of the transistor device 100, a potential change on the gate structure 128 may shift the quasi-Fermi level of the barrier layer 112 compared to the quasi-Fermi level of the channel layer 106, thereby modulating the electron concentration in the channel 108 within the portion of the substrate 110 below the gate structure 128. As described above, one or more aspects of the gate structure 128 in the manufacturing stage 2900 may be similar to Fig.13 Those aspects of the gate structure 128 in the manufacturing stage 1300 of FIG. 1 and are not repeated here for the sake of brevity.

[0118] Next reference Fig.18 Step 1824 and Fig.30 , at manufacturing stage 3000, the first photoresist layer 2702, the second photoresist layer 2704, and the second portion of the gate metal deposited on the surface of the second photoresist layer 2704 are simultaneously removed via a stripping process. For example, in the stripping process, a photoresist stripper (e.g., a solvent such as acetone, 1-methyl-2-pyrrolidone, or dimethyl sulfoxide) can be applied to remove the first photoresist layer 2702 and the second photoresist layer 2704, which separates (i.e., "strips") the excess gate metal on the surface of the second photoresist layer 2704.

[0119] Although combined Fig.18 Steps 1818, 1820, 1822, 1824 and Figure 27-30The manufacturing stages 2700, 2800, 2900, 3000 of the present invention describe a double-layer lift-off process, but it should be understood that this is for illustration and not limitation. For example, in one or more other embodiments, other photolithography processes (e.g., using a single photoresist layer developed with an undercut profile) may be used instead when forming the gate structure 128.

[0120] Next reference Fig.18 Step 1826 and Fig.31 At manufacturing stage 3100, an ILD layer 130 is formed over the substrate 110 (e.g., in contact with a surface of each of the second dielectric layer 118 and the gate structure 128). In one or more embodiments, the ILD layer 130 has a thickness in a range of about 500 angstroms to about 10,000 angstroms, although other suitable thicknesses may also be used. As non-limiting examples, the ILD layer 130 may be formed of silicon nitride, silicon oxide, silicon oxynitride, or other suitable dielectric materials.

[0121] Next reference Fig.18 Step 1828 and Fig.32 , at the manufacturing stage 3200, a patterned dry etch is performed to form an opening 3202 in the ILD layer 130. For example, during the manufacturing stage 3200, an anisotropic dry etch process (e.g., as a non-limiting example, an RIE process or other plasma etching process) is performed to remove a portion of the ILD layer 130 to form the opening 3202. The opening 3202 may overlap the field plate trench 1708. The first spacer layer 148 may act as an etch stop layer for this dry etching process, thereby mitigating or preventing damage to the surface 113 of the substrate 110. This causes the exposed portion of the first spacer layer 148 to be damaged by the dry etching process (e.g., due to plasma damage). In one or more embodiments, the ILD layer 130 is formed of a material having an etch rate similar to that of the material of the second spacer layer 2502, so that the remaining portion 2604 of the second spacer layer 2502 disposed in the field plate trench 1708 is removed together with the portion 130 of the ILD layer by this dry etching process.

[0122] Next reference Fig.18 Step 1830 and Fig.33 During the manufacturing stage 3300, a wet etch is performed to remove the exposed portions of the first spacer layer 148 (i.e., exposed through the opening 3202). For example, the exposed portions of the first spacer layer 148 (those portions located in the field plate trench 1708) that were damaged by the dry etch process in step 1828 are removed via this wet etch process. Some portions of the first spacer layer 148 remain upon completion of this wet etch process, and these portions are disposed on the upper surface of the second dielectric layer 118.

[0123] Next reference Fig.18 Step 1832 and Fig.34 At manufacturing stage 3400, a third dielectric layer 1702 is formed over the substrate 110. The third dielectric layer 1702 may be formed directly on the surface of the ILD layer 130, on the top and side surfaces of the second dielectric layer 118 in the field plate trench 1708, on the side surfaces of the first dielectric layer 116 in the field plate trench 1708, and on the surface 113 of the substrate 110 in the field plate trench 1708. In one or more embodiments, the third dielectric layer 1702 may be formed of a dielectric material, such as, by way of non-limiting example, Al2O3, SiN, Si3N4, SiO2, SiON, AlN, SiAlN, HfO2, ZrO2, TiO2, or another suitable material that may be deposited via PECVD or LPCVD. The third dielectric layer 1702 may have a thickness in a range of about 30 angstroms to about 5000 angstroms.

[0124] Next reference Fig.18 Step 1834 and Fig.35 , at manufacturing stage 3500, a field plate 1704 is formed on the third dielectric layer 1702. For example, a patterned conductive layer (e.g., deposited via sputtering, evaporation, or chemical vapor deposition, as non-limiting examples, and then patterned using a suitable photolithography process) can be formed over the substrate 110 to form the field plate 1704. For example, the conductive layer can include a conductive material such as TiW, TiWN, WSi, or other suitable materials. The conductive layer can have a thickness in the range of about 100 angstroms to about 5,000 angstroms, although other suitable thicknesses can also be used.

[0125] Using a dielectric layer (i.e., third dielectric layer 1702) formed after forming field plate trench 1708 to separate field plate 1704 from surface 113 of substrate 110 ensures that this dielectric material has not been damaged by the dry etching process used to form opening 3202 in ILD layer 130 overlapping field plate trench 1708 at step 1828. Removing and replacing damaged dielectric material in field plate trench 1708 reduces the likelihood of charge carrier traps existing in field plate trench 1708, which advantageously improves the performance of transistor device 1700. This approach also provides better thickness uniformity of the dielectric material separating field plate 1704 from surface 113 in field plate trench 1708, which advantageously reduces process variations regarding the amount of separation between field plate 1704 and surface 113 in field plate trench 1708, and advantageously improves the stability of the gate threshold voltage of transistor device 1700.

[0126] It should be understood that additional processing steps may be performed to fabricate transistor device 1700, and these additional processing steps may be performed during the Fig.18 As non-limiting examples, such processing steps may include depositing and patterning additional dielectric layers (e.g., dielectric layer 138 or other applicable dielectric layers) and metal layers (e.g., interconnect layers 140, 141 or other applicable metal layers).

[0127] The above description refers to elements or nodes or features being "connected" or "coupled" together. As used herein, unless otherwise expressly stated, "connection" means that one element is directly joined to another element (or is directly communicated with another element), and not necessarily mechanically joined. Similarly, unless otherwise expressly stated, "coupling" means that one element is directly or indirectly joined to another element (or is directly or indirectly communicated with another element), and not necessarily mechanically joined. Therefore, although the schematic diagram shown in the figure depicts an exemplary arrangement of elements, there may be other intervening elements, devices, features or components in the embodiments of the depicted subject matter. In addition, unless otherwise stated, the term "amplifier" used herein should be understood as a "power amplifier".

[0128] Although at least one exemplary embodiment has been presented in the above detailed description, it should be understood that there are a large number of variations. It should also be understood that one or more exemplary embodiments described herein are not intended to limit the scope, applicability or configuration of the claimed subject matter in any way. In fact, the above detailed description will provide a convenient guide for implementing the described one or more embodiments to those skilled in the art. It should be understood that various changes may be made to the functions and arrangements of the elements, including equivalents and foreseeable equivalents known at the time of filing this patent application, without departing from the scope defined in the claims.

Claims

1. A transistor device, characterized in that: include: Semiconductor substrate; a first dielectric layer, the first dielectric layer being disposed on a surface of the semiconductor substrate; a second dielectric layer disposed directly on the first dielectric layer, wherein a gate channel is at least partially defined via a first opening extending through the first dielectric layer and the second dielectric layer; a gate structure disposed directly on the surface of the semiconductor substrate in the gate channel, wherein portions of the first dielectric layer and the second dielectric layer are directly interposed between portions of the gate structure and the surface of the semiconductor substrate; as well as At least one dielectric spacer structure is disposed in the gate trench and between the gate structure and the semiconductor substrate, wherein the at least one dielectric spacer structure is in direct contact with respective side surfaces of the first dielectric layer and the second dielectric layer that at least partially define the gate trench.

2. The transistor device according to claim 1, characterized in that The at least one dielectric spacing structure comprises: a first layer disposed in direct contact with the respective side surfaces of the first dielectric layer and the second dielectric layer and with the surface of the semiconductor substrate; and A second layer is disposed in direct contact with each of the first layer and the gate structure.

3. The transistor device according to claim 2, characterized in that A portion of the first layer is disposed directly between the second dielectric layer and the surface of the semiconductor substrate.

4. The transistor device according to claim 1, characterized in that Also included is an interlayer dielectric layer disposed above the first dielectric layer, the second dielectric layer, and the gate structure.

5. The transistor device according to claim 4, characterized in that Also includes: A field plate is disposed to at least partially overlap the interlayer dielectric layer and the gate structure, such that the interlayer dielectric layer is interposed between the gate structure and the field plate.

6. The transistor device according to claim 5, characterized in that The field plate extends through a second opening in the first dielectric layer, the second dielectric layer, and the interlayer dielectric layer, wherein the second opening at least partially defines a field plate trench.

7. The transistor device according to claim 6, characterized in that Also includes: A third dielectric layer is directly disposed on surfaces of the interlayer dielectric layer, the first dielectric layer, and the second dielectric layer, and on the surface of the semiconductor substrate, wherein the field plate is directly disposed on the third dielectric layer.

8. The transistor device according to claim 7, characterized in that The third dielectric layer is disposed in the field plate trench and separates the field plate from the surface of the semiconductor substrate.

9. A method for manufacturing a transistor device, characterized in that The method comprises: providing a semiconductor substrate; forming a first dielectric layer on the semiconductor substrate; forming a second dielectric layer on the first dielectric layer; The gate trench is formed by the following steps: performing a patterned dry etch to form a first opening in the second dielectric layer; and performing a first wet etch to form a second opening in the first dielectric layer; forming a dielectric spacer structure in the gate trench; and A gate structure is formed, the gate structure being at least partially disposed in the gate trench and contacting surfaces of the semiconductor substrate, the second dielectric layer, and the dielectric spacer structure.

10. The method according to claim 9, characterized in that Forming the gate structure includes: forming a first patterned photoresist layer having a third opening overlapping the gate channel over the semiconductor substrate; forming a second patterned photoresist layer having a fourth opening overlapping the gate channel over the semiconductor substrate; and A metal is deposited over the semiconductor substrate, a first portion of the metal being deposited through the third opening and the fourth opening to form the gate structure, and a second portion of the metal being deposited on a surface of the first patterned photoresist layer.

Images