Transistor with recessed field plate and manufacturing method thereof

Abstract

The invention provides a transistor device and a manufacturing method thereof. Wherein the transistor device may include a first dielectric layer disposed on a surface of the semiconductor substrate, a second dielectric layer disposed directly on the first dielectric layer, a third dielectric layer disposed on the second dielectric layer, a gate structure disposed directly on the surface of the semiconductor substrate in the gate channel, and a field plate disposed to overlap the gate structure. A gate may be defined via an opening extending through the first dielectric layer, the second dielectric layer, and the third dielectric layer. Portions of the first dielectric layer and the second dielectric layer may be directly between the gate structure and the surface of the semiconductor substrate. A portion of the field plate may be disposed in a field plate channel at least partially defined via a second opening extending through the second dielectric layer and the third dielectric layer.

Description

Technical Field

[0001] Embodiments of the subject matter described herein relate generally to transistor devices, and more particularly, to semiconductor power transistor field plates. Background Art

[0002] High power field effect transistor (FET) devices are widely used in a variety of electronic components and systems. Although various advances have been made in improving the gain, efficiency and other characteristics of power FETs used to provide amplification in radio frequency (RF) communication systems, challenges remain in manufacturing such devices. For example, due in part to the transparency of silicon carbide (SiC) substrates and in part due to side effects such as heteroepitaxial growth (used to grow gallium nitride (GaN) on SiC) resulting in a lack of sufficiently uniform flatness of GaN substrates on SiC, manufacturing FETs with short gate lengths using only photolithography is more challenging for GaN-based FETs on SiC than for silicon (Si)-based FETs. As another example, dielectric layers exposed to multiple dry etching processes during device fabrication may experience plasma damage and etching-induced thickness variations, thereby unduly affecting performance and reliability. Summary of the invention

[0003] A brief overview of various exemplary embodiments is presented below. Some simplifications and omissions may be made in the following overview, which is intended to highlight and introduce some aspects of the various exemplary embodiments, but not to limit the scope. A detailed description of the exemplary embodiments sufficient to allow a person of ordinary skill in the art to obtain and use these concepts will be presented in subsequent sections.

[0004] In an exemplary embodiment, a transistor device includes a semiconductor substrate; a first dielectric layer, the first dielectric layer being disposed on a surface of the semiconductor substrate; a second dielectric layer, the second dielectric layer being disposed directly on the first dielectric layer; a third dielectric layer, the third dielectric layer being disposed on a portion of the second dielectric layer; a gate structure; and a field plate. A gate channel is at least partially defined by a first opening extending through the first dielectric layer, the second dielectric layer, and the third dielectric layer. The gate structure is disposed directly on the surface of the semiconductor substrate in the gate channel. Portions of the first dielectric layer and the second dielectric layer are directly between portions of the gate structure and the surface of the semiconductor substrate. The field plate is disposed to at least partially overlap the gate structure. A portion of the field plate is disposed in a field plate channel at least partially defined by a second opening extending through at least the second dielectric layer and the third dielectric layer.

[0005] In one or more embodiments, the transistor device further includes an interlayer dielectric layer disposed over the first dielectric layer, the second dielectric layer, the third dielectric layer, and the gate structure.

[0006] In one or more embodiments, the field plate at least partially overlaps the interlayer dielectric layer, such that the interlayer dielectric layer is interposed between the gate structure and the field plate.

[0007] In one or more embodiments, the transistor device further includes a fourth dielectric layer, which is at least partially disposed directly on the surface of the semiconductor substrate in the field plate trench.

[0008] In one or more embodiments, a portion of the fourth dielectric layer is directly disposed on surfaces of the interlayer dielectric layer, the first dielectric layer, the second dielectric layer, and the third dielectric layer.

[0009] In one or more embodiments, the field plate is disposed directly on the fourth dielectric layer.

[0010] In one or more embodiments, the fourth dielectric layer separates the field plate from the surface of the semiconductor substrate in the field plate trench.

[0011] In one or more embodiments, the first dielectric layer and the third dielectric layer each include a first dielectric material, the second dielectric layer and the interlayer dielectric layer each include a second dielectric material, and the second dielectric material has an etching rate different from that of the first dielectric material with respect to at least one wet etching process.

[0012] In an exemplary embodiment, a method for manufacturing a transistor device includes providing a semiconductor substrate; forming a first dielectric layer on the semiconductor substrate; forming a second dielectric layer on the first dielectric layer; forming a gate trench and a field plate trench by the following steps: performing a first patterned dry etch to form a first opening and a second opening in the second dielectric layer; and performing a first wet etch to form a third opening and a fourth opening in the first dielectric layer; forming a third dielectric layer directly on the second dielectric layer and directly on a surface of the semiconductor substrate exposed by the third opening and the fourth opening; removing a first portion of the third dielectric layer from the gate trench; forming a gate structure, the gate structure being at least partially disposed in the gate trench and contacting surfaces of the semiconductor substrate, the first dielectric layer, and the second dielectric layer; and forming a field plate overlapping the gate structure, wherein at least a portion of the field plate is disposed in the field plate trench.

[0013] In one or more embodiments, the method further includes forming a first patterned photoresist layer having a fifth opening overlapping the gate trench over the semiconductor substrate; and forming a second patterned photoresist layer having a sixth opening overlapping the gate trench over the semiconductor substrate. Removing the first portion of the third dielectric layer from the gate trench includes: after forming the first patterned photoresist layer and the second patterned photoresist layer, performing a second wet etch to remove the first portion of the third dielectric layer.

[0014] In one or more embodiments, the method further includes forming an interlayer dielectric layer on the gate structure and the third dielectric layer, wherein the field plate is disposed above the interlayer dielectric layer.

[0015] In one or more embodiments, the method further includes performing a second patterned dry etch to form a seventh opening in the interlayer dielectric layer, exposing a portion of the third dielectric layer through the seventh opening.

[0016] In one or more embodiments, the method further includes performing a second wet etch to remove a second portion of the third dielectric layer exposed through the seventh opening before forming the field plate; and forming a fourth dielectric layer disposed on the surface of the interlayer dielectric layer and on the surface of the semiconductor substrate in the field plate channel before forming the field plate.

[0017] In one or more embodiments, the field plate is formed in direct contact with the fourth dielectric layer, and the fourth dielectric layer is directly interposed between the field plate and the surface of the semiconductor substrate in the field plate trench.

[0018] In an exemplary embodiment, a method for manufacturing a transistor device includes providing a semiconductor substrate; forming a first dielectric layer on the semiconductor substrate; forming a second dielectric layer on the first dielectric layer; forming a gate trench and a field plate trench by at least the following steps: performing a first patterned dry etch to form a first opening and a second opening in the second dielectric layer; forming a third dielectric layer directly on a surface of the first dielectric layer and directly on a surface of the second dielectric layer exposed by the first opening and the second opening; performing a first wet etch to remove a first portion of the first dielectric layer and a first portion of the third dielectric layer from the gate trench, thereby exposing the surface of the semiconductor substrate in the gate trench; forming a gate structure, the gate structure being at least partially disposed in the gate trench and contacting surfaces of the semiconductor substrate, the first dielectric layer, and the second dielectric layer; and forming a field plate overlapping the gate structure, wherein at least a portion of the field plate is disposed in the field plate trench.

[0019] In one or more embodiments, the method further includes forming a first patterned photoresist layer having a third opening overlapping the gate channel above the semiconductor substrate; and forming a second patterned photoresist layer having a fourth opening overlapping the gate channel above the semiconductor substrate, wherein the first wet etching is performed after forming the second patterned photoresist layer.

[0020] In one or more embodiments, the method further includes forming an interlayer dielectric layer on the gate structure and the third dielectric layer, wherein the field plate is disposed above the interlayer dielectric layer.

[0021] In one or more embodiments, the method further includes performing a second patterned dry etch to form a fifth opening in the interlayer dielectric layer, exposing a portion of the third dielectric layer through the fifth opening.

[0022] In one or more embodiments, the method further includes performing a second wet etch to remove a second portion of the third dielectric layer exposed through the fifth opening before forming the field plate; and forming a fourth dielectric layer disposed on the surface of the interlayer dielectric layer and on the surface of the semiconductor substrate in the field plate channel before forming the field plate.

[0023] In one or more embodiments, the field plate is formed in direct contact with the fourth dielectric layer, and the fourth dielectric layer is directly interposed between the field plate and the surface of the semiconductor substrate in the field plate trench. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] A more complete understanding of the subject matter may be obtained by referring to the detailed description and claims when considered in conjunction with the following drawings, in which like reference numerals refer to like elements throughout the drawings.

[0025] Figure 1 is a cross-sectional side view of a transistor device according to various embodiments.

[0026] Figure 2 is a method for manufacturing a Figure 1 A process flow chart of a method for a transistor device.

[0027] Figure 3-17 is a diagram illustrating a method of combining Figure 2 The various manufacturing stages of the method Figure 1 Cross-sectional view of a transistor device.

[0028] Fig.18 is a method for manufacturing a Figure 1 A process flow chart of a method for a transistor device.

[0029] Figure 19-32 is a diagram illustrating a method of combining Fig.18 The various manufacturing stages of the method Figure 1 Cross-sectional view of a transistor device. DETAILED DESCRIPTION

[0030] The following detailed description is merely illustrative in nature and is not intended to limit the subject matter or the embodiments of the present application and the use of these embodiments. In addition, there is no intention to be bound by any explicit or implicit theory presented in the foregoing technical field, background technology or the following detailed description.

[0031] For simplicity and clarity of illustration, the drawings illustrate general constructions, and descriptions and details of well-known features and techniques may be omitted to avoid unnecessary confusion of the embodiments described herein. In addition, the elements in the drawings may not be drawn to scale. For example, the dimensions of certain elements or regions in the drawings may be enlarged relative to other elements or regions to help improve understanding of the embodiments described herein.

[0032] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims can be used to distinguish similar elements, and are not necessarily used to describe a specific sequence or time order. It should be understood that the terms used in this way are interchangeable where appropriate, so that the embodiments described herein can, for example, operate in a sequence different from the sequence shown or described herein. In addition, the terms "including", "having" and any variations thereof are intended to cover non-exclusive inclusions, so that the process, method, object or device including a series of elements is not necessarily limited to those elements, but may include other elements that are not explicitly listed or inherent to such a process, method, object or device. As used herein, the term "coupled" is defined as being connected directly or indirectly in an electrical or non-electrical manner. As used herein, the terms "substantially" and "substantially" mean that it is sufficient to achieve the purpose of the statement in a practical manner, and slight defects (if any) are not important for the purpose of the statement. As used herein, the words "exemplary" and "example" mean "serving as an example, instance or illustration". Any embodiment described as exemplary or example herein should not necessarily be interpreted as being preferred or advantageous over other embodiments.

[0033] Unless otherwise stated, directional references such as "top", "bottom", "left", "right", "above", "below", etc. are not intended to require any preferred orientation, but are made for illustration purposes with reference to the orientation of the corresponding figure or figures.

[0034] For the sake of brevity, conventional semiconductor manufacturing techniques may not be described in detail herein. In addition, certain terms may also be used herein for reference only and are therefore not intended to be limiting. For example, unless the context clearly indicates, the terms "first", "second", and other such numerical terms referring to structures do not imply a sequence or order.

[0035] Various embodiments described herein relate to transistor devices and associated fabrication methods in which one or more dielectric layers damaged by exposure to dry etching (e.g., due to plasma damage) are removed, replaced, or covered (at least partially) during a fabrication process. As will be described, removal and replacement of dry-etch damaged dielectric layers can advantageously reduce performance variations associated with such dielectric layers, can advantageously improve thickness uniformity of dielectric layers in transistor devices, and can advantageously reduce the incidence of charge carrier capture at or near the surface of a semiconductor substrate in a field plate channel.

[0036] In one or more embodiments, when manufacturing a transistor device, a first dielectric layer is formed on the surface of a semiconductor substrate, and a second dielectric layer is formed on the first dielectric layer. The gate channel and the field plate channel are formed at least in part by first performing a patterned dry etch on the second dielectric layer, during which the first dielectric layer acts as an etch stop layer to avoid damage to the surface of the semiconductor substrate. In one or more embodiments, portions of the first dielectric layer exposed (and possibly damaged) during the dry etch are subsequently removed via patterned or unpatterned wet etching. In one or more other embodiments, these portions of the first dielectric layer are removed alternatively via the same wet etching process used to remove the first and second portions of the third dielectric layer (described below).

[0037] In one or more embodiments, a portion of the field plate trench and the gate trench are formed simultaneously via dry etching and wet etching for removing portions of the second dielectric layer and portions of the first dielectric layer, respectively. The surface of the semiconductor substrate is exposed through the field plate trench. Subsequently, a third dielectric layer is formed over the substrate, wherein a first portion and a second portion of the third dielectric layer are formed directly on the surface of the semiconductor substrate in the gate trench and the field plate trench, respectively, thereby protecting the surface of the semiconductor substrate during subsequent processing steps. The first portion of the third dielectric layer is removed via wet etching (e.g., as a non-limiting example, in conjunction with a photolithography stripping process associated with the formation of the gate structure). After removing the first portion of the third dielectric layer in the gate trench, a conductive gate structure is formed by depositing a gate metal in and around the gate trench. After forming the gate structure, an interlayer dielectric (ILD) layer is formed over the gate structure, the second dielectric layer, and on a portion of the third dielectric layer disposed in the field plate trench. A patterned dry etch is performed to form an opening in the ILD layer overlapping the field plate trench, wherein a second portion of the third dielectric layer disposed in the field plate trench serves as an etch stop for the patterned dry etch of the ILD layer.

[0038] In one or more embodiments, a wet etch is then performed to remove the second portion of the third dielectric layer disposed in the field plate trench and exposed through the opening in the ILD layer (these portions may have been damaged during the patterned dry etch of the ILD layer), thereby exposing the surface of the semiconductor substrate. A fourth dielectric layer is then formed over the ILD layer and on the surface of the semiconductor substrate exposed in the field plate trench. A conductive field plate is then formed on the fourth dielectric layer, wherein at least a portion of the field plate is disposed in the field plate trench.

[0039] By lining the field plate trench with a fourth dielectric layer instead of possibly damaged portions of the first dielectric layer and / or the third dielectric layer, the material thickness between the field plate and the semiconductor substrate can be more accurately controlled. In addition, by removing potentially damaged portions of the first dielectric layer and the third dielectric layer in the field plate trench and subsequently depositing the fourth dielectric layer in the field plate trench, charge carrier capture due to such damaged dielectric layers can be reduced or avoided, which can advantageously improve the threshold voltage stability of the transistor device.

[0040] In one or more other embodiments, the portion of the third dielectric layer in the field plate trench is not removed, the fourth dielectric layer is not formed over the ILD layer, and instead the field plate is formed directly on the portion of the ILD layer and on the second portion of the third dielectric layer disposed in the field plate trench. This can advantageously reduce the surface of the semiconductor substrate exposed in the field plate trench, but may affect thickness uniformity. In one or more such embodiments, if the first dielectric layer is not removed before forming the third dielectric layer, the surface of the semiconductor substrate exposed in the field plate trench can be further reduced.

[0041] Figure 1 1 is a cross-sectional side view of a transistor device 100 according to one or more embodiments. The transistor device 100 may be formed on a semiconductor die having a base semiconductor substrate 110 (sometimes referred to herein as "substrate 110") and an overlying buildup structure 120. The substrate 110 is defined by an upper surface 113 and a lower surface 111 and a sidewall extending between the substrate lower surface 111 and the substrate upper surface 113. The buildup structure 120 includes a plurality of additional electrical structures, patterned conductive layers, and dielectric layers therein, and the buildup structure 120 is disposed in direct contact with and overlying the upper surface 113 of the substrate 110.

[0042] In one or more embodiments, an active region 150 is defined corresponding to a portion of the substrate 110 and an overlying portion of the buildup structure 120. One or more isolation regions 114 located at the upper surface 113 may be included within the substrate 110. The active region 150 may include a portion of the substrate 110 extending between at least two isolation regions 114.

[0043] In one or more embodiments, the semiconductor substrate 110 may include a main semiconductor substrate 102 (sometimes referred to herein as "main substrate 102") and a plurality of layers overlying the main substrate 102. In one or more embodiments, the layers overlying the main substrate 102 may include a buffer layer 104, a channel layer 106, and a barrier layer 112, all of which will be described in more detail below.

[0044] In one or more embodiments, the stacked structure 120 is formed on and above the upper surface 113 of the substrate 110 and includes various electrical structures (e.g., gate electrode 128, ohmic contact structures 134, 136), dielectric layers (e.g., dielectric layers 116, 118, 130, 138, 148, 152), and patterned conductive layers (e.g., field plate 135, interconnect layers 140, 141).

[0045] In one or more embodiments, a backside metal layer 142 is formed on the lower surface 111 of the substrate 110. The backside metal layer 142 may be electrically connected to a conductive material 146 (i.e., an electrically conductive material) formed in a through substrate via (TSV) 144, which electrically connects the backside metal layer 142 to the interconnect layer 140 at the upper surface 113 of the substrate 110.

[0046] A transistor 101 is formed in an active region 150 of the transistor device 100. In one or more embodiments, the transistor 101 is a field effect transistor (FET) including a gate electrode 128 (sometimes referred to herein as a "control electrode 128" or "gate structure 128"), a first ohmic contact structure 134 (sometimes referred to herein as a "source electrode 134" or "current carrying electrode" 134) proximate to but spaced apart from a first sidewall of the gate electrode 128, and a second ohmic contact structure 136 (sometimes referred to as a "drain electrode 136" or "current carrying electrode 136") proximate to but spaced apart from a second sidewall of the gate electrode 128, each of which is disposed at an upper surface 113 of a substrate 110 and formed in a buildup structure 120 overlying the substrate 110. In one or more embodiments, the transistor 101 is a high electron mobility transistor (HEMT). In one or more embodiments, the transistor 101 is a gallium nitride (GaN) HEMT. It should be understood that these are non-limiting examples and that transistor 101 may be another suitable type of transistor according to one or more other embodiments.

[0047] The ohmic contact structures 134, 136 are formed at and above the upper surface 113 of the substrate 110. In one or more embodiments, the respective interfaces between the ohmic contact structures 134, 136 and the respective portions of the substrate 110 correspond to non-rectifying low-resistance junctions (i.e., “ohmic contacts”) through which current can be easily conducted between the semiconductor material of the substrate 110 and the conductive material of the ohmic contact structures 134, 136. For example, the ohmic contact structures 134, 136 can be formed substantially in a plane relative to each other, and the source electrode 134 and the drain electrode 136 can both extend through at least the dielectric layers 116, 118 (sometimes referred to herein as “first dielectric layer 116” and “second dielectric layer 118”, respectively) to directly contact the upper surface 113 of the substrate 110. In addition, the ohmic contact structures 134, 136 can be electrically coupled to opposite ends of the channel 108 disposed in the channel layer 106 of the substrate 110, respectively. The first ohmic contact structure 134 can be electrically coupled to the TSV 144 and the backside metal layer 142 through patterned portions of one or more interconnect metal layers (e.g., interconnect layer 140) of the buildup structure 120. For example, the second ohmic contact structure 136 can be electrically coupled to an output (not shown) of the transistor device 100 via the interconnect layer 141.

[0048] In one or more embodiments, the gate electrode 128 may be a metal structure electromagnetically coupled to the channel 108. In one or more embodiments, the gate electrode 128 includes a metal material, such as, as a non-limiting example, gold, nickel, copper, tungsten, or any suitable combination of these metal materials. In one or more other embodiments, the gate electrode 128 includes a non-metal material, such as, as a non-limiting example, appropriately doped polysilicon. According to an embodiment, the gate electrode 128 extends through at least the first dielectric layer 116, the second dielectric layer 118, and the third dielectric layer 148 to contact the upper surface 113 of the substrate 110 between the ohmic contact structures 134, 136. The openings in the first dielectric layer 116 and the second dielectric layer 118 are sometimes referred to herein as "gate channels" through which portions of the gate electrode 128 are formed. The region of the buildup structure 120 where the gate electrode 128 is formed is sometimes referred to herein as a "gate channel region". In one or more embodiments, the interface where the gate electrode 128 contacts the substrate 110 is a Schottky contact.

[0049] In one or more embodiments, the build-up structure 120 includes dielectric layers 116, 118, 148 disposed above the upper surface 113 of the substrate 110, an interlayer dielectric (ILD) layer 130 formed on the gate electrode 128 and a portion of the dielectric layer 118, a dielectric layer 152 formed on the surface 113 on a portion of the ILD layer 130 and in a field plate trench 154, a field plate 135 formed on a portion of the fourth dielectric layer 152 (an overlapping portion of the gate electrode 128) and in the field plate trench 154, and a dielectric layer 138 formed over the field plate 135 and a portion of the ILD layer 130. The field plate trench 154 is at least partially defined by openings in the first dielectric layer 116 and the second dielectric layer 118. As mentioned above, the gate electrode 128 may extend through the openings in the dielectric layers 116, 118. Each of the gate electrode 128 and the ohmic contact structures 134, 136 contacts the upper surface 113 of the substrate 110 at various points directly above the channel 108. In one or more embodiments, the first dielectric layer 116 can have a thickness in a range of about 30 angstroms to about 1,500 angstroms, and the second dielectric layer 118 can have a thickness in a range of about 100 angstroms to about 4,000 angstroms, although other suitable thickness values ​​may also be used. Herein, unless otherwise stated, a value is considered to be "about" or "approximately" equal to a stated number if it is within + / -10% of the stated number.

[0050] In one or more embodiments, the dielectric layers 116, 118, 148, 152 are formed of a respective dielectric material, such as aluminum oxide (Al2O3), silicon nitride (SiN; sometimes Si3N4), silicon oxide (SiO2), silicon oxynitride (SiON), aluminum nitride (AlN), silicon aluminum nitride (SiAlN), hafnium oxide (HfO2), zirconium oxide (ZrO2), titanium oxide (TiO2), or other suitable dielectric materials. In one or more embodiments, the first dielectric layer 116 and the third dielectric layer 148 may be etched separately relative to the second dielectric layer 118 with respect to one or more etching processes (e.g., as non-limiting examples, a wet chemical etching process, such as buffered oxide etching (BOE) or phosphoric acid etching; or a dry etching process, such as reactive ion etching (RIE) or other suitable plasma etching processes). For example, the first dielectric layer 116 and the third dielectric layer 148 may each be formed of the same first dielectric material (e.g., an oxide material, such as aluminum oxide (AlOx)), and the second dielectric layer 118 may be formed of the same second dielectric material (e.g., a nitride material, such as silicon nitride (SiNx)) that is separately etchable relative to the first dielectric material. In one or more other embodiments, the first dielectric layer 116 and the third dielectric layer 148 may be formed of different dielectric materials (e.g., different oxide materials), respectively. For example, the first dielectric layer 116 may be formed of an oxide (e.g., as a non-limiting example, SiO2, ZrO2, HfO2, Al2O3, or TiO2), the second dielectric layer 118 may be formed of a nitride (e.g., as a non-limiting example, SiN, AlN, SiAlN), and the third dielectric layer 148 may be formed of an oxide material (e.g., as a non-limiting example, SiO2, ZrO2, HfO2, Al2O3, or TiO2). As used herein, two given materials are considered to be "individually etchable" with respect to a given etching process if, with respect to the given etching process, the etching rate of the first of the two materials is significantly greater (e.g., approximately 1.5 times greater or greater) than the etching rate of the second of the two materials.

[0051] In one or more embodiments, the dielectric layers 116, 118, 148, 152 are formed over the substrate 110 using a corresponding chemical vapor deposition process such as low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), or atomic layer deposition (ALD). For example, in one or more embodiments, the first dielectric layer 116 and the third dielectric layer 148 may each be AlO formed using an ALD process. x In one or more embodiments, the second dielectric layer 118 may be SiNx formed using a PECVD process.

[0052] The field plate 135 may be formed by a portion of the first conductive layer that at least partially overlaps the gate electrode 128, the dielectric layers 116, 118, 148, and the ILD layer 130. The field plate 135 may be at least partially disposed in the field plate trench 154, wherein the field plate 135 is separated from the surface 113 of the substrate 110 in the field plate trench 154 by the fourth dielectric layer 152. At various points above the trench 108 (along the path extending directly to the field plate 154), the field plate 135 may be formed by a portion of the first conductive layer that at least partially overlaps the gate electrode 128, the dielectric layers 116, 118, 148, and the ILD layer 130. Figure 1 108), a conductive material strip (not shown in the cross section currently shown) is formed in region 132 to electrically connect field plate 135 to interconnect layer 140. At other points above trench 108, dielectric material from dielectric layer 138 may alternatively be formed in region 132, such as Figure 1 The conductive material strip formed in region 132 (in conjunction with interconnect layer 140) electrically couples field plate 135 to source electrode 134 and conductive material 146 of TSV 144 (e.g., to a ground or reference potential for situations where back metal 142 is coupled to or otherwise configured to provide an electrical ground or reference potential).

[0053] The field plate 135 may be formed of one or more conductive materials, such as, for example, titanium tungsten (TiW), titanium tungsten nitride (TiWN), tungsten silicide (WSi), as non-limiting examples. In one or more embodiments, at least some portions of the field plate 135 overlie the gate electrode 128 and are thus proximate to one or more sidewalls and an upper surface of the gate electrode 128, wherein portions of the ILD layer 130 and the fourth dielectric layer 152 are disposed directly between the field plate 135 and the gate electrode 128.

[0054] The fourth dielectric layer 152 may be formed after forming the field plate trench 154 and before forming the field plate 135. Using a dielectric layer formed after forming the field plate trench 154 (i.e., using the fourth dielectric layer 152) to separate the field plate 135 from the surface 113 of the substrate 110 ensures that this dielectric material has not been damaged by an etch (e.g., dry etch) used to form an opening in the ILD layer 130 that overlaps the field plate trench 154. Removing and replacing damaged dielectric material in the field plate trench 154 reduces the likelihood of charge carrier traps existing in the field plate trench 154, which advantageously improves the performance of the transistor device 100, including reducing threshold voltage instabilities of the transistor device 100. This approach also provides better thickness uniformity of the dielectric material separating the field plate 135 from the surface 113 in the field plate trench 154, which advantageously reduces process variations regarding the amount of separation between the field plate 135 and the surface 113 in the field plate trench 154.

[0055] The arrangement shown in the current example is for illustration and not limitation. For example, in one or more other embodiments, the fourth dielectric layer 152 may be omitted, and the third dielectric layer 148 (alone or in combination with the first dielectric layer 116 according to various embodiments) may instead cover the surface 113 of the substrate 110 in the field plate trench 154. In such embodiments, at least because the third dielectric layer 148 is not removed to expose the surface 113 of the substrate 110 after forming the opening in the ILD layer 130, the surface 113 of the substrate 110 may be advantageously reduced in exposure.

[0056] Figure 2 is a diagram illustrating a method for manufacturing a transistor device (eg, Figure 1 For enhanced understanding, Figure 2 Can be used with Figure 3-17 Also check out, Figure 3-17 Depicts products in various stages of manufacture Figure 1 1. A cross-sectional view of one or more embodiments of a transistor device 100.

[0057] First reference Figure 2 Step 202 and Figure 3 , in a first manufacturing stage 300, a semiconductor substrate 110 is provided, and an active region 150 is defined in the semiconductor substrate 110. As previously mentioned, the semiconductor substrate 110 may include a main semiconductor substrate 102 (sometimes referred to as "main substrate 102") and a plurality of layers overlying the main substrate 102. In one or more embodiments, the layers overlying the main substrate 102 include a buffer layer 104, a channel layer 106, and a barrier layer 112.

[0058] In one or more embodiments, the main substrate 102 includes an upper surface 302 and can be formed of silicon carbide (SiC). In one or more other embodiments, the main substrate 102 can include other materials, such as sapphire, silicon (Si), gallium nitride (GaN), aluminum nitride (AlN), diamond, boron nitride (BN), polycrystalline SiC, silicon on insulator, gallium arsenide (GaAs), indium phosphide (InP) and other substantially insulating or highly resistive materials.

[0059] The buffer layer 104 may be formed on the upper surface 302 of the main substrate 102. The buffer layer 104 may include one or more Group III nitride semiconductor layers. In one or more embodiments, the buffer layer 104 includes multiple layers of semiconductor material, wherein each layer of the buffer layer 104 may include, for example, an epitaxially grown Group III nitride layer. In such an embodiment, the epitaxially grown Group III nitride layer of the buffer layer 104 may include, for example, a nitrogen (N) polarity (i.e., N-face) or gallium (Ga) polarity (i.e., Ga-face) material. In one or more other embodiments, the semiconductor layer of the buffer layer 104 may not be epitaxially grown. In yet other embodiments, the semiconductor layer of the buffer layer 104 may include Si, GaAs, InP or other suitable materials.

[0060] In one or more embodiments, the buffer layer 104 may include an Al2O3 layer having a molar fraction of aluminum of X. X Ga 1-X N represents at least one AlGaN mixed crystal layer of a composition of , and X can take a value between 0 and 1. The total thickness of the buffer layer 104 including all of its constituent layers can be between about 100 angstroms and about 100,000 angstroms, but other thicknesses can also be used. An extreme X value of 0 produces pure GaN, while a value of 1 produces pure aluminum nitride (AlN). In one or more embodiments, the buffer layer 104 can include a nucleation zone composed of AlN. The nucleation zone begins at the interface between the host substrate 102 and the buffer layer 104 and can extend from about 100 angstroms to about 1,000 angstroms into the buffer layer 104. The buffer layer 104 can include additional Al formed above the nucleation zone. X Ga 1-X N layer. Additional Al X Ga 1-X The thickness of the N layer may be between about 100 angstroms and about 50,000 angstroms, although other thicknesses may be used. X Ga 1-X The N layer can be configured as a GaN layer (X=0), where Al X Ga 1-X The N layer is not intentionally doped (NID). Alternatively, additional Al X Ga 1-X The N layer may be configured as one or more GaN layers, wherein the one or more GaN layers are intentionally doped with a dopant, which may include iron (Fe), chromium (Cr), carbon (C), or other suitable dopants that render the buffer layer 104 substantially insulating or highly resistive. The dopant concentration may be about 10 17 cm -3 With about 10 19 cm -3 However, other higher or lower concentrations may be used.X Ga 1-X The N layer can be configured to have X = 0.01 to 0.10, where Al X Ga 1X N is NID, or alternatively, where Al X Ga 1-X N is intentionally doped with Fe, Cr, C, combinations of these components, or other suitable dopant species. In one or more other embodiments, additional Al X Ga 1-X The N layer can be configured as a superlattice, where additional Al X Ga 1-X The N layer consists of a series of alternating NID layers or doped Al X Ga 1-X N layers, where the value of X takes a value between 0 and 1. In yet other embodiments, the buffer layer 104 may include a Y Ga 1-Y N, where the indium mole fraction Y can take a value between 0 and 1. The thickness of the InGaN layer can be between about 10 angstroms and about 1,000 angstroms, although other thicknesses can also be used.

[0061] In one or more embodiments, the channel layer 106 may be formed on the buffer layer 104. The channel layer 106 may include one or more III-nitride semiconductor layers. The channel layer 106 may include Al X Ga 1-X N layers, where X takes a value between 0 and 1. In one or more embodiments, the channel layer 106 is configured as GaN (X=0), although other X values ​​may also be used. The thickness of the channel layer 106 may be between about 50 angstroms and about 10,000 angstroms, although other thicknesses may also be used. The channel layer 106 may be NID, or alternatively, may include Si, Ge, C, Fe, Cr, or other suitable dopants. The dopant concentration may be about 10 16 cm -3 With about 10 19 cm -3 In other embodiments, the channel layer 106 may include NID or doped In Y Ga 1-Y N, where the indium mole fraction Y can take a value between 0 and 1.

[0062] According to one or more embodiments, the barrier layer 112 may be formed over the channel layer 106. The barrier layer 112 may include one or more III-N semiconductor layers. The barrier layer 112 may have a larger band gap and / or a larger spontaneous polarization than the channel layer 106, and when the barrier layer 112 is over the channel layer 106, the channel 108 may be formed in the form of a two-dimensional electron gas (2-DEG) within the channel layer 106 adjacent to the interface between the channel layer 106 and the barrier layer 112. In addition, the tensile strain between the barrier layer 112 and the channel layer 106 may cause additional piezoelectric charges to be introduced into the 2-DEG and the channel 108. The barrier layer 112 may include a multi-layer structure, wherein the first layer of the barrier layer 112 may include at least one NID Al X Ga 1-X N layers, where X takes a value between 0 and 1. In one or more embodiments, X may take a value between 0.1 and 0.35, although other X values ​​may also be used. The first layer of barrier layer 112 may have a thickness between about 50 angstroms and about 1,000 angstroms, although other thicknesses may also be used. Barrier layer 112 may be NID, or alternatively, may include Si, Ge, C, Fe, Cr, or other suitable dopants. The dopant concentration may be about 10 16 cm -3 with 10 19 cm -3 However, other higher or lower concentrations may also be used.

[0063] In one or more embodiments, an additional AlN interlayer barrier (not shown) may be formed between the channel layer 106 and the barrier layer 112. The AlN interlayer barrier may introduce additional spontaneous and piezoelectric polarization, thereby increasing the channel charge and improving electron confinement of the resulting 2-DEG forming the channel 108.

[0064] In other embodiments, the barrier layer 112 may include a Y Al 1-Y N, wherein the indium mole fraction Y can take a value between about 0.1 and about 0.2, although other values ​​of Y can also be used. In the case of using InAlN to form the barrier layer 112, the thickness of the barrier layer 112 can be between about 50 angstroms and about 1,000 angstroms, although other thicknesses can also be used. In the case of using InAlN to form the barrier layer 112, the InAlN can be NID, or alternatively, can include Si, Ge, C, Fe, Cr or other suitable dopants. The dopant concentration can be between about 10 16 cm -3 With about 10 19 cm -3 However, other higher or lower concentrations may also be used.

[0065] In one or more embodiments, a capping layer (not shown) may be formed over the barrier layer 112. When included, the capping layer provides a stable surface for the substrate 110 and serves to protect the upper surface 113 of the substrate 110 from chemical and environmental exposure incidental to wafer processing. The capping layer may include one or more III-N semiconductor layers and is supported by the barrier layer 112. In one or more embodiments, the capping layer includes GaN. The thickness of the capping layer may be between about 5 angstroms and about 100 angstroms, although other thicknesses may also be used. The capping layer may be NID, or alternatively, may include Si, Ge, C, Fe, Cr, or other suitable dopants. The dopant concentration may be about 10 16 cm -3 with 10 19 cm -3 However, other higher or lower concentrations may also be used.

[0066] The isolation regions 114 may be formed via an implantation process configured to damage the epitaxial layer and / or other semiconductor layers to produce a high resistive region of the substrate 110, thereby rendering the substrate 110 highly resistive or semi-insulating in the high resistive region while leaving the crystal structure intact in the active region 150. In other embodiments (not shown), one or more of the isolation regions 114 may be formed by removing a portion of one or more of the epitaxial layer and / or other semiconductor layers of the substrate 110 and leaving an active region "table" (e.g., active region 150) surrounded by the isolation regions 114 (i.e., surrounded by a region of highly resistive or semi-insulating material). Subsequently, a high resistive or semi-insulating material may be formed within the active region 150. Figure 1 transistor 101.

[0067] Next reference Figure 2 Step 204 and Figure 4 During the manufacturing stage 400, a first dielectric layer 116 is formed on (e.g., directly on and in contact with) the upper surface 113 of the semiconductor substrate 110. As described above, in one or more embodiments, the first dielectric layer 116 may have a thickness in a range of about 30 angstroms to about 1,500 angstroms. The first dielectric layer 116 may be formed of a dielectric material, such as, as non-limiting examples, Al2O3, SiN, Si3N4, SiO2, SiON, AlN, SiAlN, HfO2, ZrO2, TiO2, or another suitable material that may be deposited via chemical vapor deposition (e.g., LPCVD). In one or more embodiments, the first dielectric layer 116 may include an oxide (e.g., as non-limiting examples, SiO2, ZrO2, HfO2, Al2O3, or TiO2).

[0068] Next reference Figure 2 Step 206 and Figure 5 During the manufacturing stage 500, a second dielectric layer 118 is formed on the first dielectric layer 116 (e.g., directly on and in contact with the first dielectric layer 116). As described above, in one or more embodiments, the second dielectric layer 118 can have a thickness in a range of about 100 angstroms to about 4,000 angstroms. The second dielectric layer 118 can be formed of a dielectric material, such as, as non-limiting examples, Al2O3, SiN, Si3N4, SiO2, SiON, AlN, SiAlN, HfO2, ZrO2, TiO2, or another suitable material that can be deposited via plasma enhanced chemical vapor deposition (e.g., PECVD). In one or more embodiments, the second dielectric layer 118 can include a nitride (e.g., as non-limiting examples, SiN, AlN, SiAlN).

[0069] Next reference Figure 2 Step 208 and Figure 6 During fabrication stage 600, a patterned dry etch is performed to form openings 602, 604 in second dielectric layer 118. Herein, a "patterned etch process" refers to a process that performs material etching in conjunction with a photolithography process such that material is etched through openings in a patterned photoresist layer.

[0070] For example, during the manufacturing stage 600, a dry etching process (e.g., as a non-limiting example, an RIE process or other plasma etching process) is performed in conjunction with a photolithography process to remove portions of the second dielectric layer 118, thereby forming openings 602, 604 in the second dielectric layer 118, each of which exposes the surface of the first dielectric layer 116. The first dielectric layer 116 can act as an etch stop layer for this dry etching process, thereby mitigating or preventing damage to the surface 113 of the substrate 110. This makes it possible for the exposed portions 606, 608 of the first dielectric layer 116 to be damaged by the dry etching process (e.g., due to plasma damage).

[0071] In addition, some material in the exposed portion 608 of the first dielectric layer 116 is removed during the dry etching process, and the amount of material removed in this manner may be process dependent and may not be uniform across transistor devices fabricated simultaneously (e.g., when processing a wafer including multiple transistor devices). This may result in uncertainty in the thickness of the exposed portion 608 and non-uniformity of the exposed portion 608.

[0072] Next reference Figure 2 Step 210 and Figure 7During the manufacturing stage 700, a wet etch is performed to remove portions 606, 608 of the first dielectric layer 116 that may be damaged due to exposure to the etching process in step 208. The wet etch forms openings 702, 704 that extend through the first dielectric layer 116 and the second dielectric layer 118, respectively. In one or more embodiments, the wet etch is a patterned wet etch. In one or more other embodiments, the wet etch is performed without using a photolithography process, and instead the openings 702, 704 are formed by utilizing an existing pattern generated by the dry etching process performed in step 208.

[0073] In one or more embodiments, portions 606, 608 of the first dielectric layer 116 are removed via an anisotropic wet etching process that selectively etches the dielectric substance (e.g., oxide material) of the first dielectric layer 116 at a higher etching rate than the dielectric material (e.g., nitride material) of the second dielectric layer 118. As shown, the wet etching may partially undercut the second dielectric layer 118 in the region of the openings 702, 704. The opening 702 may define a portion of the second dielectric layer 118 that may be formed in a subsequent manufacturing stage (e.g., Fig.11 The gate structure is at least partially formed at least a portion of the gate channel of the gate structure at the manufacturing stage 1100. The opening 704 may define a portion of the gate channel of the gate structure at a subsequent manufacturing stage (eg, Fig.17 The process of manufacturing the field plate 135 at least partially forms at least a portion of the field plate trench 154 of the field plate 135. As used herein, "wet etching" generally refers to wet chemical etching unless otherwise specified.

[0074] Removing the portion 608 of the first dielectric layer 116 in this manner avoids the portion 608 from acting as a charge carrier trapping center in the transistor 101 due to any damaged portion 608 that may result from the dry etching in step 208. Removing the portion 608 of the first dielectric layer 116 also avoids or reduces thickness non-uniformities in the first dielectric layer 116 due to partial etching of the portion 608 during the dry etching in step 208. Additionally, in conventional methods, the exposed portion of the first dielectric layer would need to be thick enough to act as an etch stop layer for multiple etching processes. In contrast, in embodiments of the present invention, the exposed portions 606, 608 of the first dielectric layer 116 act as an etch stop layer only immediately before being removed, which allows the use of a relatively thin first dielectric layer 116. By using a thinner first dielectric layer 116, the amount of undercutting that occurs when a wet etch is performed to remove the portions 606, 608 can be advantageously reduced.

[0075] Next reference Figure 2 Step 212 and Figure 8During the manufacturing stage 800, a third dielectric layer 148 is formed over the substrate 110. The third dielectric layer 148 may be formed directly on the top and side surfaces of the second dielectric layer 118, the side surfaces of the first dielectric layer 116, and the surface 113 of the substrate 110 exposed by the openings 702, 704 in the gate trench 802 and the field plate trench 154. In one or more embodiments, the third dielectric layer 148 may be formed of a dielectric material, such as, as non-limiting examples, Al2O3, SiN, Si3N4, SiO2, SiON, AlN, SiAlN, HfO2, ZrO2, TiO2, or another suitable material that may be deposited via chemical vapor deposition (e.g., LPCVD). In one or more embodiments, the third dielectric layer 148 may include an oxide (e.g., as non-limiting examples, SiO2, ZrO2, HfO2, Al2O3, or TiO2).

[0076] Next reference Figure 2 Step 214 and Fig. 9 During the manufacturing stage 900, a first patterned photoresist layer 902 and a second patterned photoresist layer 904 are formed over the substrate 110. For example, the first patterned photoresist layer 902 and the second patterned photoresist layer 904 can be formed via respective photolithography processes, each of which includes spin coating a photoresist material (e.g., a resin) over the substrate 110, exposing the photoresist material to ultraviolet (UV) light through a patterned mask and baking at a predetermined temperature, and removing portions of the photoresist material using a developer (e.g., removing those portions exposed to UV light when a positive photoresist material is used, or removing those portions not exposed to UV when a negative photoresist material is used). An opening 906 is formed through the first photoresist layer 902 and the second photoresist layer 904, exposing a region including the gate channel 802 (i.e., a "gate channel region") through the opening 906.

[0077] In one or more embodiments, the first photoresist layer 902 can be developed simultaneously with the second photoresist layer 904. As shown, the opening in the first photoresist layer 902 can be wider than the opening in the second photoresist layer 904, such that the second photoresist layer 904 overhangs the first photoresist layer 902 in the region of the opening 906.

[0078] In an exemplary embodiment, the first photoresist layer 902 has a thickness of about 0.5 μm to about 2 μm, but it is understood that other suitable thicknesses may be used. In an exemplary embodiment, the second photoresist layer 904 has a thickness of between about 0.25 μm and about 1.5 μm, but other suitable thicknesses may also be used.

[0079] Next reference Figure 2 Step 216 and Fig.10 During the manufacturing stage 1000, a wet etch is performed to remove exposed portions of the third dielectric layer 148. For example, portions of the third dielectric layer 148 exposed through the opening 906 are removed via this wet etch process. Some portions of the third dielectric layer 148 remain when this wet etch process is completed, and these portions are disposed under the photoresist layer 902.

[0080] Next reference Figure 2 Step 218 and Fig.11 During the manufacturing stage 1100, a gate structure 128 is formed through the opening 906 in the first photoresist layer 902 and the second photoresist layer 904. The gate structure 128 can be electromagnetically coupled to the channel 108 through the upper surface 113 of the substrate 110 and the barrier layer 112. During operation of the transistor device 100, a potential change on the gate structure 128 can shift the quasi-Fermi level of the barrier layer 112 compared to the quasi-Fermi level of the channel layer 106, thereby modulating the electron concentration in the channel 108 within the portion of the substrate 110 below the gate structure 128.

[0081] In one or more embodiments, the gate structure 128 may be configured as a Schottky gate and may be formed over and in direct contact with the substrate upper surface 113 using a Schottky material layer and a conductive metal layer. In one or more embodiments, a Schottky or other suitable material may be combined with a highly conductive material in a metal stack to form the gate structure 128. For example, a Schottky material layer may first be formed in contact with the substrate 110, and a conductive low stress metal may be deposited over the Schottky material to form the gate structure 128. In one or more other embodiments, the gate structure 128 may be formed on a gate dielectric or gate oxide (not shown) on the upper surface 113 of the substrate 110, thereby forming a metal insulator semiconductor (MIS) junction or a metal oxide semiconductor (MOS) junction that may be electrically coupled to the channel 108 through the gate dielectric or gate oxide layer.

[0082] According to one or more embodiments, the gate structure 128 may have a T-shaped cross-section, as shown in the current example, with a vertical stem through at least the first dielectric layer 116 and the second dielectric layer 118 in the gate channel 802 on the substrate 110, and a wider portion above the vertical stem with a horizontal portion overlying and contacting the upper surface of the second dielectric layer 118. In one or more other embodiments (not shown), the gate structure 128 may have a square or circular cross-sectional shape. In one or more other embodiments, the vertical stem or lower portion of the gate structure 128 may be recessed through the upper surface 113 of the semiconductor substrate 110 and may partially extend into the barrier layer 112, thereby increasing the electrical coupling of the gate structure 128 to the channel 108 through the barrier layer 112.

[0083] The gate metal of the gate structure 128 may be deposited by evaporation, sputtering, chemical vapor deposition or other suitable processes. For example, a first portion of the deposited gate metal may be disposed in the opening 906 to form at least a portion of the gate structure 128, and a second portion of the deposited gate metal may be disposed on the upper surface of the second photoresist layer 904.

[0084] Next reference Figure 2 Step 220 and Fig.12 , at manufacturing stage 1200, the first photoresist layer 902, the second photoresist layer 904, and the second portion of the gate metal deposited on the surface of the second photoresist layer 904 are simultaneously removed via a stripping process. For example, in the stripping process, a photoresist stripper (e.g., a solvent such as acetone, 1-methyl-2-pyrrolidone, or dimethyl sulfoxide) can be applied to remove the first photoresist layer 902 and the second photoresist layer 904, which separates (i.e., "strips") the excess gate metal on the surface of the second photoresist layer 904.

[0085] Although combined Figure 2 Steps 214, 216, 218, 220 and Figure 9-12 The manufacturing stages 900, 1000, 1100, 1200 of the present invention describe a double-layer lift-off process, but it should be understood that this is for illustration and not limitation. For example, in one or more other embodiments, other photolithography processes (e.g., using a single photoresist layer developed with an undercut profile) may be used instead when forming the gate structure 128.

[0086] Next reference Figure 2 Step 222 and Fig.13At manufacturing stage 1300, an ILD layer 130 is formed over the substrate 110 (e.g., in contact with a surface of each of the second dielectric layer 118 and the gate structure 128). In one or more embodiments, the ILD layer 130 has a thickness in a range of about 500 angstroms to about 10,000 angstroms, although other suitable thicknesses may also be used. As non-limiting examples, the ILD layer 130 may be formed of silicon nitride, silicon oxide, silicon oxynitride, or other suitable dielectric materials.

[0087] Next reference Figure 2 Step 224 and Fig.14 , at manufacturing stage 1400, a patterned dry etch is performed to form an opening 1402 in the ILD layer 130. For example, during manufacturing stage 1400, an anisotropic dry etch process (e.g., as a non-limiting example, a RIE process or other plasma etch process) may be performed to remove portions of the ILD layer 130 to form the opening 1402. The opening 1402 may overlap the field plate trench 154. The third dielectric layer 148 may act as an etch stop layer for this dry etch process, thereby mitigating or preventing damage to the surface 113 of the substrate 110. This causes the exposed portion of the third dielectric layer 148 to be damaged by the dry etch process (e.g., due to plasma damage).

[0088] Next reference Figure 2 Step 226 and Fig.15 At manufacturing stage 1500, a wet etch is performed to remove exposed portions of the third dielectric layer 148 (i.e., portions exposed through the opening 1402). For example, exposed portions of the third dielectric layer 148 (those portions located in the field plate trenches 154) that were damaged by the dry etch process at step 1828 are removed via this wet etch process. Portions of the third dielectric layer 148 remain upon completion of this wet etch process, and these portions are disposed between the upper surface of the second dielectric layer 118 and the ILD layer 130. Removal of these portions of the third dielectric layer 148 exposes the upper surface 113 of the substrate 110 (i.e., through the opening 1402).

[0089] Next reference Figure 2 Step 228 and Fig.16At manufacturing stage 1600, a fourth dielectric layer 152 is formed over the substrate 110. The fourth dielectric layer 152 may be formed directly on the surface of the ILD layer 130, on the top and side surfaces of the second dielectric layer 118 in the field plate trenches 154, on the side surfaces of the first dielectric layer 116 in the field plate trenches 154, and on the surface 113 of the substrate 110 in the field plate trenches 154. In one or more embodiments, the fourth dielectric layer 152 may be formed of a dielectric material, such as, by way of non-limiting example, Al2O3, SiN, Si3N4, SiO2, SiON, AlN, SiAlN, HfO2, ZrO2, TiO2, or another suitable material that may be deposited via PECVD or LPCVD. The fourth dielectric layer 152 may have a thickness in a range of about 30 angstroms to about 5000 angstroms.

[0090] Next reference Figure 2 Step 230 and Fig.17 At manufacturing stage 1700, a field plate 135 is formed on the fourth dielectric layer 152 (e.g., as a non-limiting example, deposited via sputtering, evaporation, or chemical vapor deposition, and then patterned using a suitable photolithography process). For example, a patterned conductive layer can be formed over the substrate 110 (e.g., as a non-limiting example, deposited via sputtering, evaporation, or chemical vapor deposition, and then patterned using a suitable photolithography process) to form the field plate 135. For example, the conductive layer can include a conductive material such as TiW, TiWN, WSi, or other suitable materials. The conductive layer can have a thickness in a range of about 100 angstroms to about 5,000 angstroms, although other suitable thicknesses can also be used.

[0091] Separating the field plate 135 from the surface 113 of the substrate 110 using a dielectric layer (i.e., fourth dielectric layer 152) formed after forming the field plate trench 154 ensures that this dielectric material has not been damaged by the dry etching process used at step 226 to form the opening 1402 in the ILD layer 130 extending through the third dielectric layer 148 overlapping the field plate trench 154. Removing and replacing damaged dielectric material in the field plate trench 154 reduces the likelihood of charge carrier traps existing in the field plate trench 154, which advantageously improves the performance of the transistor device 100. This approach also provides better thickness uniformity of the dielectric material separating the field plate 135 from the surface 113 in the field plate trench 154, which advantageously reduces process variations with respect to the amount of separation between the field plate 135 and the surface 113 in the field plate trench 154, and advantageously improves the stability of the gate threshold voltage of the transistor device 100.

[0092] It should be understood that additional processing steps may be performed to fabricate the transistor device 100, and these additional processing steps may be performed during the Figure 2As non-limiting examples, such processing steps may include depositing and patterning additional dielectric layers (e.g., dielectric layer 138 or other applicable dielectric layers) and metal layers (e.g., interconnect layers 140, 141 or other applicable metal layers).

[0093] In one or more embodiments, it may be desirable to simultaneously remove portions of the second dielectric layer and the third dielectric layer in the gate trench and the field plate trench rather than individually to reduce the number of times the surface 113 of the substrate 110 in these regions is exposed. Reducing the exposure of the surface 113 can advantageously reduce the likelihood that the surface 113 will be damaged during the manufacturing process. In addition, simultaneously removing portions of the second dielectric layer and the third dielectric layer rather than removing them in separate wet etching steps can reduce the total number of process steps required to manufacture the transistor device 100. For example, Fig.18 is a diagram illustrating a method for manufacturing a transistor device (eg, Figure 1 100) wherein a corresponding wet etching process simultaneously removes portions of the second dielectric layer and the third dielectric layer from the gate trench and the field plate trench. To enhance understanding, Fig.18 Can be used with Figure 19-32 Also check out, Figure 19-32 Depicts products in various stages of manufacture Figure 1 1. A cross-sectional view of one or more embodiments of a transistor device 100.

[0094] First reference Fig.18 Step 1802 and Fig.19 In a first manufacturing stage 1900, a semiconductor substrate 110 is provided and an active region 150 is defined in the semiconductor substrate 110. It should be noted that various features of step 1802 and the first manufacturing stage 1900 correspond to the above-mentioned steps in conjunction with Figure 2 Step 202 and Figure 3 For the features described in the manufacturing stage 300 of the present invention, similar reference numerals are used to represent similar elements. For the sake of brevity, the description of these elements will not be repeated here.

[0095] Next reference Fig.18 Step 1804 and Fig. 20During the manufacturing stage 2000, a first dielectric layer 116 is formed on (e.g., directly on and in contact with) the upper surface 113 of the semiconductor substrate 110. As described above, in one or more embodiments, the first dielectric layer 116 may have a thickness in a range of about 30 angstroms to about 1,500 angstroms. The first dielectric layer 116 may be formed of a dielectric material, such as, as non-limiting examples, Al2O3, SiN, Si3N4, SiO2, SiON, AlN, SiAlN, HfO2, ZrO2, TiO2, or another suitable material that may be deposited via chemical vapor deposition (e.g., LPCVD). In one or more embodiments, the first dielectric layer 116 may include an oxide (e.g., as non-limiting examples, SiO2, ZrO2, HfO2, Al2O3, or TiO2).

[0096] Next reference Fig.18 Step 1806 and Fig.21 During the manufacturing stage 2100, a second dielectric layer 118 is formed on the first dielectric layer 116 (e.g., directly on and in contact with the first dielectric layer 116). As described above, in one or more embodiments, the second dielectric layer 118 can have a thickness in a range of about 100 angstroms to about 4,000 angstroms. The second dielectric layer 118 can be formed of a dielectric material, such as, as non-limiting examples, Al2O3, SiN, Si3N4, SiO2, SiON, AlN, SiAlN, HfO2, ZrO2, TiO2, or another suitable material that can be deposited via plasma enhanced chemical vapor deposition (e.g., PECVD). In one or more embodiments, the second dielectric layer 118 can include a nitride (e.g., as non-limiting examples, SiN, AlN, SiAlN).

[0097] Next reference Fig.18 Step 1808 and Fig. 22During the manufacturing stage 2200, a patterned dry etch is performed to form an opening 2202 and an opening 2204 in the second dielectric layer 118. For example, during the manufacturing stage 2200, a dry etch process (e.g., as a non-limiting example, an RIE process or other plasma etch process) is performed in combination with a photolithography process to remove portions of the second dielectric layer 118, thereby forming openings 2202, 2204 in the second dielectric layer 118, through which the surface of the first dielectric layer 116 is exposed. The first dielectric layer 116 can act as an etch stop layer for this dry etch process, thereby mitigating or preventing damage to the surface 113 of the substrate 110. This makes it possible for the exposed portions 2206, 2208 of the first dielectric layer 116 to be damaged by the dry etch process (e.g., due to exposure to plasma).

[0098] In addition, some material of the exposed portion 2208 of the first dielectric layer 116 is removed during the dry etching process, and the amount of material removed in this manner depends on the process and may not be uniform across transistor devices fabricated simultaneously (e.g., when processing a wafer including multiple transistor devices). This results in uncertainty in the thickness of the exposed portion 2208 and reduces the thickness uniformity of the exposed portion 2208.

[0099] Next reference Fig.18 Step 1810 and Fig.23 During the manufacturing stage 2300, a third dielectric layer 148 is formed over the substrate 110. The third dielectric layer 148 may be formed directly on the top and side surfaces of the second dielectric layer 118, and on the upper surface of the first dielectric layer 116 in the gate trench 2302 and the field plate trench 154 (e.g., corresponding to the surface of the damaged portions 2206, 2208 of the first dielectric layer 116). In one or more embodiments, the third dielectric layer 148 may be formed of a dielectric material, such as, as non-limiting examples, Al2O3, SiN, Si3N4, SiO2, SiON, AlN, SiAlN, HfO2, ZrO2, TiO2, or another suitable material that may be deposited via chemical vapor deposition (e.g., LPCVD). In one or more embodiments, the third dielectric layer 148 may include an oxide (e.g., as non-limiting examples, SiO2, ZrO2, HfO2, Al2O3, or TiO2).

[0100] Next reference Fig.18 Step 1812 and Fig.24During the manufacturing stage 2400, a first patterned photoresist layer 2402 and a second patterned photoresist layer 2404 are formed over the substrate 110. For example, the first patterned photoresist layer 2402 and the second patterned photoresist layer 2404 can be formed via respective photolithography processes, each of which includes spin coating a photoresist material (e.g., a resin) over the substrate 110, exposing the photoresist material to ultraviolet (UV) light through a patterned mask and baking at a predetermined temperature, and removing portions of the photoresist material using a developer (e.g., removing those portions exposed to UV light when a positive photoresist material is used, or removing those portions not exposed to UV when a negative photoresist material is used). An opening 2406 is formed through the first photoresist layer 902 and the second photoresist layer 904, exposing a region including the gate channel 2302 (i.e., a "gate channel region") through the opening 2406.

[0101] In one or more embodiments, the first photoresist layer 2402 can be developed simultaneously with the second photoresist layer 2404. As shown, the opening in the first photoresist layer 2402 can be wider than the opening in the second photoresist layer 2404, such that the second photoresist layer 2404 overhangs the first photoresist layer 2402 in the region of the opening 2406.

[0102] In an exemplary embodiment, the first photoresist layer 2402 has a thickness of about 0.5 μm to about 2 μm, but it is understood that other suitable thicknesses may be used. In an exemplary embodiment, the second photoresist layer 2404 has a thickness of between about 0.25 μm and about 1.5 μm, but other suitable thicknesses may also be used.

[0103] Next reference Fig.18 Step 1814 and Fig.25 During the manufacturing stage 2500, a wet etch is performed to remove the exposed portion of the third dielectric layer 148 and the portion of the first dielectric layer 116 (e.g., the damaged portion 2206) in the gate trench 2302. For example, the portion of the third dielectric layer 148 exposed by the opening 2406 is removed via this wet etching process. Some portions of the third dielectric layer 148 remain upon completion of this wet etching process, and these portions are disposed below the photoresist layer 2402. By simultaneously removing the portions of the third dielectric layer 148 and the first dielectric layer 116 in the gate trench 2302 in this manner, exposure of the surface 113 of the substrate 110 in the gate trench 2302 after forming the first dielectric layer 116 and before forming the third dielectric layer 148 is advantageously avoided, and the number of process steps performed is advantageously reduced.

[0104] Next reference Fig.18 Step 1816 and Fig.26 , at manufacturing stage 2600, a gate structure 128 is formed through an opening 2406 that extends through the first photoresist layer 2402 and the second photoresist layer 2404. The gate structure 128 may be electromagnetically coupled to the channel 108 through the upper surface 113 of the substrate 110 and the barrier layer 112. During operation of the transistor device 100, a potential change on the gate structure 128 may shift the quasi-Fermi level of the barrier layer 112 compared to the quasi-Fermi level of the channel layer 106, thereby modulating the electron concentration in the channel 108 within the portion of the substrate 110 below the gate structure 128. As described above, one or more aspects of the gate structure 128 in the manufacturing stage 2600 may be similar to Fig.11 Those aspects of the gate structure 128 in the manufacturing stage 1100 of FIG. 11 and are not repeated here for the sake of brevity.

[0105] Next reference Fig.18 Step 1818 and Fig. 27 During the manufacturing stage 2700, the first photoresist layer 2402, the second photoresist layer 2404, and the second portion of the gate metal deposited on the surface of the second photoresist layer 2404 are simultaneously removed via a stripping process. For example, in the stripping process, a photoresist stripper (e.g., a solvent such as acetone, 1-methyl-2-pyrrolidone, or dimethyl sulfoxide) can be applied to remove the first photoresist layer 2402 and the second photoresist layer 2404, which separates (i.e., "strips") the excess gate metal on the surface of the second photoresist layer 2404.

[0106] Although it has been combined Fig.18 Steps 1812, 1814, 1816, 1818 and Figure 24-27 The manufacturing stages 2400, 2500, 2600, 2700 of the embodiment of the present invention describe a double-layer lift-off process, but it should be understood that this is for illustration and not limitation. For example, in one or more other embodiments, when forming the gate structure 128, other photolithography processes (e.g., using a single photoresist layer developed with an undercut profile) may be used instead.

[0107] Next reference Fig.18 Step 1820 and Fig.28During the manufacturing stage 2800, an ILD layer 130 is formed over the substrate 110 (e.g., in contact with a surface of each of the second dielectric layer 118 and the gate structure 128). In one or more embodiments, the ILD layer 130 has a thickness in a range of about 500 angstroms to about 10,000 angstroms, although other suitable thicknesses may also be used. As non-limiting examples, the ILD layer 130 may be formed of silicon nitride, silicon oxide, silicon oxynitride, or other suitable dielectric materials.

[0108] Next reference Fig.18 Step 1822 and Fig.29 , at the manufacturing stage 2900, a patterned dry etch is performed to form an opening 2902 in the ILD layer 130. For example, during the manufacturing stage 2900, a dry etching process (e.g., as a non-limiting example, a RIE process or other plasma etching process) can be performed to remove a portion of the ILD layer 130 to form the opening 2902. The opening 2902 can overlap the field plate trench 154. The third dielectric layer 148 can act as an etch stop layer for this dry etching process, thereby mitigating or preventing damage to the surface 113 of the substrate 110. This causes the exposed portion of the third dielectric layer 148 to be damaged by the dry etching process (e.g., due to plasma damage).

[0109] Next reference Fig.18 Step 1824 and Fig.30 During the manufacturing stage 3000, a wet etch is performed to remove the exposed portions of the third dielectric layer 148 in the field plate trenches 154 (i.e., exposed through the openings 2902) and portions of the first dielectric layer 116 (e.g., damaged portions 2208), thereby exposing the surface 113 of the substrate 110 in the field plate trenches 154. For example, the exposed portions of the third dielectric layer 148 (those portions located in the field plate trenches 154) that were damaged by the dry etching process in step 1822 are removed via this wet etching process. Some portions of the third dielectric layer 148 remain when this wet etching process is completed, and these portions are disposed between the upper surface of the second dielectric layer 118 and the ILD layer 130. By simultaneously removing portions of the third dielectric layer 148 and the first dielectric layer 116 in the field plate trench 154 in this manner, exposure of the surface 113 of the substrate 110 in the field plate trench 154 after forming the first dielectric layer 116 and before forming the third dielectric layer 148 is advantageously avoided, and the number of process steps performed is advantageously reduced.

[0110] Next reference Fig.18 Step 1826 and Fig.31In the manufacturing stage 3100, a fourth dielectric layer 152 is formed over the substrate 110. The fourth dielectric layer 152 may be formed directly on the surface of the ILD layer 130, on the top and side surfaces of the second dielectric layer 118 in the field plate trench 154, on the side surfaces of the first dielectric layer 116 in the field plate trench 154, and on the surface 113 of the substrate 110 in the field plate trench 154. In one or more embodiments, the fourth dielectric layer 152 may be formed of a dielectric material, such as, as non-limiting examples, Al2O3, SiN, Si3N4, SiO2, SiON, AlN, SiAlN, HfO2, ZrO2, TiO2, or another suitable material that may be deposited via PECVD or LPCVD. The fourth dielectric layer 152 may have a thickness in a range of about 30 angstroms to about 5000 angstroms.

[0111] Next reference Fig.18 Step 1828 and Fig.32 , at manufacturing stage 3200, a field plate 135 is formed on the fourth dielectric layer 152. For example, a patterned conductive layer (e.g., deposited via sputtering, evaporation, or chemical vapor deposition, as non-limiting examples, and then patterned using a suitable photolithography process) can be formed over the substrate 110 to form the field plate 135. For example, the conductive layer can include a conductive material such as TiW, TiWN, WSi, or other suitable materials. The conductive layer can have a thickness in a range of about 100 angstroms to about 5,000 angstroms, although other suitable thicknesses can also be used.

[0112] Using a dielectric layer (i.e., fourth dielectric layer 152) formed after forming field plate trench 154 to separate field plate 135 from surface 113 of substrate 110 ensures that this dielectric material has not been damaged by the dry etching process used at step 1824 to form opening 2902 in ILD layer 130 extending through third dielectric layer 148 that overlaps field plate trench 154. Removing and replacing damaged dielectric material in field plate trench 154 reduces the likelihood of charge carrier traps existing in field plate trench 154, which advantageously improves the performance of transistor device 100. This approach also provides better thickness uniformity of the dielectric material separating field plate 135 from surface 113 in field plate trench 154, which advantageously reduces process variations regarding the amount of separation between field plate 135 and surface 113 in field plate trench 154, and advantageously improves the stability of gate threshold voltage of transistor device 100.

[0113] It should be understood that additional processing steps may be performed to fabricate the transistor device 100, and these additional processing steps may be performed during the Fig.18As non-limiting examples, such processing steps may include depositing and patterning additional dielectric layers (e.g., dielectric layer 138 or other applicable dielectric layers) and metal layers (e.g., interconnect layers 140, 141 or other applicable metal layers).

[0114] The above description refers to elements or nodes or features being "connected" or "coupled" together. As used herein, unless otherwise expressly stated, "connection" means that one element is directly joined to another element (or is directly communicated with another element), and not necessarily mechanically joined. Similarly, unless otherwise expressly stated, "coupling" means that one element is directly or indirectly joined to another element (or is directly or indirectly communicated with another element), and not necessarily mechanically joined. Therefore, although the schematic diagram shown in the figure depicts an exemplary arrangement of elements, there may be other intervening elements, devices, features or components in the embodiments of the depicted subject matter. In addition, unless otherwise stated, the term "amplifier" used herein should be understood as a "power amplifier".

[0115] Although at least one exemplary embodiment has been presented in the above detailed description, it should be understood that there are a large number of variations. It should also be understood that one or more exemplary embodiments described herein are not intended to limit the scope, applicability or configuration of the claimed subject matter in any way. In fact, the above detailed description will provide a convenient guide for implementing the described one or more embodiments to those skilled in the art. It should be understood that various changes may be made to the functions and arrangements of the elements, including equivalents and foreseeable equivalents known at the time of filing this patent application, without departing from the scope defined in the claims.

Claims

1. A transistor device, characterized in that: include: Semiconductor substrate; a first dielectric layer, the first dielectric layer being disposed on a surface of the semiconductor substrate; a second dielectric layer, the second dielectric layer being disposed directly on the first dielectric layer; a third dielectric layer disposed on a portion of the second dielectric layer, wherein a gate channel is at least partially defined via a first opening extending through the first dielectric layer, the second dielectric layer, and the third dielectric layer; a gate structure disposed directly on the surface of the semiconductor substrate in the gate channel, wherein portions of the first dielectric layer and the second dielectric layer are directly interposed between portions of the gate structure and the surface of the semiconductor substrate; as well as A field plate is disposed to at least partially overlap the gate structure, wherein a portion of the field plate is disposed in a field plate channel at least partially defined via a second opening extending through at least the second dielectric layer and the third dielectric layer.

2. The transistor device according to claim 1, characterized in that Also included is an interlayer dielectric layer disposed above the first dielectric layer, the second dielectric layer, the third dielectric layer, and the gate structure.

3. The transistor device according to claim 2, characterized in that The field plate at least partially overlaps the interlayer dielectric layer such that the interlayer dielectric layer is interposed between the gate structure and the field plate.

4. The transistor device according to claim 3, characterized in that Additionally included is a fourth dielectric layer at least partially disposed directly on the surface of the semiconductor substrate in the field plate trench.

5. The transistor device according to claim 4, characterized in that Portions of the fourth dielectric layer are directly disposed on surfaces of the interlayer dielectric layer, the first dielectric layer, the second dielectric layer, and the third dielectric layer.

6. The transistor device according to claim 5, characterized in that The field plate is disposed directly on the fourth dielectric layer.

7. The transistor device according to claim 6, characterized in that The fourth dielectric layer separates the field plate from the surface of the semiconductor substrate in the field plate trench.

8. The transistor device according to claim 4, characterized in that The first dielectric layer and the third dielectric layer each include a first dielectric material, the second dielectric layer and the interlayer dielectric layer each include a second dielectric material, and the second dielectric material has a different etch rate than the first dielectric material for at least one wet etching process.

9. A method for manufacturing a transistor device, characterized in that The method comprises: providing a semiconductor substrate; forming a first dielectric layer on the semiconductor substrate; forming a second dielectric layer on the first dielectric layer; The gate trench and field plate trench are formed by the following steps: performing a first patterned dry etch to form a first opening and a second opening in the second dielectric layer; and performing a first wet etch to form a third opening and a fourth opening in the first dielectric layer; forming a third dielectric layer directly on the second dielectric layer and directly on the surface of the semiconductor substrate exposed by the third opening and the fourth opening; removing a first portion of the third dielectric layer from the gate trench; forming a gate structure, the gate structure being at least partially disposed in the gate trench and contacting surfaces of the semiconductor substrate, the first dielectric layer, and the second dielectric layer; and A field plate is formed overlapping the gate structure, wherein at least a portion of the field plate is disposed in the field plate trench.

10. A method for manufacturing a transistor device, characterized in that The method comprises: providing a semiconductor substrate; forming a first dielectric layer on the semiconductor substrate; forming a second dielectric layer on the first dielectric layer; The gate trench and the field plate trench are formed by at least the following steps: performing a first patterned dry etch to form a first opening and a second opening in the second dielectric layer; forming a third dielectric layer directly on a surface of the first dielectric layer and directly on a surface of the second dielectric layer exposed through the first opening and the second opening; performing a first wet etch to remove a first portion of the first dielectric layer and a first portion of the third dielectric layer from the gate trench, thereby exposing the surface of the semiconductor substrate in the gate trench; forming a gate structure, the gate structure being at least partially disposed in the gate trench and contacting surfaces of the semiconductor substrate, the first dielectric layer, and the second dielectric layer; and A field plate is formed overlapping the gate structure, wherein at least a portion of the field plate is disposed in the field plate trench.

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